lanxicy.com

第一范文网 文档专家

第一范文网 文档专家

Vol. 32, No. 7

Journal of Semiconductors

July 2011

A new high voltage SOI LDMOS with triple RESURF structure

Hu Xiarong(胡夏融)? , Zhang Bo(张波), Luo Xiaorong(罗小蓉), Yao Guoliang(姚国亮), Chen Xi(陈曦), and Li Zhaoji(李肇基)

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

Abstract: A novel triple RESURF (T-resurf) SOI LDMOS structure is proposed. This structure has a P-type buried layer. Firstly, the depletion layer can extend on both sides of the P-buried layer, serving as a triple RESURF and leading to a high drift doping and a low on-resistance. Secondly, at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The proposed structure is used in SOI devices for the first time. The T-resurf SOI LDMOS with BV D 315 V is obtained by simulation on a 6 m-thick SOI layer over a 2 m-thick buried oxide layer, and its Rsp is reduced from 16.5 to 13.8 m cm2 in comparison with the double RESURF (D-resurf) SOI LDMOS. When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV2 /Ron . It reduces Rsp by 25% in 400 V SOI LDMOS and by 38% in 550 V SOI LDMOS compared with the D-resurf structure. Key words: SOI LDMOS; double resurf; triple resurf; REBULF; breakdown voltage DOI: 10.1088/1674-4926/32/7/074006 EEACC: 2560

1. Introduction

RESURF technology has been widely used in order to obtain a high breakdown voltage and low on-resistance in a lateral double-diffused metal–oxide–semiconductor fieldeffect-transistor (LDMOSFET). D-resurf and T-resurf structures have been realized in the bulk silicon LDMOS to reduce on-resistance?1 5? . However, the T-resurf structure has not been reported to be applied to SOI LDMOS before and the optimization of P-buried layer has not been discussed yet. The P-layer can reduce bulk electric field in a high doping concentration in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The P-type buried layer can be easily implemented by using ion implantation without an extra process compared with the D-resurf structure.

7 15 cm 3 for a T-resurf SOI LDMOS with tM D 1.5 m, D-resurf has a high electric field peak E0 in the interface of the P-top and N-drift region. However, T-resurf (tM D 1.5 m) has two lower electric field peaks E1 and E2 , which results in a reduced bulk electric field and the electric field concentration effect disappears. This effect is similar to the effects of REBULF technology?6 8? . Moreover, the value of E1 and E2 is almost the same as the interface electric field EI12 , so a uniformly distributed bulk electric field is obtained in the SOI layer. This field distribution modulates the electric field at the drain side, leading to an enhanced average bulk field and thus an improved BV, as seen in Fig. 2(b). When tM D 3 m, the T-resurf structure has just one high electric field peak E3 . This shows that the electric field peak approaches the bottom of the SOI layer. Moreover, the interface electric field of T-resurf (tM D 3 m) is much lower than that of T-resurf (tM D 1.5 m) at the drain

2. Structure and mechanism

The cross section of a T-resurf SOI LDMOS is shown in Fig. 1. ts and Nd are the thickness and doping concentration of the SOI layer. tp , Lp and Np are the thickness, length and doping concentration of the P-buried layer, respectively. tM represents the distance from the top of the P-buried layer to the surface. The field plate here is used to avoid premature breakdown. Figure 2 shows the electric field and potential distributions of D-resurf and T-resurf SOI LDMOSFETs. BV represents the breakdown voltage and Rsp represents the specific on-resistance. Figure 2(a) indicates that the vertical location (i.e. tM / of the P-layer has great influence on the bulk electric field distributions. At the optimal doping concentration Nd D

Fig. 1. Schematic cross sections of a T-resurf SOI LDMOS.

* Project supported by the National Natural Science Foundation of China (Nos. 60806025, 60976060). ? Corresponding author. Email: h1 x2 r3@126.com c 2011 Chinese Institute of Electronics Received 5 January 2011, revised manuscript received 13 March 2011

074006-1

J. Semicond. 2011, 32(7)

Hu Xiarong et al.

Fig. 3. Off-state state and on-state characteristics comparison of Dresurf and T-resurf SOI LDMOS. (a) Comparison of specific onresistance versus breakdown voltage of D-resurf and T-resurf SOI LDMOS (ts D 6 m, tI D 2 m, Ld D 20 m, Lp D 17 m, tp D 1 m). (b) On-state vertical current density along x D Ld /2 in SOI layer (VG D 15 V and VD D 1 V, the BV D 315 V).

structure to 315 V when two devices have the same Rsp D 13.8 m cm2 . The current density in the vertical direction at the on-state is given in Fig. 3(b). T-resurf with tM D 1.5 m has the largest current density above and below the P-layer compared with the other two structures.

Fig. 2. Electric field and potential distributions of D-resurf and Tresurf structures (ts D 6 m, tI D 2 m, Ld D 20 m, Lp D 17 m, tp D 1 m). (a) Vertical electric field along x D 15 m (Ld /2) in SOI layer. (b) Electric field and potential distributions at the drain. (c) Electric field distributions in the x -direction at the surface.

3. Results and discussion

The parameters of P-buried layer are optimized with the 2-D simulator MEDICI. It can be observed from Fig. 4(a) that the T-resurf structure with tM D 1.5 m has the highest Nd of 7 15 cm 3 at the maximal BV, which results in a 16% decrease in Rsp compared with optimized Nd D 5.6 15 cm 3 of the D-resurf structure. Figure 4(b) shows the dependence of BV and Rsp on different tM . The best T-resurf optimal area is 1 m < tM < 1.5 m. Figure 5 shows the dependence of BV and Rsp on Lp . Theoretically, Np should be increased to maintain the charge balance when the value of Lp is low. However, according to the SOI RESURF condition (the D-resurf model is used to approximate the T-resurf structure herein)?9? , Np should not be too high in order to fully deplete, which causes a decreased in Nd as shown Fig. 5(a). Hence, a narrower P-buried layer has a smaller optimized Nd to maintain the BV of 315 V and the Rsp

side, so the BV is decreased. The surface electric field is shown in Fig. 2(c). The vertical location of the P-layer has an obvious modulation effect on the surface field. T-resurf with tM D 1.5 m has the lowest electric field at the source side and highest electric field at the drain side. The doping concentration of the drift region can be therefore the highest. Figure 3 shows the off-state and on-state characteristics of D-resurf and T-resurf SOI LDMOSFETs. In Fig. 3(a), Rsp of T-resurf with tM D 1.5 m decreases to 13.8 m cm2 from 16.5 m cm2 of D-resurf LDMOS with the same BV = 315 V; or the BV of T-resurf increases from 286 V of D-resurf

074006-2

J. Semicond. 2011, 32(7)

Hu Xiarong et al.

Fig. 4. Influence of tM on BV and Rsp (ts D 6 m, tI D 2 m, Ld D 20 m, tp D 1 m, Lp D 17 m). (a) Sensitivity of BV and Rsp with Nd for different tM . (b) Dependence of BV and Rsp on different tM . The best T-resurf optimal area is obtained here.

Fig. 5. Dependence of BV and Rsp on Lp (the middle of the P layer is at x D 15 m which is also the middle of the drift region. tp D 1 m, tM D 1:5 m). (a) Sensitivity of BV and Rsp with Nd for different Lp . (b) Dependence of BV and Rsp on Lp at the same Nd D 7 1016 cm 3 . The best T-resurf optimal area is obtained here.

is increased. But when Lp > 18 m, the Rsp increases dramatically because the JFET resistance near the source becomes the main element of Rsp ?10? . Figure 5(b) indicates the influence of Lp . When 16 m < Lp < 18 m, the optimal T-resurf area is obtained. In general, T-resurf with optimal tM can reduce the bulk electric field in a high drift region doping and enhance electric field at the drain side, which results in a uniform bulk electric field distributions and a high FOM of BV2 /Ron . This also applies to the SOI LDMOS with ts > 6 m. The vertical electric field distributions at the drain side are compared in Fig. 6 at ts D 6, 10 and 20 m. When ts increases, the SOI layer sustains more proportion of the BV and the modulation effect of P-layer is more apparent. T-resurf with ts D 20 m has the same critical electric field as D-resurf structure but the BV is increased by 118 V due to the enhanced bulk electric field, while T-resurf with ts D 10 m and ts D 6 m is increased by 68 V and 29 V, respectively. Figure 7 shows the phenomenon. At the same BV for the D-resurf and T-resurf structures, T-resurf has higher Nd and Np as seen in Fig. 7(a). T-resurf also has higher (Nd; T Nd; D //Nd; D for a larger ts value. Figure 7(b) shows the dependence of BV and Rsp on ts . T-resurf structure reduces Rsp by 25% in 400 V SOI LDMOS and reduces Rsp by 38% in 550 V SOI LDMOS, compared with D-resurf structure.

Fig. 6. Comparison of D-resurf and T-resurf electric field at the drain side when ts D 6, 10 and 20 m (tI D 2 m, tp D 1 m). The doping concentration of drift region is Nd D 7 15 cm 3 for ts D 6 m, Nd D 3:4 15 cm 3 for ts D 10 m, Nd D 1:2 15 cm 3 for ts D 20 m (each Nd is T-resurf optimal doping concentration) and the lateral dimension is designed to meet the vertical breakdown conditions.

4. Conclusion

A novel T-resurf SOI LDMOS structure has been proposed. This structure has been reported in SOI LDMOS and

074006-3

J. Semicond. 2011, 32(7)

Hu Xiarong et al. tric field distributions and an enhanced BV. The T-resurf structure provides the on-resistance reduction of 16%, 25% and 38% compared with D-resurf structure in 315 V, 400 V and 550 V SOI LDMOS, respectively.

References

[1] Imam M, Hossain Z, Quddus M, et al. Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process. IEEE Trans Electron Devices, 2003, 50(7): 1697 [2] Disney D R, Paul A K, Darwish M, et al. A new 800 V lateral MOSFET with dual conduction paths. Proceedings of International Symposium on Power Semiconductor Devices & ICs, Osaka, 2001: 399 [3] Banerjee S, Parthasarathy V, Manley M. Design of stable 700 V lateral MOSFET for new generation, low-cost off-line SMPS. Proceedings of International Symposium on Power Semiconductor Devices & ICs, USA, 2010: 269 [4] Luo X R, Wang Y G, Yao G L, et al. High voltage partial SOI LDMOS with a variable low-k dielectric buried layer and a buried p-layer. IEEE Electron Device Lett, 2010, 31(6): 594 [5] Hua T T, Guo Y F, Sheu G. A 2D analytical model of bulk-silicon triple RESURF devices. Proceedings of International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2010: 1850 [6] Zhang Bo, Duan Baoxing, Li Zhaoji. Breakdown voltage analysis of a REBULF LDMOS structure with an n+-floating layer. Chinese Journal of Semiconductors, 2006, 27(4): 730 [7] Cheng J B, Zhang B, Li Z J. A novel 1200 V LDMOSFET with floating buried layer in substrate. IEEE Electron Device Lett, 2008, 29(6): 645 [8] Cheng J B, Zhang B, Li Z J. Longitudinal junction termination technique by multiple floating buried-layers for LDMOST. Electron Lett, 2008, 44(15): 933 [9] Guo Yufeng, Fang Jian, Zhang Bo, et al. A 2D analytical model of SOI double RESURF effect. Chinese Journal of Semiconductors, 2005, 26(4): 764 [10] Hossain Z, Imam M, Fulton J. Double-RESURF 700 V Nchannel LDMOS with best-in-class on-resistance. Proc Int ISPSD Conf, 2002: 137

Fig. 7. Comparison of Rsp , BV and Nd , Np versus ts of D-resurf and T-resurf SOI LDMOS for ts D 6, 10 and 20 m (tI D 2 m, tp D 1 m). (a) Dependence of Nd and Np on ts . (b) Dependence of BV and Rsp on ts . The lateral dimension is designed to meet the vertical breakdown conditions.

the optimization of P-buried layer has been investigated for the first time. The buried P-layer can reduce bulk electric field in drift region in a high doping concentration and enhance electric field at the drain side, which results in a uniform bulk elec-

074006-4

相关文章:

更多相关标签:

- 高压Double RESURF LDMOS器件设计与工艺模拟
- 一种用于开关电源启动电路的新型自偏置高压器件结构
- 基于SOI 技术高压LDMOS 击穿电压的
- 考虑埋氧层电荷时的SOI高压器件纵向耐压模型
- 高压LDMOS 功率器件的研究
- SOI硅膜厚度对RESURF LDMOS参数的影响
- 基于SOI 技术高压LDMOS 击穿电压的
- 高压Double RESURF LDMOS器件设计与工艺模拟
- TRIPLE RESURF LDMOS器件的优化设计
- 1 200V MR D-RESURF LDMOS与BCD
- 基于漏区边界曲率分析的射频RESURF LDMOS耐压与导通电阻优化
- SOI_LDMOS功率器件的研究与制备
- 一种新型的低导通电阻折叠硅SOI LDMOS
- 阶梯掺杂薄漂移区RESURF LDMOS耐压模型
- 1200V MR D-RESURF LDMOS与BCD兼容工艺研究