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nRF24LE1


nRF24LE1
Ultra-low Power Wireless System On-Chip Solution

Product Specification v1.4
Key Features
? ? ? ? ? ? ? ? ? ? ? ? nRF24L01+ 2.4 GHz transceiver (250 kbps, 1

Mbps and 2 Mbps air data rates) Fast microcontroller (8051 compatible) 16 kB program memory (on-chip Flash) 1 kB data memory (on-chip RAM) 1 kB NV data memory 512 bytes NV data memory (extended endurance) AES encryption HW accelerator 16-32bit multiplication/division co-processor (MDU) 6-12 bit ADC High flexibility IOs Serves a set of power modes from ultra low power to a power efficient active mode Several versions in various QFN packages: X 4x4mm QFN24 X 5x5mm QFN32 X 7x7mm QFN48 Support for HW debugger HW support for firmware upgrade

Applications
? Computer peripherals X Mouse X Keyboard X Remote control X Gaming Advanced remote controls X Audio/Video X Entertainment centers X Home appliances Goods tracking and monitoring: X Active RFID X Sensor networks Security systems X Payment X Alarm X Access control Health, wellness and sports X Watches X Mini computers X Sensors Remote control toys

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All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. April 2010

nRF24LE1 Product Specification Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification.

Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications are not implied. Exposure to limiting values for extended periods may affect device reliability.

Life support applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Data sheet status Objective product specification

This product specification contains target specifications for product development. Preliminary product specification This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. Product specification This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Contact details
For your nearest dealer, please see www.nordicsemi.com Main office:

Otto Nielsens veg 12 7004 Trondheim Norway Phone: +47 72 89 89 00 Fax: +47 72 89 89 89 ww.nordicsemi.no

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Revision History
Date March 2009 September 2009 Version 1.2 1.3 Description Updated Figure 33., Figure 34. and Table 35.. Added Table 93. Updated BOM, Table 28., Table 29.,Table 34.,Table 46., Table 53., Table 61.,Table 87., Table 101., Table 113., Table 115., sections 6.3.4.1, 9.1, 9.3 13.3.3, 29.1.2, 29.2.2, 29.3.2 and 30.1. Simplified way of writing binary numbers and denoting register bits. Updated Figure 9., Figure 10., Figure 30., Note: on page 87, Figure 46., Figure 51. and Figure 52. Updated section 2.1, section 12.3 , section 13.3.1, Table 14. , Table 15., Table 27.,Table 58., Table 111. ,Table 114. and Table 115.Updated BOM information in chapter 29.

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Contents
1 Introduction .............................................................................................. 10 1.1 Prerequisites ....................................................................................... 10 1.2 Writing conventions ............................................................................. 10 2 Product overview ..................................................................................... 11 2.1 Features .............................................................................................. 11 2.2 Block diagram ..................................................................................... 13 2.3 Pin assignments .................................................................................. 14 2.3.1 24-pin 4x4 QFN-package variant .................................................... 14 2.3.2 32-pin 5x5 QFN-package variant .................................................... 14 2.3.3 48-pin 7x7 QFN-package variant .................................................... 15 2.4 Pin functions ........................................................................................ 15 3 RF Transceiver ......................................................................................... 16 3.1 Features .............................................................................................. 16 3.2 Block diagram ..................................................................................... 17 3.3 Functional description ......................................................................... 17 3.3.1 Operational Modes ......................................................................... 17 3.3.2 Air data rate .................................................................................... 21 3.3.3 RF channel frequency .................................................................... 21 3.3.4 Received Power Detector measurements ...................................... 21 3.3.5 PA control ....................................................................................... 21 3.3.6 RX/TX control ................................................................................. 22 3.4 Enhanced ShockBurst? ..................................................................... 22 3.4.1 Features ......................................................................................... 22 3.4.2 Enhanced ShockBurst? overview ................................................. 22 3.4.3 Enhanced Shockburst? packet format .......................................... 23 3.4.4 Automatic packet assembly ............................................................ 26 3.4.5 Automatic packet disassembly ....................................................... 27 3.4.6 Automatic packet transaction handling ........................................... 28 3.4.7 Enhanced ShockBurst flowcharts ................................................... 30 3.4.8 MultiCeiver? .................................................................................. 33 3.4.9 Enhanced ShockBurst? timing ...................................................... 35 3.4.10 Enhanced ShockBurst? transaction diagram ................................ 38 3.4.11 Compatibility with ShockBurst? ..................................................... 42 3.5 Data and control interface ................................................................... 43 3.5.1 SFR registers .................................................................................. 43 3.5.2 SPI operation .................................................................................. 44 3.5.3 Data FIFO ....................................................................................... 46 3.5.4 Interrupt .......................................................................................... 47 3.6 Register map ....................................................................................... 48 3.6.1 Register map table ......................................................................... 48 4 MCU ........................................................................................................... 54 4.1 Block diagram ..................................................................................... 55 4.2 Features .............................................................................................. 55 4.3 Functional description ......................................................................... 56

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4.3.1 Arithmetic Logic Unit (ALU) ............................................................ 56 4.3.2 Instruction set summary ................................................................. 56 4.3.3 Opcode map ................................................................................... 60 5 Memory and I/O organization .................................................................. 62 5.1 PDATA memory addressing ................................................................ 63 5.2 MCU Special Function Registers ........................................................ 63 5.2.1 Accumulator - ACC ......................................................................... 63 5.2.2 B Register – B ................................................................................ 63 5.2.3 Program Status Word Register - PSW ........................................... 64 5.2.4 Stack Pointer – SP ......................................................................... 64 5.2.5 Data Pointer – DPH, DPL ............................................................... 64 5.2.6 Data Pointer 1 – DPH1, DPL1 ........................................................ 65 5.2.7 Data Pointer Select Register – DPS ............................................... 65 5.2.8 PCON register ................................................................................ 65 5.2.9 Special Function Register Map ....................................................... 66 5.2.10 Special Function Registers reset values ........................................ 67 6 Flash memory ........................................................................................... 70 6.1 Features .............................................................................................. 70 6.2 Block diagram ..................................................................................... 70 6.3 Functional description ......................................................................... 71 6.3.1 Using the NV data memory ............................................................ 71 6.3.2 Flash memory configuration ........................................................... 71 6.3.3 Brown-out ....................................................................................... 76 6.3.4 Flash programming from the MCU ................................................. 77 6.3.5 Flash programming through SPI ..................................................... 77 6.3.6 Hardware support for firmware upgrade ......................................... 81 7 Random Access memory (RAM) ............................................................. 84 7.1 SRAM configuration ............................................................................ 84 8 Timers/counters ....................................................................................... 86 8.1 Features .............................................................................................. 86 8.2 Block diagram ..................................................................................... 86 8.3 Functional description ......................................................................... 87 8.3.1 Timer 0 and Timer 1 ....................................................................... 87 8.3.2 Timer 2 ........................................................................................... 89 8.4 SFR registers ...................................................................................... 91 8.4.1 Timer/Counter control register – TCON .......................................... 91 8.4.2 Timer mode register - TMOD .......................................................... 92 8.4.3 Timer 0 – TH0, TL0 ........................................................................ 92 8.4.4 Timer 1 – TH1, TL1 ........................................................................ 92 8.4.5 Timer 2 control register – T2CON .................................................. 93 8.4.6 Timer 2 – TH2, TL2 ........................................................................ 93 8.4.7 Compare/Capture enable register – CCEN .................................... 94 8.4.8 Capture registers – CC1, CC2, CC3 .............................................. 94 8.4.9 Compare/Reload/Capture register – CRCH, CRCL ....................... 95 8.5 Real Time Clock - RTC ....................................................................... 95 8.5.1 Features ......................................................................................... 95

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8.5.2 Functional description of SFR registers .......................................... 95 9 Interrupts .................................................................................................. 99 9.1 Features .............................................................................................. 99 9.2 Block diagram ..................................................................................... 99 9.3 Functional description .......................................................................... 100 9.4 SFR registers ....................................................................................... 100 9.4.1 Interrupt Enable 0 Register – IEN0.................................................. 101 9.4.2 Interrupt Enable 1 Register – IEN1 ................................................. 101 9.4.3 Interrupt Priority Registers – IP0, IP1 .............................................. 101 9.4.4 Interrupt Request Control Registers – IRCON ................................ 102 10 Watchdog................................................................................................... 103 10.1 Features ............................................................................................... 103 10.2 Block diagram ...................................................................................... 103 10.3 Functional description .......................................................................... 103 11 Power and clock management................................................................. 105 11.1 Block diagram ...................................................................................... 105 11.2 Modes of operation .............................................................................. 105 11.3 Functional description .......................................................................... 110 11.3.1 Clock control.................................................................................... 110 11.3.2 Power down control – PWRDWN .................................................... 113 11.3.3 Operational mode control - OPMCON ............................................. 114 11.3.4 Reset result – RSTREAS ................................................................ 114 11.3.5 Wakeup configuration register – WUCON ....................................... 115 11.3.6 Pin wakeup configuration ................................................................ 115 12 Power supply supervisor ......................................................................... 117 12.1 Features ............................................................................................... 117 12.2 Block diagram ...................................................................................... 117 12.3 Functional description .......................................................................... 117 12.3.1 Power-on reset ................................................................................ 117 12.3.2 Brown-out reset ............................................................................... 118 12.3.3 Power-fail comparator ..................................................................... 118 12.4 SFR registers ....................................................................................... 119 13 On-chip oscillators.................................................................................... 120 13.1 Features ............................................................................................... 120 13.2 Block diagrams..................................................................................... 120 13.3 Functional description .......................................................................... 121 13.3.1 16 MHz crystal oscillator.................................................................. 121 13.3.2 16 MHz RC oscillator ....................................................................... 122 13.3.3 External 16 MHz clock ..................................................................... 122 13.3.4 32.768 kHz crystal oscillator ............................................................ 122 13.3.5 32.768 kHz RC oscillator ................................................................. 123 13.3.6 Synthesized 32.768 kHz clock......................................................... 123 13.3.7 External 32.768 kHz clock ............................................................... 123 14 MDU – Multiply Divide Unit....................................................................... 124 14.1 Features ............................................................................................... 124 14.2 Block diagram ...................................................................................... 124

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14.3 Functional description .......................................................................... 14.4 SFR registers ....................................................................................... 14.4.1 Loading the MDx registers............................................................... 14.4.2 Executing calculation ....................................................................... 14.4.3 Reading the result from the MDx registers ...................................... 14.4.4 Normalizing...................................................................................... 14.4.5 Shifting............................................................................................. 14.4.6 The mdef flag................................................................................... 14.4.7 The mdov flag .................................................................................. 15 Encryption/decryption accelerator .......................................................... 15.1 Features ............................................................................................... 15.2 Block diagram ...................................................................................... 15.3 Functional description .......................................................................... 16 Random number generator ...................................................................... 16.1 Features ............................................................................................... 16.2 Block diagram ...................................................................................... 16.3 Functional description .......................................................................... 16.4 SFR registers ....................................................................................... 17 General purpose IO port and pin assignments ...................................... 17.1 Block diagram ...................................................................................... 17.2 Functional description .......................................................................... 17.2.1 General purpose IO pin functionality ............................................... 17.2.2 PortCrossbar functionality ............................................................... 17.3 IO pin maps.......................................................................................... 17.3.1 Pin assignments in package 24 pin 4x4 mm ................................... 17.3.2 Pin assignments in package 32 pin 5x5 mm ................................... 17.3.3 Pin assignments in package 48 pin 7x7 mm ................................... 17.3.4 Programmable registers .................................................................. 18 SPI .............................................................................................................. 18.1 Features ............................................................................................... 18.2 Block diagram ...................................................................................... 18.3 Functional description .......................................................................... 18.3.1 SPI master ....................................................................................... 18.3.2 SPI slave ......................................................................................... 18.3.3 Slave SPI timing .............................................................................. 19 Serial port (UART) ..................................................................................... 19.1 Features ............................................................................................... 19.2 Block diagram ...................................................................................... 19.3 Functional description .......................................................................... 19.3.1 Serial port 0 control register – S0CON ............................................ 19.3.2 Serial port 0 data buffer – S0BUF ................................................... 19.3.3 Serial port 0 reload register – S0RELH, S0RELL ............................ 19.3.4 Serial port 0 baud rate select register - ADCON ............................. 20 2-Wire ......................................................................................................... 20.1 Features ............................................................................................... 20.2 Functional description .......................................................................... 124 124 125 126 126 126 126 126 127 128 128 128 128 130 130 130 130 131 132 132 133 133 134 135 136 137 138 140 147 147 147 148 148 150 151 155 155 155 155 156 157 157 158 159 159 159

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20.2.1 Recommended use ......................................................................... 20.2.2 Master transmitter/receiver .............................................................. 20.2.3 Slave transmitter/receiver ................................................................ 20.3 SFR registers ....................................................................................... 21 ADC ............................................................................................................ 21.1 Features ............................................................................................... 21.2 Block diagram ...................................................................................... 21.3 Functional description .......................................................................... 21.3.1 Activation ......................................................................................... 21.3.2 Input selection ................................................................................. 21.3.3 Reference selection ......................................................................... 21.3.4 Resolution........................................................................................ 21.3.5 Conversion modes........................................................................... 21.3.6 Output data coding .......................................................................... 21.3.7 Driving the analog input ................................................................... 21.3.8 SFR registers................................................................................... 22 Analog comparator ................................................................................... 22.1 Features ............................................................................................... 22.2 Block diagram ...................................................................................... 22.3 Functional description .......................................................................... 22.3.1 Activation ......................................................................................... 22.3.2 Input selection ................................................................................. 22.3.3 Reference selection ......................................................................... 22.3.4 Output polarity ................................................................................. 22.3.5 Input voltage range.......................................................................... 22.3.6 Configuration examples................................................................... 22.3.7 Driving the analog input ................................................................... 22.3.8 SFR registers................................................................................... 23 PWM ........................................................................................................... 23.1 Features ............................................................................................... 23.2 Block diagram ...................................................................................... 23.3 Functional description .......................................................................... 24 Absolute maximum ratings ...................................................................... 25 Operating condition .................................................................................. 26 Electrical specifications ........................................................................... 26.1 Power consumption.............................................................................. 27 HW debugger support .............................................................................. 27.1 Features ............................................................................................... 27.2 Functional description .......................................................................... 28 Mechanical specifications........................................................................ 29 Reference circuits ..................................................................................... 29.1 Q48 application example...................................................................... 29.1.1 Schematic ........................................................................................ 29.1.2 Layout .............................................................................................. 29.1.3 Bill Of Materials (BOM) .................................................................... 29.2 Q32 application example...................................................................... 159 159 160 162 165 165 165 165 165 166 166 166 166 167 168 169 171 171 171 171 171 171 172 172 172 172 172 173 174 174 174 174 176 177 178 183 185 185 185 186 188 188 188 189 189 190

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29.2.1 Schematic ........................................................................................ 29.2.2 Layout .............................................................................................. 29.2.3 Bill Of Materials (BOM) .................................................................... 29.3 Q24 application example...................................................................... 29.3.1 Schematic ........................................................................................ 29.3.2 Layout .............................................................................................. 29.3.3 Bill Of Materials (BOM) .................................................................... 30 Ordering information ................................................................................ 30.1 Package marking ................................................................................. 30.1.1 Abbreviations ................................................................................... 30.2 Product options .................................................................................... 30.2.1 RF silicon ......................................................................................... 30.2.2 Development tools ........................................................................... 31 Glossary..................................................................................................... 190 191 191 192 192 193 193 194 194 194 195 195 195 196

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nRF24LE1 Product Specification 1 Introduction

The nRF24LE1 is a member of the low-cost, high-performance family of intelligent 2.4 GHz RF transceivers with embedded microcontrollers. The nRF24LE1 is optimized to provide a single chip solution for ULP wireless applications. The combination of processing power, memory, low power oscillators, real-time counter, AES encryption accelerator, random generator and a range of power saving modes provides an ideal platform for implementation of RF protocols. Benefits of using nRF24LE1 include tighter protocol timing, security, lower power consumption and improved co-existence performance. For the application layer the nRF24LE1 offers a rich set of peripherals including: SPI, 2-wire, UART, 6 to 12 bit ADC, PWM and an ultra low power analog comparator for voltage level system wake-up. The nRF24LE1 comes in three different package variants: ? ? ? An ultra compact 4x4mm 24 pin QFN (7 generic I/O pins) A compact 5x5mm 32 pin QFN (15 generic I/O pins) A 7x7mm 48 pin QFN (31 generic I/O pins)

The 4x4mm 24 pin QFN is ideal for low I/O count applications where small size is key. Examples include wearable sports sensors and watches. The 5x5mm 32 pin QFN is ideal for medium I/O count applications such as wireless mouse, remote controls and toys. The 7x7mm 48 pin QFN is designed for high I/O count products like wireless keyboards.

1.1

Prerequisites

In order to fully understand the product specification, a good knowledge of electronics and software engineering is necessary.

1.2

Writing conventions

This product specification follows a set of typographic rules that makes the document consistent and easy to read. The following writing conventions are used: ? ? ? Commands, bit state conditions, and register names are written in Courier. Pin names and pin signal conditions are written in Courier bold. Cross references are underlined and highlighted in blue.

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nRF24LE1 Product Specification 2 2.1 Product overview Features

Features of the nRF24LE1 include: ? Fast 8-bit microcontroller: X Intel MCS 51 compliant instruction set X Reduced instruction cycle time, up to 12x compared to legacy 8051 X 32 bit multiplication – division unit Memory: X Program memory: 16 kB of Flash memory with security features (up to 1k erase/ write cycles) X Data memory: 1 kB of on-chip RAM memory X Non-volatile data memory: 1 kB X Non-volatile data memory extended endurance: 512 bytes (up to 20k erase/ write cycles) A number of on-chip hardware resources are available through programmable multi-purpose input/ output pins (7-31 pins dependent on package variant): X GPIO X SPI master X SPI slave X 2-Wire master/ slave X Full duplex serial port X PWM X ADC X Analog comparator X External interrupts X Timer inputs X 32.768 kHz crystal oscillator X Debug interface High performance 2.4 GHz RF-transceiver X True single chip GFSK transceiver X Enhanced ShockBurst? link layer support in HW: X Packet assembly/disassembly X Address and CRC computation X Auto ACK and retransmit X On the air data rate 250 kbps, 1 Mbps or 2 Mbps X Digital interface (SPI) speed 0-8 Mbps X 125 RF channel option, with 79 (2.402 GHz-2.480 GHz) channels within 2.400 - 2.4835 GHz X Short switching time enable frequency hopping X Fully RF compatible with nRF24LXX X RF compatible with nRF2401A, nRF2402, nRF24E1, nRF24E2 in 250 kbps and 1 Mbps mode A/D converter: X 6, 8, 10 or 12 bit resolution X 14 input channels X Single ended or differential input X Full-scale range set by internal reference, external reference or VDD X Single step mode with conversion time down to 3 ?s X Continuous mode with 2, 4, 8 or 16 kbps sampling rate X Low current consumption; only 0.1mA at 2 ksps X Mode for measuring supply voltage

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? Analog comparator: X Used as wakeup source X Low current consumption (0.75?A typical) X Differential or single-ended input X Single-ended threshold programmable to 25%, 50%, 75% or 100% of VDD or an arbitrary reference voltage from pin X 14-channel input multiplexer X Rail-to-rail input voltage range X Programmable output polarity Encryption/decryption accelerator X Utilize time and power effective AES firmware Random number generator: X Non-deterministic architecture based on thermal noise X No seed value required X Non-repeating sequence X Corrector algorithm ensures uniform statistical distribution X Data rate up to 10 kB per second X Operational while the processor is in standby System reset and power supply monitoring: X On-chip power-on and brown-out reset X Watchdog timer reset X Reset from pin X Power-fail comparator with programmable threshold and interrupt to MCU On-chip timers: X Three16-bit timers/counters operating at the system clock (sources from the 16 MHz on-chip oscillators) X One 16-bit timer/counter operating at the low frequency clock (32.768 kHz) On-chip oscillators: X 16 MHz crystal oscillator XOSC16M X 16 MHz RC-oscillator RCOSC16M X 32.768 kHz crystal oscillator XOSC32K X 32.768 kHz RC-oscillator RCOSC32K Power management function: X Low power design supporting fully static stop/ standby X Programmable MCU clock frequency from 125 kHz to 16 MHz X On chip voltage regulators supporting low power mode X Watchdog and wakeup functionality running in low power mode On chip support for FS2 or nRFprobe? HW debug Complete firmware platform available: X Hardware abstraction layer (HAL) Functions X Library functions X Gazell Wireless protocol X Application examples

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nRF24LE1 Product Specification 2.2 Block diagram
Program (FLASH) VREG1V7 1.9 V 3.6V VREG1V2 VDD_1V2
MEM-bus

Data (SRAM)

NVMEM (FLASH)

VDD_1V7 Memory bus decoder

IRAM 256 byte

MCU
SFR-bus

System Config

Crypt CoProc

RNG

RTC

Watch dog

Interrupt Control

Timers

Serial ports

R80515

GPIO

SPI Master

SPI Slave

2-Wire M/S

Wakeup Config

L01 i/f (SPI)

RF Transceiver

OCI Digital Crossbar POR Brown out detector XOSC 16 MHz RCOSC 16 MHz XOSC 32 kHz RCOSC 32 kHz Retention Latches
Debounce mux Debounce CK16M

PWM

ADC i/f

ADC

Comparator

Power Management

WakeUP OnPin

Debounce mux Debounce CLKLF

Pin Crossbar

Multi purpose pins - bidir dig/ analog

Figure 1. nRF24LE1 block diagram To find more information on the blocks, see Table 1. below: Name Memory (Program, Data, NVMEM) Power management RF Transceiver 2-Wire SPI (Master and Slave) GPIO PWM Watchdog Reference Chapter 5 on page 62 Chapter 11 on page 105 Chapter 3 on page 16 Chapter 20 on page 159 Chapter 18 on page 147 Chapter 17 on page 132 Chapter 23 on page 174 Chapter 10 on page 103

Table 1. Block diagram cross references

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nRF24LE1 Product Specification 2.3
2.3.1

Pin assignments
24-pin 4x4 QFN-package variant
P0.0 XC1 XC2 VDD VSS IREF
24 23 22 21 20 19

P0.1 VDD DEC1 DEC2 PROG VSS

1 2 3 4 5 6 7

nRF24LE1D QFN24 4x4
Exposed die pad 8 9 10 11 12 9

18 17 16 15 14 13

VDD VSS ANT2 ANT1 VDD_PA RESET

Figure 2. nRF24LE1D pin assignment (top view) for a QFN24 4x4 mm package

2.3.2

32-pin 5x5 QFN-package variant
P0.0 XC1 XC2 P1.6 P1.5 VDD VSS IREF
32 31 30 29 28 27 26 25 24

P0.1 VDD DEC1 DEC2 P0.2 PROG P0.3 VSS

VDD P0.2 P0.3 P0.4 P0.5 P0.6

1 2 3 4 5 6 7 8 Exposed die pad 9 10 11 12 13 14 15 16

nRF24LE1E QFN32 5x5

23 22 21 20 19 18 17

VDD VSS ANT2 ANT1 VDD_PA RESET P1.4 P1.3

Figure 3. nRF24LE1E pin assignment (top view) for a QFN32 5x5 mm package

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2.3.3 48-pin 7x7 QFN-package variant
P0.0 P3.6 XC1 XC2 P3.5 P3.4 P3.3 P3.2 P3.1 VDD VSS IREF
48 47 46 45 44 43 42 41 40 39 38 37

P0.1 P0.2 VDD DEC1 DEC2 P0.3 P0.4 P0.5 P0.6 PROG P0.7 VSS

1 2 3 4 5 6 7 8 9 10 11 12 Exposed die pad 13 14 15 16 17 18 19 20 21 22 23 24

36 35 34 33

nRF24LE1F QFN48 7x7

32 31 30 29 28 27 26 25

VDD VSS ANT2 ANT1 VDD_PA P3.0 RESET P2.7 P2.6 P2.5 P2.4 P2.3

Figure 4. nRF24LE1F pin assignment (top view) for a QFN48 7x7 mm package

2.4

Pin functions
Name VDD VSS DEC1 DEC2 P0.0 – P3.6 PROG RESET IREF VDD_PA Type Power Power Power Digital or analog I/O Digital Input Digital Input Analog Input Power Output Description Power supply (+1.9V to +3.6V DC) Ground (0V) Power supply outputs for de-coupling purposes (100nF for DEC1, 33nF for DEC2) General purpose I/O pins. Number of I/O available depends on package type. Input to enable flash programming Reset for microcontroller, active low Device reference current output. To be connected to reference resistor on PCB. Power supply output (+1.8V) for on-chip RF Power amplifier Differential antenna connection (TX and RX) Crystal connection for 16M crystal For the nRF24LE1 QFN48 7x7mm and QFN32 5x5mm connect the die pad to GND. For nRF24LE1 QFN24 4x4mm do not connect the die pad to GND.

ANT1, ANT2 RF XC1, XC2 Analog Input Exposed die Power/heat relief pad

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Table 2. nRF24LE1 pin functions 15 of 196

nRF24LE1 Product Specification 3 RF Transceiver

The nRF24LE1 uses the same 2.4 GHz GFSK RF transceiver with embedded protocol engine (Enhanced ShockBurst?) that is found in the nRF24L01+ single chip RF Transceiver. The RF Transceiver is designed for operation in the world wide ISM frequency band at 2.400 - 2.4835 GHz and is very well suited for ultra low power wireless applications. The RF Transceiver module is configured and operated through the RF transceiver map. This register map is accessed by the MCU through a dedicated on-chip Serial Peripheral interface (SPI) and is available in all power modes of the RF Transceiver module. The embedded protocol engine (Enhanced ShockBurst?) enables data packet communication and supports various modes from manual operation to advanced autonomous protocol operation. Data FIFOs in the RF Transceiver module ensure a smooth data flow between the RF Transceiver module and the nRF24LE1 MCU. The rest of this chapter is written in the context of the RF Transceiver module as the core and the rest of the nRF24LE1 as external circuitry to this module.

3.1

Features

Features of the RF Transceiver include: ? General X Worldwide 2.4 GHz ISM band operation X Common antenna interface in transmit and receive X GFSK modulation X 250kbps, 1 and 2Mbps on air data rate Transmitter X Programmable output power: 0, -6, -12 or -18dBm X 11.1mA at 0dBm output power Receiver X Integrated channel filters X 13.3mA at 2Mbps X -82dBm sensitivity at 2 Mbps X -85dBm sensitivity at 1 Mbps X -94dBm sensitivity at 250 kbps RF Synthesizer X Fully integrated synthesizer X 1 MHz frequency programming resolution X Accepts low cost ±60 ppm 16 MHz crystal X 1 MHz non-overlapping channel spacing at 1 Mbps X 2 MHz non-overlapping channel spacing at 2 Mbps Enhanced ShockBurst? X 1 to 32 bytes dynamic payload length X Automatic packet handling (assembly/disassembly) X Automatic packet transaction handling (auto ACK, auto retransmit) 6 data pipe MultiCeiver? for 6:1 star networks

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nRF24LE1 Product Specification 3.2 Block diagram
RF Transmitter
PA TX Filter GFSK Modulator

Baseband
TX FIFOs SPI
(Slave)

RFCON.rfce RFCON.rfcsn

SPI
(Master)

RF Receiver ANT1
LNA RX Filter GFSK Demodulator

Enhanced ShockBurst Baseband Engine

RFIRQ
Register map

ANT2
RF Synthesiser

RX FIFOs Power Management Radio Control

RFCON.rfcken
XOSC16M

Figure 5. RF Transceiver block diagram

3.3

Functional description

This section describes the different operating modes of the RF Transceiver and the parameters used to control it. The RF Transceiver module has a built-in state machine that controls the transitions between the different operating modes. The state machine is controlled by SFR register RFCON and RF transceiver register CONFIG, see section 3.5 for details.

3.3.1

Operational Modes

You can configure the RF Transceiver to power down, standby, RX and TX mode. This section describes these modes in detail.

3.3.1.1

State diagram

The state diagram (Figure 6.) shows the operating modes of the RF Transceiver and how they function. At the end of the reset sequence the RF Transceiver enters Power Down mode. When the RF Transceiver enters Power Down mode the MCU can still control the module through the SPI and the rfcsn bit in the RFCON register. There are three types of distinct states highlighted in the state diagram: ? ? ? Recommended operating mode: is a recommended state used during normal operation. Possible operating mode: is a possible operating state, but is not used during normal operation. Transition state: is a time limited state used during start up of the oscillator and settling of the PLL.

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nRF24LE1 Product Specification
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Legend:
Undefined

Undefined
Undefined

Recommended operating mode

Possible operating mode

Power on reset 50ms

Transition state

Recommended path between operating modes Possible path between operating modes
CE = 1 PWR_DN = 1 TX FIFO empty

Power Down PWR_UP=0 PWR_UP = 1 Start up time is 150?s

Pin signal condition Bit state condition System information

PWR_UP=0

PWR_UP = 0

Standby-I

PRIM_RX = 0 TX FIFO empty rfce = 1

PWR_UP = 0 rfce = 0

RX Settling 130 us

PRIM_RX = 1 rfce = 1

Standby-II TX FIFO not empty PRIM_RX = 0 rfce = 1 for more than 10?s

rfce = 0

TX finished with one packet rfce = 0

TX FIFO not empty rfce = 1 TX Settling 130 us

RX Mode

TX FIFO empty rfce = 1

PWR_UP=0 TX Mode PWR_UP = 0

rfce = 1 TX FIFO not empty

Figure 6. Radio control state diagram

3.3.1.2

Power down mode

In power down mode the RF Transceiver is disabled with minimal current consumption. All the register values available from the SPI are maintained and the SPI can be activated. For start up times see Table 4. on page 20. Power down mode is entered by setting the PWR_UP bit in the CONFIG register low.

3.3.1.3

Standby modes

Standby-I mode By setting the PWR_UP bit in the CONFIG register to 1, the RF Transceiver enters standby-I mode. StandbyI mode is used to minimize average current consumption while maintaining short start up times. Change to the active mode only happens if the rfce bit is enabled and when it is not enabled, the RF Transceiver returns to standby-I mode from both the TX and RX modes.

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Standby-II mode In standby-II mode extra clock buffers are active and more current is used compared to standby-I mode. The RF Transceiver enters standby-II mode if the rfce bit is held high on a PTX operation with an empty TX FIFO. If a new packet is downloaded to the TX FIFO, the PLL immediately starts and the packet is transmitted after the normal PLL settling delay (130?s). The register values are maintained and the SPI can be activated during both standby modes. For start up times see Table 4. on page 20.

3.3.1.4

RX mode

The RX mode is an active mode where the RF Transceiver is used as a receiver. To enter this mode, the RF Transceiver must have the PWR_UP bit, PRIM_RX bit and the rfce bit is set high. In RX mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the baseband protocol engine. The baseband protocol engine constantly searches for a valid packet. If a valid packet is found (by a matching address and a valid CRC) the payload of the packet is presented in a vacant slot in the RX FIFOs. If the RX FIFOs are full, the received packet is discarded. The RF Transceiver remains in RX mode until the MCU configures it to standby-I mode or power down mode. However, if the automatic protocol features (Enhanced ShockBurst?) in the baseband protocol engine are enabled, the RF Transceiver can enter other modes in order to execute the protocol. In RX mode a Received Power Detector (RPD) signal is available. The RPD is a signal that is set high when a RF signal higher than -64 dBm is detected inside the receiving frequency channel. The internal RPD signal is filtered before presented to the RPD register. The RF signal must be present for at least 40?s before the RPD is set high. How to use the RPD is described in Section 3.3.4 on page 21.

3.3.1.5

TX mode

The TX mode is an active mode for transmitting packets. To enter this mode, the RF Transceiver must have the PWR_UP bit set high, PRIM_RX bit set low, a payload in the TX FIFO and a high pulse on the rfce bit for more than 10?s. The RF Transceiver stays in TX mode until it finishes transmitting a packet. If rfce = 0, RF Transceiver returns to standby-I mode. If rfce = 1, the status of the TX FIFO determines the next action. If the TX FIFO is not empty the RF Transceiver remains in TX mode and transmits the next packet. If the TX FIFO is empty the RF Transceiver goes into standby-II mode. The RF Transceiver transmitter PLL operates in open loop when in TX mode. It is important never to keep the RF Transceiver in TX mode for more than 4ms at a time. If the Enhanced ShockBurst? features are enabled, RF Transceiver is never in TX mode longer than 4ms.

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3.3.1.6 Operational modes configuration

The following table (Table 3.) describes how to configure the operational modes. Mode RX mode TX mode TX mode Standby-II Standby-I Power Down PWR_UP register 1 1 1 1 1 0 PRIM_RX register 1 0 0 0 rfce 1 1 FIFO state

Data in TX FIFO. Will empty all levels in TX FIFOa. Minimum 10?s Data in TX FIFO.Will empty one high pulse level in TX FIFOb. 1 TX FIFO empty 0 No ongoing packet transmission -

a. If the rfce bit is held high the TX FIFO is emptied and all necessary ACK and possible retransmits are carried out. The transmission continues as long as the TX FIFO is refilled. If the TX FIFO is empty when the rfce bit is still high, the RF Transceiver enters standby-II mode. In this mode the transmission of a packet is started as soon as the rfcsn is set high after an upload (UL) of a packet to TX FIFO. b. This operating mode pulses the rfce bit high for at least 10?s. This allows one packet to transmit. This is the normal operating mode. After the packet is transmitted, the RF Transceiver enters standby-I mode.

Table 3. RF Transceiver main modes

3.3.1.7

Timing information

The timing information in this section relates to the transitions between modes and the timing for the rfce bit. The transition from TX mode to RX mode or vice versa is the same as the transition from the standby modes to TX mode or RX mode (130?s), as described in Table 4. Name Tpd2stby Tstby2a Thce Tpece2csn RF Transceiver Power Down ? Standby mode Standby modes ? TX/RX mode Minimum rfce high Delay from rfce pos. edge to rfcsn low Max. 1?sa 130?s 10?s 4?s Min. Comments

a. This presupposes that the XO is running. Please refer to CLKLFCTRL for bit 3 in Table 59. on page 112.

Table 4. Operational timing of RF Transceiver Note: If VDD is turned off, or if the nRF24LE1 enters Deep Sleep or Memory Retention mode, the register values are lost and you must configure the RF Transceiver before entering the TX or RX modes.

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3.3.2 Air data rate

The air data rate is the modulated signaling rate the RF Transceiver uses when transmitting and receiving data. It can be 250 kbps, 1 Mbps or 2 Mbps. Using lower air data rate gives better receiver sensitivity than higher air data rate. But, high air data rate gives lower average current consumption and reduced probability of on-air collisions. The air data rate is set by the RF_DR bit in the RF_SETUP register. A transmitter and a receiver must be programmed with the same air data rate to communicate with each other. The RF Transceiver is fully compatible with nRF24L01. For compatibility with nRF2401A, nRF2402, nRF24E1, and nRF24E2 the air data rate must be set to 250 kbps or 1 Mbps.

3.3.3

RF channel frequency

The RF channel frequency determines the center of the channel used by the RF Transceiver. The channel occupies a bandwidth of less than 1 MHz at 250kbps and 1Mbps and a bandwidth of less than 2 MHz at 2Mbps. The RF Transceiver can operate on frequencies from 2.400 GHz to 2.525 GHz. The programming resolution of the RF channel frequency setting is 1 MHz. At 2Mbps the channel occupies a bandwidth wider than the resolution of the RF channel frequency setting. To ensure non-overlapping channels in 2Mbps mode, the channel spacing must be 2 MHz or more. At 1Mbps and 250kbps the channel bandwidth is the same or lower than the resolution of the RF frequency. The RF channel frequency is set by the RF_CH register according to the following formula: F0= 2400 + RF_CH MHz You must program a transmitter and a receiver with the same RF channel frequency to communicate with each other.

3.3.4

Received Power Detector measurements

Received Power Detector (RPD), located in register 09, bit 0, triggers at received power levels above -64 dBm that are present in the RF channel you receive on. If the received power is less than -64 dBm, RDP = 0. The RPD can be read out at any time while the RF Transceiver is in receive mode. This offers a snapshot of the current received power level in the channel. The RPD is latched whenever a packet is received or when the MCU sets rfce low. The status of RPD is correct when RX mode is enabled and after a wait time of Tstby2a +Tdelay_AGC= 130us + 40?s. The RX gain varies over temperature which means that the RPD threshold also varies over temperature. The RPD threshold value is reduced by - 5dB at T = -40°C and increased by + 5dB at 85°C.

3.3.5

PA control

The PA (Power Amplifier) control is used to set the output power from the RF Transceiver power amplifier. In TX mode PA control has four programmable steps, see Table 5. on page 22.

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The PA control is set by the RF_PWR bits in the RF_SETUP register. SPI RF-SETUP RF output power (RF_PWR) 11 0dBm 10 -6dBm 01 -12dBm 00 -18dBm DC current consumption 11.1mA 8.8mA 7.3mA 6.8mA

Conditions: VDD = 3.0V, VSS = 0V, TA = 27?C, Load impedance = 15Ω+j88Ω. Table 5. RF output power setting for the RF Transceiver

3.3.6

RX/TX control

The RX/TX control is set by PRIM_RX bit in the CONFIG register and sets the RF Transceiver in transmit/ receive.

3.4

Enhanced ShockBurst?

Enhanced ShockBurst? is a packet based data link layer that features automatic packet assembly and timing, automatic acknowledgement and retransmissions of packets. Enhanced ShockBurst? enables the implementation of ultra low power and high performance communication. The Enhanced ShockBurst? features enable significant improvements of power efficiency for bi-directional and uni-directional systems, without adding complexity on the host controller side.

3.4.1

Features

The main features of Enhanced ShockBurst? are: ? ? ? ? 1 to 32 bytes dynamic payload length Automatic packet handling Auto packet transaction handling X Auto Acknowledgement X Auto retransmit 6 data pipe MultiCeiver? for 1:6 star networks

3.4.2

Enhanced ShockBurst? overview

Enhanced ShockBurst? uses ShockBurst? for automatic packet handling and timing. During transmit, ShockBurst? assembles the packet and clocks the bits in the data packet for transmission. During receive, ShockBurst? constantly searches for a valid address in the demodulated signal. When ShockBurst? finds a valid address, it processes the rest of the packet and validates it by CRC. If the packet is valid the payload is moved into a vacant slot in the RX FIFOs. All high speed bit handling and timing is controlled by ShockBurst?. Enhanced ShockBurst? features automatic packet transaction handling for the easy implementation of a reliable bi-directional data link. An Enhanced ShockBurst? packet transaction is a packet exchange between two transceivers, with one transceiver acting as the Primary Receiver (PRX) and the other transceiver acting as the Primary Transmitter (PTX). An Enhanced ShockBurst? packet transaction is always initiated by a packet transmission from the PTX, the transaction is complete when the PTX has received an

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acknowledgment packet (ACK packet) from the PRX. The PRX can attach user data to the ACK packet enabling a bi-directional data link. The automatic packet transaction handling works as follows: 1. 2. 3. You begin the transaction by transmitting a data packet from the PTX to the PRX. Enhanced ShockBurst? automatically sets the PTX in receive mode to wait for the ACK packet. If the packet is received by the PRX, Enhanced ShockBurst? automatically assembles and transmits an acknowledgment packet (ACK packet) to the PTX before returning to receive mode. If the PTX does not receive the ACK packet immediately, Enhanced ShockBurst? automatically retransmits the original data packet after a programmable delay and sets the PTX in receive mode to wait for the ACK packet.

In Enhanced ShockBurst? it is possible to configure parameters such as the maximum number of retransmits and the delay from one transmission to the next retransmission. All automatic handling is done without the involvement of the MCU.

3.4.3

Enhanced Shockburst? packet format

The format of the Enhanced ShockBurst? packet is described in this section. The Enhanced ShockBurst? packet contains a preamble field, address field, packet control field, payload field and a CRC field. Figure 7. shows the packet format with MSB to the left.

P re a m b le 1 b y te

A d d re s s 3 -5 b y te

P a c k e t C o n tro l F ie ld 9 b it

P a y lo a d 0 - 3 2 b y te

C R C 1 -2 b y te

Figure 7. An Enhanced ShockBurst? packet with payload (0-32 bytes)

3.4.3.1

Preamble

The preamble is a bit sequence used to synchronize the receivers demodulator to the incoming bit stream. The preamble is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilize the receiver.

3.4.3.2

Address

This is the address for the receiver. An address ensures that the correct packet is detected by the receiver. The address field can be configured to be 3, 4 or, 5 bytes long with the AW register. Note: Addresses where the level shifts only one time (that is, 000FFFFFFF) can often be detected in noise and can give a false detection, which may give a raised Packet-Error-Rate. Addresses as a continuation of the preamble (hi-low toggling) raises the Packet-Error-Rate.

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3.4.3.3 Packet Control Field

Figure 8. shows the format of the 9 bit packet control field, MSB to the left.

Payload length 6bit

PID 2bit

NO_ACK 1bit

Figure 8. Packet control field The packet control field contains a 6 bit payload length field, a 2 bit PID (Packet Identity) field and a 1 bit NO_ACK flag. Payload length This 6 bit field specifies the length of the payload in bytes. The length of the payload can be from 0 to 32 bytes. Coding: 000000 = 0 byte (only used in empty ACK packets.) 100000 = 32 byte, 100001 = Don’t care. This field is only used if the Dynamic Payload Length function is enabled. PID (Packet identification) The 2 bit PID field is used to detect if the received packet is new or retransmitted. PID prevents the PRX operation from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI. The PID and CRC fields (see section 3.4.3.5 on page 25) are used by the PRX operation to determine if a packet is retransmitted or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, the RF Transceiver compares the CRC sums from both packets. If the CRC sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. No Acknowledgment flag (NO_ACK) The Selective Auto Acknowledgement feature controls the NO_ACK flag. This flag is only used when the auto acknowledgement feature is used. Setting the flag high, tells the receiver that the packet is not to be auto acknowledged.

3.4.3.4

Payload

The payload is the user defined content of the packet. It can be 0 to 32 bytes wide and is transmitted on-air when it is uploaded (unmodified) to the device. Enhanced ShockBurst? provides two alternatives for handling payload lengths; static and dynamic. The default is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. Static payload length is set by the RX_PW_Px registers on the receiver side. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal the value in the RX_PW_Px register on the receiver side.

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Dynamic Payload Length (DPL) is an alternative to static payload length. DPL enables the transmitter to send packets with variable payload length to the receiver. This means that for a system with different payload lengths it is not necessary to scale the packet length to the longest payload. With the DPL feature the nRF24L01+ can decode the payload length of the received packet automatically instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using the R_RX_PL_WID command. Note: Always check if the packet width reported is 32 bytes or shorter when using the R_RX_PL_WID command. If its width is longer than 32 bytes then the packet contains errors and must be discarded. Discard the packet by using the Flush_RX command. In order to enable DPL the EN_DPL bit in the FEATURE register must be enabled. In RX mode the DYNPD register must be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD set.

3.4.3.5

CRC (Cyclic Redundancy Check)

The CRC is the error detection mechanism in the packet. It may either be 1 or 2 bytes and is calculated over the address, Packet Control Field and Payload. The polynomial for 1 byte CRC is X8 + X2 + X + 1. Initial value 0xFF. The polynomial for 2 byte CRC is X16+ X12 + X5 + 1. Initial value 0xFFFF. No packet is accepted by Enhanced ShockBurst? if the CRC fails.

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3.4.4 Automatic packet assembly

The automatic packet assembly assembles the preamble, address, packet control field, payload and CRC to make a complete packet before it is transmitted.
Start:

Collect Address from TX_ADDR register

TX_ADDR MSB =1

No

Yes Add preamble 0x55 Add preamble 0xAA

EN_DPL=1

Yes PCF[8:3]= #bytes in upper level of TX_FIFO No

New data in TX_FIFO

No

REUSE_TX_PL active Yes Yes PCF[2:1]++ No

SPI TX command

W_TX_PAYLOAD_NOACK

W_TX_PAYLOAD PCF[0]=0 PCF[0]=1

Collect Payload from TX_FIFO

EN_CRC = 1

Yes

CRCO = 1

No

Yes Calculate and add 2 Byte CRC based on Address, PCF and Payload Calculate and add 1 Byte CRC based on Address, PCF and Payload

No

STOP

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Figure 9. Automatic packet assembly

3.4.5

Automatic packet disassembly

After the packet is validated, Enhanced ShockBurst? disassembles the packet and loads the payload into the RX FIFO, and asserts the RX_DR IRQ.
Start

Read Address width from SETUP_AW Monitor SETUP_AW wide window of received bit stream No

Received window = RX_ADDR_Px

Yes PCF = 9 first bits received after valid address

EN_DPL=1 Yes Payload = PCF[8:3] bytes from received bit stream

No No Payload = RX_PW_Px bytes from received bit stream

CRCO = 1 Yes TX_CRC = 2 Bytes from received bit stream

No

TX_CRC = 1 Byte from received bit stream

RX_CRC = 2 Byte CRC calculated from received Address, PCF and Payload

RX_CRC = 1 Byte CRC calculated from received Address, PCF and Payload

TX_CRC = RX_CRC

Yes PCF[2:1] Changed from last packet Yes New packet received

No CRC Changed from last packet No Reject the duplicate received packet

STOP

Figure 10. Automatic packet disassembly

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3.4.6 Automatic packet transaction handling

Enhanced ShockBurst? features two functions for automatic packet transaction handling; auto acknowledgement and auto re-transmit.

3.4.6.1

Auto Acknowledgement

Auto acknowledgment is a function that automatically transmits an ACK packet to the PTX after it has received and validated a packet. The auto acknowledgement function reduces the load of the system MCU and reduces average current consumption. The Auto Acknowledgement feature is enabled by setting the EN_AA register. Note: If the received packet has the NO_ACK flag set, auto acknowledgement is not executed. An ACK packet can contain an optional payload from PRX to PTX. In order to use this feature, the Dynamic Payload Length (DPL) feature must be enabled. The MCU on the PRX side has to upload the payload by clocking it into the TX FIFO by using the W_ACK_PAYLOAD command. The payload is pending in the TX FIFO (PRX) until a new packet is received from the PTX. The RF Transceiver can have three ACK packet payloads pending in the TX FIFO (PRX) at the same time.
RX Pipe address
Address decoder and buffer controller

ACK generator

TX FIFO Payload 3 Payload 2 Payload 1

TX Pipe address

SPI Module

From MCU

Figure 11. TX FIFO (PRX) with pending payloads Figure 11. shows how the TX FIFO (PRX) is operated when handling pending ACK packet payloads. From the MCU the payload is clocked in with the W_ACK_PAYLOAD command. The address decoder and buffer controller ensure that the payload is stored in a vacant slot in the TX FIFO (PRX). When a packet is received, the address decoder and buffer controller are notified with the PTX address. This ensures that the right payload is presented to the ACK generator. If the TX FIFO (PRX) contains more than one payload to a PTX, payloads are handled using the first in – first out principle. The TX FIFO (PRX) is blocked if all pending payloads are addressed to a PTX where the link is lost. In this case, the MCU can flush the TX FIFO (PRX) by using the FLUSH_TX command. In order to enable Auto Acknowledgement with payload the EN_ACK_PAY bit in the FEATURE register must be set.

3.4.6.2

Auto Retransmission (ART)

The auto retransmission is a function that retransmits a packet if an ACK packet is not received. It is used in an auto acknowledgement system on the PTX. When a packet is not acknowledged, you can set the number of times it is allowed to retransmit by setting the ARC bits in the SETUP_RETR register. PTX enters RX mode and waits a time period for an ACK packet each time a packet is transmitted. The amount of time the PTX is in RX mode is based on the following conditions:

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? ? ? Auto Retransmit Delay (ARD) elapsed. No address match within 250?s. After received packet (CRC correct or not) if address match within 250?s.

The RF Transceiver asserts the TX_DS IRQ when the ACK packet is received. The RF Transceiver enters standby-I mode if there is no more untransmitted data in the TX FIFO and the rfce bit in the RFCON register is low. If the ACK packet is not received, the RF Transceiver goes back to TX mode after a delay defined by ARD and retransmits the data. This continues until acknowledgment is received, or the maximum number of retransmits is reached. Two packet loss counters are incremented each time a packet is lost, ARC_CNT and PLOS_CNT in the OBSERVE_TX register. The ARC_CNT counts the number of retransmissions for the current transaction. You reset ARC_CNT by initiating a new transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. You reset PLOS_CNT by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The ARD defines the time from the end of a transmitted packet to when a retransmit starts on the PTX. ARD is set in SETUP_RETR register in steps of 250?s. A retransmit is made if no ACK packet is received by the PTX. There is a restriction on the length of ARD when using ACK packets with payload. The ARD time must never be shorter than the sum of the startup time and the time on-air for the ACK packet. ? ? For 2Mbps data rate and 5-byte address; 15 byte is maximum ACK packet payload length for ARD=250?s (reset value). For 1Mbps data rate and 5-byte address; 5 byte is maximum ACK packet payload length for ARD=250?s (reset value).

ARD=500?s is long enough for any ACK payload length in 1 or 2Mbps mode. ? For 250kbps data rate and 5-byte address the following values apply: ARD 1500?s 1250?s 1000?s 750?s 500?s ACK packet size (in bytes) All ACK payload sizes < 24 < 16 <8 Empty ACK with no payload

Table 6. Maximum ACK payload length for different retransmit delays at 250kbps As an alternative to Auto Retransmit it is possible to manually set the RF Transceiver to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. The MCU must initiate each transmission of the packet with a pulse on the CE pin when this command is used.

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3.4.7 Enhanced ShockBurst flowcharts

This section contains flowcharts outlining PTX and PRX operation in Enhanced ShockBurst?.

3.4.7.1

PTX operation

The flowchart in Figure 12. outlines how a RF Transceiver configured as a PTX behaves after entering standby-I mode.
Start Primary TX

ShockBurst operation Standby-I mode
No

Is rfce=1?

Yes

No

Is rfce =1?

Yes

Standby-II mode

No

Packet in TX FIFO?

Yes No No

Packet in TX FIFO?

Yes

TX Settling

Packet in TX FIFO?

Yes

TX mode Transmit Packet

Yes

Set TX_DS IRQ Is rfce =1?

No

Is Auto ReTransmit enabled?

Yes

Yes

No_ACK?
No

RX Settling RX mode Set MAX_RT IRQ
No

Timeout?

No

Is an ACK received?
Yes

Yes

Standby-II mode
No

Yes

Has the ACK payload?

No

Has ARD elapsed? TX mode Retransmit last packet TX Settling
No

Yes

Put payload in RX FIFO. Set TX_DS IRQ and RX_DR IRQ

Set TX_DS IRQ

Number of retries = ARC?

Yes

Note: ShockBurst? operation is outlined with a dashed square. Figure 12. PTX operations in Enhanced ShockBurst?

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Activate PTX mode by setting the rfce bit in the RFCON register high. If there is a packet present in the TX FIFO the RF Transceiver enters TX mode and transmits the packet. If Auto Retransmit is enabled, the state machine checks if the NO_ACK flag is set. If it is not set, the RF Transceiver enters RX mode to receive an ACK packet. If the received ACK packet is empty, only the TX_DS IRQ is asserted. If the ACK packet contains a payload, both TX_DS IRQ and RX_DR IRQ are asserted simultaneously before the RF Transceiver returns to standby-I mode. If the ACK packet is not received before timeout occurs, the RF Transceiver returns to standby-II mode. It stays in standby-II mode until the ARD has elapsed. If the number of retransmits has not reached the ARC, the RF Transceiver enters TX mode and transmits the last packet once more. While executing the Auto Retransmit feature, the number of retransmits can reach the maximum number defined in ARC. If this happens, the RF Transceiver asserts the MAX_RT IRQ and returns to standby-I mode. If the rfce bit in the RFCON register is high and the TX FIFO is empty, the RF Transceiver enters StandbyII mode.

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3.4.7.2 PRX operation

The flowchart in Figure 13. outlines how a RF Transceiver configured as a PRX behaves after entering standby-I mode.
Start Primary RX

ShockBurst operation

Standby-I mode
No

Is rfce =1?
No Yes

RX Settling RX mode
Yes

Is rfce =1?

RX FIFO Full?
No

Yes

Packet received?
Yes

No

Put payload in RX FIFO and set RX_DR IRQ
No

Is Auto Acknowledgement enabled?

Yes

No

Is the received packet a new packet?

Yes Yes

Discard packet

Put payload in RX FIFO and set RX_DR IRQ

No

Was there payload attached with the last ACK?

Yes

Set TX_DS IRQ

No_ACK set in received packet?

No

No

Pending payload in TX FIFO?

Yes

TX Settling

TX Settling TX mode Transmit ACK with payload

TX mode Transmit ACK

Note: ShockBurst? operation is outlined with a dashed square. Figure 13. PRX operations in Enhanced ShockBurst? Activate PRX mode by setting the rfce bit in the RFCON register high. The RF Transceiver enters RX mode and starts searching for packets. If a packet is received and Auto Acknowledgement is enabled, the RF Transceiver decides if the packet is new or a copy of a previously received packet. If the packet is new

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the payload is made available in the RX FIFO and the RX_DR IRQ is asserted. If the last received packet from the transmitter is acknowledged with an ACK packet with payload, the TX_DS IRQ indicates that the PTX received the ACK packet with payload. If the No_ACK flag is not set in the received packet, the PRX enters TX mode. If there is a pending payload in the TX FIFO it is attached to the ACK packet. After the ACK packet is transmitted, the RF Transceiver returns to RX mode. A copy of a previously received packet might be received if the ACK packet is lost. In this case, the PRX discards the received packet and transmits an ACK packet before it returns to RX mode.

3.4.8

MultiCeiver?

MultiCeiver? is a feature used in RX mode that contains a set of six parallel data pipes with unique addresses. A data pipe is a logical channel in the physical RF channel. Each data pipe has its own physical address (data pipe address) decoding in the RF Transceiver.

PTX3 PTX2
Pipe 4
Pip Data

PTX4 PTX5

Data

Da ta P

Da ta

PTX1

Pi pe

ipe 1

Figure 14. PRX using MultiCeiver? The RF Transceiver configured as PRX (primary receiver) can receive data addressed to six different data pipes in one frequency channel as shown in Figure 14. Each data pipe has its own unique address and can be configured for individual behavior. Up to six RF Transceivers configured as PTX can communicate with one RF Transceiver configured as PRX. All data pipe addresses are searched for simultaneously. Only one data pipe can receive a packet at a time. All data pipes can perform Enhanced ShockBurst? functionality. The following settings are common to all data pipes: ? ? ? ? CRC enabled/disabled (CRC always enabled when Enhanced ShockBurst? is enabled) CRC encoding scheme RX address width Frequency channel

ta Da pe Pi 2

5

PRX

Frequency Channel N

e3

PTX6
ip ta P e0

Da

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nRF24LE1 Product Specification
? ? Air data rate LNA gain

The data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. Each data pipe address is configured in the RX_ADDR_PX registers. Note: Always ensure that none of the data pipes have the same address. Each pipe can have up to a 5 byte configurable address. Data pipe 0 has a unique 5 byte address. Data pipes 1-5 share the four most significant address bytes. The LSByte must be unique for all six pipes. Figure 15. is an example of how data pipes 0-5 are addressed.
Byte 4 Data pipe 0 (RX_ADDR_P0) Data pipe 1 (RX_ADDR_P1) Data pipe 2 (RX_ADDR_P2) Data pipe 3 (RX_ADDR_P3) Data pipe 4 (RX_ADDR_P4) Data pipe 5 (RX_ADDR_P5) 0xE7 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 3 0xD3 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 2 0xF0 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 1 0x35 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 0 0x77 0xC2 0xC3 0xC4 0xC5 0xC6

Figure 15. Addressing data pipes 0-5

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The PRX, using MultiCeiver? and Enhanced ShockBurst?, receives packets from more than one PTX. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. Figure 16. is an example of an address configuration for the PRX and PTX. On the PRX the RX_ADDR_Pn, defined as the pipe address, must be unique. On the PTX the TX_ADDR must be the same as the RX_ADDR_P0 and as the pipe address for the designated pipe.

PTX3

PTX4

PTX2

Data

Pi p

TX _ RX ADDR _A DD : R_ P0 0xB3 :0 xB B4B5 3B 4B B 6CD 5B 6C D

Pipe

TX _ A R X _ D D R: A DD 0x R_ P 0 : 0 B 3 B 4B 5 x B3 B4 B B 6 F 1 5B 6 F1

Da ta

Da ta

PTX1

e

5

TX RX _AD _A DR DD : R_ P0 0x :0 B3 xB B4 3B B5 4B B6 5B 0F 60 F

4

Figure 16. Example of data pipe addressing in MultiCeiver? Only when a data pipe receives a complete packet can other data pipes begin to receive data. When multiple PTXs are transmitting to a PRX, the ARD can be used to skew the auto retransmission so that they only block each other once.

A3 B6 3 B5 B4 5B6A B3 0x 3B4B B 0x R: DD _P0: _A TX ADDR _ RX

05 B6 5 B5 60 B4 B 5B 3 4 B 0 x B3B 0x R: P0: D _ D _A DR TX _AD RX

PTX5

Data

ta Da pe Pi 2
Pip e1
Data Data Data Data Data Data Pipe Pipe Pipe Pipe Pipe Pipe 0 1 2 3 4 5

Pipe 3

PTX6

D at

aP

0 ipe
R: 0 P ADD TX_ AD DR_ RX _

878 787 87 8 7 878 0x7 87878 7 :0x

PRX

Addr Addr Addr Addr Addr Addr

(RX_ADDR_P0): (RX_ADDR_P1): (RX_ADDR_P2): (RX_ADDR_P3): (RX_ADDR_P4): (RX_ADDR_P5):

0x7878787878 0xB3B4B5B6F1 0xB3B4B5B6CD 0xB3B4B5B6A3 0xB3B4B5B60F 0xB3B4B5B605

Frequency Channel N

3.4.9

Enhanced ShockBurst? timing

This section describes the timing sequence of Enhanced ShockBurst? and how all modes are initiated and operated. The Enhanced ShockBurst? timing is controlled through the Data and Control interface. The RF Transceiver can be set to static modes or autonomous modes where the internal state machine

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nRF24LE1 Product Specification
controls the events. Each autonomous mode/sequence ends with a RFIRQ interrupt. All the interrupts are indicated as IRQ events in the timing diagrams.
>10 ?s TIRQ TUL PTX SPI UL Tstdby2a TOA
IRQ: TX DS1

PTX CE

PTX IRQ

PTX MODE

Standby-I

PLL Lock

TX

Standby-I

1 IRQ if No Ack is on. TIRQ = 8.2 ?s @ 1 Mbps, TIRQ = 6.0 ?s @ 2 Mbps, Tstdby2a = 130 ?s

Figure 17. Transmitting one packet with NO_ACK on The following equations calculate various timing measurements: Symbol TOA Description Time on-air
TOA

Equation
? ? ?? 8?bit ?1[byte]+ 3,4 or 5 [bytes ]+ N [bytes ]+ 1 or 2 [bytes ]? + ? ? byte ? ? ? preamble packet length address payload CRC ? = = air data rate air data rate bit s 9 [bit ]
packet control field

[ ]
[ ]

TACK

Time on-air Ack
T ACK = ? ? ?? 8?bit ?1[byte]+ 3,4 or 5 [bytes]+ N [bytes ]+ 1 or 2 [bytes ]? + ? byte? ? ? preamble ? packet length address payload CRC ? = air data rate air data rate bit s 9 [bit ]
packet control field

TUL

Time Upload
TU L = ? ? N [bytes ] 8 ? bit ? byte ? payload length ? ? payload = SPI data rate SPI data rate bit s

[ ]

TESB

Time Enhanced Shock- TESB = TUL + 2 . Tstby2a + TOA + TACK + TIRQ Burst? cycle Table 7. Timing equations

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nRF24LE1 Product Specification

TESB Cycle >10us TIRQ

TUL PTX SPI UL

130us

TOA

IRQ: TX DS

PTX rfce PTX IRQ

PTX MODE

Standby 1

PLL Lock

TX

PLL Lock

RX

Standby 1

PRX MODE

Standby 1

PLL Lock

RX

PLL Lock

TX

PLL Lock

RX

PRX IRQ

PRX rfce

PRX SPI 130us TIRQ

IRQ:RX DR/DL 130us TACK 130us

Figure 18. Timing of Enhanced ShockBurst? for one packet upload (2 Mbps) In Figure 18. the transmission and acknowledgement of a packet is shown. The PRX operation activates RX mode (rfce=1), and the PTX operation is activated in TX mode (rfce=1 for minimum 10?s). After 130?s the transmission starts and finishes after the elapse of TOA. When the transmission ends the PTX operation automatically switches to RX mode to wait for the ACK packet from the PRX operation. When the PRX operation receives the packet it sets the interrupt for the host MCU and switches to TX mode to send an ACK. After the PTX operation receives the ACK packet it sets the interrupt to the MCU and clears the packet from the TX FIFO.

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nRF24LE1 Product Specification
In Figure 19. the PTX timing of a packet transmission is shown when the first ACK packet is lost. To see the complete transmission when the ACK packet fails see Figure 22. on page 40.

>10us 250us max

ARD TOA 130us

TUL PTX SPI UL

130us

130us

PTX CE

PTX IRQ

PTX MODE

Standby I

PLL Lock

TX

PLL Lock

RX

Standby II

PLL Lock

TX

Figure 19. Timing of Enhanced ShockBurst? when the first ACK packet is lost (2Mbps)

3.4.10

Enhanced ShockBurst? transaction diagram

This section describes several scenarios for the Enhanced ShockBurst? automatic transaction handling. The call outs in this section’s figures indicate the IRQs and other events. For MCU activity the event may be placed at a different timeframe. Note: The figures in this section indicate the earliest possible download (DL) of the packet to the MCU and the latest possible upload (UL) of payload to the transmitter.

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nRF24LE1 Product Specification
3.4.10.1 Single transaction with ACK packet and interrupts

In Figure 20. the basic auto acknowledgement is shown. After the packet is transmitted by the PTX and received by the PRX the ACK packet is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas the TX_DS IRQ is asserted when the packet is acknowledged and the ACK packet is received by the PTX.

MCU PTX

UL

IRQ

Ack received IRQ:TX DS (PID=1)

130us1

PTX

TX:PID=1

RX

PRX

RX

ACK:PID=1

Packet received IRQ: RX DR (PID=1)

MCU PRX
1 Radio Turn Around Delay

DL

Figure 20. TX/RX cycles with ACK and the according interrupts

3.4.10.2

Single transaction with a lost packet

Figure 21. is a scenario where a retransmission is needed due to loss of the first packet transmit. After the packet is transmitted, the PTX enters RX mode to receive the ACK packet. After the first transmission, the PTX waits a specified time for the ACK packet, if it is not in the specific time slot the PTX retransmits the packet as shown in Figure 21.
MCU PTX
UL IRQ

Packet PID=1 lost during transmission

No address detected. RX off to save current

Auto retransmit delay elapsed

Retransmit of packet PID=1

ACK received IRQ: TX DS (PID=1)

130us1

130us1
RX TX:PID=1

130us1
RX

PTX

TX:PID=1

ARD

PRX

RX

ACK:PID=1

Packet received. IRQ: RX DR (PID=1)

MCU PRX
1 Radio Turn Around Delay

DL

Figure 21. TX/RX cycles with ACK and the according interrupts when the first packet transmit fails

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nRF24LE1 Product Specification
When an address is detected the PTX stays in RX mode until the packet is received. When the retransmitted packet is received by the PRX (see Figure 21. on page 39), the RX_DR IRQ is asserted and an ACK is transmitted back to the PTX. When the ACK is received by the PTX, the TX_DS IRQ is asserted.

3.4.10.3

Single transaction with a lost ACK packet

Figure 22. is a scenario where a retransmission is needed after a loss of the ACK packet. The corresponding interrupts are also indicated.
MCU PTX
UL No address detected. RX off to save current Auto retransmit delay elapsed
1

IRQ Retransmit of packet PID=1
1

ACK received IRQ: TX DS (PID=1)

130us

130us
RX

130us1
TX:PID=1 RX

PTX

TX:PID=1

ARD

PRX

RX

ACK:PID=1

RX

ACK:PID=1

Packet received. IRQ: RX DR (PID=1)

ACK PID=1 lost during transmission DL

Packet detected as copy of previous, discarded

MCU PRX

1 Radio Turn Around Delay

Figure 22. TX/RX cycles with ACK and the according interrupts when the ACK packet fails

3.4.10.4

Single transaction with ACK payload packet

Figure 23. is a scenario of the basic auto acknowledgement with payload. After the packet is transmitted by the PTX and received by the PRX the ACK packet with payload is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas on the PTX side the TX_DS IRQ is asserted when the ACK packet is received by the PTX. On the PRX side, the TX_DS IRQ for the ACK packet payload is asserted after a new packet from PTX is received. The position of the IRQ in Figure 23. shows where the MCU can respond to the interrupt.
MCU PTX
UL1 UL2 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) DL IRQ Transmit of packet PID=2

130us1

≥130us3
RX TX:PID=2

PTX

TX:PID=1

PRX

RX

ACK1 PAY

RX

Packet received. IRQ: RX DR (PID=1)

Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) DL DL IRQ

MCU PRX

UL2

1 Radio Turn Around Delay 2 Uploading Payload for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us

Figure 23. TX/RX cycles with ACK Payload and the according interrupts

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nRF24LE1 Product Specification
3.4.10.5 Single transaction with ACK payload packet and lost packet

Figure 24. is a scenario where the first packet is lost and a retransmission is needed before the RX_DR IRQ on the PRX side is asserted. For the PTX both the TX_DS and RX_DR IRQ are asserted after the ACK packet is received. After the second packet (PID=2) is received on the PRX side both the RX_DR (PID=2) and TX_DS (ACK packet payload) IRQ are asserted.

MCU PTX

UL1

UL2

DL IRQ Auto retransmit delay elapsed Retransmit of packet PID=1 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY)

Packet PID=1 lost during transmission

No address detected. RX off to save current

130us1

130us1
RX TX:PID=1

130us1
RX

≥130us3
TX:PID=2

PTX

TX:PID=1

ARD

PRX

RX

ACK1 PAY

RX

Packet received. IRQ: RX DR (PID=1)

Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) DL DL

MCU PRX

UL 2

1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us

Figure 24. TX/RX cycles and the according interrupts when the packet transmission fails

3.4.10.6
MCU PTX
UL1

Two transactions with ACK payload packet and the first ACK packet lost
UL2 UL3 DL IRQ ACK received IRQ: TX DS (PID=2) RX DR (ACK2PAY)
3

No address detected. RX off to save current

Auto retransmit delay elapsed
1

Retransmit of packet PID=1
1

ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY)

130us

130us
RX

130us
TX:PID=1

1

≥ 130us
RX

130us 1
TX:PID=2 RX

≥130us3
TX:PID=3

PTX

TX:PID=1

ARD

PRX

RX

ACK1 PAY

RX

ACK1 PAY

RX

ACK2 PAY

RX

Packet received. IRQ: RX DR (PID=1)

ACK PID=1 lost during transmission DL UL2 2

Packet detected as copy of previous, discarded

Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) DL IRQ

Packet received. IRQ: RX DR (PID=3) TX DS (ACK2PAY)

MCU PRX

UL12

1 Radio Turn Around Delay 2 Uploading Payload for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us

Figure 25. TX/RX cycles with ACK Payload and the according interrupts when the ACK packet fails In Figure 25. the ACK packet is lost and a retransmission is needed before the TX_DS IRQ is asserted, but the RX_DR IRQ is asserted immediately. The retransmission of the packet (PID=1) results in a discarded packet. For the PTX both the TX_DS and RX_DR IRQ are asserted after the second transmission of ACK, which is received. After the second packet (PID=2) is received on the PRX both the RX_DR (PID=2) and TX_DS (ACK1PAY) IRQ is asserted. The callouts explains the different events and interrupts.

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nRF24LE1 Product Specification
3.4.10.7 Two transactions where max retransmissions is reached
UL IRQ

MCU PTX

No address detected. RX off to save current

Auto retransmit delay elapsed
1

Retransmit of packet PID=1
1

No address detected. RX off to save current

No address detected. RX off to save current

IRQ:MAX_RT

130 ?s
IRQ

130 ?s

130 ?s

1

≥130 ?s
RX

3

130 ?s
TX:PID=1

1

PTX

TX:PID=1

RX

TX:PID=1

RX

ARD

ARD

ARD 130 ?s1

PRX
Packet received. IRQ: RX DR (PID=1)

RX

ACK1 PAY

RX

ACK1 PAY

RX

ACK PID=1 lost during transmission DL

ACK PID=1 lost during transmission

Packet detected as copy of previous, discarded

ACK PID=1 lost during transmission

MCU PRX

UL2

1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130 ?s

Figure 26. TX/RX cycles with ACK Payload and the according interrupts when the transmission fails. ARC is set to 2. MAX_RT IRQ is asserted if the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC). In Figure 26. the packet transmission ends with a MAX_RT IRQ. The payload in TX FIFO is NOT removed and the MCU decides the next step in the protocol. A toggle of the rfce bit in the RFCON register starts a new transmitting sequence of the same packet. The payload can be removed from the TX FIFO using the FLUSH_TX command.

3.4.11

Compatibility with ShockBurst?

You must disable Enhanced ShockBurst? for backward compatibility with the nRF2401A, nRF2402, nRF24E1 and, nRF24E2. Set the register EN_AA = 0x00 and ARC = 0 to disable Enhanced ShockBurst?. In addition, the RF Transceiver air data rate must be set to 1Mbps or 250kbps.

3.4.11.1

ShockBurst? packet format

The ShockBurst? packet format is described in this chapter. Figure 27. shows the packet format with MSB to the left.
CRC 1-2 byte

Preamble 1 byte

Address 3-5 byte

Payload 1 - 32 byte

Figure 27. A ShockBurst? packet compatible with nRF2401/nRF2402/nRF24E1/nRF24E2 devices. The ShockBurst? packet format has a preamble, address, payload and CRC field that are the same as the Enhanced ShockBurst? packet format described in section 3.4.3 on page 23. The differences between the ShockBurst? packet and the Enhanced ShockBurst? packet are: ? The 9 bit Packet Control Field is not present in the ShockBurst? packet format.

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nRF24LE1 Product Specification
? The CRC is optional in the ShockBurst? packet format and is controlled by the EN_CRC bit in the CONFIG register.

3.5

Data and control interface

The data and control interface gives you access to all the features in the RF Transceiver. Compared to the standalone component SFR registers are used instead of port pins. Otherwise the interface is identical to the standalone nRF24L01+ chip.

3.5.1

SFR registers
Bit Reset value 6:0 0x01 3:0 3 2 0x0F 1 1 Type Description

Address Name/Mnemonic (Hex) 0xE4 SPIRCON0 0xE5 SPIRCON1 maskIrqRxFifoFull maskIrqRxDataReady

maskIrqTxFifoEmpty maskIrqTxFifoReady

1 0

1 1

0xE6

spiMasterStatus SPIRSTAT rxFifoFull

3:0

0x03

R/W SPI Master configuration register 0. Reserved. Do not alter. R/W SPI Master configuration register 1. R/W 1: Disable interrupt when RX FIFO is full. 0: Enable interrupt when RX FIFO is full. R/W 1: Disable interrupt when data is available in RX FIFO. 0: Enable interrupt when data is available in RX FIFO. R/W 1: Disable interrupt when TX FIFO is empty. 0: Enable interrupt when TX FIFO is empty. R/W 1: Disable interrupt when a location is available in TX FIFO. 0: Enable interrupt when a location is available in TX FIFO. R SPI Master status register.

3

0

rxDataReady

2

0

txFifoEmpty

1

1

txFifoReady

0

1

0xE7

SPIRDAT

7:0

0x00

Interrupt source. 1: RX FIFO full. 0: RX FIFO can accept more data from SPI. Cleared when the cause is removed. R Interrupt source. 1: Data available in RX FIFO. 0: No data in RX FIFO. Cleared when the cause is removed. R Interrupt source. 1: TX FIFO empty. 0: Data in TX FIFO. Cleared when the cause is removed. R Interrupt source. 1: Location available in TX FIFO. 0: TX FIFO full. Cleared when the cause is removed. R/W SPI Master data register. Accesses TX (write) and RX (read) FIFO buffers, both two bytes deep.

R

Table 8. RF Transceiver SPI master registers

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nRF24LE1 Product Specification
The RF Transceiver SPI Master is configured through SPIRCON1. Four different sources can generate interrupt, unless they are masked by their respective bits in SPIRCON1. SPIRSTAT reveals which sources that are active. SPIRDAT accesses both the TX (write) and the RX (read) FIFOs, which are two bytes deep. The FIFOs are dynamic and can be refilled according to the state of the status flags: “FIFO ready” means that the FIFO can accept data. “Data ready” means that the FIFO can provide data, minimum one byte. Addr 0xE8 Bit 7:3 2 1 0 Name rfcken rfcsn rfce R/W RW RW RW Function Reserved RF Clock Enable (16 MHz) Enable RF command. 0: enabled Enable RF Transceiver. 1: enabled Table 9. RFCON register RFCON controls the RF Transceiver SPI Slave chip select signal (CSN), the RF Transceiver chip enable signal (CE) and the RF Transceiver clock enable signal (CKEN).

3.5.2

SPI operation

This section describes the SPI commands and timing.

3.5.2.1

SPI commands

The SPI commands are shown in Table 10. on page 45 Every new command must be started by writing 0 to rfcsn in the RFCON register. The SPI command is transferred to RF Transceiver by writing the command to the SPIRDAT register. After the first transfer the RF Transceiver's STATUS register can be read from SPIRDAT when the transfer is completed. The serial shifting SPI commands is in the following format: <Command word: MSBit to LSBit (one byte)> <Data bytes: LSByte to MSByte, MSBit in each byte first> .

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nRF24LE1 Product Specification
Command name R_REGISTER W_REGISTER Command # Data bytes word (binary) 000A AAAA 1 to 5 LSByte first 001A AAAA 1 to 5 LSByte first 0110 0001 1010 0000 1110 0001 1110 0010 1 to 32 LSByte first 1 to 32 LSByte first 0 0 Operation Read command and status registers. AAAAA = 5 bit Register Map Address Write command and status registers. AAAAA = 5 bit Register Map Address Executable in power down or standby modes only. Read RX-payload: 1 – 32 bytes. A read operation always starts at byte 0. Payload is deleted from FIFO after it is read. Used in RX mode. Write TX-payload: 1 – 32 bytes. A write operation always starts at byte 0 used in TX payload. Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. Used for a PTX operation Reuse last transmitted payload. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission. Read RX payload width for the top R_RX_PAYLOAD in the RX FIFO. Note: Flush RX FIFO if the read value is larger than 32 bytes. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled using first in - first out principle. Write payload: 1– 32 bytes. A write operation always starts at byte 0. Used in TX mode. Disables AUTOACK on this specific packet. No Operation. Might be used to read the STATUS register

R_RX_PAYLOAD

W_TX_PAYLOAD FLUSH_TX FLUSH_RX

REUSE_TX_PL

1110 0011

0

R_RX_PL_WIDa

0110 0000

1

W_ACK_PAYLOADa

1010 1PPP

1 to 32 LSByte first

W_TX_PAYLOAD_NO ACKa NOP

1011 0000 1111 1111

1 to 32 LSByte first 0

a. The bits in the FEATURE register shown in Table 11. on page 53 have to be set.

Table 10. Command set for the RF Transceiver SPI The W_REGISTER and R_REGISTER commands operate on single or multi-byte registers. When accessing multi-byte registers read or write to the MSBit of LSByte first. You can terminate the writing before all bytes in a multi-byte register are written, leaving the unwritten MSByte(s) unchanged. For example, the LSByte of RX_ADDR_P0 can be modified by writing only one byte to the RX_ADDR_P0 register. The content of the status register is always read to MISO after a high to low transition on CSN.

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nRF24LE1 Product Specification
Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low transition. The pipe information is unreliable if the STATUS register is read during an RFIRQ high to low transition.

3.5.3

Data FIFO

The data FIFOs store transmitted payloads (TX FIFO) or received payloads that are ready to be clocked out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode. The following FIFOs are present in the RF Transceiver: ? ? TX three level, 32 byte FIFO RX three level, 32 byte FIFO

Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payloads for ACK packets to three different PTX operations. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO using the FLUSH_TX command. The RX FIFO in PRX can contain payloads from up to three different PTX operations and a TX FIFO in PTX can have up to three payloads stored. You can write to the TX FIFO using these three commands; W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands provide access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in PTX and PRX mode. This command provides access to the RX_PLD register. The payload in TX FIFO in a PTX is not removed if the MAX_RT IRQ is asserted.
RX FIFO 32 byte Data 32 byte 32 byte Data

RX FIFO Controller TX FIFO Controller

Control SPI command decoder Control

TX FIFO Data 32 byte 32 byte 32 byte Data

Figure 28. FIFO (RX and TX) block diagram You can read if the TX and RX FIFO are full or empty in the FIFO_STATUS register. TX_REUSE (also available in the FIFO_STATUS register) is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX.

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SPI

nRF24LE1 Product Specification
3.5.4 Interrupt

The RF Transceiver can send interrupts to the MCU. The interrupt (RFIRQ) is activated when TX_DS, RX_DR or MAX_RT are set high by the state machine in the STATUS register. RFIRQ is deactivated when the MCU writes '1' to the interrupt source bit in the STATUS register. The interrupt mask in the CONFIG register is used to select the IRQ sources that are allowed to activate RFIRQ. By setting one of the mask bits high, the corresponding interrupt source is disabled. By default all interrupt sources are enabled. Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low transition. The pipe information is unreliable if the STATUS register is read during a RFIRQ high to low transition.

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nRF24LE1 Product Specification 3.6 Register map

You can configure and control the radio (using read and write commands) by accessing the register map through the SPI.

3.6.1

Register map table

All undefined bits in the table below are redundant. They are read out as '0'. Note: Addresses 18 to 1B are reserved for test purposes, altering them makes the chip malfunction. Address (Hex) 00 Mnemonic CONFIG Reserved MASK_RX_DR Bit Reset Value Type Description

7 6

0 0

MASK_TX_DS

5

0

MASK_MAX_RT

4

0

EN_CRC CRCO

3 2

1 0

PWR_UP PRIM_RX

1 0

0 0

Configuration Register R/W Only '0' allowed R/W Mask interrupt caused by RX_DR 1: Interrupt not reflected on the RFIRQ 0: Reflect RX_DR as active low on RFIRQ R/W Mask interrupt caused by TX_DS 1: Interrupt not reflected on the RFIRQ 0: Reflect TX_DS as active low interrupt on RFIRQ R/W Mask interrupt caused by MAX_RT 1: Interrupt not reflected on RFIRQ 0: Reflect MAX_RT as active low on RFIRQ R/W Enable CRC. Forced high if one of the bits in the EN_AA is high R/W CRC encoding scheme '0' - 1 byte '1' – 2 bytes R/W 1: POWER UP, 0:POWER DOWN R/W RX/TX control 1: PRX, 0: PTX Enable ‘Auto Acknowledgment’ Function Disable this functionality to be compatible with nRF2401.

01

EN_AA Enhanced ShockBurst? Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 EN_RXADDR Reserved ERX_P5 ERX_P4 ERX_P3 ERX_P2 ERX_P1 ERX_P0

7:6 5 4 3 2 1 0 7:6 5 4 3 2 1 0

00 1 1 1 1 1 1 00 0 0 0 0 1 1

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Only '00' allowed Enable auto acknowledgement data pipe 5 Enable auto acknowledgement data pipe 4 Enable auto acknowledgement data pipe 3 Enable auto acknowledgement data pipe 2 Enable auto acknowledgement data pipe 1 Enable auto acknowledgement data pipe 0 Enabled RX Addresses Only '00' allowed Enable data pipe 5. Enable data pipe 4. Enable data pipe 3. Enable data pipe 2. Enable data pipe 1. Enable data pipe 0.

02

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nRF24LE1 Product Specification
Address (Hex) 03 Mnemonic SETUP_AW Reserved AW 7:2 1:0 000000 11 Bit Reset Value Type Description

Setup of Address Widths (common for all data pipes) R/W Only '000000' allowed R/W RX/TX Address field width '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' – 5 bytes LSByte is used if address width is below 5 bytes Setup of Automatic Retransmission R/W Auto Retransmit Delay ‘0000’ – Wait 250?s ‘0001’ – Wait 500?s ‘0010’ – Wait 750?s …….. ‘1111’ – Wait 4000?s (Delay defined from end of transmission to start of next transmission)b R/W Auto Retransmit Count ‘0000’ –Re-Transmit disabled ‘0001’ – Up to 1 Re-Transmit on fail of AA …… ‘1111’ – Up to 15 Re-Transmit on fail of AA RF Channel R/W Only '0' allowed R/W Sets the frequency channel the RF Transceiver operates on RF Setup Register R/W Enables continuous carrier transmit when high. R/W Only '0' allowed R/W Set RF Data Rate to 250kbps. See RF_DR_HIGH for encoding. R/W Force PLL lock signal. Only used in test R/W Select between the high speed data rates. This bit is don’t care if RF_DR_LOW is set. Encoding: RF_DR_LOW, RF_DR_HIGH: ‘00’ – 1Mbps ‘01’ – 2Mbps ‘10’ – 250kbps ‘11’ – Reserved R/W Set RF output power in TX mode '00' – -18dBm '01' – -12dBm '10' – -6dBm '11' – 0dBm

04

SETUP_RETR ARDa

7:4

0000

ARC

3:0

0011

05

RF_CH Reserved RF_CH

7 6:0

0 0000010

06

RF_SETUP CONT_WAVE Reserved RF_DR_LOW PLL_LOCK RF_DR_HIGH

7 6 5 4 3

0 0 0 0 1

RF_PWR

2:1

11

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nRF24LE1 Product Specification
Address (Hex) Mnemonic Obsolete 07 STATUS Bit 0 Reset Value Type Don’t care Status Register (In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) Only '0' allowed Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFOc. Write 1 to clear bit. Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. Maximum number of TX retransmits interrupt Write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable further communication. Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. Transmit observe register Count lost packets. The counter is overflow protected to 15, and discontinues at max until reset. The counter is reset by writing to RF_CH. Count retransmitted packets. The counter is reset when transmission of a new packet starts. Description

Reserved RX_DR

7 6

0 0

R/W R/W

TX_DS

5

0

R/W

MAX_RT

4

0

R/W

RX_P_NO

3:1

111

R

TX_FULL

0

0

R

08

OBSERVE_TX PLOS_CNT

7:4 3:0

0 0

R R

ARC_CNT

09

RPD Reserved RPD

7:1 0

000000 0

R R

Received Power Detector. This register is called CD (Carrier Detect) in the nRF24L01. The name is different in the RF Transceiver due to the different input power level threshold for this bit. See section 3.3.4 on page 21.

0A 0B 0C 0D

RX_ADDR_P0

39:0 39:0 7:0 7:0

RX_ADDR_P1

RX_ADDR_P2 RX_ADDR_P3

R/W Receive address data pipe 0. 5 Bytes maximum length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) 0xC2C2C R/W Receive address data pipe 1. 5 Bytes maximum 2C2C2 length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) 0xC3 R/W Receive address data pipe 2. Only LSB. MSBytes are equal to RX_ADDR_P1 39:8 0xC4 R/W Receive address data pipe 3. Only LSB. MSBytes are equal to RX_ADDR_P139:8

0xE7E7E 7E7E7

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nRF24LE1 Product Specification
Address (Hex) 0E 0F 10 Mnemonic RX_ADDR_P4 RX_ADDR_P5 Bit 7:0 7:0 39:0 Reset Value 0xC5 0xC6 0xE7E7E 7E7E7 Type Description

R/W Receive address data pipe 4. Only LSB. MSBytes are equal to RX_ADDR_P[139:8] R/W Receive address data pipe 5. Only LSB. MSBytes are equal to RX_ADDR_P[139:8] R/W Transmit address. Used for a PTX operation only. (LSByte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX operation with Enhanced ShockBurst? enabled. R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed

TX_ADDR

11

RX_PW_P0 Reserved RX_PW_P0

7:6 5:0

00 0

12

RX_PW_P1 Reserved RX_PW_P1

7:6 5:0

00 0

13

RX_PW_P2 Reserved RX_PW_P2

7:6 5:0

00 0

14

RX_PW_P3 Reserved RX_PW_P3

7:6 5:0

00 0

15

RX_PW_P4 Reserved

7:6

00

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nRF24LE1 Product Specification
Address (Hex) Mnemonic RX_PW_P4 Bit 5:0 Reset Value 0 Type Description

R/W Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes FIFO Status Register R/W Only '0' allowed R Used for a PTX operation Pulse the rfce high for at least 10?s to Reuse last transmitted payload. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX R TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. R TX FIFO empty flag. 1: TX FIFO empty. 0: Data in TX FIFO. R/W Only '00' allowed R RX FIFO full flag. 1: RX FIFO full. 0: Available locations in RX FIFO. R RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. W Written by separate SPI command ACK packet payload to data pipe number PPP given in SPI command. Used in RX mode only. Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled first in first out. W Written by separate SPI command TX data payload register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only.

16

RX_PW_P5 Reserved RX_PW_P5

7:6 5:0

00 0

17

FIFO_STATUS Reserved TX_REUSE

7 6

0 0

TX_FULL TX_EMPTY

5 4

0 1

Reserved RX_FULL

3:2 1

00 0

RX_EMPTY

0

1

N/A

ACK_PLD

255:0

X

N/A

TX_PLD

255:0

X

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nRF24LE1 Product Specification
Address (Hex) N/A Mnemonic RX_PLD Bit 255:0 Reset Value X Type R Description Read by separate SPI command. RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX channels share the same FIFO.

1C

DYNPD Reserved DPL_P5 DPL_P4 DPL_P3 DPL_P2 DPL_P1 DPL_P0

7:6 5 4 3 2 1 0

0 0 0 0 0 0 0

Enable dynamic payload length R/W Only ‘00’ allowed R/W Enable dynamic payload length data pipe 5. (Requires EN_DPL and ENAA_P5) R/W Enable dynamic payload length data pipe 4. (Requires EN_DPL and ENAA_P4) R/W Enable dynamic payload length data pipe 3. (Requires EN_DPL and ENAA_P3) R/W Enable dynamic payload length data pipe 2. (Requires EN_DPL and ENAA_P2) R/W Enable dynamic payload length data pipe 1. (Requires EN_DPL and ENAA_P1) R/W Enable dynamic payload length data pipe 0. (Requires EN_DPL and ENAA_P0) R/W R/W R/W R/W R/W Feature Register Only ‘00000’ allowed Enables Dynamic Payload Length Enables Payload with ACK Enables the W_TX_PAYLOAD_NOACK command

1D

FEATURE Reserved EN_DPL EN_ACK_PAYd EN_DYN_ACK

7:3 2 1 0

0 0 0 0

a. Please take care when setting this parameter. If the ACK payload is more than 15 byte in 2 Mbps mode the ARD must be 500 ?s or more, if the ACK payload is more than 5 byte in 1Mbps mode the ARD must be 500 ?s or more. In 250 kbps mode (even when the payload is not in ACK) the ARD must be 500?s or more. b. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode for a minimum of 250 ?s, but it stays in RX mode to the end of the packet if that is longer than 250 ?s. Then it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and then retransmits the packet. c. The RX_DR IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt should be: 1) read payload through SPI, 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from step 1). d. If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Payload Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive the ACK packets with payloads. If the ACK payload is more than 15 byte in 2 Mbps mode the ARD must be 500 ?s or more, and if the ACK payload is more than 5 byte in 1 Mbps mode the ARD must be 500 ?s or more. In 250 kbps mode (even when the payload is not in ACK) the ARD must be 500 ?s or more.

Table 11. Register map of the RF Transceiver

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nRF24LE1 Product Specification 4 MCU

The nRF24LE1 contains a fast 8-bit MCU, which executes the normal 8051 instruction set. The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Most of the one-byte instructions are performed in a single cycle. The MCU uses one clock per cycle. This leads to a performance improvement rate of 8.0 (in terms of MIPS) with respect to legacy 8051 devices. The original 8051 had a 12 clock architecture. A machine cycle needed 12 clocks and most instructions were either one or two machine cycles. Except for MUL and DIV instructions, the 8051 used either 12 or 24 clocks for each instruction. Each cycle in the 8051 also used two memory fetches. In many cases, the second fetch was a dummy, and extra clocks were wasted. Table 12. shows the speed advantage compared to a legacy 8051. A speed advantage of 12 implies that the instruction is executed twelve times faster. The average speed advantage is 8.0. However, the real speed improvement seen in any system depends on the instruction mix. Speed advantage 24 12 9.6 8 6 4.8 4 3 Average: 8.0 Number of instructions 1 27 2 16 44 1 18 2 Sum: 111 Number of opcodes 1 83 2 38 89 2 31 9 Sum: 255

Table 12. Speed advantage summary

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nRF24LE1 Product Specification 4.1 Block diagram
Memory control
Internal Flash and RAM PC DPTR DPTR1 DPS

Timer 0 and 1
TL0 TL1 TH0 TH1 TCON TMOD Timer inputs

Timer 2
Memory/SFR Interface

T2CON TH2

RAM/SFR control
SP

TL2

CRCL CRCH CCL1 CCH1 CCL2 CCH2 CCL3 CCH3

ALU
ACC B PSW

ISR

IP0 IEN0

IP1 IEN1

Interrupt inputs

MDU
MD0 MD2 MD4 ARCON

SERIAL 0 S0CON

S0BUF

MD1 MD3 MD5

Serial 0 Interface
Port Port Port Port 0 1 2 3

GPIO

P0, P1, P2, P3

Figure 29. MCU block diagram

4.2
? ?

Features
Control Unit X 8-bit instruction decoder X Reduced instruction cycle time (up to 12 times in respect to standard 80C51) Arithmetic-Logic Unit X 8-bit arithmetic and logical operations X Boolean manipulations X 8 x 8 bit multiplication and 8 / 8 bit division Multiplication-Division Unit X 16 x 16 bit multiplication X 32 / 16 bit and 16 / 16 bit division X 32-bit normalization X 32-bit L/R shifting Three 16-bit Timers/Counters X 80C51-like Timer 0 & 1 X 80515-like Timer 2 Compare/Capture Unit, dedicated to Timer 2 X Software control capture Full Duplex Serial Interfaces X Serial 0 (80C51-like) X Synchronous mode, fixed baud rate

?

? ? ?

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nRF24LE1 Product Specification
8-bit UART mode, variable baud rate 9-bit UART mode, fixed baud rate X 9-bit UART mode, variable baud rate X Baud Rate Generator Interrupt Controller X Four Priority Levels with 13 interrupt sources Memory interface X 16-bit address bus X Dual Data Pointer for fast data block transfer Hardware support for software debug
X X

? ? ?

4.3
4.3.1

Functional description
Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit (ALU) provides 8-bit division, 8-bit multiplication, and 8-bit addition with or without carry. The ALU also provides 8-bit subtraction with borrow and some bitwise logic operations, that is, logical AND, OR, Exclusive OR or NOT. All operations are unsigned integer operations. Additionally, the ALU can increment or decrement 8-bit registers. For accumulator only, it can rotate left or right through carry or not, swap nibbles, clear or complement bits and perform a decimal adjustment. The ALU is handled by three registers, which are memory mapped as special function registers. Operands for operations may come from accumulator ACC, register B or from outside of the unit. The result may be stored in accumulator ACC or may be driven outside of the unit. The control register, that contains flags such as carry, overflow or parity, is the PSW (Program Status Word) register. The nRF24LE1 also contains an on-chip co-processor MDU (Multiplication Division Unit). This unit enables 32-bit division, 16-bit multiplication, shift and normalize operations, see chapter 14 on page 124 for details.

4.3.2

Instruction set summary

All instructions are binary code compatible and perform the same functions as they do within the legacy 8051 processor. The following tables give a summary of the instruction set with the required corresponding clock cycles. Description Add register to accumulator Add directly addressed data to accumulator Add indirectly addressed data to accumulator Add immediate data to accumulator Add register to accumulator with carry Add directly addressed data to accumulator with carry Add indirectly addressed data to accumulator with carry Add immediate data to accumulator with carry Subtract register from accumulator with borrow Subtract directly addressed data from accumulator with borrow SUBB A, @Ri Subtract indirectly addressed data from accumulator with borrow SUBB A, #data Subtract immediate data from accumulator with borrow INC A Increment accumulator Mnemonic ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A, direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A, direct Code 0x28-0x2F 0x25 0x26-0x27 0x24 0x38-0x3F 0x35 0x36-0x37 0x34 0x98-0x9F 0x95 Bytes Cycles 1 1 2 2 1 2 2 2 1 1 2 2 1 2 2 2 1 1 2 2 2 2 1

0x96-0x97 1 0x94 0x04 2 1

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nRF24LE1 Product Specification
Mnemonic INC Rn INC direct INC @Ri INC DPTR DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV DA A Description Increment register Increment directly addressed location Increment indirectly addressed location Increment data pointer Decrement accumulator Decrement register Decrement directly addressed location Decrement indirectly addressed location Multiply A and B Divide A by B Decimal adjust accumulator Table 13. Arithmetic operations Mnemonic ANL A, Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A, direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description AND register to accumulator AND directly addressed data to accumulator AND indirectly addressed data to accumulator AND immediate data to accumulator AND accumulator to directly addressed location AND immediate data to directly addressed location OR register to accumulator OR directly addressed data to accumulator OR indirectly addressed data to accumulator OR immediate data to accumulator OR accumulator to directly addressed location OR immediate data to directly addressed location Exclusive OR register to accumulator Exclusive OR indirectly addressed data to accumulator Exclusive OR indirectly addressed data to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to directly addressed location Exclusive OR immediate data to directly addressed location Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator Code 0x58-0x5F 0x55 0x56-0x57 0x54 0x52 0x53 0x48-0x4F 0x45 0x46-0x47 0x44 0x42 0x43 0x68-0x6F 0x66-0x67 0x66-0x67 0x64 0x62 0x63 0xE4 0xF4 0x23 0x33 0x03 0x13 0xC4 Bytes 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Cycles 1 2 2 2 3 4 1 2 2 2 3 4 1 2 2 2 3 4 1 1 1 1 1 1 1 Code 0x08-0x0F 0x05 0x06-0x07 0xA3 0x14 0x18-0x1F 0x15 0x16-0x17 0xA4 0x84 0xD4 Bytes Cycles 1 2 2 3 1 3 1 1 1 1 1 2 2 3 1 3 1 5 1 5 1 1

Table 14. Logic operations

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nRF24LE1 Product Specification

Mnemonic MOV A,Rn MOV A,direct MOV A,@Ri

Description Move register to accumulator Move directly addressed data to accumulator Move indirectly addressed data to accumulator MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register MOV Rn,direct Move directly addressed data to register MOV Rn,#data Move immediate data to register MOV direct,A Move accumulator to direct MOV direct,Rn Move register to direct MOV Move directly addressed data to directly directl,direct2 addressed location MOV Move indirectly addressed data to directly direct,@Ri addressed location MOV Move immediate data to directly addressed direct,#data location MOV @Ri,A Move accumulator to indirectly addressed location MOV Move directly addressed data to indirectly @Ri,direct addressed location MOV Move immediate data to indirectly addressed @Ri,#data location MOV Load data pointer with a 16-bit immediate DPTR,#datal6 MOVC Load accumulator with a code byte relative A,@A+DPTR to DPTR MOVC Load accumulator with a code byte relative A,@A+PC to PC MOVX A,@Ri Movea external RAM (8-bit addr) to accumulator MOVX Movea external RAM (16-bit addr) to A,@DPTR accumulator MOVX @Ri,A Movea accumulator to external RAM (8-bit addr) MOVX Movea accumulator to external RAM (16-bit @DPTR,A addr) PUSH direct Push directly addressed data onto stack POP direct Pop directly addressed location from stack XCH A,Rn Exchange register with accumulator XCH A,direct Exchange directly addressed location with accumulator XCH A,@Ri Exchange indirect RAM with accumulator XCHD A,@Ri Exchange low-order nibbles of indirect and accumulator

Code 0xE8-0xEF 0xE5 0xE6-0xE7 0x74 0xF8-0xFF 0xA8-0xAF 0x78-0x7F 0xF5 0x88-0x8F 0x85 0x86-0x87 0x75 0xF6-0xF7 0xA6-0xA7 0x76-0x77 0x90 0x93 0x83 0xE2-0xE3 0xE0 0xF2-0xF3 0xF0 0xC0 0xD0 0xC8-0xCF 0xC5 0xC6-0xC7 0xD6-0xD7

Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1

Cycles 1 2 2 2 2 4 2 3 3 4 4 3 3 5 3 3 3 3 4 4 5 5 4 3 2 3 3 3

a. The MOVX instructions perform one of two actions depending on the state of pmw bit (pcon.4).

Table 15. Data transfer operations

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nRF24LE1 Product Specification

Mnemonic ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addrl6 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel CJNE A, direct, rel CJNE A,#data,rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP

Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if directly addressed bit is set Jump if directly addressed bit is not set Jump if directly addressed bit is set and clear bit Compare directly addressed data to accumulator and jump if not equal Compare immediate data to accumulator and jump if not equal Compare immediate data to register and jump if not equal Compare immediate data to indirect addressed value and jump if not equal Decrement register and jump if not zero Decrement directly addressed location and jump if not zero No operation

Code xxx10001b 0x12 0x22 0x32 xxx00001b 0x02 0x80 0x73 0x60 0x70 0x40 0x50 0x20 0x30 0x10 0xB5 0xB4 0xB8-0xBF 0xB6-B7 0xD8-DF 0xD5 0x00

Bytes 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1

Cycles 6 6 4 4 3 4 3 2 3 3 3 3 4 4 4 4 4 4 4 3 4 1

Table 16. Program branches Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Description Clear carry flag Clear directly addressed bit Set carry flag Set directly addressed bit Complement carry flag Complement directly addressed bit AND directly addressed bit to carry flag AND complement of directly addressed bit to carry OR directly addressed bit to carry flag OR complement of directly addressed bit to carry Move directly addressed bit to carry flag Move carry flag to directly addressed bit Table 17. Boolean manipulation Code 0xC3 0xC2 0xD3 0xD2 0xB3 0xB2 0x82 0xB0 0x72 0xA0 0xA2 0x92 Bytes 1 2 1 2 1 2 2 2 2 2 2 2 Cycles 1 3 1 3 1 3 2 2 2 2 2 3

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nRF24LE1 Product Specification
4.3.3 Opcode map
Mnemonic NOP AJMP addr11 JUMP addrl6 RRA INCA INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 JBC bit, rel ACALL addr11 LCALL add r16 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DECR3 DECR4 DECR5 DECR6 DECR7 JB bit, rel AJMP addr11 RET RL A ADD A, #data ADD A, direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 JNB bit, rel ACALL addr11 Opcode 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H Mnemonic ANL A,@R0 ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 JZ rel AJMP addr11 XRL direct, A XRL direct, #data XRL A, #data XRL A,direct XRLA,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 JNZ rel ACALL addr11 ORL C, bit JMP @A+DPTR MOV A, #data MOV direct, #data MOV @R0,#data MOV @R1, #data MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data MOV R5, #data MOV R6, #data MOV R7, #data SJMP rel AJMP addr11 ANL C, bit MOVC A,@A+PC DIV AB MOV direct, direct MOV direct,@R0 MOV direct,@R1 Opcode ACH ADH AE AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH Mnemonic MOV R4,direct MOV R5,direct MOV R6,direct MOV R7,direct ANL C,/bit ACALL addr11 CPL bit CPLC CJNE A,#data,rel CJNE A, direct, rel CJNE @R0,#data,rel CJNE @R1, #data,rel CJNE R0, #data,rel CJNE R1,#data,rel CJNE R2,#data,rel CJNE R3,#data,rel CJNE R4,#data,rel CJNE R5,#data,rel CJNE R6,#data,rel CJNE R7,#data,rel PUSH direct AJMP addr11 CLR bit CLR C SWAP A XCH A, direct XCH A,@R0 XCH A,@R1 XCH A,R0 XCH A,R1 XCH A,R2 XCHA,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCHA,R7 POP direct ACALL addr11 SETB bit SETB C DAA DJNZ direct, rel XCHDA,@R0 XCHD A,@R1 DJNZ R0,rel DJNZ R1,rel DJNZ R2,rel DJNZ R3,rel DJNZ R4,rel DJNZ R5,rel

Opcode 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H

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nRF24LE1 Product Specification
Opcode 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H Mnemonic RETI RLC A ADDC A,#data ADDC A, direct ADDC A,@R0 ADDC A,@R1 ADDC A,R0 ADDC A,R1 ADDC A,R2 ADDC A,R3 ADDC A,R4 ADDC A,R5 ADDC A,R6 ADDC A,R7 JC rel AJMP addr11 ORL direct, A ORL direct, #data ORL A, #data ORL A, direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORLA,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORLA,R7 JNC rel ACALL addr11 ANL direct, A ANL direct, #data ANL A, #data ANL A, direct Opcode 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH Mnemonic MOV direct,R0 MOV direct,R1 MOV direct,R2 MOV direct,R3 MOV direct,R4 MOV direct, R5 MOV direct,R6 MOV direct,R7 MOV DPTR, #datal6 ACALL addr11 MOV bit, C MOVCA,@A+DPTR SUBB A, #data SUBB A, direct SUBB A,@R0 SUBB A,@R1 SUBB A, R0 SUBB A,R1 SUBB A,R2 SUBB A,R3 SUBB A,R4 SUBB A,R5 SUBB A,R6 SUBB A,R7 ORL C,/bit AJMP addr11 MOV C, bit INC DPTR MUL AB MOV @R0,direct MOV @R1,direct MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct Opcode DE DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Mnemonic DJNZ R6,rel DJNZ R7,rel MOVX A,@DPTR AJMP addr11 MOVX A,@R0 MOVX A,@R1 CLR A MOVA, direct MOVA,@R0 MOV A,@R1 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 MOVX @DPTR,A ACALL addr11 MOVX @R0,A MOVX @R1,A CPL A MOV direct, A MOV @R0,A MOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A

Table 18. Opcode map

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nRF24LE1 Product Specification 5 Memory and I/O organization

The MCU has 64 kB of separate address space for code and data, an area of 256 byte for internal data (IRAM) and an area of 128 byte for Special Function Registers (SFR). The nRF24LE1 memory blocks has a default setting of 16 kB program memory (flash), 1 kB of data memory (SRAM) and 2 blocks (1 kB standard endurance/512 bytes extended endurance) of non-volatile data memory (flash), see default memory map in Figure 30. Read- or write access to the grey areas in this figure may behave unpredictably.
Data Space (XDATA, accessible by MOVX)
0xFFFF NV Data Memory 512 byte 0xFE00 NV Data Memory 512 byte 0xFC00 NV Data Memory 256 byte Extended endurance NV Data Memory 256 byte Extended endurance

Code Space (accessible by MOVC)
0xFFFF

IRAM 0xFF 0x3FFF Accessible by indirect addressing only 0x80 0x7F Accessible by direct and indirect addressing 0x0000 0x00

SFR 0xFF Accessible by direct addressing only 0x80

0x0400 0x0200 0x0000 DataNonRetentive (SRAM) 512 byte DataRetentive (SRAM) 512 byte

Program memory (Flash) 16 kbyte

Special Function Registers

Figure 30. Memory map The lower 128 bytes of the IRAM contains work registers (0x00 - 0x1F) and bit addressable memory (0x20 - 0x2F). The upper half can only be accessed by indirect addressing. The lowest 32 bytes of the IRAM form four banks, each consisting of eight registers (R0 - R7). Two bits of the program memory status word (PSW) select which bank is used. The next 16 bytes of memory form a block of bit-addressable memory, accessible through bit addresses 0x00 - 0x7F.

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nRF24LE1 Product Specification 5.1 PDATA memory addressing

The nRF24LE1 supports PDATA (Paged Data memory) addressing into data space. One page (256 bytes) can be accessed by an indirect addressing scheme through registers R0 and R1 (@R0, @R1). The MPAGE register controls the start address of the PDATA page: Addr 0xC9 Bit 7:0 R/W R/W Function Start address of the PDATA page Table 19. MPAGE register MPAGE sets the upper half of the 16 bit address space. For example, setting MPAGE to 0x80 starts PDATA from address 0x8000. Reset value: 0x00

5.2
5.2.1

MCU Special Function Registers
Accumulator - ACC

Accumulator is used by most of the MCU instructions to hold the operand and to store the result of an operation. The mnemonics for accumulator specific instructions refer to accumulator as A, not ACC. Address 0xE0 bit7 acc.7 bit6 acc.6 bit5 acc.5 bit4 acc.4 bit3 acc.3 bit2 acc.2 bit1 acc.1 bit0 acc.0

Table 20. ACC register

5.2.2

B Register – B

The B register is used during multiplying and division instructions. It can also be used as a scratch-pad register to hold temporary data. Address 0xF0 bit7 b.7 bit6 b.6 bit5 b.5 bit4 b.4 bit3 b.3 bit2 b.2 bit1 b.1 bit0 b.0

Table 21. B register

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nRF24LE1 Product Specification
5.2.3 Program Status Word Register - PSW

The PSW register contains status bits that reflect the current state of the MCU. Note: The Parity bit can only be modified by hardware upon the state of ACC register. Address Bit Name Description 0xD0 7 cy Carry flag: Carry bit in arithmetic operations and accumulator for Boolean operations. 6 ac Auxiliary Carry flag: Set if there is a carry-out from 3rd bit of Accumulator in BCD operations 5 f0 General purpose flag 0 4-3 rs Register bank select, bank 0..3 (0x00-0x07, 0x08-0x0f, 0x10-0x17, 0x180x1f) 2 ov Overflow flag: Set if overflow in Accumulator during arithmetic operations 1 f1 General purpose flag 1 0 p Parity flag: Set if odd number of ‘1’ in ACC. Table 22. PSW register

5.2.4

Stack Pointer – SP

This register points to the top of stack in internal data memory space. It is used to store the return address of a program before executing interrupt routine or subprograms. The SP is incremented before executing PUSH or CALL instruction and it is decremented after executing POP or RET(I) instruction (it always points to the top of stack). Address 0x81 Register name SP Table 23. SP register

5.2.5

Data Pointer – DPH, DPL
Address 0x82 0x83 Register name DPL DPH Table 24. Data Pointer register (DPH:DPL)

The Data Pointer Registers can be accessed through DPL and DPH. The actual data pointer is selected by DPS register. These registers are intended to hold 16-bit address in the indirect addressing mode used by MOVX (move external memory), MOVC (move program memory) or JMP (computed branch) instructions. They may be manipulated as 16-bit register or as two separate 8-bit registers. DPH holds higher byte and DPL holds lower byte of indirect address. It is generally used to access external code or data space (for example, MOVC A, @A+DPTR or MOV A, @DPTR respectively).

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nRF24LE1 Product Specification
5.2.6 Data Pointer 1 – DPH1, DPL1
Address 0x84 0x85 Register name DPL1 DPH1 Table 25. Data Pointer 1 register (DPH1:DPL1) The Data Pointer Register 1 can be accessed through DPL1 and DPH1. The actual data pointer is selected by DPS register. These registers are intended to hold 16-bit address in the indirect addressing mode used by MOVX (move external memory), MOVC (move program memory) or JMP (computed branch) instructions. They may be manipulated as 16-bit register or as two separate 8-bit registers. DPH1 holds higher byte and DPL1 holds lower byte of indirect address. It is generally used to access external code or data space (for example, MOVC A,@A+DPTR or MOV A,@DPTR respectively). The Data Pointer 1 is an extension to the standard 8051 architecture to speed up block data transfers.

5.2.7

Data Pointer Select Register – DPS

The MCU contains two Data Pointer registers. Both of them can be used as 16-bits address source for indirect addressing. The DPS register serves for selecting active data pointer register. Address Bit Name 0x92 7:1 0 dps Description Not used Data Pointer Select. 0: select DPH:DPL, 1: select DPH1:DPL1 Table 26. DPS register

5.2.8

PCON register

The PCON register is used to control the Program Memory Write Mode and Serial Port 0 baud rate doubler. Address Bit Name Description 0x87 7 smod Serial port 0 baud rate select, see Table 91. on page 151 and Table 93. on page 156. 6 gf3 General purpose flag 3 5 gf2 General purpose flag 2 4 pmw Program memory write mode: 1: MOVX instructions will access memory code space 0: MOVX instructions will access memory data space 3 gf1 General purpose flag 1 2 gfo General purpose flag 0 1 Not used. This bit must always be cleared. Always read as 0. 0 Not used. This bit must always be cleared. Always read as 0. Table 27. PCON register

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nRF24LE1 Product Specification
5.2.9 Special Function Register Map

The map of Special Function Registers is shown in Table 28. Undefined locations must not be read or written. Address 0xF8-0xFF X000 FSR X001 FPCR X010 FCR X011 Reserved X100 X101 SPIMCON0 SPIMCON1 X110 SPIMSTAT X111 SPIMDAT

0xF0-0xF7 B 0xE8-0xEF RFCON MD0 MD1 MD2 0xE0-0xE7 ACC W2CON1 W2CON0 Reserved 0xD8-0xDF ADCON W2SADR W2DAT COMPCON 0xD0-0xD7 PSW ADCCON ADCCON ADCCON1 3 2 0xC8-0xCF T2CON MPAGE CRCL CRCH 0xC0-0xC7 IRCON CCEN CCL1 CCH1 0xB8-0xBF IEN1 IP1 S0RELH Reserved 0xB0-0Xb7 P3 RSTREA PWM- RTC2CON S CON 0xA8-0xAF IEN0 IP0 S0RELL RTC2CPT0 1 0xA0-0xA7 P2 PWMDC PWMDC CLKCTRL 0 1 0x98-0x9F S0CON S0BUF Reserved Reserved 0x90-0x97 P1 free DPS P0DIR 0x88-0x8F TCON TMOD TL0 TL1 0x80-0x87 P0 SP DPL DPH

MD3 MD4 MD5 ARCON SPIRCON0 SPIRCON1 SPIRSTAT SPIRDAT POFCON CCPDATIA CCPCCPDATO DATIB ADCDATH ADCDATL RNGCTL RNGDAT TL2 TH2 WUOPC1 WUOPC0 CCL2 CCH2 CCL3 CCH3 SPISCON0 SPISSTAT SPISDAT RTC2CMP0 RTC2CMP1 RTC2CPT 00 RTC2CPT10 CLKLFC- OPMCON WDSV TRL PWRDWN WUCON INTEXP MEMCON Reserved P1DIR TH0 DPL1 Reserved P2DIR TH1 DPH1 P0CON P3DIR Reserved Reserved P1CON P2CON P3CON

Table 28. Special Function Registers locations The registers in the X000 column in B register are both byte and bit addressable. The other registers are only byte addressable.

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nRF24LE1 Product Specification
5.2.10 Special Function Registers reset values
Reset value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Description Accumulator ADC Configuration Register 1 ADC Configuration Register 2 ADC Configuration Register 3 ADC Data high byte ADC Data low byte Arithmetic Control Register B Register Compare/Capture Enable Register Compare/Capture Register 1, high byte Compare/Capture Register 2, high byte Compare/Capture Register 3, high byte Compare/Capture Register 1, low byte Compare/Capture Register 2, low byte Compare/Capture Register 3, low byte Encryption/Decryption accelerator Data In Register A Encryption/Decryption accelerator Data In Register B Encryption/Decryption accelerator Data Out Register 32 kHz (CLKLF) control Clock control Comparator Control Register Compare/Reload/Capture Register, high byte Compare/Reload/Capture Register, low byte Data Pointer High 0 Data Pointer Low 0 Data Pointer High 1 Data Pointer Low 1 Data Pointer Select Register Flash Command Register Flash Protect Configuration Register Flash Status Register Interrupt Enable Register 0 Interrupt Priority Register / Enable Register 1 Interrupt Expander Register Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Memory Configuration Register Start address of the PDATA page Operational Mode Control Port 0 value Port 0 Configuration Register Port 0 pin direction control

Register name Address ACC ADCCON1 ADCCON2 ADCCON3 ADCDATH ADCDATL ARCON B CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CCPDATIA CCPDATIB CCPDATO CLKLFCTRL CLKCTRL COMPCON CRCH CRCL DPH DPL DPH1 DPL1 DPS FCR FPCR FSR IEN0 IEN1 INTEXP IP0 IP1 IRCON MD0 MD1 MD2 MD3 MD4 MD5 MEMCON MPAGE OPMCON P0 P0CON P0DIR 0xE0 0xD3 0xD2 0xD1 0xD4 0xD5 0xEF 0xF0 0xC1 0xC3 0xC5 0xC7 0xC2 0xC4 0xC6 0xDD 0xDE 0xDF 0xAD 0xA3 0xDB 0xCB 0xCA 0x83 0x82 0x85 0x84 0x92 0xFA 0xF9 0xF8 0xA8 0xB8 0xA6 0xA9 0xB9 0xC0 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xA7 0xC9 0xAE 0x80 0x9E 0x93

0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x10 0xFF

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nRF24LE1 Product Specification
Register name Address P1 P1CON P1DIR P2 P2CON P2DIR P3 P3CON P3DIR POFCON PSW PWMCON PWMDC0 PWMDC1 PWRDWN RFCON RNGCTL RNGDAT RSTREAS RTC2CMP0 RTC2CMP1 RTC2CON RTC2CPT00 RTC2CPT01 RTC2CPT10 S0BUF S0CON S0RELH S0RELL SP SPIMCON0 SPIMCON1 SPIMDAT SPIMSTAT SPIRCON0 SPIRCON1 SPIRDAT SPIRSTAT SPISCON0 SPISDAT SPISSTAT T2CON TCON TH0 TH1 TH2 TL0 TL1 TL2 TMOD W2CON0 0x90 0x9F 0x94 0xA0 0x97 0x95 0xB0 0x8F 0x96 0xDC 0xD0 0xB2 0xA1 0xA2 0xA4 0xE8 0xD6 0xD7 0xB1 0xB4 0xB5 0xB3 0xB6 0xAB 0xAC 0x99 0x98 0xBA 0xAA 0x81 0xFC 0xFD 0xFF 0xFE 0xE4 0xE5 0xE7 0xE6 0xBC 0xBF 0xBE 0xC8 0x88 0x8C 0x8D 0xCD 0x8A 0x8B 0xCC 0x89 0xE2 Reset value 0xFF 0x10 0xFF 0xFF 0x10 0xFF 0xFF 0x10 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x40 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0xD9 0x07 0x02 0x0F 0x00 0x03 0x01 0x0F 0x00 0x03 0xF0 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 Description Port 1 value Port 1 Configuration Register Port 1 pin direction control Port 2 value Port 2 Configuration Register Port 2 pin direction control Port 3 value Port 3 Configuration Register Port 3 pin direction control Power-fail Comparator Configuration Register Program Status Word PWM Configuration Register PWM Duty Cycle for channel 0 PWM Duty Cycle for channel 1 Power-down control RF Transceiver Control Register Random Number Generator Control Register Random Number Generator Data Register Reset Reason Register RTC2 Compare Value Register 0 RTC2 Compare Value Register 1 RTC2 Configuration Register RTC2 Capture Value Register 00 RTC2 Capture Value Register 01 RTC2 Capture Value Register 10 Serial Port 0, Data Buffer Serial Port 0, Control Register Serial Port 0, Reload Register, high byte Serial Port 0, Reload Register, low byte Stack Pointer SPI Master Configuration Register 0 SPI Master Configuration Register 1 SPI Master Data Register SPI Master Status Register RF Transceiver SPI Master Configuration Register 0 RF Transceiver SPI Master Configuration Register 1 RF Transceiver SPI Master Data Register RF Transceiver SPI Master Status Register SPI Slave Configuration Register 0 SPI Slave Data Register SPI Slave Status Register Timer 2 Control Register Timer/Counter Control Register Timer 0, high byte Timer 1, high byte Timer 2, high byte Timer 0, low byte Timer 1, low byte Timer 2, low byte Timer Mode Register 2-Wire Configuration Register 0

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nRF24LE1 Product Specification
Register name Address W2CON1 W2DAT W2SADR ADCON WDSW WUCON WUOPC0 WUOPC1 0xE1 0xDA 0xD9 0xD8 0xAF 0xA5 0xCF 0xCE Reset value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Description 2-Wire Configuration Register 1/Status Register 2-Wire Data Register 2-Wire Slave Address Register Serial Port 0 Baud Rate Select register (only adcon.7 bit used) Watchdog Start Value Register Wakeup configuration register Wakeup On Pin Configuration Register 0 Wakeup On Pin Configuration Register 1

Table 29. Special Function Registers reset values

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nRF24LE1 Product Specification 6 Flash memory

This section describes the operation of the embedded flash memory. MCU can read and write the memory and under special circumstances the MCU can also perform erase and write operations, for instance, when performing a firmware upgrade. The Flash memory is configured and programmed through an external SPI slave interface. After programming, read and write operations from the external interfaces can be disabled for code protection.

6.1
? ? ? ? ? ? ? ? ? ? ?

Features
16 kB code memory 1k NV data memory Page size 512 bytes for NV data memory and program memory Two pages of 256 bytes each for extended endurance memory 32 pages of main block + 1 InfoPage Endurance minimum 1000 write/erase cycles Extended endurance memory, minimum 20000 write/erase cycles Direct SPI programmable Configurable MCU write protection Readback protection HW support for FW upgrades

6.2

Block diagram

The Flash block in nRF24LE1 is split in 16 kB of generic code space memory and 1.5 kB of Non Volatile data memory.

to/from MCU

FCSN FSCK FMOSI FMISO SPI Slave

MUX

NVM Control

Flash

PROG

Cclk

Figure 31. nRF24LE1 Flash block diagram

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nRF24LE1 Product Specification 6.3 Functional description

The Flash block gives the MCU its code space for program storage and NVM space for storing of application data. Two pages of 256 bytes each of the NVM memory have extended endurance and can be erased/ written a minimum of 20000 times as opposed to 1000 for the ‘normal’ flash based NVM. The different parts of the memory can be accessed by the MCU through normal code and data space operations. Configuration and setup of the memory behavior during normal mode (that is, when MCU is running application code) is defined by data stored in a separate InfoPage. During the chip reset/start-up sequence the configuration data in the InfoPage is read and stored in the memory configuration SFR’s.

6.3.1

Using the NV data memory

The 1.5 kB NV memory is divided into two 256-byte extended endurance pages and two 512 byte normal endurance pages. Table 30. shows the mapping of those four pages for MCU access, SPI access and the page number used for erase (both MCU and SPI). Data memory area Extended endurance data Normal endurance data MCU address SPI address 0xFA00 - 0xFAFF NA 0xFB00 - 0xFBFF NA 0xFC00 - 0xFDFF 0x4400 0x45FF 0xFE00 - 0xFFFF 0x4600 0x47FF Page no. 32 33 34 35

Table 30. Mapping for MCU access, SPI access and page number for erase The NV data memory is read/written as normal flash as described in section 6.3.3 on page 76, except that when writing the NV memory the PMW bit in the PCON register must be cleared. When writing/reading the XDATA memory addresses must be used. In order to erase a NV data memory page, the corresponding flash page address (32 - 35) must be used. Note that a NV data memory byte can only be written once for every page erase. The memory mapping for the NV data memory is illustrated in Figure 30. on page 62.

6.3.2

Flash memory configuration

The on-chip flash memory is divided into 2 blocks, the 16 kB + 1.5 kB NVM main block (MB) and a 512 byte Information Page (IP). The memory configuration is stored in the InfoPage (IP) and the following configuration can be done: 1. 2. 3. Split the code space of the main block into 2 areas, protected and unprotected (against MCU erase/write operations). Disable Read and Write access to the flash from external interfaces SPI and HW debug. Enable HW debug features.

All configuration of the flash memory must be done through the external SPI interface. The configuration information is stored in the InfoPage during programming of the device and is read out to the flash configuration SFR’s during each reset/startup sequence of the circuit.

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nRF24LE1 Product Specification
6.3.2.1 InfoPage content

The InfoPage is a separate page (512 bytes) of flash memory that contains Nordic system tuning parameters and the configurable options of the flash memory. Any changes to the flash memory configuration must be done by updating this page. The InfoPage content is as follows: InfoPage data Device system Number of unprotected pages: NUPP (page address of start of protected area) Reserved Flash main block read back protect Name DSYS
a

Size 32 bytes 1 byte

NUPP

Address Comment 0x00 Reserved for device use. Do not erase or modify. 0x20 Read out to register FPCR during start up NUPP=0xFF: all pages are unprotected

RDISMB

2 bytes 1 byte

0x21 0x23

Reserved, must be 0xFF Disable flash main block access from external interfaces (SPI, HW debug). Byte value: ? 0xFF: Flash main block accessible from external interfaces ? Other value: No read/erase/write of flash main block from external interfaces. Only read of info page Can only be changed once by SPI command RDISMB. Can only be reset by SPI command ERASE ALL Enable on chip HW debug features and JTAG interface. Byte value: ? 0xFF: HW debug features disabled ? other value: HW debug features and JTAG interface enabled

Enable HW debug

ENDEBUG

1 byte

0x24

Reserved For user data

-

219 bytes 256 bytes

0x25 0x100

Reserved, must be 0xFF Free to use

a. NOTE: This InfoPage area is used to store nRF24LE1 system and tuning parameters. Erasing the content of this area WILL cause changes to device behavior and performance.

Table 31. InfoPage content DSYS - Device System parameters This InfoPage area is used by the nRF24LE1 to store core data like tuning parameters. Erasing and/or changing this area will cause severe changes to device behavior. The operations that can affect this area are SPI commands ERASE ALL, ERASE PAGE and PROGRAM operations to any of these flash addresses with the bit INFEN in register FSR set to logic 1. If you are going to utilise the ERASE ALL SPI command the content of this InfoPage area must be read out, stored and written back into nRF24LE1 after the ERASE ALL command finishes.

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nRF24LE1 Product Specification
Protected pages and data pages The flash area can be split into a unprotected and a protected area. Protecting an area of the flash means that the area is read only for the MCU, but it can still be read, erased and written by the SPI interface. The feature protects a part of the code space against illegal erase/write operations from the MCU. The protected area can typically be used for firmware upgrade functions (see section 6.3.6 on page 81). The code space area of the flash main block is divided into 32 pages with 512 bytes page size. Leaving this byte unchanged (NUPP=0xFF) will leave all the 32 pages of the code space unprotected, i.e. the MCU can erase and write to any section of it. If a number <32 is put in NUPP, the code space of the flash main block will be split in a number of unprotected (= NUPP) and protected pages (31-NUPP). The number put in NUPP is the page number of the first protected page. For example, NUPP=12 gives 12 unprotected pages (0-11) and 20 protected pages (12-31). Please see Figure 32. If you have split the flash main block in 2, the value of the STP bit in the FSR register will decide where the MCU starts code execution from. In the normal case STP is logic 0 and the code execution will start at code space address 0x0000. If STP is set to logic 1 the code execution will start from the start of the protected area. The STP bit is set during the reset/start up sequence and will be set to logic 1 if there are an odd number of ones in the 16 topmost addresses of the flash data memory. See Figure 32.

0xFFFF Page size 0 InfoPage 0xFC00 0xFBFF 0xFA00 0x3FFF NUPP

The content of the 16 highest addresses is read during startup and saved as BootStartSelector NV Data Memory 1 kB NV Data Memory 512 bytes Extendend endurance

Data Space (XDATA, accessible by MOVX)

16 kB Protected Program Memory

BootstartSelector

NUPP < 32 Split flash in 2

Code Space (accessible by MOVC) Unprotected Program Memory Odd number of 1's, set start program execution at the bottom of protected area.

0 0x0000

Even number of 1's, set start program execution at address ”0"

Figure 32. Flash main block protected area Such a trigger to enable code execution from protected memory might seem cumbersome, but it is made so to ensure safe code execution during firmware upgrades. Please see chapter 27 on page 185 for further details. RDISMB - Read DISable Main Block

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nRF24LE1 Product Specification
By changing this byte from 0xFF the SPI and other external interfaces no longer have any access to the flash main block and only read access to the InfoPage. The byte is changed by the RDISMB SPI command and since it cuts the SPI access to the flash main block, must be the last command sent to a nRF24LE1 during flash programming. The only SPI command that can give SPI access to the flash again is ERASE ALL. Note: ERASE ALL will also erase the entire InfoPage. Using ERASE ALL without first reading out and store InfoPage area DSYS for later write back, will render the device non functional! ENDEBUG - Enable HW debug Changing this byte from 0xFF will enable the on chip HW debug features and the JTAG debug interface. The on chip HW debug features will change device pin out and needs either a nRFprobeTM or FS2 HW debug tools to be utilized. Please see chapter 27 on page 185 for more details on HW debug features.

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nRF24LE1 Product Specification
6.3.2.2 Memory configuration SFR

During the boot sequence the content of the flash InfoPage (IP) is transferred to the memory configuration SFR’s. The same memory configuration SFR’s are used for later interfacing from both SPI and MCU.

Address Mnemonic (hex) 0xF8 FSR ENDEBUG

Bit 7

Reset value 0, until read from Flash IP

SPI SFR access access R/W
a

Description

Flash Status Register R/W Initial value read from byte ENDEBUG in flash IP. ENDEBUG: 0: HW debug features disabled 1: HW debug features enabled When RDISMB=0, ENDEBUG may by set directly by SFR write, but it can not be cleared by SFR. R Enable code execution start from protected flash area (page address NUPP) STP: 0: Even number of logic 1 in 16 MSB of NVM 1: Odd number of logic 1 in 16 MSB of NVM R/W Flash write enable latch. Enables flash write/erase operations from external interfaces (SPI and HW debug) WEN will be cleared after each SPI write or erase operation, but not after a MCU operations. Flash ready flag, active low.

STP

6

WEN

5

R 0, until calculated from 16 MSB flash in NVM 0 R/W

RDYN

4

1

R

R

INFEN

3

0

R/W

Will be set when read out of flash IP is completed in the MCU boot sequence R/W Flash IP Enable Will re-direct general SPI read/write/erase commands from the flash MB to the IP. Except SPI command ERASE ALL, which will erase both MB and IP Flash MB readback protection enabled, active low. RDISMB: 0: External interfaces have full access to the flash 1: MB read/write/erase and IP erase/write commands from external interfaces (SPI and HW debug) disabled. Will only be reset after use of SPI command ERASE ALL Reserved

RDISMB

2

1, until read from flash InfoPage

R/Wa

R

-

1

1

R

R

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nRF24LE1 Product Specification
Address Mnemonic (hex) 0xF9 FPCR NUPP 7 6:0 1 Bit 0 Reset value 0 SPI SFR Description access access R R/W Reserved Flash Protect Config Register R R Reserved R R Number of unprotected pages. NUPP will contain the page address of the first protected page if used. Note that this setting (32>NUPP>=0) reserves the 16 highest bytes of the 1 kB NV data memory area, regardless of other settings. Flash Command Register R/W A (SFR) write to this register erases the page with address equal to the register value, if value is < 36. (max page address). Addresses 32-35 will erase data pages.

0xFA

FCR Flash command register

7:0

0

a. Can only be written indirectly through InfoPage, by dedicated SPI command, and is ignored by WRSR command.

Table 32. Registers for MCU and SPI for FLASH configuration control

6.3.3

Brown-out

There is an on-chip power-fail brown-out detector, see chapter 12 on page 117, which ensures that any flash memory program or erase access will be ignored when the Power Fail (POF) signal, see Figure 53. on page 119, is active. Both the micro controller and the Flash memory write operation still function according to specification, and any write operation that was started will be completed. Flash erase operations will be aborted. The Power-fail comparator is disabled after startup and can be enabled by setting bit 7 in POFCON (refer to Table 66. on page 119.) If the supply voltage drops below ~1.7V, that is when the Brown-Out Reset (BOR) signal (see Figure 53.) is active, the chip will be reset. If the power supply rises again before reaching the reset threshold, there will be no reset. In this case, any ongoing erase access will be aborted, possibly in an unsafe way, but a byte program access will not be aborted. In order to have an indication that shows this has happened, one will need to enable the Power Failure interrupt (POFIRQ, see Table 48 on page 101). To ensure proper programming of the flash in the cases where power supply may be unreliable, the user should take the following precautions: ? Make sure there is no partial erase. X If the device is reset during an erase cycle, always assume that the erase was unsuccessful. X If there is no reset, make sure that the erase duration is longer than 20 ms. A sample firmware code for such a check may be found in nRFGo SDK. X Make sure the data read back from the flash is identical to what is written to flash. The mechanism above will guarantee that the data is safely stored to flash if the value does compare. If the compare fails, the write has been ignored due to a power supply event. X Make sure that the time from “Power fail” to “Reset” is longer than one write operation (46?s) by a sufficient reservoir on the supply.

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6.3.4 Flash programming from the MCU

This section describes how you can write and erase the flash memory using the MCU.

6.3.4.1

MCU write and erase operations in the main block

When a flash write is initiated, the MCU is halted for 740 clock cycles (46?s @16 MHz) for each byte written. When a page erase is initiated, the MCU can be halted for up to 360,000 clock cycles (22.5 ms @16 MHz). During this time the MCU does not respond to any interrupts. Firmware must assure that page erase does not interfere with normal operation of the nRF24LE1. The MCU can perform erase page and write operations to the unprotected part and the data part of the flash main block. It is required that the clock frequency of the microcontroller system is 16 MHz during flash write operations. To allow erase and write flash operations the MCU must run the following sequence: 1. 2. 3. 4. Set WEN (bit 5) in the FSR register high to enable flash erase/write access. The flash is now open for erase and write from the MCU until WEN in FSR is set low again. Before updating the flash memory it must be erased. Erase operations can only be performed on whole pages. To erase a page, write page address (range 0-31) to the FCR register. Set PMW (bit 4) in the PCON register high to enable program memory write mode. Programming the flash is done through normal memory write operations from the MCU. Bytes are written individually (there is no auto increment) to the flash using the specific memory address.

When the programming code executes from the flash, erase or write operation is self timed and the CPU stops until the operation is finished. If the programming code executes from the XDATA RAM the code must wait until the operation has finished. This can be done either by polling the RDYN bit in the FSR register to go low or by a wait loop. Do not set WEN low before the write or erase operation is finished. Memory address is identical to the flash address, see chapter 5 on page 62 for memory mapping.

6.3.5

Flash programming through SPI

The on-chip flash is designed to interface a standard SPI device for programming. The interface uses an 8bit instruction register and a set of instructions/commands to program and configure the flash memory.

6.3.5.1

SPI slave interface

To program the memory the SPI slave interface is used. SPI slave connection to the flash memory is activated by setting pin PROG = 1 while the reset pin is kept inactive. After the PROG pin is set to 1, apply a pulse on the RESET pin. Selected nRF24LE1 GPIO pins are automatically configured as a SPI slave as shown in Table 33. Further information on SPI slave timing can be found in chapter 18 on page 147. 24pin-4x4 P0.5 P0.4 P0.3 P0.2 32pin-5x5 P1.1 P1.0 P0.7 P0.5 48pin-7x7 P2.0 P1.6 P1.5 P1.2

FCSN FMISO FMOSI FSCK

Table 33. Flash SPI slave physical interface for each nRF24LE1 package alternative Note: After activation of the PROG pin you must wait at least 1.5 ms before you input the first flash command.

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The program interface uses an 8 bit instruction register and a set of commands to program and configure the flash memory.

Command WREN WRDIS RDSR WRSR

Command format 0x06 0x04 0x05 0x01

Address NA NA NA NA

# Data bytes 0 0 1 1

Command operation Set flash write enable latch. Bit WEN register FSR Reset flash write enable latch. Bit WEN in register FSR Read FLASH Status Register (FSR) Write FLASH Status Register (FSR). Note: The DBG bit in FSR can only be set by the MCU Read data from FLASH

READ

0x03

PROGRAM

0x02

ERASE PAGE

0x52

2 bytes, First flash address to to be read 2 bytes, first flash address to be written 1 byte NA

1-18432

1-1024

Write data to FLASH Note: WEN must be set.

0 0

Erase addressed page Note: WEN must be set. Erase all pages in FLASH main block and infopage. When FSR.INFEN is low, only the main block is erased. When FSR.INFEN=1, both the main block and Info Page are erased. Note: WEN must be set. Read FLASH Protect Configuration Register FPCR Enable Flash readback protection Note: WEN must be set Enable HW debug features Note: WEN must be set. Operation can only be done once

ERASE ALL

0x62

a

RDFPCR RDISMB

0x89 0x85 0x86

NA NA NA

1 0 0

ENDEBUG

a. NOTE: The InfoPage area DSYS are used to store nRF24LE1 system and tuning parameters. Erasing the content of this area WILL cause changes to device behavior and performance. InfoPage area DSYS should ALWAYS be read out and stored prior to using ERASE ALL. Upon completion of the erase the DSYS information must be written back to the flash InfoPage.

Table 34. Flash operation commands The signalling of the SPI interface is shown in Figure 33. and Figure 34.

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FCSN FSCK FMOSI FMISO
C7 C6 C5 C4 C3 C2 C1 C0

D7

D6 D5

D4

D3

D2

D1

D0

FCSN FSCK FMOSI FMISO
C7 C6 C5 C4 C3 C2 C1 C0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 33. SPI read operation for direct and addressed command
Optional

FCSN FSCK FMOSI FMISO
C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

FCSN FSCK FMOSI FMISO
C7 C6 C5 C4 C3 C2 C1 C0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 34. SPI write operations for direct and addressed commands.

Abbreviations Cx Ax Dx

Description SPI Command bit Flash address. Sequence MS to LS byte, MS to LS bit. SPI data bit, Sequence LS to MS byte, MS to LS bit. Presence depending on SPI command.

Table 35. Flash SPI interface signal abbreviations

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WREN / WRDIS flash write enable/disable: SPI commands WREN and WRDIS sets and resets the flash write enable latch WEN in register FSR. This latch enables all write and erase operations in the flash blocks. The device will power-up in write disable state, and automatically go back to write disable state after each write/erase SPI command (FCSN set high). Each erase and write command over the SPI interface must therefore be preceded by a WREN command. Both WREN and WRDIS are 1-byte SPI commands with no data. RDSR / WRSR read/write flash status register SPI commands RDSR and WRSR read and writes to the flash status register FSR. Both commands are 1 and are followed by a data byte for the FSR content, see Figure 33. and Figure 34. READ SPI command READ reads out the content of an addressed position in the flash main block. It must be followed by 2 bytes denoting the start address of the read operation, see Figure 33. If bit INFEN in register FSR is enabled, the read operation will be conducted from the InfoPage instead. If the FCSN line is kept active after the first data byte is read out the read command can be extended, the address is auto incremented and data continues to shift out. The internal address counter rolls over when the highest address is reached, allowing the complete memory to be read in one continuous read command. A read back of the flash main block content is only possible if the read disable bit RDISMB in the FSR register is not set. PROGRAM SPI command PROGRAM, programs the content of the addressed position in the flash main block. It must be followed by 2 bytes denoting the start address of the write operation, see Figure 34. If bit INFEN in register FSR is enabled, the write operation will access the InfoPage instead. Before each write operation the write enable latch WEN must be enabled through the WREN SPI command. It is possible to write up to 1 kB (two pages) in one PROGRAM command. The first byte can be anywhere in a page. A byte can not be reprogrammed without erasing the whole sector. The device automatically returns to flash write disable (WEN=0) after completion of a PROGRAM command (pin FCSN=1). ERASE PAGE SPI command ERASE PAGE erases 1 addressed page (512 bytes) in the flash main block. The command must be followed by a 1 byte page address (0-31 for pages in the code memory, 32-35 for pages in the NVM), see Figure 34. Before each erase operation the write enable latch WEN must be enabled through the WREN SPI command. The on-chip driven erase sequence is started when the FCSN pin is set high after the ERASE PAGE command. During the erase sequence all SPI commands are ignored except the RDSR command.

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The device automatically returns to flash write disable (WEN=0) after completion of an ERASE PAGE command sequence. ERASE ALL SPI command ERASE ALL, erases all pages in flash main block (code space and NVM) and InfoPage. It is a 1 byte SPI command with no data. Before the erase operation the write enable latch WEN must be enabled through the WREN SPI command. The on-chip erase sequence is started when the FCSN pin is set high after the ERASE ALL command. During the erase sequence all SPI commands are ignored except RDSR. If infen (bit 3 in FSR) is set high before execution of the ERASE ALL command both the InfoPage and the MainBlock are erased, otherwise only the MainBlock is erased. The device returns to write disable after completion of an ERASE ALL command. RDFPCR - Read Flash Protect Configuration register SPI command RDFPCR reads out the flash protect configuration register (FPCR), which contains the configuration of MCU write protected pages in the flash main block. The command is followed by 1 byte data.

RDISMB - Enable Read DISable of MainBlock) SPI command RDISMB enables the readback protection of the flash. The command disables all read/erase and write access to the flash main block from any external interface (SPI or HW debug JTAG). It also disabled erase and write operations in the InfoPage, but read InfoPage read operations are still possible. This will protect code and data in the device from being retrieved through the external flash interfaces. Before the RDISMB command the write enable latch WEN must be enabled through the WREN SPI command. Once the RDISMB command is sent all SPI connection/control of the flash from the SPI interface is lost. It is important that this command is the last one to be sent in a flash programming sequence. The command is a 1 byte command with no data. ENDEBUG - Enable DEBUG SPI command ENDEBUG enables the on chip support for HW debug. It will also enable the HW debug JTAG interface. Before the operation the write enable latch WEN must be enabled by SPI command WREN. After the HW debug features are enabled, only an ERASE ALL operation on the flash can reset it. The command is a 1 byte command with no data.

6.3.6

Hardware support for firmware upgrade

When some of the flash memory is configured as MCU write protected (FPCR.NUPP) and nRF24LE1 is restarted from the protected area, the memory mapping actually changes to make FW upgrades safer. Figure 35. shows an example with unprotected and protected area of the flash code space as it will be after programming the flash.

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Data Space
0xFFFF NV Data Memory 1.5 kB 0xFA00 0xFFFF

Code Space

0x8000

0x8000

0x3FFF 0x3000 0x2FFF

Protected Program memory 4 kB

0x03FF

DataNonRetentive DataRetentive

Unprotected Program memory 10 kB

0x0000

0x0000

Figure 35. Example memory map with 4 kB of protected flash program memory After restart address mapping is changed so the protected area now is mapped from address 0x0000 and upwards as shown in Figure 36.

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Data Space
0xFFFF NV Data Memory 1.5 kB 0xFA00 0xFFFF

Code Space

0x83FF

DataNonRetentive DataRetentive 0x8000

0x8000

0x2FFF Unprotected Program memory 10 kB

0x0FFF

0x0000

0x0000

Protected Program memory 4 kB

Figure 36. Example memory map with 4 kB of protected flash program memory The unprotected area is now available in the data space for easy update. Please note that the SRAM blocks in this case is mapped from address 0x8000 independently of MEMCON bit 2. This feature may be used for instance to do a firmware upgrade over air. Example of use of this mechanism: ? ? ? ? ? ? ? ? ? Application is running in unprotected area and the program doing the FW upgrade resides in protected area. Communicating device initiates a firmware upgrade over air. MCU sets WEN. One bit in one of the 16 MS Bytes in the NV Data memory is programmed to 0. Resulting in a odd numbers of logic 1’s in this area. The system can now be reset, and because of STP it will restart from the protected area. Erase and write operations can now be performed safely in the unprotected area. In case of a power failure or another reset/restart before the upgrade is finished, the MCU will start execution in the protected area because the number of logic 1’s in the 16 MSB of the NVM is not yet changed. When the upgrade is finished, another bit in one of the 16 highest addressed bytes is programmed to 0. The system can now be restarted, and it will restart from the unprotected area. running the new firmware.

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nRF24LE1 Product Specification 7 Random Access memory (RAM)

The nRF24LE1 contains two separate RAM blocks. These blocks are used to save temporary data or programs. The MCU internal RAM (IRAM) is the fastest and most flexible, but with only 256 bytes it is very limited. To accommodate more temporary storage of data or code the nRF24LE1 has an additional 1024x8bit (1kB) SRAM memory block default located in the XDATA address space from address 0x0000 to 0x03FF. The location of the SRAM blocks in the MCU address space can be changed, see section 7.1. A special feature of the nRF24LE1 SRAM block is that it is composed of two physical 512 byte blocks called DataRetentive (lower 512 bytes) and DataNonRetentive. DataRetentive, in contrast to DataNonRetentive, keeps its memory content during the Memory Retention power down modes (see chapter 11 on page 105).

7.1

SRAM configuration

It is possible to configure the location in address space of each SRAM block as described in Figure 37.

Data Space

Code Space

0x83FF DataNonRetentive 0x8200 0x81FF 0x8000 DataRetentive DataNonRetentive DataRetentive

0x03FF 0x0200 0x01FF 0x0000

DataNonRetentive DataRetentive

DataNonRetentive DataRetentive

Figure 37. Configurability of SRAM address space location

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You can address the SRAM memory blocks both as data and code. The MEMCON register controls this behavior: Addr 0xA7 Bit 7:3 2 R/W Function Reserved R/W SRAM address location: 0: SRAM blocks start from address 0x0000 1: SRAM blocks start from address 0x8000 R/W DataNonRetentive mapping: 0: Mapped as data 1: Mapped as code R/W DataRetentive mapping: 0: Mapped as data 1: Mapped as code Table 36. MEMCON register Reset value: 0x00

1

0

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8

Timers/counters

The nRF24LE1 contains a set of counters used for timing up important system events. One of the timers (RTC2) is also available in power down mode where it can be used as a wakeup source.

8.1

Features

nRF24LE1 includes the following set of timers/counters: ? ? Three 16-bit timers/counters (Timer 0, Timer 1 and Timer 2) which can operate as either a timer with a clock rate based on the MCU clock, or as an event counter clocked by signals from the programmable digital I/O. RTC2 is a configurable, linear, 16-bit real time clock with capture and compare capabilities. Input clock frequency is 32.768 kHz.

8.2

Block diagram

Timer 1/Timer 0 T1 (from pin) T0 (from pin)
TH1 TH0 TCON TMOD TL1 TL0

tf1 (irq) tf0 (irq)

Timer 2
TH2 TL2

T2 (from pin)
t2ex

T2CON CRCH CCH3 CCH2 CCH1 CCEN CRCL CCL3 CCL2 CCL1

tf2 (irq) exf2 (irq)

ckCpu

RTC2 /2
RTC2CMP1 RTC2CPT01 RTC2CPT10 RTC2CON CLKLF RTC2CMP0 RTC2CPT00

TICK (irq)

Figure 38. Block diagram of timers/counters

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8.3
8.3.1

Functional description
Timer 0 and Timer 1

In timer mode, Timers 0 and 1 are incremented every 12 clock cycles. In the counter mode, the Timers 0 and 1 are incremented when the falling edge is detected at the corresponding input pin T0 for Timer 0, or T1 for Timer 1. Note: Timer input pins T0, T1 and, T2 must be configured as described in section 17.3 on page 135. Since it takes two clock cycles to recognize a 1-to-0 event, the maximum input count rate is ? of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 clock cycle. Timer 0 and Timer 1 status and control are in TCON and TMOD register. The actual 16-bit Timer 0 value is in TH0 (8 msb) and TL0 (8 lsb), while Timer 1 uses TH1 and TL1. Four operating modes can be selected for Timers 0 and 1. Two Special Function Registers, TMOD and TCON, are used to select the appropriate mode.

8.3.1.1

Mode 0 and Mode 1

In mode 0, Timers 0 and 1 are each configured as a 13-bit register (TL0/TL1 = 5 bits, TH0/TH1 = 8 bits). The upper three bits of TL0 and TL1 are unchanged and should be ignored. In mode 1 Timer 0 is configured as a 16-bit register.
Cclk

/12 TMOD.ct0=0

T0 (from pin) TCON.tr0 TMOD.gate0 IFP

TL0

TH0

TCON.tf0

TMOD.ct0=1

Figure 39. Timer 0 in mode 0 and 1

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nRF24LE1 Product Specification Likewise, in mode 1, Timer 1 is configured as a 16-bit register.
Cclk

/12 TMOD.ct1=0

T1 (from pin)

TL1

TH1

TCON.tf1

TMOD.ct1=1

TCON.tr1

Figure 40. Timer 1 in mode 0 and 1

8.3.1.2

Mode 2

In this mode, Timers 0 and 1 are each configured as an 8-bit register with auto reload.
Cclk

/12 TMOD.ct0=0

T0 (from pin)

TL0
TMOD.ct0=1

TCON.tf0

TCON.tr0 TMOD.gate0 IFP

TH0

Figure 41. Timer 0 in mode 2
Cclk

/12
TMOD.ct1=0

T1 (from pin)

TMOD.ct1=1

TL1

TCON.tf1

TCON.tr1

TH1
Figure 42. Timer 1 in mode 2

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8.3.1.3

Mode 3

In mode 3 Timers 0 and 1 are configured as one 8-bit timer/counter and one 8-bit timer, but timer 1 in this mode holds its count. When Timer 0 works in mode 3, Timer 1 can still be used in other modes by the serial port as a baud rate generator, or as an application not requiring an interrupt from Timer 1.

TH0
Cclk

TCON.tf1

/12 TMOD.ct0=0

TCON.tr1

TL0
T0 (from pin) TR0N.tr0 TMOD.gate0

TCON.tf0

TMOD.ct0=1

IFP

Figure 43. Timer 0 in mode 3

8.3.2

Timer 2

Timer 2 is controlled by T2CON while the value is in TH2 and TL2. Timer 2 also has four capture and one compare/reload registers which can read a value without pausing or reload a new 16-bit value when Timer 2 reaches zero, see chapter 8.4.7 on page 94 and chapter 8.4.8 on page 94.
Cclk

Prescaler

Timer 2

CCL3 ++ CCH3 CCL3 CCH3 CCL2 + CCH2

CCL1 + CCH1

CRCL + CRCH

Figure 44. Timer 2 block diagram

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8.3.2.1

Timer 2 description

Timer 2 can operate as a timer, event counter, or gated timer.

Interrupt (exf2) T2 (count enable) t2ex exen2 th2 + tl2
Reload Mode 1 Reload Mode 0

Interrupt (tf2)

crch + crcl

Figure 45. Timer 2 in Reload Mode

8.3.2.2

Timer mode

Timer mode is invoked by setting the t2i0=1 and t2i1=0 in the T2CON register. In this mode, the count rate is derived from the clk input. Timer 2 is incremented every 12 or 24 clock cycles depending on the 2:1 prescaler. The prescaler mode is selected by bit t2ps of T2CON register. When t2ps=0, the timer counts up every 12 clock cycles, otherwise every 24 cycles.

8.3.2.3

Event counter mode

This mode is invoked by setting the t2i0=0 and t2i1=1 in the T2CON register. In this mode, Timer 2 is incremented when external signal T2 (see section 8.4 on page 91 for more information on T2) changes its value from 1 to 0. The T2 input is sampled at every rising edge of the clock. Timer 2 is incremented in the cycle following the one in which the transition was detected. The maximum count rate is ? of the clock frequency.

8.3.2.4

Gated timer mode

This mode is invoked by setting the t2i0=1 and t2i1=1 in the T2CON register. In this mode, Timer 2 is incremented every 12 or 24 clock cycles (depending on T2CON t2ps flag). Additionally, it is gated by the external signal T2. When T2=0, Timer 2 is stopped.

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8.3.2.5

Timer 2 reload

A 16-bit reload from the CRC register can be done in two modes: ? ? Reload Mode 0: Reload signal is generated by Timer 2 overflow (auto reload). Reload Mode 1: Reload signal is generated by negative transition at t2ex.
Note: t2ex is connected to an internal clock signal which is half frequency of CLKLF (see section 11.3.1 on page 110.)

8.4
8.4.1

SFR registers
Timer/Counter control register – TCON

TCON register reflects the current status of MCU Timer 0 and Timer 1 and it is used to control the operation of these modules. Address Reset value 0x00 Bit Name Auto Description clear Yes Timer 1 overflow flag. Set by hardware when Timer1 overflows. No Timer 1 Run control. If cleared, Timer 1 stops. Yes Timer 0 overflow flag. Set by hardware when Timer 0 overflows. No Timer 0 Run control. If cleared, Timer 0 stops. Yes External interrupt 1 flag. Set by hardware. No External interrupt 1 type control. 1: falling edge, 0: low level Yes External interrupt 0 flag. Set by hardware. No External interrupt 0 type control. 1: falling edge, 0: low level Table 37. TCON register

0x88

7 6 5 4 3 2 1 0

tf1 tr1 tf0 tr0 ie1 it1 ie0 it0

The tf0, tf1 (Timer 0 and Timer 1 overflow flags), ie0 and ie1 (external interrupt 0 and 1 flags) are automatically cleared by hardware when the corresponding service routine is called.

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8.4.2

Timer mode register - TMOD

TMOD register is used for configuration of Timer 0 and Timer 1. Address Reset Bit Name Description value 0x00 7 gate1 Timer 1 gate control 6 ct1 Timer 1 counter/timer select. 1: Counter, 0: Timer 5-4 mode1 Timer 1 mode 00 – Mode 0: 13-bit counter/timer 01 – Mode 1: 16-bit counter/timer 10 – Mode 2: 8-bit auto-reload timer 11 – Mode 3: Timer 1 stopped 3 gate0 Timer 0 gate control 2 ct0 Timer 0 counter/timer select. 1: Counter, 0: Timer 1-0 mode0 Timer 0 mode 00 – Mode 0: 13-bit counter/timer 01 – Mode 1: 16-bit counter/timer 10 – Mode 2: 8-bit auto-reload timer 11 – Mode 3: two 8-bit timers/counters Table 38. TMOD register

0x89

8.4.3

Timer 0 – TH0, TL0
Address 0x8A 0x8C Register name TL0 TH0

Table 39. Timer 0 register (TH0:TL0)

These registers reflect the state of Timer 0. TH0 holds higher byte and TL0 holds lower byte. Timer 0 can be configured to operate as either a timer or a counter.

8.4.4

Timer 1 – TH1, TL1
Address 0x8B 0x8D Register name TL1 TH1

Table 40. Timer 1 register (TH1:TL1)

These registers reflect the state of Timer 1. TH1 holds higher byte and TL1 holds lower byte. Timer 1 can be configured to operate as either timer or counter.

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8.4.5

Timer 2 control register – T2CON

T2CON register reflects the current status of Timer 2 and is used to control the Timer 2 operation. Address Reset Bit Name Description value 0x00 7 t2ps Prescaler select. 0: timer 2 is clocked with 1/12 of the ckCpu frequency. 1: timer 2 is clocked with 1/24 of the ckCpu frequency. 6 i3fr Int3 edge select. 0: falling edge, 1: rising edge 5 i2fr Int2 edge select: 0: falling edge, 1: rising edge 4:3 t2r Timer 2 reload mode. 0X – reload disabled, 10 – Mode 0, 11 – Mode 1 2 t2cm Timer 2 compare mode. 0: Mode 0, 1: Mode 1 1-0 t2i Timer 2 input select. 00: stopped, 01: f/12 or f/24, 10: falling edge of T2, 11: f/12 or f/24 gated by T2. Table 41. T2CON register

0xC8

8.4.6

Timer 2 – TH2, TL2
Address 0xCC 0xCD Register name TL2 TH2

Table 42. Timer 2 (TH2:TL2)

The TL2 and TH2 registers reflect the state of Timer 2. TH2 holds higher byte and TL2 holds lower byte. Timer 2 can be configured to operate in compare, capture or, reload modes.

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8.4.7

Compare/Capture enable register – CCEN

The CCEN register serves as a configuration register for the Compare/Capture Unit associated with the Timer 2.
Address Reset value 0x00 Bit Name Description

0xC1

7:6

coca3

5:4

coca2

3:2

coca1

1:0

coca0

compare/capture mode for CC3 register 00: compare/capture disabled 01: reserved 10: reserved 11: capture on write operation into register CCL3 compare/capture mode for CC2 register 00: compare/capture disabled 01: reserved 10: reserved 11: capture on write operation into register CCL2ah3 compare/capture mode for CC1 register 00: compare/capture disabled 01: reserved 10: reserved 11: capture on write operation into register CCL1ah3 compare/capture mode for CRC register 00: compare/capture disabled 01: reserved 10: compare enabled 11: capture on write operation into register CRCLah3

Table 43. CCEN register

8.4.8

Capture registers – CC1, CC2, CC3

The Compare/Capture registers (CC1, CC2, CC3) are 16-bit registers used by the Compare/Capture Unit associated with the Timer 2. CCHn holds higher byte and CCLn holds lower byte of the CCn register.
Address 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 Register name CCL1 CCH1 CCL2 CCH2 CCL3 CCH3

Table 44. Capture Registers - CC1, CC2 and CC3

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8.4.9

Compare/Reload/Capture register – CRCH, CRCL
Address 0xCA 0xCB Reset value 0x00 0x00 Register name CRCL CRCH

Table 45. Compare/Reload/Capture register - CRCH, CRCL

CRC (Compare/Reload/Capture) register is a 16-bit wide register used by the Compare/Capture Unit associated with Timer 2. CRCH holds higher byte and CRCL holds lower byte.

8.5

Real Time Clock - RTC

RTC2 contains two registers that can be used for capturing timer values; one loaded at positive edge of the 32.768 kHz clock and another register clocked by the MCU clock for better resolution. Both registers are updated as a consequence of an external event. RTC2 can also give an interrupt at predefined intervals due to value equality between the timer and a compare register. RTC2 ensures that the functions the interrupt is used for are awoken prior to the interrupt.

8.5.1
? ? ? ? ?

Features
32.768 kHz, sub-?A. 16-bit. Linear. Compare with IRQ (TICK). Resolution: 30.52 ?s. Capture with increased resolution: 125 ns.

8.5.2

Functional description of SFR registers

The following registers control RTC2.
Address (Hex) 0xB3 Name/Mnemonic RTC2CON sfrCapture Bit Reset value Type Description

4:0 4

0

R/W RTC2 configuration register. W Trigger signal. When the MCU writes a ‘1’ to this register field, RTC2 will capture the timer value. The value is stored in RTC2CPT00 and RTC2CPT01. An additional counter clocked by the MCU clock will at this point contain the number of MCU clock cycles from the previous positive edge of the 32.768 kHz clock (edge detect @ MCU clock). The value is stored in RTC2CPT1.

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nRF24LE1 Product Specification

Address (Hex)

Name/Mnemonic enableExternalCapture

Bit

3

Reset value 0

Type

Description

compareMode

2:1

00

rtc2Enable

0

0

0xB4

RTC2CMP0

7:0

0xFF

0xB5 0xB6

RTC2CMP1

7:0 7:0

0xFF 0x00

RTC2CPT00

0xAB

RTC2CPT01

7:0

0x00

0xAC

RTC2CPT10

7:0

0x00

R/W 1: Timer value is captured if required by an IRQ from the Radio (edge detect @ MCU clock). The value is stored in RTC2CPT00 and RTC2CPT01. An additional counter clocked by the MCU clock will at this point contain the number of MCU clock cycles from the previous positive edge of the 32.768 kHz clock (edge detect @ MCU clock). The value is stored in RTC2CPT1. 0: Capture by Radio disabled. R/W Compare mode. 11: The Rtc2 IRQ is assigned when the timer value is equal to the concatenation of RTC2CMP1 and RTC2CMP0. RTC2 ensures that the functions for which the IRQ is intended, are all awoken prior to the Rtc2 IRQ. When the Rtc2 IRQ is assigned, the timer is reset. 10: Same as above, except that the Rtc2 IRQ will not reset the timer. The timer will always wrap around at overflow. 0x: Compare disabled. OK R/W 1: RTC2 is enabled. The clock to the RTC2 core functionality is running. 0: RTC2 is disabled. The clock to the RTC2 core functionality stands still and the timer is reset. R/W RTC2 compare value register 0. Contains LSByte of the value to be compared to the timer value to generate Rtc2 IRQ. Resolution: 30.52 ?s. R/W RTC2 compare value register 1. Contains MSByte of the value to be compared to the timer value to generate Rtc2 IRQ. R RTC2 capture value register 00. Contains LSByte of the timer value at the time of the capture event. Resolution: 30.52 ?s. R RTC2 capture value register 01. Contains MSByte of the timer value at the time of the capture event. R RTC2 capture value register 1. Contains the value of the counter that counts the number of MCU clock cycles from the previous positive edge of the 32.768 kHz clock until the capture event. The counter value is truncated by one bit (LSBit). Resolution: 125 ns.

Table 46. RTC2 register map

The Rtc2 timer is a 16 bit timer counting from zero and upwards at the rate of the 32.768 kHz clock. When the Rtc2 timer is equal to the concatenation of RTC2CMP1 and RTC2CMP0, an Rtc2 IRQ, also referred to as TICK, is generated. There is an uncertainty of one CLKLF period, 30.52?s, from when the Rtc2 is started or a new value is given to the RTC2 compare value registers and until the IRQ is given.

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nRF24LE1 Product Specification The time for the IRQ is given by the range:

? [RTC2CMP1 : RTC2CMP0] ? timer [RTC2CMP1 : RTC2CMP0] ? timer + 1? , ? ? [s] 32768 32768 ? ?
where [RTC2CMP1:RTC2CMP0] is the concatenation of RTC2CMP1 and RTC2CMP0 into a 16 bits word and timer is the current value of the Rtc2 timer when the RTC2 compare value register was updated or the Rtc2 enabled. If compare mode 11 is used, the Rtc2 IRQ will be given every

[RTC2CMP1 : RTC2CMP0] + 1 [s] 32768
second. The RTC2 compare value is updated every time RTC2CMP1 or RTC2CMP0 is written. This might give unwanted behavior if precaution is not taken when updating any of the variables. When new values are written to RTC2CMP1 and RTC2CMP0, the Rtc2 IRQ should be disabled to prevent unwanted Rtc2 IRQ. To make sure everything is up and running when the Rtc2 IRQ is given in Register retention or Memory retention timers on, the MCU is pre-started before the IRQ is given. If XOSC16M is enabled, the pre-start time is long enough to make sure that this clock is up and running before the IRQ is given.1 If RCOSC16M is enabled by CLKCTRL[5:4], this will be the clock source in the pre-start period. To save power, the user could choose to go to Standby while waiting for the IRQ. If only RCOSC16M is enabled, the pre-start time is shorter, making sure that the RC-oscillator is up and running before the Rtc2 IRQ is given. This same, short pre-startup time is used from Register Retention to Active if XOSC16M is running while in Register retention2CLKCTRL[7] = 1. This implies that the time from going to Register retention or Memory retention and until the Rtc2 IRQ is given, always must be longer then the pre-start time: 49 CLKLF periods for the long pre-start and 2 CLKLF for the short pre-start. The Rtc2 counter uses the 32.768 kHz low frequency clock for the Rtc2 timer, and one of the 32.768 kHz sources must be enabled when using the Rtc2. See section 13.3 on page 121 for the 32.768 kHz clock. Reading RTC2CMP0 and RTC2CMP1: ? Disable the Rtc2 IRQ, until both registers have been written.

1. The crystal start-up time must be <1.5 ms to ensure that XOSC16M is clock source on arrival of the Rtc2 IRQ. Refer to section 13.3.1 on page 121 for further details. 2. To get the short pre-startup time when going to Register retention with XOSC16M running in the power down mode, make sure XOSC16M is running before going to Register retention. If it is not, the long pre-start time is used, and the minimum value for the long pre-startup for the RTC2 compare value register should be used. This apples only the first time going to Register retention after enabling XOSC16M in Register retention.

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nRF24LE1 Product Specification

Reading RTC2CPT00, RTC2CPT01 and RTC2CPT10: ? Disable The Radio IRQ until all three registers have been read.

Uncertainty in capture values: ? 250 ns.

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nRF24LE1 Product Specification 9 Interrupts

nRF24LE1 has an advanced interrupt controller with 18 sources, as shown in Figure 46. The unit manages dynamic program sequencing based upon important real-time events as signalled from timers, the RF Transceiver, pin activity, and so on.

9.1
? ? ?

Features
Interrupt controller with 18 sources and 4 priority levels Interrupt request flags available Interrupt from pin (configurable)

9.2

Block diagram
GPINT2 GPINT1 GPINT0 (INT 0) RFRDY (IADC) tf0 RFIRQ (INT2) POFIRQ (INT1) MSDONE WIRE2IRQ SSDONE (INT3) tf1 WUOPIRQ (INT4) ri0 ti0 S0CON[1] X16IRQ ADCIRQ RNGIRQ (INT5) exf2 tf2 TICK (INT6) IEN1[7] IRCON[6] IEN1[5] IRCON[5]
CLKCTRL[3] source: INTEXP source: INTEXP

Request flags IFP
edge/level TCON[0]

Auto clear request flags TCON[1] (ie0)

IEN0[7] IEN0[0] IEN1[0] IP1[0] IP0[0]

IRCON[0] IEN0[1] TCON[5] edge sel: T2CON[5]
edge/level TCON[2]

IRCON[1] (iex2) TCON[3] (ie1)

IEN1[1] IEN0[2]

IP1[1] IP0[1]

IEN0[3] TCON[7] IRCON[3] (iex4) S0CON[0] IEN1[3] IP1[3] IP0[3]

Processing sequence

edge sel: T2CON[6]

IRCON[2] (iex3)

IEN1[2]

IP1[2] IP0[2]

MCU interrupt

IEN0[4] IP1[4] IP0[4]

MISCIRQ

IRCON[4] (iex5) IRCON[7]

IEN1[4]

IEN0[5] IP1[5] IP0[5]

Figure 46. Block diagram of interrupt structure

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nRF24LE1 Product Specification 9.3 Functional description
85H

When an enabled interrupt occurs, the MCU vectors to the address of the interrupt service routine (ISR) associated with that interrupt, as listed in Table 47. The MCU executes the ISR to completion unless another interrupt of higher priority occurs.
Source IFP vector 0x0003 Polarity low/fall Description Interrupt from pin GP INT0, GP INT1 or GP INT2 as selected by bits 3,4 or 5 in SFR INTEXP. Only one of the bits may be set at a time. Timer 0 overflow interrupt Power Failure interrupt Timer 1 overflow interrupt Serial channel receive interrupt Serial channel transmit interrupt Timer 2 overflow interrupt Timer 2 external reload RF SPI ready RF interrupt Master SPI transaction completed 2-Wire transaction completed Slave SPI transaction completed Wakeup on pin interrupt Miscellaneous interrupt is the sum of: ? XOSC16M started (X16IRQ) ? ADC Ready (ADCIRQ) interrupt ? RNG ready (RNGIRQ) interrupt Internal Wakeup (from RTC2) interrupt

tf0 POFIRQ tf1 ri0 ti0 tf2 exf2 RFRDY RFIRQ MSDONE WIRE2IRQ SSDONE WUOPIRQ MISCIRQ

0x000B 0x0013 0x001B 0x0023 0x0023 0x002B 0x002B 0x0043 0x004B 0x0053 0x0053 0x0053 0x005B 0x0063

high low/fall high high high high High high fall/rise fall/rise fall/rise fall/rise risea rise

TICK

0x006B

rise

a. Polarity is always rise on interrupt, but pin polarity can be selected by bit 2 in the OPMCON register as described in Table 61. on page 114.

Table 47. nRF24LE1 interrupt sources Note: RFIRQ, WUOPIRQ, MISCIRQ and TICK are not activated unless wakeup is enabled by WUCON (see section 11.3.5 on page 115).

9.4

SFR registers

Various SFR registers are used to control and prioritize between different interrupts. The TCON, IRCON, SCON, IP0, IP1, IEN0, IEN1 and INTEXP are described in this section. In addition the TCON and T2CON are used, the description for these registers can be found in chapter 8 on page 86.

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nRF24LE1 Product Specification
9.4.1 Interrupt Enable 0 Register – IEN0

The IEN0 register is responsible for global interrupt system enabling/disabling and also Timer 0, 1 and 2, Port 0 and Serial Port individual interrupts enabling/disabling.
Address Bit Description 0xA8 7 1: Enable interrupts. 0: all interrupts are disabled 6 Not used 5 1: Enable Timer2 (tf2/exf2) interrupt. 4 1: Enable Serial Port (ri0/ti0) interrupt. 3 1: Enable Timer1 overflow (tf1) interrupt 2 1: Enable Power failure (POFIRQ) interrupt 1 1: Enable Timer0 overflow (tf0) interrupt. 0 1: Enable Interrupt From Pin (IFP) interrupt. Table 48. IEN0 register

9.4.2

Interrupt Enable 1 Register – IEN1

The IEN1 register is responsible for RF, SPI and Timer 2 interrupts.
Address Bit Description 0xB8 7 1: Enable Timer2 external reload (exf2) interrupt 6 Not used 5 1: Internal wakeup (TICK) interrupt enable 4 1: Miscellaneous (MISCIRQ) interrupt enable 3 1: Wakeup on pin (WUOPIRQ) interrupt enable 2 1: 2-Wire completed (WIRE2IRQ) interrupt, SPI master/slave completed (MSDONE/SSDONE) interrupt enable 1 1: RF (RFIRQ) interrupt enable 0 1: RF SPI ready (RFRDY) interrupt enable Table 49. IEN1 register

2-Wire Master SPI and Slave SPI share the same interrupt line.
Address 0xA6 Bit 7:6 5 4 3 2 1 0 Description Reset value 0x01

not used 1: Enable GP INT2 (from pin) to IFP 1: Enable GP INT1 (from pin)1 to IFP 1: Enable GP INT0 (from pin) 0 to IFP 1: Enable 2-Wire completed (WIRE2IRQ) interrupt 1: Enable Master SPI completed (MSDONE)interrupt 1: Enable Slave SPI completed (SSDONE) interrupt
Table 50. INTEXP register

9.4.3

Interrupt Priority Registers – IP0, IP1

The 14 interrupt sources are grouped into six priority groups. For each of the groups, one of four priority levels can be selected. They can be selected by setting appropriate values in IP0 and IP1 registers.

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nRF24LE1 Product Specification
The contents of the Interrupt Priority registers define the priority levels for each interrupt source according to the tables below.
Address Bit Description 0xA9 7:6 Not used 5:0 Interrupt priority. Each bit together with corresponding bit from IP1 register specifies the priority level of the respective interrupt priority group. Table 51. IP0 register Address Bit Description 0xB9 7:6 Not used 5:0 Interrupt priority. Each bit together with corresponding bit from IP0 register specifies the priority level of the respective interrupt priority group. Table 52. IP1 register Group 0 1 2 3 4 5 Interrupt bits IP1[0], IP0[0] IP1[1], IP0[1] IP1[2], IP0[2] IP1[3], IP0[3] IP1[4], IP0[4] IP1[5], IP0[5] Priority groups RFRDY RFIRQ MSDONE WUOPIRQ ti0 TICK

IFP tf0 POFIRQ tf1 ri0 tf2/exf2

SSDONE MISCIRQ

Table 53. Priority groups IP1[x] 0 0 1 1 IP0[x] 0 1 0 1 Priority level Level 0 (lowest) Level 1 Level 2 Level 3 (highest) Table 54. Priority levels (x is the number of priority group)

9.4.4

Interrupt Request Control Registers – IRCON

The IRCON register contains interrupt request flags.
Address Bit Auto clear No No Yes Yes Yes Yes Description

0xC0

7 6 5 4 3 2 1 0

Yes No

Timer 2 external reload (exf2) interrupt flag Timer 2 overflow (tf2) interrupt flag Internal wakeup (TICK) interrupt flag Miscellaneous (MISCIRQ) interrupt flag Wakeup on pin (WUOPIRQ) interrupt flag 2-Wire completed (WIRE2IRQ), Master/Slave SPI (MSDONE/SSDONE) interrupt flag RF (RFIRQ) interrupt flag RF SPI ready (RFRDY) interrupt flag
Table 55. IRCON register

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nRF24LE1 Product Specification 10 Watchdog

The on-chip watchdog forces a system reset if the running software for some reason encounters a hang situation.

10.1
? ? ? ? ?

Features
32.768 kHz, sub-?A. 16-bit with an offset of 8 bits. Minimum Watchdog timeout interval: 7.8125 ms. Maximum Watchdog timeout interval: 512 s. Disable (reset) only by a system reset, or possibly when the chip enters the following power saving modes: Register retention and Memory retention. See section 17.3.2 on page 137 for details.

10.2

Block diagram
SFR Bus 0xAF Watchdog control High Byte Low Byte Watchdog start value

x256 Watchdog enable

24 bits Watchdog counter CLKLF 32.768 kHz clock Watchdog reset

Figure 47. Watchdog block diagram

10.3

Functional description

The following register controls the Watchdog.
Address (Hex) 0xAF Name/Mnemonic Bit Reset value Type Description

WDSV

15:0

0x0000

R/W Watchdog start value register. MSByte and LSByte of the word are written and read as separate bytes.

Table 56. Watchdog register

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nRF24LE1 Product Specification
watchdogStartValue (WDSV) contains the upper 16 bits of the Watchdog counters initial value. This 16 bits word is read and written as two separate bytes, LSByte and MSByte. LSByte is read and written first. After a write to WDSV, the next read of WDSV will always give the LSByte, and after a read, the next byte written will always be to the LSByte. In other words, to write to WDSV, two bytes must be written without a read between the writes, and vice-versa for read operations. Readout of WDSV will not give the current value of the Watchdog counter, but the start value for the counter. After a reset, the default state of the Watchdog is disabled. The Watchdog is activated when both bytes of WDSV have been written. The Watchdog counter then counts down from WDSV*256 towards 0. When 0 is reached, the complete microcontroller, as well as the peripherals, are reset. A reset from th

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