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机组复习题


Reviews of Computer Organization

2014-06-02

Review of Computer Organization
A.Types:Fill*10,Choose*10, Explain*15,Short answer*20, Calculate*20,Design*25 B.Basic Co

ncepts
1.Computer System 2.Two’s Complement Representation 3.Floating point number: ⑴General definition ⑵IEEE-754 standard notation 4.Arithmetic operation: ⑴Booth multiplication ⑵Floating-point Addition/Subtraction 5.Memory Hierarchy ⑴Read/Write operation ⑵Interconnection of RAM chips for Large Capacity 6.Instruction Set Architecture: ⑴Instruction Definition ⑵Instruction Set ⑶Instruction Set Characteristics ⑷Design Principles of Instruction Set ⑸Typical Instruction Set & Virtual Machine ⑹Examples of Instruction Set 7.CPU: ⑴Functions ⑵Basic organization ⑶CPU control flow ⑷Microprogrammed control unit ⑸Hardwired control unit ⑹Instruction cycle ⑺Pipeline technique ⑻CPU control modes 8.System Bus ⑴ Bus Structures ⑵ Bus Characteristics ⑶ Bus Arbitrament ⑷ Bus Transaction ⑸ Bus Examples ⑹Instruction cycle ⑺Pipeline technique ⑻CPU control modes 9.Input/Output System ⑴ Definition ⑵ Interface Characteristics/Functions ⑶Organization & OS functions in the Input/Output System ⑷Interrupt Mechanism ①Interrupt Source ②Interrupt Request ③Interrupt Response ④Interrupt Processing ⑤ Interrupt Interface ⑸DMA ①DMA mode ②DMA Controller ③DMA Operations ④DMA Sharing modes ⑹ Channel ①Channel Mode: ②Channel Functions ③Channel Program ④Channel Hierarchy

C.Explain the following terminology
1.Instruction Cycle:The processing performed by a CPU to execute a single instruction 2.Computer Iinstructions Set:A complete set of the operators of the instructions of a computer together with a description of the types of meanings that can be attributed to their operands. 3.Nonvolatile memory:Memory whose contents are stable and do not require a constant power source 4.Volatile Memory:A memory in which a constant electrical power source is required to maintain the contents of memory. If the power is switched off,the stored information is lost 5.CPU:That portion of a computer that fetches and executes instructions. It consists of an ALU,a
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Reviews of Computer Organization

2014-06-02

control unit, and registers 6.ALU:performs arithmetic operations,logic operation,and related operations. 7.Bus arbitration:The process of determining which competing bus master will be permitted access to the bus 8.Bus Master:A device attached to a bus that is capable of initiating and controlling communication on the bus 9.Cache Memory:A special buffer storage,smaller and faster than main storage,that is used to hold a copy of instructions and data in main storage 10.Control Storage:A ROM that contains all microcodes in a CISC computer 11.Associative memory:A memory whose storage locations are identified by their contents,or by a part of their contents,rather than by their names or positions 12.CISC:complex instruction set computer 13.RISC:ewduced instruction set computer 14.Control registers:CPU registers employed to control CPU operation.Most of these registers are not user visible 15.OS:Software that controls the execution of programs and that provides services such as resource allocation,scheduling,input/output control,and data management 16. Computer organization:Refers to the operational units and their interconnections that realize the architectural specifications 17.Associative memory:A memory whose storage locations are identified by their contents,or by a part of their contents,rather than by their names or positions 18.Control registers:CPU registers employed to control CPU operation.Most of these registers are not user visible 19.Program Status Word:used to hold and indicate the status of the computer system 20.Pipeline:A processor organization in which the processor consists of a number of stages, allowing multiple instructions to be executed concurrently

D.Short answers
1.What does“CPU” stand for? Explain its functions in a computer Answer: The CPU stands for central processing unit ①instruction control②operation control③timing control④data calculation⑤exception processing and interrupt processing 2. Characteristics of Harvard architecture Answer:In Harvard architecture, there are 4 sets of buses: ① a set of data buses for carrying data in and out of the CPU ②a set of address buses for accessing data operands ③a set of buses to carry the opcodes ④a set of address buses to access the opcodes 3.The major difference between CISC and RISC computer Answer:①system designing②implementation of controller ③designing goal④function of cache memory⑤compilation processing 4.What do RISC,VLIW,CISC and EPIC stand for? Answer: ①RISC:Reduced instruction set computer ②CISC:complex instruction set computer ③EPIC:Explicitly parallel instruction computing ④VLIW:Very long instruction word
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Reviews of Computer Organization

2014-06-02

5. State the PCI local bus characteristics Answer: ①it has a maximum speed of 33MHz②it has 32-and 64-bit datapath③it supports burst mode data transfer④it supports bus mastering⑤it is compatible with ISA and EISA⑥it is processor independent 6.Major features of USB Answer:①A single USB port of the PC can accommodate up to 127 devices ②The data transfer rate is between 1.5 to 12 Mbps at this time ③USB is hot-pluggable ④USB does not have to burden the system’s power supply ⑤Face to the future 7.The external characteristics of computer system Answer: ①High-speedness; ②Generality; ③accuracy; ④Logicality 8. The internal characteristics of computer system Answer: ①High-speed elements ②Stored program ③Digitization ④Logical judgment 9. In the IBM PC/XT, how many K bytes of memory are used by the interrupt vector table,and what are the beginning and ending address of the table? Answer: ①1KB ②the beginning address:00000H ③the ending address:003FFH 10. Characteristics of SCSI Answer:①Doubling the bus width can double the transfer rate without changing the clock rate ②Doubling the clock rate on the same bus width can double the transfer rate ③Fast transfer rate canbe achieved by using synchronous data transfer mode instead of asynchronous data transfer mode ④Using LVD signaling improves the signal-to-noise ratio and increase the cable length ⑤SCSI cables can be extended up to 75 meters ⑥Many new features added to ULTRA 3 SCSI improve its speed and quality of services 11.Give the definition of the bus bandwidth and variables that affect it Answer: ⑴Definition:The rate of data transfer of a bus is called bus bandwidth. ⑵variables that affect it:①the width of the data bus, ②the bus cycle frequency 12. A number of positive aspects to the RAID 1 organization Answer: ①A read request can be serviced by either of the two disks that contains the requested data,whichever one involves the minimum seek time plus rotational latency,②A write request requires that both corresponding strips be updated,but this can be done in parallel,③Recovery from a failure is simple.When a drive fails,the data may still accessed from the second drive 13.The functions of the memory address register and the counter register Answer: ①The memory address of the first byte of the block of data to be transferred is loaded in the memory address register ②The number of bytes to be transferred is loaded in the counter register 14. The major advances since the birth of the computer Answer: ①The family concept;②Microprogrammed control unit;③Cache memory; ④Pipelining;⑤Multiple processors;⑥RISC architecture

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Reviews of Computer Organization

2014-06-02

E.Calculate the following questions:
1.Booth multiplication 2.Floating-point Addition/Subtraction 3. 32-bit IEEE754 floating point number notation

F. Complete the following design
The memory of a computer has a capacity of 128M word× 32 bits/word .It is implemented with 32M× 8 bit DRAM chips

⑴How many DRAM chips are needed by the main memory ⑵Plot the schematic diagram of the memory organization showing the connection of all the address bits and the connections between decoders and memory chips. ⑶Give the address range of the first DRAM chip & the last DRAM chip ⑷The width of memory buffer register

G.Knowledge points:
1. The CPU/memory relation is an example of synchronous protocol 2. The CPU/printer relation is an example of asynchronous protocol 3. The device that initiates the communication is the master 4. The 8086/88 has assigned INT 2 to NMI 5. After the 8086 is reset(cold boot),the contents of CS=FFFFH and IP=0000H 6.When the computer is RESET, 8086 chip take over the system buses 7. When an interrupt is executed the 8086 saves the FR,CS,and IP on the stack 8.In response to activation of HOLDR, the CPU finishes the current .bus cycle before handing the buses to DMA 9. The CPU stands for central processing unit 10. The ALU stands for arithmetic logic unit 11.Register to memory operation exists for the STORE instruction in RISC 12.Itanium uses the EPIC instruction system architecture 13.To maintain data integrity, the checksum method is used for ROM type memory 14. To maintain data integrity, the parity bit method for DRAM memory 15. Each cell of DRAM must be refreshed every 15 micro-seconds 16. NV-RAM is used in the CMOS RAM of the x86 PC 17.SRAM is used for cache 18.RAS and CAS are associated with DRAM 19.DRAM is volatile memory 20. RS-232C is not TTL-compatible 21. The transfer of data using parallel lines is faster but more expensive 22. The start and stop bits are used in the asynchronous data communication 23. To support 16M colors, the number of bits set aside for color depth must be 24 24. The 74LS138 has total of 8 outputs 25. The Y output of the 74LS138 is active low 26. The CS pin of the memory chip is normally an active low 27. RISC processor normally have 32 general-purpose registers,each 32 bits 28.Address bus is not bidirectional 29.CISC of CPU has the greatest variety of instructions 30.ES register are not used to access the stack in the 8086 CPU
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Reviews of Computer Organization

2014-06-02

31.ADD instruction cannot affect TF bit of the flag register status 32.CS register cannot be split into high and low bytes 33. In instruction “OUT DX,AL”,the port address is .8 bits 34.The 8288 chip issues two INTA s to 8259 when INTR of the 8086 is activated 35.The Centronics printer standard uses parallel data transfer 36. IEEE1394 buses is HOT-pluggable 37.Given the decimal signed number X =+35.5 and Y =+86.0,suppose the format of the floating-point
number is following:its exponent has 6 bits(2 bits for sign),and its mantissa has 10 bits(2 bits for sign).Please perform the following add operation: (X+Y)2’complement 38. Given multiplicand M=+0.1011 and multiplier Y=+0.1101.Please demonstrate the step-by-step results of implementation of the hardware multiplication (M× Y) 2’complement by the Booth algorithm for two’s complement multiplication.Check your result by performing the calculation by hand,also directly in two’s complement notation

39. Complete the following design
The memory of a computer has a capacity of 512M word× 16 bits/word .It is implemented with 128M× 8 bit DRAM chips.Please answer the following questions:

⑴How many DRAM chips are needed by the main memory ⑵Plot the schematic diagram of the memory organization showing the connection of all the address bits and the connections between decoders and memory chips. ⑶Explain the related problems for designing memory interface with the CPU ⑷Give the address range of the last/first128M× 8 bit DRAM chip.

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