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INTEL D系列芯片组


Intel? Atom? Processor D2000 Series and N2000 Series
External Design Specification - Volume 1 of 2
For use with Next Generation Intel? Atom? Processor based (Desktop and Mobile) Pla

tform [Formerly Cedar Trail - D and Cedar Trail - M]. Refer to Doc ID 449931 for Volume 2. October 2011 Revision 2.0

Intel Confidential

Document Number: 449930

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL? PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel? 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Hyper-Threading Technology requires a computer system with a processor supporting Hyper-Threading Technology and HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you see. See http://www.intel.com/technology/hypertheading/ for more information including details on which processor supports HT Technology. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Click here for details. See the Processor Spec Finder or contact your Intel representative for more information. Intel, Intel Atom and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright ? 2011 Intel Corporation. All rights reserved.

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Contents
1 Introduction ........................................................................................................... 15 1.1 Intel? Atom? Processor D2000 series and N2000 series Features ........................... 15 1.2 System Memory Features ................................................................................... 16 1.3 Direct Media Interface Features ........................................................................... 17 1.4 Graphics Processing Unit Features ....................................................................... 17 1.5 Video............................................................................................................... 18 1.6 Clocking ........................................................................................................... 19 1.7 Power Management ........................................................................................... 19 1.7.1 Terminology .......................................................................................... 20 1.8 References ....................................................................................................... 21 1.9 System Block Diagram ....................................................................................... 23 1.9.1 PHOLD Limitation on Legacy Feature ......................................................... 23 Signal Description.................................................................................................... 24 2.1 CPU Legacy Signal ............................................................................................. 25 2.2 System Memory Interface................................................................................... 27 2.3 DMI - Direct Media Interface ............................................................................... 29 2.4 PLL Signals ....................................................................................................... 29 2.5 Analog Display Signals ....................................................................................... 30 2.6 LVDS Signals .................................................................................................... 31 2.7 DDI Audio Interface ........................................................................................... 32 2.8 DDI Port 0........................................................................................................ 33 2.9 DDI Port1......................................................................................................... 34 2.10 JTAG/ITP Signals ............................................................................................... 35 2.11 Error and Thermal Protection .............................................................................. 35 2.12 Processor Core Power Signals.............................................................................. 36 2.13 Graphics, DMI and Memory Core Power Signals ..................................................... 37 2.14 Ground ............................................................................................................ 38 Functional Description ............................................................................................. 39 3.1 System Memory Controller.................................................................................. 39 3.1.1 System Memory Organization Modes ......................................................... 39 3.1.2 System Memory Technology Supported ..................................................... 39 3.1.3 Rules for populating DIMM slots ............................................................... 41 3.2 Graphics Processing Unit .................................................................................... 41 3.2.1 3-D Core Key Features ............................................................................ 41 3.2.2 2D Engine ............................................................................................. 45 3.2.3 Analog Display Port Characteristics ........................................................... 46 3.2.4 Digital Display Interfaces......................................................................... 47 3.2.5 Multiple Display Configurations................................................................. 53 3.3 Thermal Sensor................................................................................................. 54 3.3.1 PCI Device 0, Function 0 ......................................................................... 54 3.4 Power Management ........................................................................................... 54 3.4.1 Interface Power States Supported............................................................. 54 3.4.2 Intel? Hyper-Threading Technology ......................................................... 54 Electrical Specifications ........................................................................................... 56 4.1 Power and Ground Balls ..................................................................................... 56 4.2 Decoupling Guidelines ........................................................................................ 56 4.2.1 Voltage Rail Decoupling ........................................................................... 56

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4.3 4.4 4.5 4.6 4.7 4.8 4.9

4.10 5

Processor Clocking .............................................................................................57 4.3.1 PLL Power Supply ...................................................................................58 Voltage Identification (VID).................................................................................58 Catastrophic Thermal Protection ..........................................................................64 Reserved or Unused Signals ................................................................................65 Signal Groups ...................................................................................................65 Test Access Port (TAP) Connection .......................................................................65 AC and DC Specifications ....................................................................................66 4.9.1 Flexible Motherboard Guidelines (FMB) ......................................................66 4.9.2 Voltage and Current Specifications ............................................................66 4.9.3 DC Specifications ....................................................................................73 4.9.4 AC Specification......................................................................................82 Processor Power Up Specifications...................................................................... 112

Mechanical Specifications and Ball Information ..................................................... 113 5.1 Mechanical Specifications ................................................................................. 113 5.1.1 Mechanical Drawings ............................................................................ 113 5.1.2 Loading Specifications .......................................................................... 114 5.2 Processor Ballout Assignment for SC and DC ....................................................... 114 Signal Quality Specifications .................................................................................. 134 6.1 Signal Quality Specifications and Measurement Guidelines..................................... 134 6.1.1 Overshoot/Undershoot Guidelines ........................................................... 134 6.1.2 Overshoot/Undershoot Magnitude ........................................................... 135 6.1.3 Overshoot/Undershoot Pulse Duration ..................................................... 135 Power Management ............................................................................................... 137 7.1 ACPI state Supported ....................................................................................... 137 7.1.1 System States...................................................................................... 137 7.1.2 Processor Idle States............................................................................. 137 7.1.3 Integrated Graphics Display States ......................................................... 138 7.1.4 Integrated Memory Controller States ....................................................... 138 7.1.5 DMI states ........................................................................................... 138 7.1.6 Interface State Combinations ................................................................. 139 7.2 Processor Core Power Management .................................................................... 139 7.2.1 Enhanced Intel SpeedStep? Technology .................................................. 139 7.2.2 Dynamic Cache Sizing ........................................................................... 140 7.2.3 Low-Power Idle States........................................................................... 141 7.2.4 Graphics Power Management.................................................................. 143 7.2.5 Thread C-state Description..................................................................... 145 7.2.6 Processor Core/ C-states Description ....................................................... 146 7.2.7 Package C-States ................................................................................. 147 7.3 IMC Power Management ................................................................................... 151 7.3.1 Disabling Unused System Memory Outputs............................................... 151 7.3.2 DRAM Power Management and Initialization ............................................. 151 7.4 DMI Power Management ................................................................................... 152 Thermal Specifications and Design Considerations................................................. 156 8.1 Thermal Specifications...................................................................................... 156 8.1.1 Intel? Thermal Monitor ......................................................................... 157 8.1.2 Digital Thermal Sensor .......................................................................... 159 8.1.3 Out of Specification Detection................................................................. 160 8.1.4 PROCHOT# Signal Pin ........................................................................... 160 Testability ............................................................................................................. 162

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9.1 9.2 10

JTAG Boundary Scan........................................................................................ 162 TAP Instructions and Opcodes ........................................................................... 162

Debug Tool Specifications...................................................................................... 164

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Figures
Figure 1-1D2000 series/N2000 series System Block Diagram ................................................23 Figure 3-2LVDS Signals and Swing Voltage.........................................................................48 Figure 3-3LVDS Clock and Data Relationship.......................................................................48 Figure 3-4Panel Power Sequencing ....................................................................................49 Figure 3-5HDMI Overview ................................................................................................51 Figure 3-6DP Overview ....................................................................................................52 Figure 4-7Vcc and Icc Processor Loadline ...........................................................................68 Figure 4-8Vcc AC Vs DC Loadline ......................................................................................68 Figure 4-9Definition of Differential Voltage and Differential Voltage Peak-to-Peak ....................81 Figure 4-10Definition of Pre-emphasis ...............................................................................82 Figure 4-11V/I Curves for SDO Buffers ..............................................................................85 Figure 4-12V/I Curves for SDI buffers................................................................................85 Figure 4-13V/I Curves for SDO buffers...............................................................................88 Figure 4-14Maximum AC Waveforms for 3.3 V Signaling ......................................................90 Figure 4-15Maximum AC Waveforms for 1.5 V Signaling ......................................................91 Figure 4-16Differential Clock Waveform (measured single-ended) ....................................... 104 Figure 4-17Differential Clock Waveform (using differential probe for measurement) ............... 104 Figure 4-18TAP Valid Delay Timing Waveform ................................................................... 105 Figure 4-19Test Reset (TRST#), Async GTL Input and PROCHOT# Timing Waveform ............. 105 Figure 4-20THERMTRIP # Power Down Sequence .............................................................. 105 Figure 4-21AC Test Circuit ............................................................................................. 106 Figure 4-22LVDS Interface: Load and Transition Time ........................................................ 106 Figure 4-23LVDS Interface: Transmitting Position (Data to Strobe) ...................................... 107 Figure 4-24LDDC_DATA, LDDC_CLK, LCTLA_CLK, LCTLB_DATA, CRT_DDC_DATA, and CRT_DDC_CLK Timing Diagram ................................................................................ 107 Figure 4-25DDR3 DQ Setup/Hold Relationship to/from DQS/DQSB (Read Operation).............. 107 Figure 4-26DDR3 DQ and DM Valid before and after DQS/DQSB (Write Operation) ................ 108 Figure 4-27DDR3 Write Pre-amble Duration...................................................................... 108 Figure 4-28DDR3 Write Post-amble Duration .................................................................... 108 Figure 4-29DDR3 Command Signals Valid before and after CK Rising Edge ........................... 109 Figure 4-30DDR3 CKE Valid before and after CK Rising Edge............................................... 109 Figure 4-31DDR3 CSB Valid before and after CK Rising Edge .............................................. 109 Figure 4-32DDR3 ODT Valid before CK Rising Edge............................................................ 110 Figure 4-33DDR3 Clock Cycle Time.................................................................................. 110 Figure 4-34DDR3 Skew between System Memory Differential Clock Pairs (CK/CKB) ............... 110 Figure 4-35DDR3 CK High Time ...................................................................................... 110 Figure 4-36DDR3 CK Low Time ....................................................................................... 111 Figure 4-37DDR3 DQS Falling Edge Output Access Time to CK Rising Edge ........................... 111 Figure 4-38DDR3 DQS Falling Edge Output Access Time From CK Rising Edge ....................... 111 Figure 4-39DDR3 CK Rising Edge Output Access Time to the 1st DQS Rising Edge ................. 111 Figure 4-40Boot up sequence timing diagram (S5-S0) ....................................................... 112 Figure 5-41 Mechanical Drawings .................................................................................... 113 Figure 5-42 Pinmap (Top View, Upper-Left Quadrant) ........................................................ 114 Figure 5-43 Pinmap (Top View, Upper-Right Quadrant) ...................................................... 115 Figure 5-44 Pinmap (Top View, Lower-Left Quadrant) ........................................................ 116 Figure 5-45Pinmap (Top View, Lower-Right Quadrant) ....................................................... 117 Figure 6-46Overshoot, Undershoot, and Ringback Illustration ............................................. 136 Figure 7-47Idle Power Management Breakdown of the Processor Cores ................................ 142 Figure 7-48Thread and Core C-state Entry and Exit ........................................................... 142 Figure 7-49Processor Core Low-Power States ................................................................... 143 Figure 7-50Package C-state Entry and Exit ....................................................................... 149 Figure 9-51JTAG Boundary Scan Test Mode Initialization Cycles .......................................... 162

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Tables
Table 1-1Summary of the Resolution of Graphic interface .................................................... 18 Table 1-2The Display core clock Frequency by Skus ............................................................ 19 Table 1-327 MHz Requirement Range ................................................................................ 19 Table 2-4Signal Type ...................................................................................................... 24 Table 2-5Signal Description Buffer Types ........................................................................... 24 Table 2-6CPU Legacy Signal ............................................................................................. 25 Table 2-7Memory Channel A ............................................................................................ 27 Table 2-8Memory Reference and Compensation .................................................................. 28 Table 2-9Reset and Miscellaneous Signal ........................................................................... 28 Table 2-10DMI - Processor to Intel NM10 Express Chipset Serial Interface.............................. 29 Table 2-11PLL Signals ..................................................................................................... 29 Table 2-12Analog Display Signals ..................................................................................... 30 Table 2-13LVDS Signals .................................................................................................. 31 Table 2-14DDI Audio Signals............................................................................................ 32 Table 2-15DDI Port 0 ...................................................................................................... 33 Table 2-16DDI Port 1 ...................................................................................................... 34 Table 2-17JTAG/ITP Signals ............................................................................................. 35 Table 2-18Error and Thermal Protection............................................................................. 35 Table 2-19Processor Core Power Signals ............................................................................ 36 Table 2-20Power Signals ................................................................................................. 37 Table 2-21Ground........................................................................................................... 38 Table 3-22Support DRAM Devices ..................................................................................... 40 Table 3-23Supported Memory Size Per Rank ...................................................................... 40 Table 3-24Support Memory Configurations......................................................................... 40 Table 3-25Analog Port Characteristics ............................................................................... 46 Table 3-26Panel Power Sequence Timing Parameters .......................................................... 50 Table 3-27Main Memory States ........................................................................................ 54 Table 4-28PLL Reference Clock ......................................................................................... 57 Table 4-29VRD 12.0 Voltage Identification Definition ........................................................... 58 Table 4-30Processor Core Active and Idle Mode DC Voltage and Current Specifications ............ 66 Table 4-31Istep.............................................................................................................. 68 Table 4-32Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications .............. 69 Table 4-33Input Clocks (BCLK, HPL_CLKIN, DPL_REFCLKIN, EXP_CLKIN) Differential Specification 73 Table 4-34DDR3 Signal Group DC Specifications ................................................................. 73 Table 4-35CPU Sideband CMOS Signal Group DC Specification .............................................. 74 Table 4-36CPU Sideband OD 25 Ohm 1.05V Signal Group DC Specification............................. 75 Table 4-37CPU Sideband OD 12.5 Ohms 1.05 V Signal Group DC Specification........................ 75 Table 4-38CPU Sideband OD 1.8 V Signal Group DC Specification.......................................... 75 Table 4-393.3-V DC Specification...................................................................................... 76 Table 4-401.5-V DC specification ...................................................................................... 76 Table 4-41High Voltage GPIO CMOS Signal DC Specification ................................................. 77 Table 4-42R,G,B/CRT DAC Display DC specification (Functional Operating Range) ................... 77 Table 4-43High Voltage GPIO OD Signal DC Specification ..................................................... 78 Table 4-44CRT_HSYNC and CRT_VSYNC DC Specification..................................................... 79 Table 4-45LVDS Interface DC Specification (Functional Operating Range, VCCLVDS = 1.8 V ±5%) ........................................................................................... 79 Table 4-46DDI Main Transmitter DC specification ................................................................ 79 Table 4-47DDI AUX Channel DC Specification ..................................................................... 81 Table 4-48Input Clock AC Characteristics ........................................................................... 82 Table 4-49High Voltage GPIO OD Signal AC Specification ..................................................... 84 Table 4-50SDO 3.3 V Buffer AC Specification...................................................................... 85

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Table 4-51SDI 3.3 V Buffer AC Specification .......................................................................86 Table 4-52SDO 1.5-V Buffer AC Specification......................................................................88 Table 4-53SDI 1.5-V Buffer AC Specification.......................................................................89 Table 4-543.3 V Parameters for Maximum AC Signalling Waveforms ......................................91 Table 4-551.5V Parameters for Maximum AC Signalling Waveforms .......................................91 Table 4-56Resistance value for the AC rating Waveform.......................................................92 Table 4-57TAP Signal Group AC Specification......................................................................92 Table 4-58Boundary Scan AC Specification .........................................................................92 Table 4-59LVDS Signal Quality Specification .......................................................................93 Table 4-60LVDS Interface AC Characteristics at Various Frequencies......................................93 Table 4-61DDI Main Transmitter AC specification ................................................................96 Table 4-62DDI AUX Channel AC Specification......................................................................98 Table 4-63R,G,B / CRT DAC Display AC Specification ...........................................................98 Table 4-64CRT_HSYNC and CRT_VSYNC AC Specification .....................................................99 Table 4-65LDDC_DATA, LDDC_CLK, LCTLA_CLK, LCTLB_DATA, CRT_DDC_DATA, and CRT_DDC_CLK Timing Specification .......................................................................... 100 Table 4-66DMI Interface Timing...................................................................................... 100 Table 4-67DDR3 Interface Timing Specification ................................................................. 101 Table 5-68Processor Ball list by Ball Name ....................................................................... 117 Table 6-69Input Signal Group Ringback Duration Specification ............................................ 135 Table 7-70System States ............................................................................................... 137 Table 7-71Processor Core/ States Support ....................................................................... 137 Table 7-72Integrated Graphics Display Device Control ....................................................... 138 Table 7-73Main Memory States....................................................................................... 138 Table 7-74DMI States.................................................................................................... 138 Table 7-75G, S and C State combinations......................................................................... 139 Table 7-76D, S and C state Combinations ........................................................................ 139 Table 7-77Coordination of Thread Low-power States at the /Core Level................................ 143 Table 7-78Coordination of Core Power States at the package Level...................................... 148 Table 8-79Power Specifications for the Standard Voltage Processor (updated)....................... 157 Table 9-80Supported TAP Instructions ............................................................................. 163

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Revision History
Document Number 449930 Revision Number 0.5 ? Initial Release General Updates ? Updated Max Pixel for VGA value up to 350 MHz ? Removed DVI information ? Removed all information related to BCLK ? Updated the Deep Power Down technology (code named C6) related information Chapter 1 ? Updated Table 1-1 - DP N2000 series 162 MHz, VGA (N2000 series max at 267 MHz and D2000 series at 355 MHz) ? General Update on Section 1.4, “Graphics Processing Unit Features” on page 12 ? General Update on Section 1.6, “Clocking” on page 13 Chapter 2 ? Updated Table 2-4 - added HV_GPIO_RCOMP and MV_GPIO_RCOMP and updated the PREQ# pull-up connection ? Updated Table 2-8- changed DMI_IREF1P8 to DMI_REF1P5 ? Updated Table 2-13 - changed BREF18V to BREF1P5 449930 0.7 ? Updated Table 2-17: Added SVID_CLK frequency details. Chapter 3 ? Updated Section 3.2.5, “Multiple Display Configurations” on page 45 - Removed Window*2000, XP and Vista* Chapter 4 ? Added the SKU based Iccmax & I_TDC number to Table 4-27 and Table 4-28. ? Updated Table 4-32 — In Note-5 name change to PROCHOT#, PBE# and THERMTRIP# — In Note-6 name change to TRST#, CPUSLP#, PBE#, INIT#, SMI#, DPRSTP#, DPLSLP#, STPCLK# and SVID_ALERT#. ? Updated Table 4-31 - added Input Leakage current. ? Updated Table 4-33 - Note-5 SVID_ALERT# removed ? Updated Table 4-34 - In Note-5 changed PREY# and PREQ# ? Updated Table 4-35 - In Note-5 changed RESET# ? Added Table 4-26, “PLL Reference Clock” on page 49 PLL reference clock ? Updated Table 4-38 - Note-3 changed October 2010 Description Date May 2010

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Document Number 449930

Revision Number 0.7

Description ? Updated Figure 4-7, “V/I Curves for SDO buffers” on page 78 for TJSU,TJH and TJCO ? Added Section 4.9.3.3, “Intel? HD Audio DC Specification” on page 65 ? Added Section 4.9.4.3, “Intel? HD Audio AC Specification” on page 74 Chapter 5 ? Figure 5-39, “Pinmap (Top View, Lower-Right Quadrant)” on page 107 & Table 5-66, “Processor Ball list by Ball Name” on page 107: Updated pin names of BREF1P5 & DMI_REF1P5 and Newly Added the STRAP_L27 and STRAP_K28 Chapter 1 ? Updated Section 1.2, “System Memory Features” Modified the Raw Card RC-A (2Rx16) to do not support categories. Chapter 4 ? Updated Table 4-30 - added VCCGFX,BOOT detail.

Date October 2010

449930

0.71

? Updated Table 4-47 - removed high period of SCL Clock max of 0.8 ?s Chapter 5 ? Updated Table 5-66 & Figure 5-37 - updated the pin naming from LINT00 and LINT10 to INTR/LINT00 and NMI/LINT10 respectively. ? Updated Table 5-66 - updated BREF1P5 signal Chapter 1 ? Section 1.3 - Updated the DMI lane due to POR changed ? Section 1.4 and Table 1-1 - Updated LVDS support 18 bpp and 24 bpp ? Table 1-2- Added the 27 MHz clock requirement Chapter 2 ? Table 2-14 — Updated DDI0_DDC_SDA, DDI0_DDC_SCL Description — Updated BREFREXT pull up voltage supply ? Table 2-15 - Updated DDI1_AUXP, DDI1_AUXN, DDI1_HPD, DDI1_DDC_SDA and DDI1_DDC_SCL description ? Table 2-19- VCCDIO voltage updated to 1.05 V and description updated to CRT digital voltage only Chapter 3 ? Section 3.2.4.1, “LVDS” - Removed the irrelevant sentence on two channel LVDS ? Section 3.2.4.2, “LVDS Pair States” & Section 3.2.4.3, “Single Channel Mode” - Removed the irrelevant information on common mode ? Section 3.2.4.9,Section 3.2.4.10 & Section 3.2.4.11 Newly inserted eDP, DP Aux Channel & DP Hot-Plug Detect (HPD)

November 2010

449930

1.0

December 2010

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Document Number

Revision Number Chapter 4

Description

Date

? Table 4-29 - Updated Vcc_HFM, Vcc_LFM and Icc ? Table 4-30 — Updated VCCGFX - AVID and VCCGFX — Updated the Max and I_TDC current ? Table 4-32 - Updated input leakage current to 40 ?A ? Table 4-36 - Updated input Leakage Current to ±30 ?A (PRDY) and ±15 ?A (PREQ) 449930 1.0 ? Table 4-38 & Table 4-41 - Updated input leakage current to ±45 ?A ? Table 4-43 - insert input leakage current to 40 ?A ? Table 4-44 - Updated CTX symbol and added Notes 5 ? Table 4-45 - Updated CAUX symbol and added Notes 6 ? Removed Table 4-41 - LVDS interface DC specification table which is redundant with current Table 4-42 Chapter 8 ? Table 8-76 - update D2500, D2700, N2600 and N2800 core frequency range. Chapter 1 ? Section 1.1- Updated the package technologies to FCBGA11 449930 1.1 ? Section 1.2 - Updated the Max Memory size by sku Chapter 4 ? Table 4-27 - Updated the DPL_REFSSCCLKP, DPL_REFSSCCLKN required all time. ? Table 4-33- Updated VIH and VIL information Chapter 1 ? Section 1.1 — Corrected the 4-way to 8-way L1 instructions cache ? Section 1.2 — Corrected the memory size unit from MB to GB — update the CDV-M fanless only support one DIMM configuration. ? Section 1.4 — Update to DirectX 10.1 and OGL 3.0 — Update to DP and eDP to 1.1 — Include HDCP and PAVP detail ? Section 1.5 — Update of WMV, MPEG4 part 2 and part 10 detail Chapter 3 ? Added Section 3.2.4.13, “PAVP (Protected Audio and Video Path)” Chapter 4 ? Table 4-30 - Included Graphic core supply loadline ? Table 4-35 - Update Ii range from -15 to 15 ?A ? Added Section 4.9.4, “AC Specification” ? Figure 4-35 - Updated SLP_S3# January 2011 December 2010

449930

1.5

April 2011

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Document Number

Revision Number Chapter 5

Description

Date

449930

1.5

? Figure 5-38 & Table 5-68 - Updated to INTR/LINT00 (pin D20) and NMI/LINT10 (pin C22) Chapter 7 ? Section 7.2.5.2 - Changed RSTINB to RESET# ? Added Section 7.2.4, “Graphics Power Management” General ? Updated all Processor code name to Marketing Code name Chapter 1 ? Section 1.2 - Removed x16 chip data bit information ? Section 3.1.2- Removed all x16 chip data bit information Chapter 2 ? Table 2-4 - Updated DMI signal description ? Table 2-5 - Updated PRDY# and PREY# ? Table 2-12- Updated the LVDS_DDC_CLK, LVDS_DDC_DATA, LVDS_CTRL_CLK and LVDS_CTRL_DATA signal description

April 2011

449930

1.6

Chapter 4 ? Figure 4-2 - Updated the Vcc Tolerance ? Figure 4-3 - Added new figure on the Vcc AC Vs DC ? Table 4-29 - Updated LFM VID by sku ? Table 4-31 - Updated Vccgfx Range for N2000 series Chapter 7 ? Removal of Intel? Rapid Memory Power Management (Intel? RMPM) (also known as CxSR) & The Intel? Atom? Processor D2000 series and N2000 series Smart 2D Display Technology (Intel? S2DDT) Chapter 8 ? Section 8.1.2- Updated the notes DTS range detail information.

June 2011

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Document Number

Revision Number Chapter 1

Description

Date

? Section 1.1 - Updated 32KB 4-way L1 instruction cache ? Section 1.2 - Updated the Page Size of 1 KB and 2 KB, DRAM Chip Data Width: x8 and x16 and Supports Max densities 1Gbit, 2Gbit for both x8 and x16 for DDR3 ? Section 1.4 — Updated Clock frequency and render clock frequency information — Updated to latest Icc max value for Vcc core and VccGfx ? Section 1.6 — Updates on memory clocks and display clock non-SSC for display PLL — Included the display core clock frequency information — Updates to support DX*9. Chapter 2 ? Table 2-11 - Updated DAC_IREF resistor value change from 680 Ohms to 649 Ohms ? Table 2-19 - Updated VCCADMI_SFRPLL Chapter 3 ? Updated Tables Table 3-22, Table 3-23, Table 3-24 for memory Raw card A & C Chapter 4 ? Table 4-31- Updated VCCRAMxxx D2000 series and VCCADMI_SFRPLL ? Table 4-28 - Clock updates ? Section 4.3 - Updated clock related information ? Table 4-48 - Removed the irrelevant clock speeds 166 MHz and 200 MHz ? Table 4-29 and Table 4-31 - Updated Iccmax and Itdc values ? Table 4-47- Updated the parameter for DMI DC spec ? Table 4-45 & Table 4-60 - Updated the DDI HDMI parameters Chapter 5 ? Figure 5-41 - Updated mechanical drawing ? Table 5-68 - Updated DDR3_DRAMRST# from ‘I’ to ‘O’ Chapter 7 ? Updated the States in Section 7.1.2 Section 7.2.7; Table 7-71 and Table 7-74 Chapter 8 ? Table 8-79 - Updated the CPU frequency range and power data.

449930

2.0

October 2011

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Revision Number Descriptions Revision 0.5 0.6–0.7 0.7 0.8–0.9 1.0 1.1–1.4 1.5 1.6–1.9 NDA - 2.0 Public - XXXXXX-001 2.1 and up Associated Life Cycle Milestone Design Win Phase When Needed Simulations Complete When Needed First Silicon Samples When Needed Qualification Silicon Samples When Needed First SKU Launch When Needed Release Information Required Release Project Dependent Required Release Project Dependent Required Release Project Dependent Project Dependent Project Dependent Required Release Product Launch Project Dependent

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Introduction

1

Introduction
This External Design Specification (EDS) provides Direct Current (DC) and Alternate Current (AC) electrical specifications, signal integrity, differential signaling specifications, pinout and signal definitions, interface functional descriptions, and additional feature information pertinent to the implementation and operation of the processor on its respective platform.

Note:

Throughout this document, the Intel? Atom? Processor D2000 series and N2000 series processor is referred to as processor and Intel? NM10 Express Chipset is referred to as chipset. The processor is built on 32-nanometer Hi-K process technology. The processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, GMCH, and ICH). The two-chip platform consists of a processor and the chipset and enables higher performance, lower cost, easier validation, and improved xy footprint. Included in this family of processors is an integrated memory controller (IMC), integrated graphics processing unit (GPU) and integrated I/O on a single silicon die. This single die solution is known as a monolithic processor.

1.1

Intel? Atom? Processor D2000 series and N2000 series Features
The following list provides some of the key features on this processor:

? On die, primary 32kB, 4-way L1 instructions cache and 24kB, 6-way L1 write-back
data cache

? Intel? Hyper-Threading Technology 2-threads per core except for D2500 - no HT
support

? 512-kB, 8-way ECC protected L2 cache per core processor ? Support for IA 32-bit ? Intel? Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and Supplemental
Streaming SIMD Extensions 3 (SSSE3) support

? Intel? 64 architecture ? Micro-FCBGA11 packaging technologies ? Thermal management support via Intel? Thermal Monitor (TM1 & TM2) - ELD TM1
only

? Supports C0 and C1 states only for D2000 series; C0-C4, C1E-C4E and Deep Power
Down Technology (code named C6) state for N2000 series processor

? Execute Disable Bit support for enhanced security

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Introduction

1.2

System Memory Features
? One channel of DDR3 ? memory (consists of 64 data lines):
— Maximum of two SODIMMs per channel for D2000 series and N2800 Processor performance, containing single or double-sided SODIMM — Maximum of one SODIMMs per channel for N2600 series Processor only, containing single or double-sided SODIMM - Please refer to CDT-M PDG for single DIMM slot configuration design.

? Memory DDR3 data transfer rates of 800 MT/s (6.4 GB/s) and 1066 MT/s
(8.5 GB/s)

? Only non-ECC SODIMMs are supported ? Support Small Outline DIMMs Raw Cards RC-A (2Rx16), RC-B(1Rx8), RC-C (1Rx16)
and RC-F (2Rx8). — Does not support RC-D (2Rx16 dual die), and RC-E(2Rx16) — Please refer to CDT PDGs for detail platform supportable Memory Configuration and limitation.

? Support unbuffered SODIMMs ? I/O Voltage of 1.5 V for DDR3 ? Max memory size by sku: N2600 series 2 GB; N2800, D2500 & D2700 series 4 GB ? Supports total memory size of 512 MB, 1 GB, 2 GB and 4 GB max ? Supports Max densities 1Gbit, 2Gbit, 4Gbit for both x8 and x16 for DDR3 ? DRAM Chip Data Width: x8 and x16 ? Banks / DRAM Chip: 8 ? Support up to 32 simultaneous open pages per channel (assuming 4 ranks of
8 devices)

? Support Partial Writes to memory using Data Mask signals (DM) ? Enhances Address Mapping ? Support DIMM page size of 1 KB and 2 KB ? Support data burst length of 8 and Burst Chopped of 4 for all memory
configurations

? Support memory thermal management scheme to selectively manage reads and/or
writes. Memory thermal management can be triggered by either on-die thermal sensor, or by preset limits. Management limits are determined by weighted sum of various commands that are scheduled on the memory interface.

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1.3

Direct Media Interface Features
? Compliant to Direct Media Interface (DMI) ? Support 2 lanes in each direction for N2000 series processor and 4 lanes in each
direction for D2000 series, Gen1 (2.5 Gbps) per lane per direction, point-to-point DMI interface to Intel? NM10 Express Chipset or PCH respectively.

? The N2000 series processor can only work on boards that have a DMI x2
connection. It will not work on a board with a DMI x4 connection. While the D2000 series processor is only work on the board have a DMI x4 connection.

? 100 MHz reference. ? Support 64 bit downstream address (only 36-bit addressable from CPU) ? Support APIC messaging support. Will send Intel-defined “End of Interrupt”
broadcast message when initiated by CPU.

? Support messaging in both directions, including Intel-Vendor specific messages. ? Support Message Signal Interrupt (MSI) messages. ? Support Power Management state change messages. ? Support SMI, SCI and SERR error indication. ? Support PCI INTA interrupt from CHAP Counters device and Integrated Graphics. ? Support Intel? NM10 Express Chipset with on board hybrid AC-DC coupling
solution.

? Support polarity inversion (However, NM10 does not support)

1.4

Graphics Processing Unit Features
? Support Directx*9 compliant Pixel Shader* v3.0 and OGL 3.0 ? 640 MHz (D2700 & N2800) and 400 MHz (D2500 & N2600) graphic core frequency ? 200MHz render clock frequency ? Seven display planes, Display Plane A, B, Display Sprite C (can be connected to
either pipes), Display OV (can be connected to either pipes), Cursor A, Cursor B, and VGA

? Two display pipes, Pipe A and B support the dual independent displays ? Max Pixel Clock: SC LVDS: 112 MHz, 18bpp (N2000 series) & 18bpp and 24bpp
(D2000 series); DDI: 2x 4, 1.62GHz, 2.7GHz; VGA: up to 350MHz

? Display Ports: eDP/DP x4, HDMI, LVDS (single channel), CRT/DAC ? Embedded panel: eDP1.1 or LVDS ? External panel: DP1.1, HDMI1.3a, LVDS, CRT/DAC. ? Supports HDCP 1.3 & PAVP1.1c (D2700 & N2800 processor) for Blu-ray playback
while HDCP is needed for High Definition playback in D2000 series and N2000 series processor

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Introduction

— PAVP: Collection of HW-based security mechanisms designed to provide a secure path for content from a media player application to the graphics hardware — HDCP: Specification developed by Intel Corporation to protect digital entertainment content across the DVI interface
?

Subsequently ported to HDMI and Display Port

? Supports HDMI 1.3a through SW lip-sync ? Supports DX*10: 64-bit FP color format, NPO2 Tiling, and 180 degree rotation ? Supports NV12 data format ? 3x3 Panel Fitter shared by two pipes ? Support Intel HD Audio Codec ? Support Intel? Display Power Saving Technology (Intel? DPST) 4.0 ? No Frame Buffer Compensation (FBC) ? No TVOut
Table 1-1. Summary of the Resolution of Graphic interface
Interfaces LVDS (Single Ch) Processor N2000 series D2000 series N2000 series D2000 series N2000 series D2000 series N2000 series D2000 series N2000 series D2000 series Max Resolution 1366 x 768 1440 x 900 1366 x 768 1920 x 1080 1920 x 1200 1920 x 1200 1600 x 1200 2560 x 1600 1920 x 1200 1920 x 1200 60 Hz; 18 bpps 60 Hz; 18 & 24 bpps 60 Hz 60 Hz 60 Hz at 267 MHz Max 60 Hz at 355 MHz Max 60 Hz with 4 lanes at 162 MHz link clock 60 Hz with 4 lanes at 270 MHz link clock 60 Hz; up to 165MHz 60 Hz; up to 165MHz Remark

eDP

VGA (CRT/DAC)

DP

HDMI/ DVI

1.5

Video
? The Intel? Atom? Processor D2000 series and N2000 series supports full MPEG2
(VLD/ iDCT/MC), WMV, Fast video Composing, HW decode/ acceleration for MPEG4 Part 10 (AVC/H.264) & VC-1; 720p60, 1080i60, 1080p@24 up to 20 Mps

? MPEG4 part2 does not utilize Next Generation Intel? Atom? Processor based
(Desktop and Mobile) Platform H/W

? No hardware assist for Flash Decode from Adobe 11.0 and onwards ? D2700 and N2800 processor supports Blu-Ray* 2.0 playback - 1 x HD and 1 x SD
streaming

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? Video image Enhancement: Hue, Saturation, Brightness, Contrast (HSBC) adjust,
Bob De-Interlacing

? Support two Streams of 1080p HD @ 267 MHz

1.6

Clocking
? Differential Host clock of 100 MHz (HPL_CLKINP/HPL_CLKINN). ? Memory clocks - 100MHz differential for both DDR3-800 and DDR3-1066
— When running DDR3-800 or DDR3-1066, the 1x memory clocks is generated from internal Host PLL and the 2x memory clock is generated from Memory PLL

? The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN) generates the
DMI core clock of 250 MHz.

? Display timings are generated from display PLLs that use a 96 MHz differential nonSSC for VGA only, and 100 MHz differential clock with SSC or non-SSC as reference.

? Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled
until PWROK is asserted.

? The Display core clock Frequency by Skus
Table 1-2. The Display core clock Frequency by Skus
Display Core Clock Frequency/ MHz D2500 355 D2700 355 N2600 200 N2800 267 Remark

? 27 MHz crystal is needed to resolve digital display quality concerns.
Table 1-3. 27 MHz Requirement Range
Min/MHz 26.9919 Nominal/ MHz 27 Max/MHz 27.0081 Remark 300ppm

1.7

Power Management
? PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3) ? SMRAM space remapping to A0000h (128 kB) ? Support extended SMRAM space above 256 MB, additional 1MB TSEG from the base
of graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by CPU).

? ACPI Rev 1.0b compatible power management ? Support CPU states: C0 and C1 (for D2000 series); C0-C4, C1E-C4E, Deep Power
Down Technology (code named C6)(for N2000 series)

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? Support System states: S0, S3, S4 and S5 ? Support CPU Thermal Management (TM1 & TM2) while D2000 series is TM1 only

1.7.1

Terminology
Term BGA BLT CRT DDR3 DMA DMI DTS ECC Execute Disable Bit Ball Grid Array Block Level Transfer Cathode Ray Tube Third generation Double Data Rate SDRAM memory technology Direct Memory Access Direct Media Interface Digital Thermal Sensor Error Correction Code The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel? 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Micro Flip Chip Ball Grid Array Legacy component - Graphics Memory Controller Hub. Platforms designed for the N2000 series and D2000 series do not use an (G)MCH. Graphics Processing Unit The legacy I/O Controller Hub component that contains the main PCI interface, LPC interface, USB2, Serial ATA, and other I/O functions. It communicates with the legacy (G)MCH over a proprietary interconnect called DMI. Platforms designed for the Intel? Atom? Processor D2000 series and N2000 series do not use an ICH. Integrated Memory Controller 64-bit memory extensions to the IA-32 architecture. Liquid Crystal Display Last Level Cache. The LLC is the shared cache amongst all processor execution cores Low Voltage Differential Signaling A high speed, low power data transmission standard used for display connections to LCD panels. MCP NCTF Multi-Chip Non-Critical to Function: NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. Description

Micro-FBGA (G)MCH

GPU ICH

IMC Intel? 64 Technology LCD LLC LVDS

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Term Processor Processor Core

Description The 64-bit, multi-core component The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SO-DIMM. System Control Interrupt. Used in ACPI protocol. Simultaneous Multi-Threading A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Thermal Averaging Constant Thermal Design Power Top of Memory Time-To-Market Processor core power supply Processor ground Graphics core power supply DDR3 power rail Variable Length Decoding

Rank

SCI SMT Storage Conditions

TAC TDP TOM TTM VCC VSS VCCGFX V_SM VLD

1.8

References
Material and concepts available in the following documents may be beneficial when reading this document:
Document Intel? Atom? Processor D2500, D2700, N2600 and N2800 Series Processor Thermal/Mechanical Specifications and Design Guidelines RS - Intel? Atom? Processor D2500, D2700, N2600 and N2800 Series BIOS Writer’s Guide (BWG) IMVP 7 - Intel? Atom? Processor D2500, D2700, N2600 and N2800 Series Processor Power Delivery Design Guidelines Cedar Trail-M Platform Design Guide Cedar Trail-D Platform Design Guide 449933 449934 Note 1 Document Number

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Introduction

Document Intel? Atom? Processor D2500 and D2700 Series Dual-Core – Boundary Scan Description Language (BSDL) File (pending publication) Intel? NM10 Express Chipset – External Design Specification (EDS) Intel? NM10 Express Chipset – Thermal and Mechanical Design Guide [Cedar Trail] Platform – Debug Port Design Guide Intel? 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide NOTES: 1. Contact your Intel representative for the latest revision of this document.

Document Number 450082 413547 417912 447561

http:// www.intel.com/ products/processor/ manuals/index.htm

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1.9

System Block Diagram

Figure 1-1. D2000 series/N2000 series System Block Diagram

VG A

Analog Display

System M em ory D DR2/3 DD R 3

D P/ eD P
CH A

LVD S HDMI

C PU
DD R 3 800/1067 M hz :

DMI

U SB 2. 0 8 Ports G PIO SATA 2 Ports Intel? High D efinition Audio C odec(s) SPI Flash

Pow er M anagem ent C lock G eneration

N M 10 Express C hipset

SM Bus2.0 / I2 C

G b LAN

SPI LPC
PC Ie Bus

W LAN 4 PC Ie Slots

Firm ware

SIO

1.9.1

PHOLD Limitation on Legacy Feature
PHOLD protocol is a mechanism for ISA to lock the system so that it can do a DMA. Hence, the Intel? Atom? Processor D2000 series and N2000 series does NOT support PHOLD protocol which impacts the devices behind LPC (ISA) Super I/O only (No LPC mastering is allowed). These will need to be connected via USB adaptor if required. This will not impact other legacy devices such as serial port, keyboard/mouse as well as USB based peripheral. If one of these devices are connected to LPC and a PHOLD is requested, CDV will drop the request, set an error bit, and the system will immediately hang.

§

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Signal Description

2

Signal Description
This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type:

Table 2-4. Signal Type
Notations I O I/O Signal Type Input Pin Output Pin Bi-directional Input/Output Pin

The signal description also includes the type of buffer used for the particular signal. Table 2-5. Signal Description Buffer Types
Signal CMOS DMI CMOS buffers. 1.05 V tolerant Direct Media Interface signals. These signals are compatible with PCI Express 1.0 Signalling Environment AC Specifications but are DC coupled. The buffers is 1.05V/1.08V and not 3.3 V tolerant. High Voltage buffers. 3.3 V tolerant DDR3 buffers: 1.5 tolerant Open Drain Gunning Transceiver Logic signaling technology. Refer to GTL+ I/O Specification fro complete details. Test Access Port signal Analog reference or output. May be used as a threshold voltage or for buffer compensation Voltage reference signal This signal is asynchronous and has no timing relationship with any reference clock. Low Voltage Differential Signalling. A high speed, low power data transmission standard used for display connections to LCD panels. Description

HVCMOS DDR3 GTL+ TAP Analog Ref Asynch LVDS

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2.1

CPU Legacy Signal

Table 2-6. CPU Legacy Signal (Sheet 1 of 2)
Signal Name EXTBGREF HV_GPIO_RCOMP MV_GPIO_RCOMP PBE# Description External Band gap Reference. SOC and Core Debug feature. RCOMP for 3.3V GPIO pins: 50 ohm 1% PD to VSS. RCOMP for DFX_GPIO_GRPx pins: 50 ohm 1% PD to VSS. When STPCLK# is not asserted, the Intel? Atom? Processor D2000 series and N2000 series processor will always deassert PBE#. Direction I N/A N/A Type Core Analog Analog Analog

Core O Open Drain

The Intel? Atom? Processor D2000 series and N2000 series processor is always allowed to use PBE to request a break to
C0 - even if in C4 and in Deep Power Down Technology (code named C6) INIT# INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. CPU then restarts at the reset vector. Snoops are handled during INIT# assertion. Interrupt Request/Local APIC Interrupt 0: When the APIC is disabled, the LINT0 signal becomes INTR, a maskable asynchronous interrupt request signal. This signal (and NMI/LINT1) must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. NMI/ LINT10 Non-Maskable Interrupt Request/Local APIC Interrupt 1: When the APIC is disabled, the LINT1 signal becomes NMI, a non-maskable asynchronous interrupt request signal. This signal (and INTR/LINT0) must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. CPUPWRGOOD CPUPWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Rise time and monotonicity requirements are shown in Chapter 4 Electrical Specifications. CPUPWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of CPUPWRGOOD. It must also meet the minimum pulse width specification. The CPUPWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

I

Core CMOS

INTR /LINT00

I

Core CMOS

I

Core CMOS

I

Core CMOS

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Signal Description

Table 2-6. CPU Legacy Signal (Sheet 2 of 2)
Signal Name SMI# Description System Management Interrupt. When asserted, CPU enters System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. Stop Clock: When asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units, except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. PRDY# PREQ# Probe Mode Ready: CPU’s response to PREQ# assertion. Indicates CPU is in probe mode. Input unused. Probe Mode Request: Assertion is a Request for the CPU to enter probe mode. CPU will response with PRDY# assertion once it has entered. PREQ# can be enabled to cause the CPU to break from C4 and C6. External 51-Ohms resistor to 1.8 V. CPUSLP# DPRSTP# CPI Sleep DPRSTP# when asserted on the platform causes the processor to transition from Deep Sleep State to the Deeper Sleep State. In order to return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the chipset. This function is supported for N2000 series only processor DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep State. In order to return to the Sleep State, DPSLP# must be de-asserted. DPSLP# is driven by the chipset. This function is supported for N2000 series only processor. I CMOS Core CMOS O CMOS Direction Type Core CMOS

I

STPCLK#

I

Core CMOS

I

CMOS

I

DPSLP#

I

Core CMOS

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2.2

System Memory Interface

Table 2-7. Memory Channel A
Signal Name DDR3_CK[3:0] DDR3_CK#[3:0] DDR3_CS#[3:0] DDR3_CKE[3:0] Description SDRAM and inverted Differential Clock: (3pairs per DIMM) The differential clock pair is used to latch the command into DRAM. Each pair corresponds to rank on DRAM side. Chip Select: (1 per Rank). Used to qualify the command on the command bus for a particular rank. Clock Enable: (power management - 1 per Rank) It is used during DRAM power up/power down and Self refresh. DDR3_MA[15:0] Multiplexed Address. Memory address bus for writing data to memory and reading data from memory. These signals follow common clock protocol w.r.t. CK/CK# pairs Bank Select: These signals define which banks are selected within each SDRAM rank Write Enable Control Signal: Used with SA_WE# and SA_CAS# (along with, control signal, SA_CS#) to define the SDRAM Commands. Write Enable Control Signal: Used with SA_WE# and SA_CAS# (along with control signal, SA_CS#) to define the SDRAM Commands. Write Enable Control Signal: Used with SA_WE# and SA_CAS# (along with control signal, SA_CS#) to define the SDRAM Commands. Data Lines. Write Enable Control Signal: Used with SA_WE# and SA_CAS# (along with control signal, SA_CS#) to define the SDRAM Commands. Write Enable Control Signal: Used with SA_WE# and SA_CAS# (along with control signal, SA_CS#) to define the SDRAM Commands. Data Strobes: SA_DQS[7:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write transactions. For Read, the Strobe crossover and data are edge aligned, whereas in the Write command, the strobe crossing is in the centre of the data window. ODT signal going to DRAM in order to turn ON the DRAM ODT during Write. O DDR3 O DDR3 Direction Type

O

DDR3

O

DDR3

DDR3_BS[2:0] DDR3_RAS#

O

DDR3

O

DDR3

DDR3_CAS#

O

DDR3

DDR3_WE#

O

DDR3

DDR3_DQ[63:0]

I/O

DDR3

DDR3_DM[7:0]

O

DDR3

DDR3_DQS[7:0] DDR3_DQS#[7:0]

I/O

DDR3

DDR3_ODT[3:0]

O

DDR3

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Table 2-8. Memory Reference and Compensation
Signal Name DDR3_ODTPU Description This signal needs to be terminated to VSS on board using the RES of 275 ohms. This external resistor termination scheme is used for Resistor compensation of DDR ODT strength. This signal needs to be terminated to VSS on board using the RES of 35 ohms. This external resistor termination scheme is used for Resistor compensation of DQ buffers This signal needs to be terminated to VSS on board using the RES. This external resistor termination scheme is used for Resistor compensation of CMD buffers. Please refer to reference board design for RES value DDR interface Reference Voltage This signal indicates the status of 1.5-V power supply. I DDR3_MON1P DDR3_MON1N DDR3_MON2P DDR3_MON2N DDR3_REFP DDR3_REFN NOTE: Please refer to appropriate platform design guide for connections recommendations. 100MHz Differential Board clock input for DDR PLL. I Different ial Clock These signals are for internal electrical validation. They do not carry functionality on customer platform Direction O Type Analog

DDR3_DQPU

O

Analog

DDR3_CMDPU

O

Analog

DDR3_VREF DDR3_DRAM_PWROK

I

Analog Asynchro nous CMOS

O

CMOS

Table 2-9. Reset and Miscellaneous Signal (Sheet 1 of 2)
Signal Name PWROK/ DDR3_VCCA_PWROK HPLL_REFCLK_P, HPLL_REFCLK_N RESET# Description PowerOK: Asserted once the VRM is settled. Used primarily in the DDR PHY to determine S3. Differential refclk for the Intel? Atom? Processor D2000 series and N2000 series processor's HPLL. The “_P” signal corresponds to the rising edge of the internal clock. 100 MHz. 100 MHz Reset: Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will de-assert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is de-asserted. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RESET# de-assertion. I CMOS Direction I Type CMOS

I

CMOS

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Table 2-9. Reset and Miscellaneous Signal (Sheet 2 of 2)
Signal Name RSVD_* RSVD_NCTF_* RSVD_TP_* XDP_RSVD_[17:0] Description Reserved. Must be left unconnected on the board. Intel does not recommend a test point on the board for this ball. Reserved/non-critical to function. Pin for mechanical reliability. A test point may be placed on the board for this ball. Reserved-test-point. A test point may be placed on the board for this ball. Reserved XDP debug signals. Direction NC I/O I/O Type

NOTE: RSVD_* numbering needs to be observed for BSDL testing purposes.

2.3

DMI - Direct Media Interface

Table 2-10.DMI - Processor to Intel NM10 Express Chipset Serial Interface
Signal Name DMI_RXP[3:0] DMI_RXN[3:0] DMI_TXP[3:0] DMI_TXN[3:0] Description DMI input from Intel NM10 Express Chipset: Direct Media Interface receive differential pair. DMI output to Intel NM10 Express Chipset: Direct Media Interface transmit differential pair. Connects externally to a 7.5 kOhms pull-up to 1.5 V (DMI_REF1P5) DMI_RCOMP This pin and the external resistor is used to set internal bias level. Package resistance must be less than 0.15 Ohms for this Bump. DMI_REF1P5 current reference for DMI. Connects to 1.5 V I I Direction I O Type DMI DMI

2.4

PLL Signals

Table 2-11.PLL Signals (Sheet 1 of 2)
Signal Name DDR3_REFP DDR3_REFN HPLL_REFCLK_N HPLL_REFCLK_P DMI_REFCLKP DMI_REFCLKN DPL_REFCLKN DPL_REFCLKP Differential PLL Clock In. 27 MHz XTAL required to reduce error to <1000 ppm I Differential DMI Clock In I Differential Host Clock In I Description Differential DDR3 I/O Clock In Direction I Type Diff Clk CMOS Diff Clk CMOS Diff Clk CMOS Diff Clk CMOS

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Table 2-11.PLL Signals (Sheet 2 of 2)
Signal Name DPL_REFSSCLKN DPL_REFSSCLKP Description Differential Spread Spectrum Clock In Direction I Type Diff Clk CMOS

2.5

Analog Display Signals

Table 2-12.Analog Display Signals
Signal Name CRT_RED Description RED Analog Video Output: this signal is a CRT analog video signal output from the internal color palette DAC. The DAC is designed to drive a double terminated 75 Ohm DC resistance without the need for external buffering. A dual 150 Ohm termination scheme is implemented on the board for optimal signal integrity: one 150 Ohm termination to ground placed in close proximity to the chip and one 150 Ohm termination resistor to ground placed in close proximity to the VGA connector. The equivalent DC resistance of the two 150 Ohm termination resistors with the 75 Ohm termination within the CRT display is 37.5 Ohms (DC). GREEN Analog Video Output: this signal is a CRT analog video signal output from the internal color palette DAC. The DAC is designed to drive a double terminated 75 Ohm DC resistance without the need for external buffering. A dual 150 Ohm termination scheme is implemented on the board for optimal signal integrity: one 150 Ohm termination to ground placed in close proximity to the chip and one 150 Ohm termination resistor to ground placed in close proximity to the VGA connector. The equivalent DC resistance of the two 150 Ohm termination resistors with the 75 Ohm termination within the CRT display is 37.5 Ohms (DC). BLUE Analog Video Output: this signal is a CRT analog video signal output from the internal color palette DAC. The DAC is designed to drive a double terminated 75 Ohm DC resistance without the need for external buffering. A dual 150 Ohm termination scheme is implemented on the board for optimal signal integrity: one 150 Ohm termination to ground placed in close proximity to the chip and one 150 Ohm termination resistor to ground placed in close proximity to the VGA connector. The equivalent DC resistance of the two 150 Ohm termination resistors with the 75 Ohm termination within the CRT display is 37.5 Ohms (DC). CRT_IRTN: this signal is the complement video signal output from the internal color palette DAC channels and this signal connects directly to the ground plane of the board DAC_IREF Resistor: resistor for the internal color palette DAC reference circuit. A 680 Ohm 0.5% resistor is required to be connected between DAC_IREF and the board ground plane. CRT Horizontal Synchronization: This signal is used as the vertical sync (polarity is programmable) or “sync interval”. 3.3V output. Direction Type

O

Analog

CRT_GREEN

O

Analog

CRT_BLUE

O

Analog

CRT_IRTN

O

Analog

DAC_IREF

O

Analog

CRT_HSYNC

O

HVCMOS

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Table 2-12.Analog Display Signals
Signal Name CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA Description CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable). 3.3V output. Monitor Control Clock Monitor Control Data Direction O I/O I/O Type HVCMOS COD COD

2.6

LVDS Signals

Table 2-13.LVDS Signals
Signal Name LVDS_TXP[3:0] LVDS_TXN[3:0] LVDS_CLKP LVDS_CLKN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL PANEL_VDDEN PANEL_BKLTEN PANEL_BKLTCTL LVDS_CTRL_CLK Description Differential data output - positive Differential data output - negative Differential clock output - positive Differential clock output - negative LVDS Reference Current. Need 2.37 kOhm (high precession type 1% or less) pull-down resistor Reserved. No connect. VREFH: DC reference pin. DC reference pin can be connected to Vss. VREFL: DC reference pin can be connected to Vss. LVDS or eDP panel power enable: Panel power enable control. LVDS or eDP panel backlight enable: Panel backlight enable control. LVDS or eDP panel backlight brightness control: Panel brightness control. Display Data Channel clock: LVDS I2C backlight control: Some panels still support this, but most have gone to using PWM Display Data Channel data: LVDS I2C backlight control: Some panels still support this, but most have gone to using PWM LVDS I2C EDID: LVDS I2C EDID: LVDS Flat Panel I2C Clock and Data for EDID read and control. LVDS_DDC_DATA sampled as a pin-strap for LVDS port presence detect. LVDS_DDC_DATA LVDS Flat Panel I2C Clock and Data for EDID read and control. I2C based control signal (data) for External SSC clock chip control. LVDS_DDC_DATA sampled as a pin-strap for LVDS port presence detect. Direction O O O O I I I I O O O Type LVDS LVDS LVDS LVDS Ref Analog Analog Analog HVCMOS HVCMOS HVCMOS

I/O

COD

LVDS_CTRL_DATA

I/O

COD

LVDS_DDC_CLK

I/O

COD

I/O

COD

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2.7

DDI Audio Interface

Table 2-14.DDI Audio Signals (Sheet 1 of 2)
Signal Name AZIL_BCLK Description Intel HD Audio BCLK: Bit Clock: 24.00-MHz clock sourced from the controller and connecting to all codecs on the Link. Intel HD Audio Reset: Active low link reset signal. RST# is sourced from the controller and connects to all Codecs on the link. Assertion of RST# results in all link interface logic being reset to default power on state. Intel HD Audio SYNC: This signal marks input and output frame boundaries (frame synch) as well as identifies outbound data streams (stream tags). SYNC is always sourced from the controller and connects to all codecs on the link Intel HD Audio SDI - Serial Data In: Point-topoint serial data input signals driven by each codec (in this case the Intel? Atom? Direction I Type CMOS

AZIL_RST#

I

CMOS

AZIL_SYNC

I

CMOS

AZIL_SDI

Processor D2000 series and N2000 series
processor) to the controller. Data is single pumped; codecs drive SDI and the controller samples SDI with respect to the rising edge of BCLK. Controllers are required to support weak pull-down on all SDI signals. These pull-down are active whenever the controller is powered or in a wake enabled state. SDI pull-down are required to prevent spurious wake event in electrically noisy environments. Note: Although the name is misleading, the Intel? Atom? Processor D2000 series and N2000 series processor follows prior GMCH

I/O

CMOS

Intel? Atom? Processor D2000 series and N2000 series processor should connect to the
SDI pin on the Intel HD Audio Controller/ICH. This is why this pin’s direction is “I/O” - Input and Output.

naming convention: the SDI pin on the GMCH/

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Table 2-14.DDI Audio Signals (Sheet 2 of 2)
Signal Name AZIL_SDO Description Intel HD Audio SDO - Serial Data Out: one or more serial data output signal(s) driven by the Controller to all codecs on the link. Data is double pumped - i.e., the controller drives data onto SDO, and codecs sample data present on SDO with respect to every edge of BCLK. Note: Although the name is misleading, the Intel? Atom? Processor D2000 series and N2000 series processor follows prior GMCH naming convention: the SDO pin on the GMCH/Intel? Atom? Processor D2000 series and N2000 series processor should connect to the SDO pin on the Intel HD Audio Controller/ICH. This is why this pin's direction is Input (“I”) I CMOS Direction Type

2.8

DDI Port 0

Table 2-15.DDI Port 0 (Sheet 1 of 2)
Signal Name DDI0_TXP[3:0], DDI0_TXN[3:0] HDMI/DVI: _TX[0]: TMDSB_DATA2 _TX[1]: TMDSB_DATA1 _TX[2]: TMDSB_DATA0 _TX[3]: TMDSB_BLK DP: _TX[0]: DPort Lane 0 (BLUE, HSYNC, VSYNC) _TX[1]: DPort Lane 1 (GRN, CTL0, CTL1) _TX[2]: DPort Lane 2 (RED, CTL2, CTL3) _TX[3]: DPort Lane 3 DDI0_AUXP, DDI0_AUXN DDI0_HPD DDI0_DDC_SDA, DDI0_DDC_SCL DP: Display port aux HDMI/DVI: Unused DDI0 Hot Plug Detect I2C Control Clock and Data. HDMI and DP dual mode DDI0_DDC_SDA sampled as a pin-strap for HDMI/DVI/DP port presence detect. I/O OD I/O I Diff CMOS O Diff Description PORT0: Capable of HDMI/DVI/DP Direction Type

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Table 2-15.DDI Port 0 (Sheet 2 of 2)
Signal Name Description Connects externally to a 7.5 kOhms±1% Pull up to a 1.50 V ±5% voltage supply (BREF1P5). This pin and the external resistor is used to set internal bias levels. Reference Voltage: Connects externally to a 1.50 V ±5% voltage supply. Needed to create voltage references. Used also as supply for all ESD & Clamp connections. NOTE: This connects to 1.50 V not 1.80 V. Fixed (non-SSC) Display PLL Reference: 27 MHz XTAL, 96 MHz, 100 MHz DPL_REFCLKP, DPL_REFCLKN 96 & 100 MHz: Result in <= 5000 ppm error (1 Judder event every X sec). 27 MHz XTAL: Result in <= 1000 ppm error (1 Judder event every X sec). I Diff Direction Type

BREFREXT

N/A

Analog

BREF1P5

I

Analog

2.9

DDI Port1

Table 2-16.DDI Port 1
Signal Name DDI1_TXP[3:0], DDI1_TXN[3:0] HDMI/DVI: TX[0]: TMDSB_DATA2 TX[1]: TMDSB_DATA1 TX[2]: TMDSB_DATA0 TX[3]: TMDSB_BLK eDP/DP: TX[0]: DPort Lane 0 (BLUE, HSYNC, VSYNC) TX[1]: DPort Lane 1 (GRN, CTL0, CTL1) TX[2]: DPort Lane 2 (Red, CTL2, CTL3) TX[3]: DPort Lane 3 DDI1_AUXP, DDI1_AUXN DDI1_HPD DDI1_DDC_SDA, DDI1_DDC_SCL DP: Display port aux HDMI/DVI: Unused DDI1 Hot Plug Detect I2C Control Clock and Data. HDMI and DP dual mode DDI1_DDC_SDA sampled as a pin-strap for HDMI/DVI/DP port presence detect. DPL_REFSSCCLKP, DPL_REFSSCCLKN SSC Display PLL Reference: 100 MHz SSC (Spread Spectrum Clocking) I/O OD I/O I Diff OD O Diff Description PORT1: Capable of HDMI/DVI/DP/eDP Direction Type

I

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2.10

JTAG/ITP Signals

Table 2-17.JTAG/ITP Signals
Signal Name TCLK Description TCLK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST_B (Test Reset) resets the Test Access Port (TAP) logic. Direction I Type CMOS

TDI

I

CMOS

TDO

O

OD

TMS TRST#

I I

CMOS CMOS

2.11

Error and Thermal Protection

Table 2-18.Error and Thermal Protection (Sheet 1 of 2)
Signal Name Description Processor Hot: Asserted if any Intel? Atom? Processor D2000 series and N2000 series processor thermal sensor (one in each CPU and one in the MCH) indicates the part is hot. If any of these sensors trip or if the external pin is asserted, all sensors act as if the pin was asserted. Each sensor can be programmed to cause various actions on assertion or deassertion such as: an interrupt (SCI, SMI, MSI for example), 2x DDR self refresh mode, DDR bandwidth throttling, CPU or GFX performance throttling. In Deep Power Down Technology (code named C6), the CPU’s prochot output will automatically deassert. The bi-directional nature of the pin (ability for system to assert the signal), allows a system design to protect various external components from overheating situations. PMIC/VR, ICH, or external logic can choose to drive this in the event it's overheating to reduce vcc_cpu and vcc_GFX current consumption. Direction Type

PROCHOT#

I/O

I: CMOS O: OD

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Table 2-18.Error and Thermal Protection (Sheet 2 of 2)
Signal Name Description Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125 C. This is signaled to the system by the THERMTRIP# pin. Refer to the appropriate platform design guide for termination requirements. Direction Type

THERMTRIP#

O

Open Drain

2.12

Processor Core Power Signals

Table 2-19.Processor Core Power Signals
Signal Name VCC_CPU VCC_CPUSENSE Description Processor core power supply. The voltage supplied to these pins is determined by the VID pins. VCC_CPUSENSE and VSS_CPUSENSE provide an isolated, low impedance connection to the processor core voltage and ground. They can be used to sense or measure voltage near the silicon. VCC_CPUSENSE and VSS_CPUSENSE provide an isolated, low impedance connection to the processor core voltage and ground. They can be used to sense or measure voltage near the silicon. sVID Alert: Used by the VR to signal the prior request has not reach the requested operating point. sVID Data: Used by Intel? Atom? Processor D2000 series and N2000 series processor to send request and data to the VR and then by the VR to respond. Data is driven with a 12.5 Ohms Pull Down. sVID Clock: sVID request are driven out on SVID_DATA using this as the clock and are then registered in the VR using this for the clock. When the VR responds with data on SVID_DATA, it also uses this clock (still sent by Intel? Atom? Processor D2000 series and N2000 series processor) to drive the data. This means the VR starts driving data/alert using a clock that is late (by the Intel? Atom? Processor D2000 series and N2000 series processor>VR flight time + VR setup time). Clock is driven with a 12.5 Ohms PD. Frequency: 25 MHz when using DDR3-800 26 MHz with DDR3-1066 I Direction Type PWR

Analog

VSS_CPUSENSE

Analog

SVID_ALERT#

OD

SVID_DATA

I/O

OD

SVID_CLK

O

OD

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2.13

Graphics, DMI and Memory Core Power Signals

Table 2-20.Power Signals
Signal Name VCCAZILAON VCC_GFX V_SM VCCADMI_SFRPLL VCCADMI VCCADAC VCCTHRM VCCADP VCCADP_0 VCCADP_1 VCCAGPIO VCCRAMXXX Description Audio Power Supply Graphics core power supply - D2000 series only DDR I/O power supply DMI SFR PLL power supply DMI I/O power supply CRT/VGA DAC power supply GFX, CPU0 and CPU1 Thermal Sensor power supply DDI I/O power supply Display PLLs SFR power Supply Display PLLs SFR power Supply GPIO power supply CPU L2 Caches, DTS and Arrays Power Supply N2000 series D2000 series VCCDIO VCCADLLDDR VCCFHV VCCAGPIO_LV VCCAGPIO_REF VCCAGPIO_DIO VCCADDR VCCAHPLL VCCDLVDS VCCALVDS VCCSFRMPL VCCACKDDR VCCDMPL VCCCKDDR CRT digital Voltage DDR DLL power supply Graphic, CPU 1 and CPU 0 power supply Low Voltage GPIO and LVDS Digital power supply Reference Voltage to VCCAGPIO(3.3V) & VCCAGPIO_DIO (1.8V) Debug I/O power Supply DDR Digital power supply CPU0 and CPU1 Quiet power supply LVDS power supply LVDS power supply MPLL power supply DDR clock power supply MPLL Digital power supply DDR clock power supply 1.05 1.067 1.05 1.05 1.05 1.05 1.5 1.8 1.05 1.05 1.8 1.8 1.5 1.05 1.05 1.5 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Direction/V 3.3 1.05 1.5 1.5 1.05 1.8 1.8 1.05 1.5 1.5 3.3 Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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2.14

Ground
Signal Name VSS VSSA_CRTDAC VSSGFX_sense Description VSS are the ground pins for the processor and should be connected to the system ground plane. This analog ground signal should connect directly to the board ground plane This signal can be left float when is use for D2000 series Direction Type GND GND GND

Table 2-21.Ground

§

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3
3.1

Functional Description
System Memory Controller
The system memory controller supports DDR3 (SO-DIMM only) protocols with one 64 bit wide single channel accessing two DIMMs. The controller supports a maximum of two non-ECC DDR3 SODIMMs or two un-buffered DDR3 DIMMs, single or double sided; thus allowing up to four device ranks.

3.1.1

System Memory Organization Modes
The system memory controller supports only one memory organization mode: single channel. In this mode, all memory cycles are directed to a single channel.

3.1.2

System Memory Technology Supported
The system memory controller supports the following DDR3 Data Transfer Rates, DIMM Modules and DRAM Device Technologies:

? DDR3 Data Transfer Rates: 800MT/s (6.4 GB/s) and 1066MT/s (8.5 GB/s) ? DDR3 SODIMM Modules (unbuffered, non-ECC)
— Raw Card A = 2 rank of x16 SDRAM (double sided) — Raw Card B = 1 rank of x8 SDRAM (double sided) — Raw Card C = 1 rank of x16 SDRAM (single sided) — Raw Card F = 2 ranks of x8 SDRAM (double Sided) Note: x8 means that each SDRAM component has 16/8 data lines. x16 means that each SDRAM component has 16 data lines.

? DDR3 DRAM Device Technology:
Standard 1-Gb and 2-Gb technologies and addressing are supported for both x8 and x16 devices. There is no support for SO-DIMMs with different technologies or capacities on opposite sides of the same SO-DIMM. If one side of a SO-DIMM is populated, the other side is either identical or empty.

? Supported DDR3 SO-DIMM module configurations
“Single sided” above is a logical term referring to the number of Chip Selects attached to the DIMM. A real DIMM may put the components on both sides of the substrate, but be logically indistinguishable from single sided DIMM if all components on the DIMM are attached to the same Chip Select signal. There is no support for DIMMs with different technologies or capacities on opposite sides of the same DIMM. If one side of a DIMM is populated, the other side is either identical or empty.

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There is no support for 4Gb & 8Gb technology. Supported components for DDR3 at 800MTs and 1066 MTs. Table 3-22.Support DRAM Devices
DRAM Density 1Gb 2Gb 1Gb 2Gb Data Width x8 x8 x16 x16 Banks 8 8 8 8 Bank Address BA[2:0] BA[2:0] BA[2:0] BA[2:0] Row Address A[13:0] A[14:0] A[12:0] A[13:0] Column Address A[9:0] A[9:0] A[9:0] A[9:0] Page Size 1KB 1KB 2KB 2KB

Table 3-23.Supported Memory Size Per Rank
Memory Size/ Rank 1GB 2GB 512MB 1GB DRAM Chips/ Rank 8 8 4 4 DRAM Chip Density 1Gb 2Gb 1Gb 2Gb DRAM Chip Data Width x8 x8 x16 x16 Page Size @ 64-bit Data Bus 8KB = 1KB * 8 chips 8KB = 1KB * 8 chips 8KB = 2KB * 4chips 8KB = 2KB * 4 chips

Table 3-24.Support Memory Configurations
DRAM Chip Density (Gb) 1 1 1 1 Memory Size (MB) 512 1024 1024 2048 # of chips needed 4 8 8 16 DRAM Chip Data Width 16 8 16 8 Data Bus Width 64 64 64 64 # of Ranks needed 1 1 2 2 # of chips /rank 4 8 4 8

2 2 2 2

1024 2048 2048 4096

4 8 8 16

16 8 16 8

64 64 64 64

1 1 2 2

4 8 4 8

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3.1.3

Rules for populating DIMM slots
The frequency of system memory will be the lowest frequency of all DIMMs in the system, as determined through the SPD registers on the DIMMs. Timing parameters [CAS latency (or CL + AL for DDR3), tRAS, tRCD, tRP] must be programmed to match within a channel.

3.2

Graphics Processing Unit
Intel? Atom? Processor D2000 series and N2000 series contains an integrated graphics engine, video decode and a display controller that supports two pipes to LVDS, CRT, HDMI/DVI, DP, eDP.

3.2.1

3-D Core Key Features
The Intel? Atom? Processor D2000 series and N2000 series GPU 3D has two pipe scalable unified shader implementation. — 3-D Peak Performance — Fill Rate: 4 Pixels per clock — Vertex Rate: One Triangle 8 clocks (Transform Only) — Vertex / Triangle Ratio average = 1 vtx/tri, peak 0.5 vtx/tri

? Texture max size = 2048 x 2048 ? Programmable 4x and 2x multi-sampling anti-aliasing (MSAA)
— Rotated grid — ISP performance related to AA mode, TSP performance unaffected by AA mode

? Optimized memory efficiency using multi-level cache architecture ? Optimized memory efficiency using multi-level texture cache architecture
3.2.1.1 Shading Engine Key Features
The unified pixel/vertex shader engine supports a broad range of instructions.

? Unified programming model
— Multi-threaded with 16 concurrently running threads and up to 64 data simultaneous instances — Zero-cost swapping in/out of threads — Cached program execution model – max program size 262144 instructions — Dedicated pixel processing instructions — Dedicated vertex processing instructions — 4096 32-bit registers and 48 40-bit registers — 3-way 10 bit integer and 4-way 10 bit integer operations

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? SIMD pipeline supporting operations in:
— 32-Bit IEEE Float — 2-way, 16-bit fixed point — 4-way, 8-bit integer — 32-bit integer — 32-bit bit-wise (logical only)

? Static and Dynamic flow control
— Subroutine calls — Loops — Conditional branches — Zero-cost instruction predication

? Procedural Geometry
— Allows generation of more primitives on output compared with input data — Effective geometry compression — High order surface support

? External data access
— Permits reads from main memory by cache (can be bypassed) — Permits writes to main memory — Data fence facility provided — Dependent texture reads

3.2.1.2

Vertex Processing
Modern graphics processors perform two main procedures to generate 3-D graphics. First, vertex geometry information is transformed and lit to create a 2-D representation in the screen space. Those transformed and lit vertices are then processed to create display lists in memory. The pixel processor then rasterizes these display lists on a regional basis to create the final image. The Intel? Atom? Processor D2000 series and N2000 series integrated graphics supports DMA data accesses from SDRAM. DMA accesses are controlled by a main scheduler and data sequencer engine. This engine coordinates the data and instruction flow for the vertex processing, pixel processing, and general purpose operations. Transform, lighting, and tiling operations are performed by the vertex processing pipeline. A 3-D object is usually expressed in terms of triangles, each of which is made up of three vertices defined by X-Y-Z coordinate space. The transform and lighting process is performed by processing data through the unified shader core. The results of this process are sent to the pixel processing function. The steps to transform and light a triangle or vertex are explained below.

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3.2.1.2.1

Vertex Transform Stages

? Local space: relative to the model itself (e.g., using the model centre at reference
point). Prior to being placed into a scene with other objects.

? World space: transform LOCAL to WORLD: this is needed to bring all objects in
the scene together into a common coordinate system.

? Camera space: transform WORLD to CAMERA (also called EYE): this is required to
transform the world in order to align it with camera view. In OpenGL, the local to world and world to camera transformation matrix is combined into one, called the ModelView matrix.

? Clip space: transform CAMERA to CLIP: The projection matrix defines the viewing
frustum onto which the scene will be projected. Projection can be orthographic, or perspective. Clip is used because clipping occurs in clip space.

? Perspective space: transform CLIP to PERSPECTIVE: The perspective divide is
basically what enables 3-D objects to be projected onto a 2-D space. A divide is necessary to represent distant objects as smaller on the screen. Coordinates in perspective space are called normalized device coordinates ([-1,1] in each axis).

? Screen space: transform PERSPECTIVE to SCREEN: this is where 2-D screen
coordinates are finally computed, by scaling and biasing the normalized device coordinates according to the required render resolution. 3.2.1.2.2 Lighting Stages Lighting is used to generate modifications to the base color and texture of vertices; examples of different types of lighting are:

? Ambient lighting is constant in all directions and the same color to all pixels of an
object. Ambient lighting calculations are fast, but objects appear flat and unrealistic.

? Diffuse lighting takes into account the light direction relative to the normal vector
of the object's surface. Calculating diffuse lighting effects takes more time because the light changes for each object vertex, but objects appear shaded with more three-dimensional depth.

? Specular lighting identifies bright reflected highlights that occur when light hits an
object surface and reflects back toward the camera. It is more intense than diffuse light and falls off more rapidly across the object surface. Although it takes longer to calculate specular lighting than diffuse lighting, it adds significant detail to the surface of some objects.

? Emissive lighting is light that is emitted by an object, such as a light bulb.
3.2.1.3 Pixel Processing
After vertices are transformed and lit by the vertex processing pipeline, the pixel processor takes the vertex information and generates the final rasterized pixels to be displayed. The steps of this process include removing hidden surfaces, applying textures and shading, and converting pixels to the final display format. The vertex/pixel shader engine is described in Unified Shader.

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The pixel processing operations also have their own data scheduling function that controls image processor functions and the texture and shader routines. 3.2.1.3.1 Hidden Surface Removal The image processor takes the floating-point results of the vertex processing and further converts them to polygons for rasterization and depth processing. During depth processing, the relative positions of objects in a scene, relative to the camera, are determined. The surfaces of objects hidden behind other objects are then removed from the scene, thus preventing the processing of un-seen pixels. This improves the efficiency of subsequent pixel-processing. 3.2.1.3.2 Applying Textures and Shading After hidden surfaces are removed, textures and shading are applied. Texture maps are fetched, mipmaps calculated, and either is applied to the polygons. Complex pixelshader functions are also applied at this stage. 3.2.1.3.3 Final Pixel Formatting The pixel formatting module is the final stage of the pixel-processing pipeline and controls the format of the final pixel data sent to the memory. It supplies the unified shader with an address into the output buffer, and the shader core returns the relevant pixel data. The pixel formatting module also contains scaling functions, as well as a dithering and data format packing function.

3.2.1.4

Unified Shader
The unified shader engine contains a specialized programmable microcontroller with capabilities specifically suited for efficient processing of graphics geometries (vertex shading), graphics pixels (pixel shading), and general-purpose video and image processing programs. In addition to data processing operations, the unified shader engine has a rich set of program-control functions permitting complex branches, subroutine calls, tests, etc., for run-time program execution. The unified shader core also has a task and thread manager which tries to maintain maximum performance utilization by using a 16-deep task queue to keep the 16 threads full. The unified store contains 16 banks of 128 registers. These 32-bit registers contain all temporary and output data, as well as attribute information. The store employs features which reduce data collisions such as data forwarding, pre-fetching of a source argument from the subsequent instruction. It also contains a write back queue. Like the register store, the arithmetic logic unit (ALU) pipelines are 32-bits wide. For floating-point instructions, these correlate to IEEE floating point values. However, for integer instructions, they can be considered as one 32-bit value, two 16-bit values, or four 8-bit values. When considered as four 8-bit values, the integer unit effectively acts

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like a four-way SIMD ALU, performing four operations per clock. It is expected that in legacy applications pixel processing will be done on 8-bit integers, roughly quadrupling the pixel throughput compared to processing on float formats. 3.2.1.4.1 Multi Level Cache The multi-level cache is a three-level cache system consisting of two modules, the main cache module and a request management and formatting module. The request management module also provides Level-0 caching for texture and unified shader core requests. The request management module can accept requests from the data scheduler, unified shaders and texture modules. Arbitration is performed between the three data streams, and the cache module also performs any texture decompression that may be required.

3.2.2
3.2.2.1

2D Engine
VGA Registers
The 2D registers are a combination of registers defined for the original Video Graphics Array (VGA) and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

3.2.2.2

Logical 128-Bit Fixed BLT and 256 Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows* operating systems. The 128-bit BLT Engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The term BLT refers to a block transfer of pixel data between memory locations. The BLT engine can be used for the following:

? Move rectangular blocks of data between memory locations ? Data Alignment ? Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory locations. The allowable memory transfers are between: cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. Data to be transferred can consist of regions of memory, patterns, or solid color fills. A pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel. The BLT engine has the ability to expand monochrome data into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the destination. Transparent transfers compare destination color to source color and write according to the mode of transparency selected.

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Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source memory location, the graphics controller can specify which area in memory to begin the BLT transfer. Hardware is included for all 256 raster operations (Source, Pattern, and Destination) defined by Microsoft, including transparent BLT. The graphics controller has instructions to invoke BLT and stretch BLT operations, permitting software to set up instruction buffers and use batch processing. The graphics controller can perform hardware clipping during BLTs.

3.2.3

Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability.

Table 3-25.Analog Port Characteristics
Signal RGB Port Characteristics Voltage Range CRT/Monitor Sense Analog Copy Protection Sync on Green HSYNC VSYNC Voltage Enable/Disable Polarity Adjust Composite Sync Support Special Flat Panel Sync Stereo Sync DDC Voltage Control Support 0.7 Vp-p nominal only Analog Compare No No 3.3 V Port control VGA or port control No No No External buffered to 5 V Through GPIO interface

3.2.3.1

Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the CRT monitor. CPU’s integrated 350 MHz RAMDAC supports resolutions up to 1920 x 1200 @ 60 Hz. Three 8-bit DACs provide the R, G, and B signals to the CRT display.

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3.2.3.2

Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals should power up disabled in the high state. No composite sync or special flat panel sync support will be included.

3.2.3.3

VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used.

3.2.3.4

DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and DDC 2 is implemented. The CPU uses the CRT_DDC_CLK and CRT_DDC_DATA signals to communicate with the analog monitor. The CPU will generate these signals at 3.3V. External pull-up resistors and level shifting circuitry should be implemented on the board. The CPU implements a hardware GMBus controller that can be used to control these signals allowing for transactions speeds up to 100 kHz.

3.2.4

Digital Display Interfaces
The Intel? Atom? Processor D2000 series and N2000 series can drive HDMI, LDVS, eDP and Display Port natively. The digital ports B and or C can be configured to drive HDMI, DVI and Display Port. The digital ports are muxed onto the PEG interface. Since Intel? Atom? Processor D2000 series and N2000 series has two display ports available for its two pipes, it can support up to two different images on two different display devices. Timings and resolutions for these two images may be different.

3.2.4.1

LVDS
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. There is one LVDS transmitter channel consist of 4-data pairs and a clock pair each. The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals.

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Figure below shows a pair of LVDS signals and swing voltage. Figure 3-2. LVDS Signals and Swing Voltage

1s and 0s are represented the differential voltage between the pair of signals. As shown in the figure below a serial pattern of 1100011 represents one cycle of the clock. Figure 3-3. LVDS Clock and Data Relationship

3.2.4.2

LVDS Pair States
The LVDS pairs can be put into one of five states:

? Active ? Powered down tri-state ? Powered down 0-V ? Send zeros
When in the active state, several data formats are supported. When in powered down state, the circuit enters a low power state and drives out 0-V or tri-states on both the output pins for the entire channel. When in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is with the clock lines and timing signals sending the normal clock and timing data. The LVDS Port can be enabled/disabled using software. A disabled port enters a low power state. Once the port is enabled, individual driver pairs may be disabled based on the operating mode. Disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0s output. Individual pairs or sets of LVDS pairs can be selectively powered down when not being used. The panel power sequencing can be set to override the selected power state of the drivers during power sequencing.

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3.2.4.3

Single Channel Mode
In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data pair outputs. A dual channel interface converts 36 or 48 bits of color information plus the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of differential data outputs respectively.

Note:

Platforms using the ICH for integrated graphics support 24 bpp display panels of Type 1 only (compatible with VESA LVDS color mapping).

3.2.4.4

Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. To meet the panel power timing specification requirements two signals, LFP_VDD_EN and LFP_BKLT_EN, are provided to control the timing sequencing function of the panel and the backlight power supplies. A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The panel VDD power, the backlight on/ off state and the LVDS clock and data lines are all managed by an internal power sequencer. A requested power-up sequence is only allowed to begin after the power cycle delay time requirement T4 is met.

Figure 3-4. Panel Power Sequencing

T4

T1+T2

T5 Panel On

TX

T3

T4

Panel VDD Enable Panel BackLight Enable
Off Off

Clock/Data Lines

Valid

Power On Sequence from off state and Power Off Sequence after full On

NOTE: Support for programming parameters TX and T1 through T5 using software is provided.

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Table 3-26.Panel Power Sequence Timing Parameters
Panel Power Sequence Timing Parameters Spec Name VDD On LVDS active Backlight Backlight state LVDS state Power cycle delay From 0.1 VDD VDD stable on LVDS active Backlight off LVDS off Power Off To 0.9 VDD LVDS active Backlight on LVDS off Start power off Power on sequence start Min 0 0 200 x 0 0 x 50 400 Max 10 50 Name T1 T2 T5 TX T3 T4 Unit ms ms ms ms ms ms

3.2.4.5

LVDS DDC
The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values are then ‘locked’ into the registers to prevent unwanted corruption of the values. From that point on, the display modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a source size and enabling the VGA.

3.2.4.6

High Definition Multimedia Interface
The High-Definition Multimedia Interface (HDMI) is provided for transmitting uncompressed digital audio and video signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. It can carry high quality multi-channel audio data and all standard and high-definition consumer electronics video formats. HDMI display interface connecting the PCH and display devices utilizes transition minimized differential signaling (TMDS) to carry audiovisual information through the same HDMI cable. HDMI includes three separate communications channels: TMDS, DDC, and the optional CEC (consumer electronics control). As shown in Figure 3-5, the HDMI cable carries four differential pairs that make up the TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA Display data channel (DDC). The DDC channel is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video and auxiliary (control/status) data is transmitted across the three TMDS data channels. The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels. The digital display data signals driven natively through the PCH are AC coupled and needs level shifter to convert the AC coupled signals to the HDMI compliant digital signals.

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Figure 3-5. HDMI Overview

3.2.4.7

Digital Video Interface (DVI)
The PCH digital ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver which is similar to the HDMI protocol but the audio and CEC. Refer to the HDMI section for more information on the signals and data transmission. To drive DVI-I through the back panel the VGA DDC signals is connected along with the digital data and clock signals from one of the digital port. When a system has support for DVI-I port, then either VGA or the DVI-D through a single DVII connector can be driven but not both simultaneously. The digital display data signals driven natively through the Intel? Atom? Processor D2000 series and N2000 series are AC coupled and needs level shifter to convert the AC coupled signals to the HDMI compliant digital signals.

3.2.4.8

Display Port
Display Port is a digital communication interface that utilizes differential signalling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. Display Port is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and TV displays. A Display Port consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal. The Main Link is a uni-directional, high-bandwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bi-directional channel used for link management and device control. The Hot Plug Detect (HPD) signal serves as an interrupt request for the sink device.

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Figure 3-6. DP Overview

3.2.4.9

Embedded DisplayPort (eDP)
Embedded DisplayPort (eDP*) is a embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. eDP is supported only on Digital Display Port 1. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and a optional Hot Plug Detect signal. The eDP support on Intel? Atom? Processor D2000 series and N2000 series is possible because of the addition of the panel power sequencing pins: PANEL_VDD, PANEL_BKLT_EN and PANEL_BLKT_CTRL. The Intel? Atom? Processor D2000 series and N2000 series supports Embedded DisplayPort* (eDP*) Standard Version 1.1.

3.2.4.10

DisplayPort Aux Channel
A bi-directional AC coupled AUX channel interface replaces the I2C for EDID read, link management and device control. I2C-to-Aux bridges are required to connect legacy display devices.

3.2.4.11

DisplayPort Hot-Plug Detect (HPD)
The CDV supports HPD for Hot-Plug sink events on the HDMI and DisplayPort interface.

3.2.4.12

Blu-Ray* - HDCP (D2700 & N2800 sku only)
The HDCP Unit implements the industry standard HDCP (High-bandwidth Digital Content Protection) link protection protocol as specified by the Digital Content Protection, LLC organization. This implementation is based on version 1.1 of the specification, which includes references necessary to apply HDCP to HDMI as well as DP. This unit's end result is to provide a 24-bit Cipher stream, which is used to encrypt the data sent to user-accessible digital output port(s). This key value changes each video pixel to produce a snowy image when the receiver is not synchronized to the transmitter (SOC). The key value is specific to each receiver, and as such the HDCP

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function can only be applied to one port at a time in this configuration. The video data and data-island periods (audio) are encrypted, whereas sync and control information is not. This allows the receiver to synchronize to the stream, even if the results are scrambled.

3.2.4.13

PAVP (Protected Audio and Video Path)
The Intel? Atom? Processor D2000 series and N2000 series PAVP provided a protected path between application and Intel? Atom? Processor D2000 series and N2000 series hardware decoder for media player applications that implements a compatible key exchange and data encryption scheme. The application processed the AACS or DRM encrypted contents with the embedded AACS or DRM keys then immediately encrypted contents with a session key that was communicated with the Intel? Atom? Processor D2000 series and N2000 series. The PAVP encrypted contents can be stored in unprotected memory. When hardware decoder requests the encrypted compressed video stream the data will pass through AES engine and decrypted by it. The clear data are then forwarded directly to video decoder unit. During video decoding process video decoder temporarily store some video parameters and uncompressed pictures to system memory for its own reference, post processing by graphic engine, or send to output interface by display controller. The uncompressed pictures have less value and can be protected software mechanism provided by OS. The application should employed Tamper Resistance Software (TRS) mechanisms to protect attacks by debugger and other similar schemes when processing the above steps.

3.2.5

Multiple Display Configurations
Microsoft Windows 7* operating systems supports for multi-monitor display. Since the Intel? Atom? Processor D2000 series and N2000 series has several display ports available for its two pipes, it can support up to two different images on different display devices. Timings and resolutions for these two images may be different. The Intel? Atom? Processor D2000 series and N2000 series supports Dual Display Clone and Extended Desktop. Dual Display Clone uses both display pipes to drive the same content, at the same resolution and color depth to two different displays. This configuration allows for different refresh rates on each display. Extended Desktop uses both display pipes to drive different content, at potentially different resolutions, refresh rates, and color depths to two different displays. This configuration allows for a larger Windows Desktop by utilizing both displays as a work surface.

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3.3

Thermal Sensor
There are several registers that need to be configured to support the uncore thermal sensor functionality and SMI# generation. Customers must enable the Catastrophic Trip Point as protection for the CPU. If the Catastrophic Trip Point is crossed, then the CPU will instantly turn off all clocks inside the device. Customers may optionally enable the Hot Trip Point to generate SMI#. Customers will be required to then write their own SMI# handler in BIOS that will speed up the CPU (or system) fan to cool the part.

3.3.1

PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip point is crossed. The ERRSTS register can be inspected for the SMI alert.
Address C8-C9 CC-CDh Register Symbol ERRST SMICMD Register Name Error Status SMI Command Default Value 0000h 0000h Access RWC/S, RO RO, R/W

3.4

Power Management
The CPU uncore has many permutations of possibly concurrently operating modes. Care should be taken (Hardware and Software) to disable unused sections of the silicon when this can be done with sufficiently low performance impact. Refer to Chapter 6 and the ACPI Specification, Rev3.0 for more detail.

3.4.1

Interface Power States Supported

Table 3-27.Main Memory States
State Power up Pre-charge power down Active power down Description CKE asserted. Active mode. KE De-asserted; All banks Closed; Not a self-refresh Mode. Supported only the fast (DLL ON) exit Mode CKE De-asserted; At least one bank active; Not a self-refresh Mode. Supported only the fast (DLL ON) exit Mode

3.4.2

Intel? Hyper-Threading Technology
The processor supports Intel? Hyper-Threading Technology (Intel? HT Technology), which allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled via the BIOS and requires operating system support. For enabling details, please refer to the Intel? Atom? Processor D2000 series and N2000 series BIOS Writer’s Guide for enabling details.

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Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7* and disabling Hyper- Threading Technology via the BIOS for all previous versions of Windows operating systems. For more information on Hyper-Threading Technology, see http:// www.intel.com/products/ht/hyperthreading_more.htm.

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4
Note:

Electrical Specifications
All data and specifications for DDR3 in this chapter are based on post-silicon/ validation data. These specifications will be updated with characterized data from silicon measurements in the later version of the EDS spec document. This chapter contains signal group descriptions, absolute maximum ratings, voltage identification and power sequencing. The chapter also includes DC and AC specifications, including timing diagrams.

4.1

Power and Ground Balls
The processor has VCC and VSS (ground) inputs for on-chip power distribution. All power balls must be connected to their respective processor power planes, while all VSS balls must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop. The VCC balls must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals.

4.2

Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full-power states. This may cause voltages on power planes to sag below their minimum values, if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand (for example, coming out of an idle condition). Similarly, capacitors act as a storage well for current when entering an idle condition from a running condition. To keep voltages within specification, output decoupling must be properly designed.

Caution:

Design the board to ensure that the voltage provided to the processor remains within the specifications. Failure to do so can result in timing violations or reduced lifetime of the processor. For further information and design guidelines, refer to the appropriate platform design guide and the IMVP7 Voltage Regulator Controller Design Guidelines.

4.2.1

Voltage Rail Decoupling
The voltage regulator solution needs to provide:

? Bulk capacitance with low effective series resistance (ESR). ? A low path impedance from the regulator to the CPU. ? Bulk decoupling to compensate for large current swings generated during poweron, or low-power idle state entry/exit.

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The power delivery solution must ensure that the voltage and current specifications are met, as defined in Table 4-32. For further information regarding power delivery, decoupling, and layout guidelines refer to the appropriate platform design guide.

4.3

Processor Clocking
BCLKP, BCLKN, HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN, DPL_REFCLKINP, DPL_REFCLKINN The processor utilizes differential clocks to generate the processor core(s) and uncore operating frequencies, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 100 or 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL), which requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC). HPLL, DMIPLL and MPLL expecting the reference source clock will be generated by the same PLL and SS logic in the external clock generation

Table 4-28.PLL Reference Clock
PLL Reference Pins/Balls HPLL_REFCLK_P, HPLL_REFCLK_N Frequency Description Drives all MCH core clocks, Gfx, Video, Display and provides reference for CPU PLLs. DDRIO PLL must be matched to clock DDR at the same transfer rate as fused for HPLL. For the DMI interface to the ICH which operates at Gen1 speeds. 27 MHz XTAL required to reduce error to <1000 ppm. DPLL0 is non SSC clock If SSC is used for display, it must be connected at this pins. SSC enables better emissions testing performance (EMI) at the system level. Internally DPLL0 and DPLL1 can use each others’ reference clock. Derived from HPLL.

Host PLL (HPLL)

100 MHz

DDRIO PLL (MPLL)

DDR3_REFCLKP, DDR3_REFCLKN DMI_IREFCLKP, DMI_IREFCLKN DPL_REFCLKP, DPL_REFCLKN

100 MHz

DMIIO PLL (DMIPLL) Display I/O Fixed Ref Clock (DPLL0)

100 MHz

27 XTAL, 96, 100 Fixed Frequency.

Display I/O SSC Ref Clock (DPLL1)

DPL_REFSSCCLKP, DPL_REFSSCCLKN

100 SSC.

CPU Core PLLs (CPLL)

NONE

N/A

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4.3.1

PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 4-32 for DC specifications and to the Platform Design Guide for decoupling and routing guidelines.

4.4

Voltage Identification (VID)
The Intel? Atom? Processor D2000 series and N2000 series processor supports Serial VID based power delivery for CPU core and Graphic Core. The Next Generation Intel? Atom? Processor based Mobile Platform will support Intel MVP 7 1+1 for Core & Gfx / Vnn VR. While for Entry Level Desktop Customer option will be provided to choose either Intel Mobile Voltage Positioning (IMVP) 7 1+1 for core & gfx/ Vnn or VR12/ IMVP7 1 +0 for core and fixed Voltage LVR for Gfx/ Vnn (VR12) 1 +0 could be chapter and preferred solution. The VID specifications for the processor VCC and VAGX are defined by the IMVP 7 Voltage Regulator Controller Design Guidelines. The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages. Table 4-29 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. See the IMVP 7 Voltage Regulator Controller Design Guidelines for further details. VID signals are CMOS push/ pull drivers. Refer to Table 4-34 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes in order to minimize the power of the part. A voltage range is provided in Table 4-30. The specifications are set so that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings. This is shown in the VID range values in Table 4-30. The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage. This will represent a DC shift in the loadline. See the Voltage Regulator Down (VRD) 12.0 Design Guidelines for further details.

Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 1 of 7)
VID7 0 0 0 0 0 VID6 0 0 0 0 0 VID5 0 0 0 0 0 VID4 0 0 0 0 0 VID3 0 0 0 0 0 VID2 0 0 0 0 1 VID1 0 0 1 1 0 VID0 0 1 0 1 0 Hex bit 1 0 0 0 0 0 Hex bit 0 0 1 2 3 4 VCC (V) 0.00000 0.25000 0.25500 0.26000 0.26500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 2 of 7)
VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Hex bit 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 Hex bit 0 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 VCC (V) 0.27000 0.27500 0.28000 0.28500 0.29000 0.29500 0.30000 0.30500 0.31000 0.31500 0.32000 0.32500 0.33000 0.33500 0.34000 0.34500 0.35000 0.35500 0.36000 0.36500 0.37000 0.37500 0.38000 0.38500 0.39000 0.39500 0.40000 0.40500 0.41000 0.41500 0.42000 0.42500 0.43000 0.43500 0.44000 0.44500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 3 of 7)
VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Hex bit 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 Hex bit 0 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C VCC (V) 0.45000 0.45500 0.46000 0.46500 0.47000 0.47500 0.48000 0.48500 0.49000 0.49500 0.50000 0.50500 0.51000 0.51500 0.52000 0.52500 0.53000 0.53500 0.54000 0.54500 0.55000 0.55500 0.56000 0.56500 0.57000 0.57500 0.58000 0.58500 0.59000 0.59500 0.60000 0.60500 0.61000 0.61500 0.62000 0.62500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 4 of 7)
VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Hex bit 1 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 Hex bit 0 D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 VCC (V) 0.63000 0.63500 0.64000 0.64500 0.65000 0.65500 0.66000 0.66500 0.67000 0.67500 0.68000 0.68500 0.69000 0.69500 0.70000 0.70500 0.71000 0.71500 0.72000 0.72500 0.73000 0.73500 0.74000 0.74500 0.75000 0.75500 0.76000 0.76500 0.77000 0.77500 0.78000 0.78500 0.79000 0.79500 0.80000 0.80500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 5 of 7)
VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Hex bit 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 Hex bit 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 VCC (V) 0.81000 0.81500 0.82000 0.82500 0.83000 0.83500 0.84000 0.84500 0.85000 0.85500 0.86000 0.86500 0.87000 0.87500 0.88000 0.88500 0.89000 0.89500 0.90000 0.90500 0.91000 0.91500 0.92000 0.92500 0.93000 0.93500 0.94000 0.94500 0.95000 0.95500 0.96000 0.96500 0.97000 0.97500 0.98000 0.98500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 6 of 7)
VID7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Hex bit 1 9 9 9 9 9 9 9 9 9 9 9 A A A A A A A A A A A A A A A A B B B B B B B B B Hex bit 0 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 VCC (V) 0.99000 0.99500 1.00000 1.00500 1.01000 1.01500 1.02000 1.02500 1.03000 1.03500 1.04000 1.04500 1.05000 1.05500 1.06000 1.06500 1.07000 1.07500 1.08000 1.08500 1.09000 1.09500 1.10000 1.10500 1.11000 1.11500 1.12000 1.12500 1.13000 1.13500 1.14000 1.14500 1.15000 1.15500 1.16000 1.16500

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Table 4-29.VRD 12.0 Voltage Identification Definition (Sheet 7 of 7)
VID7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hex bit 1 B B B B B B B C C C C C C C C C C C C C C C C D D D D Hex bit 0 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 VCC (V) 1.17000 1.17500 1.18000 1.18500 1.19000 1.19500 1.20000 1.20500 1.21000 1.21500 1.22000 1.22500 1.23000 1.23500 1.24000 1.24500 1.25000 1.25500 1.26000 1.26500 1.27000 1.27500 1.28000 1.28500 1.29000 1.29500 1.30000

4.5

Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125 degree Celsius (maximum), or the THERMTRIP# signal is asserted, the Vcc

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supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to the thermal runaway of the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.

4.6

Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection guidelines:

? RSVD - these signals should not be connected ? RSVD_TP - these signals should be routed to a test point ? RSVD_NCTF - these signals are non-critical to function and may be left unconnected Arbitrary connection of these signals to VCC, VSS, or to any other signal (including each other) may result in component malfunction. See Chapter 2 for a land listing of the processor and the location of all reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ±20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines.

4.7

Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Chapter 2. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On-Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. All Control Sideband Asynchronous signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 4.9 for the DC and AC specifications.

4.8

Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. Please refer to the D2000 series and N2000 series – Boundary Scan Description Language (BSDL) File for more details. A translation buffer

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should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.

4.9

AC and DC Specifications
Section 4.9 list the DC specifications for the processor and are valid only while meeting the thermal specifications (as specified in the Thermal / Mechanical Specifications and Guidelines), clock frequency, and input voltages. Table 4-32 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.

4.9.1

Flexible Motherboard Guidelines (FMB)
This is not applicable for D2000 series and N2000 series Next Generation Intel? Atom? Processor based (Desktop and Mobile) Platform.

4.9.2

Voltage and Current Specifications
Table 4-30 and Table 4-32 list the DC specifications for the processor core and I/O buffer; they are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deeper Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at TJ = 100°C. Care should be taken to read all notes associated with each parameter.

Table 4-30.Processor Core Active and Idle Mode DC Voltage and Current Specifications (Sheet 1 of 2)
Symbol VID VCC VCC,BOOT ICC Parameter VID Range VCC for processor core Default VCC voltage for initial power up ICC for processor core Dual Core N2600 N2800 D2500 D2700 3.5 4.72 6.7 6.7 2.07 3.257 3.886 5.073 Min 0.91 0.00000- 1.21 1.0945 1.1 1.1055 V A Typ Max 1.21 I_TDC Unit V V 2, 3 Note

See Table 4-29 and Figure 4-7

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Table 4-30.Processor Core Active and Idle Mode DC Voltage and Current Specifications (Sheet 2 of 2)
Symbol VCC_HFM VCC_LFM Parameter Min 0.91 Typ Max 1.21 I_TDC Unit V V 0.70 0.75 0.90 0.90 Note 2, 3 2, 3

VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM)
N2600 N2800

VCCDPRSLP

VCC at Deeper Sleep (C4) N2600 N2800 0.70 0.75 0.35 0.6072 0.4470 0.1302 0.0810 1.3883 1.2242 0.5852 0.3649 -5.9 -9.0 0 3.872 3.696 1.9976 1.2162 V A A A A m? m? m? @VID =1.1V @VID= 1.1V @VID= 0.9V @VID= 0.7V Figure 4-7

VCCDPRSLP IAH ISGNT IDPRSLP IDPRSLP SLOPELL

VCC at Deeper Sleep (C6) ICC Auto-Halt Dual-core processors ICC Stop-Grant Dual-core processors ICC Deeper Sleep (C4) Dual-core processors ICC Deeper Sleep (C6) Dual-core processors Processor Core Supply DC Loadline Processor Core Supply AC Loadline Graphic Core Supply Loadline - N2000 series only Ripple TOB -10 -19

+10 +19

mV mV

NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Each processor is programmed with voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Please note this differs from the VID employed by the processor during a power management event. 3. These are pre-silicon estimates and are subject to change. 4. Long term reliability cannot be assured in conditions above or below Max/Min functional limits

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Figure 4-7. Vcc and Icc Processor Loadline

VCC [V]
Slope = -5.9mV/A at die VCC_SENSE, VSS_SENSE pins. Differential Remote Sense required. VCC max VCC, DC max VCC nom

10mV= RIPPLE

VCC, DC min VCC min ± VCC Tolerance = ± 11mV

0

ICC [A]
ICC max

Figure 4-8. Vcc AC Vs DC Loadline

Table 4-31.Istep

min Istep N2600 N2800 D2500 D2700

typ

-

-

max 2.2 3.0 4.0 4.0

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The I/O buffer supply voltage should be measured at the processor package pins. The tolerances shown in Table 4-32 are inclusive of all noise from DC up to 20 MHz. The voltage rails should be measured with a bandwidth limited oscilloscope with a roll-off of 3 dB/decade above 20 MHz under all operating conditions. Table 4-32 indicates which supplies are connected directly to a voltage regulator or to a filtered voltage rail. For voltage rails that are connected to a filter, they should be measured at the input of the filter. If the recommended platform decoupling guidelines cannot be met, the system designer will have to make trade-offs between the voltage regulator out DC tolerance and the decoupling performances of the capacitor network to stay within the voltage tolerances listed below. Table 4-32.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications (Sheet 1 of 4)
Symbol VCCGFX - AVID Parameter GFX supply voltage N2000 series is VID controlled voltage VCCGFX GFX supply voltage D2000 series is fixed VID Voltage VCCGFX,BOOT ICCGFX Default VCCGFX voltage for initial power up GFX supply current N2600 N2800 D2500 D2700 VCCGPIO_DIO VCCDLVD, VCCALVD VCCADAC VCCTHRM Debug I/O supply voltage LVDS supply voltage LVDS supply voltage CRT/VGA DAC supply voltage Thermal Sensor SFR supply voltage Debug I/O supply current LVDS supply current LVDS supply current CRT/VGA DAC supply current Thermal Sensor SFR supply current N2600 N2800 D2500 D2700 0.151 0.151 0.151 0.151 0.116 0.116 0.116 0.116 A 1.71 1.8 1.89 V 2 1.86 3.5707 3.4544 3.7132 1.252 2.644 2.21 2.693 A 0.9975 1.05 1.1025 0.75 1.05 V Min Typ Max I_TDC Unit Note
1

1.0945

1.1

1.1055

V

ICCGPIO_DIO ICCDLVD, ICCALVD ICCADAC ICCTHRM

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Table 4-32.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications (Sheet 2 of 4)
Symbol VCCFHV VCCADMI VCCRAMXXX VCCAGPIO_LV VCCADDR VCCACKDDR VCCADLLDDR VCCDMPL VCCDIO VCCADP VCCPLLCPU0 VCCPLLCPU1 VCCAHPLL Parameter Fusing Programming supply voltage DMI IO supply voltage CPU L2 Caches, DTS, Arrays supply voltage GPIO sVID and Legacy supply voltage DDR Digital supply voltage DDR Clk Digital Quiet supply voltage DDR DLL Quiet supply voltage MPLL Digital supply voltage Digital Logic CRT supply voltage DDI IOs supply voltage CPU0 PLL supply voltage CPU1 PLL supply voltage SOC PLL supply voltage N2000 series D2000 series 0.9975 1.0137 1.05 1.067 1.1025 1.1204 V Min Typ Max I_TDC Unit Note
1

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Table 4-32.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications (Sheet 3 of 4)
Symbol ICCFHV ICCADMI ICCRAMXXX ICCAGPIO_LV ICCADDR ICCACKDDR ICCADLLDDR ICCDMPL ICCDIO ICCADP ICCPLLCPU0 ICCPLLCPU1 ICCAHPLL Parameter Fusing Programming supply current DMI analog supply current CPU L2 Caches, DTS, Arrays supply current GPIO sVID and Legacy supply current DDR Digital supply current DDR Clk Digital Quiet supply current DDR DLL Quiet supply current MPLL Digital supply current Digital Logic CRT supply current DDI IOs supply current CPU0 PLL supply current CPU1 PLL supply current SOC PLL supply current N2600 N2800 D2500 D2700 0.99 1.13 1.268 1.268 V_SM VCCCKDDR ICC_SM ICCCKDDR DDR I/O supply voltage DDR CLK Quiet DDR I/O supply voltage DDR I/O supply current DDR CLK Quiet I/O supply current N2600 N2800 D2500 D2700 0.404 0.869 0.869 0.869 0.175 0.340 0.583 0.583 A 1.425 1.5 1.575 V 0.551 0.619 0.976 0.976 A Min Typ Max I_TDC Unit Note
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Table 4-32.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications (Sheet 4 of 4)
Symbol VCCADMI_SFR
PLL

Parameter DMI SFRPLL Supply voltage GPIOs reference supply voltage Display PLLs SFR supply voltage Display PLLs SFR supply voltage MPLL SFR input voltage with respect to VSS DDR DMI I/O Supply current GPIOs reference supply current Display PLLs SFR supply current Display PLLs SFR supply current MPLL SFR input current with respect to VSS N2600 N2800 D2500 D2700

Min

Typ

Max

I_TDC

Unit

Note
1

VCCAGPIO_RE
F

VCCADP0_SFR VCCADP1_SFR VCCSFRMPL ICCADMI ICCAGPIO_REF ICCADP0_SFR ICCADP1_SFR ICCSFRMPL

1.425

1.5

1.575

V

A

0.124 0.125 0.125 0.125

0.095 0.096 0.096 0.096 V

VCCAGPIO VCCAZILAON ICCAGPIO ICCAZILAON

GPIO supply voltage Intel HD-Audio Supply Voltage GPIO supply current Intel HD-Audio Supply current N2600 N2800 D2500 D2700 0.004 0.004 0.004 0.004 0.003 0.003 0.004 0.003 A 3.135 3.3 3.465

NOTE: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. These rails are filtered from other voltage rails on the platform and should be measured at the input of the filter. See the Platform Design Guide for proper implementation of the filter circuits. 3. VRM tolerance, ripple and core noise parameters which states that reliability cannot be assured if these are violated. 4. VCCPLLCPU0 & VCCPLLCPU1 & VCCAHPLL: AC requirement 1.5%

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4.9.3

DC Specifications
Platform reference voltages at the top of Table 4-32 are specified at DC only. VREF measurements should be made with respect to the supply voltage.

4.9.3.1

Input Clock DC Specification

Table 4-33.Input Clocks (BCLK, HPL_CLKIN, DPL_REFCLKIN, EXP_CLKIN) Differential Specification
Symbol VIL VIH VCROSS dVCROSS CIN Parameter Input Low Voltage Input High Voltage Absolute crossing voltage Range of crossing points Input Capacitance 1.0 0.3 Min -0.30 Typ 0 1.15 0.550 0.14 3.0 Max Units V V V V pF 2,3 Notes1

NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. These are pre-silicon estimates and are subject to change. 2. Crossing voltage defined as instantaneous voltage when rising edge of CLKN equalize CLKP. The crossing point must meet the absolute and relative crossing point specification simultaneously.

4.9.3.2

DDR3 DC Specifications

Table 4-34.DDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol VIL(DC) VIH(DC) Parameter Input Low Voltage Input High Voltage SM_VREF + 100mV (VDDQ / 2)* (RON / (RON+RVTT _TERM)) VDDQ ((VDDQ / VOH Output High Voltage 2)* (RON/ (RON+RVTT _TERM)) For all DDR Signals, CMD, CTL, CK, DQ, DQS V 3 Min Typ Max SM_VREF - 100mV Units V V Notes 1, 3 2, 3

VOL

Output Low Voltage

3

IIL

Input Leakage Current

40

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Table 4-34.DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol RON CI/O Parameter DDR3 Clock Buffer strength DQ/DQS/DQS# DDR3 I/O Pin Capacitance Min Typ 26 2.6 Max Units Ω pF Notes

NOTES: 1. VIL is defined as the maximum voltage level at a DDR input buffer that will be received as a logical low value. SM_VREF is normally VCC_DDR/2 2. VIH is defined as the minimum voltage level at a DDR input buffer that will be received as a logical high value. SM_VREF is normally VCC_DDR/2 3. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality specifications. 4. RON is DDR driver resistance whereas RTT_TERM is DRAM ODT resistance which is controlled by DRAM.

Table 4-35.CPU Sideband CMOS Signal Group DC Specification
Symbol VCCP VIH VIL Zpu Zpd Rwpu Rwpd Rwpu-40K Rwpd-40K Ii Parameter I/O Voltage Input High Voltage Input Low Voltage Pull up Impedance Pull down Impedance Weak Pull Impedance Weak Pull Down Impedance Weak Pull Up Impedance 40K Weak Pull Down Impedance 40K Input Pin Leakage 1 1 20 20 -15 Min 0.9975 0.8* VCCP 0.5* VCCP 60 60 4 4 70 70 15 Typ Max 1.1025 Units V V V Ohm Ohm KOhm KOhm KOhm KOhm ?A 1 2 3 3 3 3 4 4 5 Notes

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. Measured at Vccp/2. 4. Rwpu_40k and Rwpd_40k are only used for TRST_B 5. For VIN between 0V and VCCP. Measured when driver is tri-stated. 6. The DC specification applicable to TCLK, TRST#, TMS, TDI, CPUSLP#, PWRGOOD, INIT#, LINT01, LINT00, SMI#, DPRSTP#, DPLSLP#, STPCLK# and SVID_ALERT#.

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Table 4-36.CPU Sideband OD 25 Ohm 1.05V Signal Group DC Specification
Symbol VCCP VIH VIL Zpd Rwpu Rwpd Ii Parameter I/O Voltage Input High Voltage Input Low Voltage Pull down Impedance Weak Pull Impedance Weak Pull Down Impedance Input Pin Leakage 1 1 -20 Min 0.9975 0.8* VCCP 0.5 * VCCP 30 4 4 20 Typ Max 1.1025 Units V V V Ohm KOhm KOhm ?A 1 2 3 3 3 4 Notes

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. Measured at Vccp/2. 4. For VIN between 0V and VCCP. Measured when driver is tri-stated. 5. The DC specification applicable to TDO, PROCHOT#, PBE# and THERMTRIP#

Table 4-37.CPU Sideband OD 12.5 Ohms 1.05 V Signal Group DC Specification
Symbol VCCP VIH VIL Zpd Rwpu Rwpd Ii Parameter I/O Voltage Input High Voltage Input Low Voltage Pull down Impedance Weak Pull Impedance Weak Pull Down Impedance Input Pin Leakage 1 1 -40 Min 0.9975 0.8* VCCP 0.5 * VCCP 15 4 4 40 Typ Max 1.1025 Units V V V Ohm KOhm KOhm ?A 1 2 3 3 3 4 Notes

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. Measured at Vccp/2. 4. For VIN between 0-V and VCCP. Measured when driver is tri-stated. 5. The DC specification applicable SVID_DATA and SVID_CLK.

Table 4-38.CPU Sideband OD 1.8 V Signal Group DC Specification (Sheet 1 of 2)
Symbol VCCP VIH VIL Parameter I/O Voltage Input High Voltage Input Low Voltage Min 1.71 0.64* VCCP 0.41 * VCCP Typ Max 1.89 Units V V V 1 2 Notes

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Table 4-38.CPU Sideband OD 1.8 V Signal Group DC Specification (Sheet 2 of 2)
Symbol Zpd Rwpu Ii Ii Parameter Pull down Impedance Weak Pull Impedance Input Pin Leakage (PRDY) Input Pin Leakage (PREQ) 1 -30 -15 Min Typ Max 30 4 30 15 Units Ohm KOhm ?A ?A Notes 3 3 4 4

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. Measured at Vccp/2. 4. For VIN between 0V and VCCP. Measured when driver is tri-stated. 5. THe DC Specification covers PRDY# and PREQ#.

4.9.3.3

Intel? HD Audio DC Specification
This section defines the electrical characteristics of Intel HD Audio components for 3.3-V signaling scheme. The 3.3 V Intel HD Audio components can be designed with standard CMOS I/O technology. Unless specifically stated otherwise, component parameters apply at the package pins; not at bare silicon pads nor at card edge connectors.

Table 4-39.3.3-V DC Specification
Symbol VCC VIH VIL VOH VOL IIL CIN LPIN Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Input Pin Capacitance Pin Inductance Iout =-500?A Iout =1500?A 0<Vin<Vcc 0.9 x VCC 0.10 x VCC ±175 7.5 20 Condition Min 3.135 0.65 x VCC 0.35 x VCC Max 3.465 Units V V V V V ?A pF nH 2 1 Notes

NOTES: 1. For SDI buffers (or in general any bi-directional buffer with tri-state output), input leakage current also include hi-Z output leakage. 2. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.

Table 4-40.1.5-V DC specification (Sheet 1 of 2)
Symbol VCC Parameter Supply Voltage Condition Min 1.418 Max 1.583 Units V Notes

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Table 4-40.1.5-V DC specification (Sheet 2 of 2)
Symbol VIH VIL VOH VOL IIL CIN LPIN Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Input Pin Capacitance Pin Inductance Iout =-500?A Iout =1500?A 0<Vin<Vcc 0.9 x VCC 0.10 x VCC ±175 7.5 20 Condition Min 0.6 x VCC 0.4 x VCC Max Units V V V V ?A pF nH 2 1 Notes

NOTES: 1. For SDI buffers (or in general any bi-directional buffer with tri-state output), input leakage current also include hi-Z output leakage. 2. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.

Table 4-41.High Voltage GPIO CMOS Signal DC Specification
Symbol VCCP VIH VIL Zpu Zpd Ii Parameter I/O Voltage Input High Voltage Input Low Voltage Pull up Impedance Pull down Impedance Input Pin Leakage Min 3.135 2 0 40 40 -45 50 50 Typ Max 3.465 Vccp 0.8 60 60 45 Units V V V Ohm Ohm ?A 1 2 3 3 4 Notes

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. Measured at Vccp/2. 4. For VIN between 0V and VCCP. Measured when driver is tri-stated. 5. The DC specification applicable to DDI0_HPD, HV_DDI1_HPD, RESET#, PANEL_VDDEN, BKLTEN, and BKLTCTL

4.9.3.4
4.9.3.4.1

Display DC Specification
Analog Video and LVDS Signals Both interface DC Specifications are referred to the VESA Video Signal Standard, version 1 revision 2.

Table 4-42.R,G,B/CRT DAC Display DC specification (Functional Operating Range)
Symbol Parameter Resolution Min Typ 8 Max Units bits Notes 1

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Table 4-42.R,G,B/CRT DAC Display DC specification (Functional Operating Range)
Symbol Parameter Min Typ Max Units Notes 1,2,4 (white video level voltage) 1,3,4 (black video level voltage) 4,5 1,6 1,6 7

Max Luminance (full-scale)

0.665

0.700

0.770

V

Min Luminance

0.0

V

LSB Current Integral Non Linearity (INL) Differential Non-Linearity (DNL) Video Channel-to-Channel Voltage amplitude mismatch Monotonicity -1.0 -1.0

73.2

8 +1.0 +1.0 6

?A LSB LSB %

Guaranteed

NOTE: 1. Measured at each R,G,B termination according to the VESA Test Procedure – Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). 2. Max steady-state amplitude 3. Min steady-state amplitude 4. Defined for a double 75 Ohm termination 5. Set by external reference resistor value 6. INL & DNL measured and calculated according to VESA Video Signal Standards 7. Max fill-scale voltage difference among R,G,B outputs (percentage of steady-state fullscale voltage).

Table 4-43.High Voltage GPIO OD Signal DC Specification
Symbol VCCP VIH VIL VOL Ii Parameter I/O Voltage Input High Voltage Input Low Voltage Output Low Voltage Input Pin Leakage -45 Min 3.135 2 0 0.8 0.4 45 Typ Max 3.465 Units V V V V ?A 1 2 3 4 Notes

NOTES: 1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value. 3. 3mA sink current. 4. For VIN between 0V and VCCP. Measured when driver is tri-stated. 5. The DC specification covers DDI0_DDC_SDA, DDI0_DDC_SCL, DDI1_DDC_SDA ,DDI1_DDC_SCL, LVDS_DDC_CLK, LVDS_DDC_DATA, LVDS_CTRL_CLK, LVDS_CTRL_DATA, CRT_DDC_CLK, CRT_DDC_DATA

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Table 4-44.CRT_HSYNC and CRT_VSYNC DC Specification
Symbol VCCP VOH VOL IOH IOL Ii Parameter I/O Voltage Output High Voltage Output Low Voltage Output High Current Output Low Current Input Pin Leakage -35 Min 3.135 2.4 0 Typ Max 3.465 Vccp 0.5 8 8 35 Units V V V mA mA ?A 1 Notes

NOTES: 1. For VIN between 0V and VCCP. Measured when driver is tri-stated.

Table 4-45.LVDS Interface DC Specification (Functional Operating Range, VCCLVDS = 1.8 V ±5%)
Symbol VOD ΔVOD VOS ΔVOS II IOS IOZ Parameter Differential Output Voltage Change in VOD between Complementary Output States Offset Voltage Change in VOS between Complementary Output States Input Leakage Current Output Short Circuit Current Output TRI-STATE Current -3.5 ±1 1.125 1.25 Min 250 Typ 350 Max 450 50 1.375 50 40 -10 ±10 Units mV mV V mV ?A mA ?A 2 2 Notes 2 2 2 2

NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All LVDS active lanes must be terminated with 100 Ohm resistor for correct VOS performance and measurement.

4.9.3.4.2

Digital Display Interface (DDI) signals DC specification The interface DC Specifications are referred to the VESA Video Signal Standard, version 1 revision 2.

Table 4-46.DDI Main Transmitter DC specification (Sheet 1 of 2)
Symbol VTX-DIFFp-pLevel1

Parameter Differential Peak-to-peak Output Voltage Level 1 Differential Peak-to-peak Output Voltage Level 2 Differential Peak-to-peak Output Voltage Level 3

Min 0.34 0.51 0.69

Typ 0.4 0.6 0.8

Max 0.46 0.68 0.92

Units V V V

Notes 1 1 1

VTX-DIFFp-pLevel2

VTX-DIFFp-pLevel3

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Table 4-46.DDI Main Transmitter DC specification (Sheet 2 of 2)
Symbol VTX-DIFFp-pLevel4

Parameter Differential Peak-to-peak Output Voltage Level 4 No Pre-emphasis 3.5 dB Pre-emphasis 6.0 dB Pre-emphasis 9.5 dB Pre-emphasis

Min 1.02 0.0 2.8 4.8 7.6 0 12 9 75 -10 400 -10 -200 -600 -700

Typ 1.2 0.0 3.5 6.0 9.5

Max 1.38 0.0 4.2 7.2 11.4 2.0

Units V dB dB dB dB V dB dB

Notes 1 1 1 1 1 1 4 4 5 @ AVcc 3.3V

VTX-PREEMPRATIO

VTX-DC-CM RLTX-DIFF

Tx DC Common Mode Voltage Differential Return Loss at 0.675GHz at Tx Package pins Differential Return Loss at 1.35GHz at Tx Package pins

CTX Voff Vswing VOH(<=165 MHz) VOH(>165 MHz) VOL(<=165 MHz) VOL (>165 MHz)

AC Coupling Capacitor Single Ended Standby (off), output voltage Single Ended output swing voltage Single Ended high level output voltage Single Ended high level output voltage Single Ended low level output voltage Single Ended low level output voltage

200 10 600 10 +10 -400 -400

nF mV mV mV mV mV mV

@ AVcc 3.3V @ AVcc 3.3V @ AVcc 3.3V @ AVcc 3.3V

NOTES: 1. For embedded connection, support of programmable voltage swing levels is optional. 2. Total drive current of the transmitter when it is shorted to its ground. 3. Common mode voltage is equal to Vbias_Tx voltage shown in Figure 4-3. 4. Straight loss line between 0.675 GHz and 1.35 GHz. 5. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the transmitter side. Placement of AC coupling capacitors on.

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Table 4-47.DDI AUX Channel DC Specification
Symbol VAUX-DIFFp-p VAUX-_TERM_R VAUX-DC-CM VAUX-TURN-CM VAUX-TERM-R IAUX_SHORT CAUX Parameter AUX Peak-to-peak Voltage at a transmitting Device AUX CH termination DC resistance AUX DC Common Mode Voltage AUX turn around common mode voltage AUX CH termination DC resistance AUX Short Circuit Current Limit AC Coupling Capacitor 75 100 90 200 0 Min 0.39 100 2.0 0.4 Typ Max 1.38 Units V Ohm V V Ohm mA nF 5 6 Notes 1 2 3 4

NOTES: 1. VAUX-DIFFp-p= 2*|VAUXP – VAUXM| 2. Informative 3. Common mode voltage is equal to Vbias_Tx (or Vbias_Rx) voltage. 4. Steady state common mode voltage shift between transmit and receive modes of operation. 5. Total drive current of the transmitter when it is shorted to its ground. 6. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the transmitter side. Placement of AC coupling capacitors on.

Figure 4-9. Definition of Differential Voltage and Differential Voltage Peak-to-Peak

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Figure 4-10.Definition of Pre-emphasis

4.9.4

AC Specification
The processor timings specified in this section are defined at the processor pads. Therefore, proper simulation of the signals is the only means to verify proper timing and signal quality. See Chapter 5 for the ball listing and Chapter 2 for signal definitions. The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel.

Note:

Care should be taken to read all notes associated with a particular timing parameter.

4.9.4.1

Input Clock AC Characteristics
The specifications below are taken from the CK505 Clock Synthesizer / Driver Specification document. Any further details can be obtained in the CK505 Specification. These specifications are valid at the silicon pad of the processor only. Ledges on the clock signals will be observed if measuring the clocks at the vias on the bottom of the processor, since the clocks rely on reflective switching. The Frequency and Period numbers in below table are taken directly from the “AbsPerMin” and “AbsPerMax” clockclock period variation in the CK505 Clock Synthesizer / Driver Specification, with SSC enabled (except for the display clock)

Table 4-48.Input Clock AC Characteristics (Sheet 1 of 2)
Parameter Min Nom Max Unit Figures Notes

Differential DDR Clock at Frequency of 100 MHz DDR_CLKIN* Frequency 98.66 100 100.87 MHz

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Table 4-48.Input Clock AC Characteristics (Sheet 2 of 2)
Parameter DDR_CLKIN* Period DDR_CLKIN* Period Stability DDR_CLKIN* Rise and Fall Slew Rate Min 9.914 — 2.5 Nom 10 — — Max 10.136 125 8 Unit ns ps V/ns 4-16 Figures 4-16 Notes 1,5,6 2,3 4,6

Differential Host Clock at Frequency of 100 MHz HPL_CLKIN* Frequency HPL_CLKIN* Period HPL_CLKIN* Period Stability HPL_CLKIN* Rise and Fall Slew Rate 98.66 9.914 — 2.5 100 10 — — 100.87 10.136 125 8 MHz ns ps V/ns 4-16 4-16 1,5,6 2,3 4,6

Differential DMI Clock at Frequency of 100 MHz EXP_CLKIN* Frequency EXP_CLKIN* Period EXP_CLKIN* Period Stability EXP_CLKIN* Rise and Fall Slew Rate 98.66 9.914 — 2.5 100 10 — — 100.87 10.136 125 8 MHz ns ps V/ns 4-16 4-16 1,5,6 2,3 4,6

Display PLLA, PLLB Differential Clock at Frequency of 96 MHz (without SSC) DPL_REFCLKIN* Frequency DPL_REFCLKIN* Period DPL_REFCLKIN* Period Stability DPL_REFCLKIN* Rise and Fall Slew Rate 95.98 10.413 — 2.5 96 10.4167 — — 96.03 10.419 250 8 MHz ns ps V/ns 4-16 4-16 1,5,6 2,3 4,6

Display PLLA, PLLB Differential Clock at Frequency of 96 MHz (with SSC) DPL_REFSSCLKIN* Frequency DPL_REFSSCLKIN* Period DPL_REFSSCLKIN* Period Stability DPL_REFSSCLKIN* Rise and Fall Slew Rate 2.5 93.74 10.166 96 10.4167 98.85 10.668 250 8 MHz ns ps V/ns 4-16 4-16 1,5,6,7 2,3 4,6

Display PLLA, PLLB Differential Clock at Frequency of 100 MHz (with SSC) DPL_REFSSCLKIN* Frequency DPL_REFSSCLKIN* Period DPL_REFSSCLKIN* Period Stability DPL_REFSSCLKIN* Rise and Fall Slew Rate 99.76 9.914 — 2.5 100 10 — — 100.87 10.024 250 8 MHz ns ps V/ns 4-16 4-16 1,5,6,7 2,3 4,6

NOTES:

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1.

2. 3.

4. 5. 6. 7.

The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification. Min period specification is based on –300 ppm deviation from the ideal period. Max period specification is based on the summation of +300 ppm deviation from the ideal period and a +5% max variance due to spread spectrum clocking. Ideal periods for the various clocks are derived using 96 MHz, 100 MHz, 200 MHz, 266.6 MHz, and 333.33 MHz respectively. For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification. In this context, period stability is defined as the worst-case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. Slew rate is measured through the VSWING voltage range centered about differential zero. The average period over any 1 is period of time must be greater than the minimum and less than the maximum specified period. Measurement taken from differential waveform. DOT100 SSC calculations assume maximum down-spread of 2.5%.

4.9.4.2

GPIO Signal AC Specification

Table 4-49.High Voltage GPIO OD Signal AC Specification
Symbol fscl tlow thigh tr tf thd:dat tsu:dat T# Parameter SCL clock Frequency Low Period of SCL Clock High Period of SCL Clock Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Data Hold Time Data Setup Time 0 250 Min 0 4.7 4 1000 300 Typ Max 100 Unit KHz ?s ?s ns ns ?s ns Fig. 4-40 4-40 4-40 4-40 4-40 4-40 4-40 1 Notes
1,2,3

NOTE: 1. thd:dat is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

4.9.4.3
4.9.4.3.1

Intel? HD Audio AC Specification
3.3-V AC Specification The output driver on the Intel HD Audio electrical link must be able to deliver an initial voltage of at least Vil or Vih respectively at the receiver through the bus with known characteristic impedance and at the same time meeting signal quality requirements. The minimum and maximum drive characteristics of Intel HD Audio output buffers are defined by the V/I curves. Figure 4-11 and Table 4-50 describe the SDO buffer AC drive specification where as the Figure 4-12 and Table 4-51 describe the AC drive specification of the SDI buffers. The AC drive specification for SYNC, RST# and BCLK buffers is same as that of SDO.

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These curves should be interpreted as traditional ‘DC’ transistor curves with the following exceptions: ‘DC drive point’ is the only position on the curves at which steady state operation is intended, while the higher currents are only reached momentarily during bus switching transients. The ‘AC drive point’ (real definition of buffer strength) defines the minimum instantaneous current required to switch the bus. Adherence to these curves should be evaluated at worst case conditions. Minimum pull up curve is evaluated at minimum Vcc and high temperature. Minimum pull down curve is evaluated at minimum Vcc and high temperature. The maximum curve test points are evaluated at maximum Vcc and low temperature. Inputs must be clamped to both ground and power rails. The clamp diode characteristics are also listed here for reference. Figure 4-11. V/I Curves for SDO Buffers

Figure 4-12. V/I Curves for SDI buffers

Table 4-50.SDO 3.3 V Buffer AC Specification (Sheet 1 of 2)
Symbol IOH Parameter Switching Current High Condition 0 < Vout < 0.7vcc Min -23Vcc Max Unit mA

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Table 4-50.SDO 3.3 V Buffer AC Specification (Sheet 2 of 2)
Symbol Parameter Condition 0.7Vcc < Vout < 0.9Vcc Min -76.7(VccVout) (174.2/ Vcc)*(VoutVcc)*(Vout+0. 4Vcc) -57.55Vcc 23Vcc 76.7Vout (273.8/ Vcc)*Vout*(Vc c-Vout) 57.55Vcc -25+(Vin+1)/ 0.015 25+(Vin-Vcc1)/0.015 mA mA V/ns Slew_r Output rise Slew rate 0.25Vcc to 0.75Vcc 1 3 Slew rate (note1) V/ns Slew_f Output fall Slew rate 0.75Vcc to 0.25Vcc 1 3 Slew rate (note1) Max Unit mA

0.7Vcc < Vout < Vcc

mA

(Test Point) IOL Low Period of SCL Clock

Vout = 0.7Vcc Vcc > Vout >0.3Vcc 0.3Vcc > Vout > 0.1Vcc 0.3Vcc > Vout >0

mA mA mA

mA mA

(Test Point) ICL ICH Low Clamp Current High Clamp Current

Vout = 0.3Vcc -3 < Vin < -1 Vcc+4 > Vin > Vcc+1

NOTE: 1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25Vcc to 0.75Vcc load for rise and 0.75Vcc to 0.25Vcc load for fall), rather than instantaneous rate at any point within the transition range.

Table 4-51.SDI 3.3 V Buffer AC Specification (Sheet 1 of 2)
Symbol IOH Parameter switching Current High Condition 0 < Vout < 0.7vcc 0.7Vcc < Vout < 0.9Vcc 0.7Vcc < Vout < Vcc (Test Point) Vout = 0.7Vcc Min -15Vcc -50(Vcc-Vout) (113.6/ Vcc)*(VoutVcc)*(Vout+0.4 Vcc) -37.5Vcc Max Unit mA mA

mA

mA

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Table 4-51.SDI 3.3 V Buffer AC Specification (Sheet 2 of 2)
Symbol IOL Parameter Low Period of SCL Clock Condition Vcc > Vout >0.3Vcc 0.3Vcc > Vout > 0.1Vcc 0.3Vcc > Vout >0 (Test Point) ICL ICH Low Clamp Current High Clamp Current Output rise Slew rate Vout = 0.3Vcc -3 < Vin < -1 Vcc+4 > Vin > Vcc+1 -25+(Vin+1)/ 0.015 25+(Vin-Vcc1)/0.015 Min 15Vcc 50Vout (178.6/ Vcc)*Vout*(Vcc -Vout) 37.55Vcc mA mA V/ns Slew_r 0.25Vcc to 0.75Vcc 1 3 Slew rate (note1) V/ns Slew_f Output fall Slew rate 0.75Vcc to 0.25Vcc 1 3 Slew rate (note1) Max Unit mA mA

mA mA

NOTE: 1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25Vcc to 0.75Vcc load for rise and 0.75Vcc to 0.25Vcc load for fall), rather than instantaneous rate at any point within the transition range.

4.9.4.3.2

1.5-V AC specification The output driver on the Intel HD Audio electrical link must be able to deliver an initial voltage of at least Vil or Vih respectively at the receiver through the bus with known characteristic impedance and at the same time meeting signal quality requirements. The minimum and maximum drive characteristics of Intel HD Audio output buffers are defined by the V/I curves. Table 4-52 and Figure 4-13 describe the SDO buffer AC drive specification where as the Table 4-53 and Figure 4-14 describe the AC drive specification of the SDI buffers. The AC drive specification for SYNC, RST# and BCLK buffers is same as that of SDO. These curves should be interpreted as traditional ‘DC’ transistor curves with the following exceptions: ‘DC drive point’ is the only position on the curves at which steady state operation is intended, while the higher currents are only reached momentarily during bus switching transients. The ‘AC drive point’ (real definition of buffer strength) defines the minimum instantaneous current required to switch the bus.

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Adherence to these curves should be evaluated at worst case conditions. Minimum pull up curve is evaluated at minimum Vcc and high temperature. Minimum pull down curve is evaluated at minimum Vcc and high temperature. The maximum curve test points are evaluated at maximum Vcc and low temperature. Inputs must be clamped to both ground and power rails. The clamp diode characteristics are also listed here for reference. Figure 4-13.V/I Curves for SDO buffers

Table 4-52.SDO 1.5-V Buffer AC Specification (Sheet 1 of 2)
Symbol IOH Parameter switching Current High Condition 0 < Vout < 0.7vcc 0.7Vcc < Vout < 0.9Vcc Min -16.67Vcc -55.57(VccVout) (151.52/ Vcc)*(VoutVcc)*(Vout+0. 4Vcc) -50Vcc 16.67Vcc 57.57Vout (238.1/ Vcc)*Vout*(Vc c-Vout) 50Vcc -25+(Vin+1)/ 0.015 25+(Vin-Vcc1)/0.015 Max Unit mA mA

0.7Vcc < Vout < Vcc

mA

(Test Point) IOL Low Period of SCL Clock

Vout = 0.7Vcc Vcc > Vout >0.3Vcc 0.3Vcc > Vout > 0.1Vcc 0.3Vcc > Vout >0

mA mA mA

mA mA

(Test Point) ICL ICH Low Clamp Current High Clamp Current

Vout = 0.3Vcc -3 < Vin < -1 Vcc+4 > Vin > Vcc+1

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Table 4-52.SDO 1.5-V Buffer AC Specification (Sheet 2 of 2)
Symbol Parameter Output rise Slew rate Condition Min Max Unit V/ns Slew_r 0.25Vcc to 0.75Vcc 0.5 1.5 Slew rate (note1) V/ns Slew_f Output rise Slew rate 0.75Vcc to 0.25Vcc 0.5 1.5 Slew rate (note1)

NOTE: 1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25Vcc to 0.75Vcc load for rise and 0.75Vcc to 0.25Vcc load for fall), rather than instantaneous rate at any point within the transition range.

Table 4-53.SDI 1.5-V Buffer AC Specification
Symbol IOH Parameter switching Current High Condition 0 < Vout < 0.7vcc 0.7Vcc < Vout < 0.9Vcc 0.7Vcc < Vout < Vcc Min -9.38Vcc -31.27(VccVout) (113.64/ Vcc)*(VoutVcc)*(Vout+0.4 Vcc) -37.5Vcc 9.38Vcc 31.27Vout (178.57/ Vcc)*Vout*(Vcc -Vout) 37.55Vcc -25+(Vin+1)/ 0.015 25+(Vin-Vcc1)/0.015 0.5 1.5 V/ns Slew rate (note1) 0.75Vcc to 0.25Vcc 0.5 1.5 V/ns Slew rate (note1) Max Unit mA mA mA

(Test Point) IOL Low Period of SCL Clock

Vout = 0.7Vcc Vcc > Vout >0.3Vcc 0.3Vcc > Vout > 0.1Vcc 0.3Vcc > Vout >0

mA mA mA mA

(Test Point) ICL ICH Slew_r Low Clamp Current High Clamp Current Output rise Slew rate

Vout = 0.3Vcc -3 < Vin < -1 Vcc+4 > Vin > Vcc+1 0.25Vcc to 0.75Vcc

mA

Slew_f

Output rise Slew rate

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NOTE: 1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25Vcc to 0.75Vcc load for rise and 0.75Vcc to 0.25Vcc load for fall), rather than instantaneous rate at any point within the transition range.

4.9.4.3.3

3.3 V Maximum AC Ratings and Device Protection All Intel HD Audio buffers should be capable of withstanding continuous exposure to the waveform shown in Figure 4-14 (3.3 V) and Figure 4-15 (1.5 V). It is recommended that these waveforms be used as qualification criteria against which the long term reliability of each device is evaluated.Table 4-54 (3.3 V), Table 4-55 (1.5 V) and Table 4-56 (1.5 V) list the parameters of the waveform. This level of robustness should be guaranteed by design; it is not intended that this waveform should be used as a production test. These waveforms are applied with the equivalent of a zero impedance voltage source, driving through a series resistor directly into each Intel HD Audio input or tri-stated output pin. The open-circuit voltage of the voltage source is shown in Figure 4-14 (3.3 V) and Figure 4-15(1.5 V), which is based on the worst case overshoot and undershoot expected in actual Intel HD Audio buses. The resistor values are calculated to produce the worst case current into an effective internal clamp diode.

Figure 4-14. Maximum AC Waveforms for 3.3 V Signaling

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Figure 4-15.Maximum AC Waveforms for 1.5 V Signaling

Table 4-54.3.3 V Parameters for Maximum AC Signalling Waveforms
Symbol V1 V2 V3 Vpu Vpo trf fSDI fSDO Parameter Overshoot Voltage Undershoot Initial Voltage Undershoot Voltage Waveform peak-to-peak Waveform peak-to-peak Rise/fall time Frequency of AC rating waveform as applied to SDI input buffers Frequency of AC rating waveform as applied to SDO input buffers 1 -3 6.465 6.3 3 24 24 Min Max 6.3 3.465 Unit V V V V V V/ns MHz MHz

NOTE: 1. The voltage waveform is supplied at the resistor shown in the evaluation setup, not the package pin. 2. Any internal clamping in the device being tested will greatly reduce the voltage levels seen at the package pin.

Table 4-55.1.5V Parameters for Maximum AC Signalling Waveforms (Sheet 1 of 2)
Symbol V1 V2 V3 Vpu Vpo trf fSDI Parameter Overshoot Voltage Undershoot Initial Voltage Undershoot Voltage Waveform peak-to-peak Waveform peak-to-peak Rise/fall time Frequency of AC rating waveform as applied to SDI input buffers 0.5 -1.6 3.25 3.25 1.5 24 Min Max 3.25 1.65 Unit V V V V V V/ns MHz

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Table 4-55.1.5V Parameters for Maximum AC Signalling Waveforms (Sheet 2 of 2)
Symbol fSDO Parameter Frequency of AC rating waveform as applied to SDO input buffers Min Max 24 Unit MHz

Table 4-56.Resistance value for the AC rating Waveform
Condition Overshoot waveform at the codec Undershoot waveform ar the codec Overshoot waveform at the controller Undershoot waveform ar the controller Value 65 Ohms 101 Ohms 108 Ohms 133 Ohms

NOTE: 1. The voltage waveform is supplied at the resistor shown in the evaluation setup, not the package pin. 2. Any internal clamping in the device being tested will greatly reduce the voltage levels seen at the package pin.

4.9.4.4

JTAG AC Specification

Table 4-57.TAP Signal Group AC Specification
T# Parameter Min Max Unit Figure Notes

TJC:TCK Period TJCL:TCK Clock Low Time TJCH:TCK Clock High Time TJSU:TDI, TMS Setup Time TJH: TDI, TMS Hold Time TJCO: TCK falling to TDO output valid TJCO: TCK falling to TDO output high impedance T18: TRST$# assert time

15 0.4 * TJC 0.4 * TJC 11 5 11 11 2

ns ns ns ns ns ns ns TJC 4-19 4-18 4-18 4-18

66 MHz

NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. It is recommended that TMS be asserted while TRST# is being deasserted. 4. Board JTAG signal skew max = ±500 ps.

Table 4-58.Boundary Scan AC Specification (Sheet 1 of 2)
T# Parameter Min Max Unit Notes

Boundary scan all non test output/float delay

0.5

15

ns

Referenced to the falling edge of TCK

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Table 4-58.Boundary Scan AC Specification (Sheet 2 of 2)
T# Parameter Min Max Unit Notes

Boundary scan all non test input setup Boundary scan all non test input hold

10 13

---

ns ?s

Referenced to the falling edge of TCK Referenced to the falling edge of TCK

4.9.4.5
4.9.4.5.1

Display AC Specification
LVDS AC characteristic The following table specifics the signal quality parameters for different signal groups

Table 4-59.LVDS Signal Quality Specification
Symbol VCCX VOS_MAX VUS_MAX VOS VUS VOS VUS Parameter LVDS supply Voltage Absolute Maximum Overshoot Absolute Maximum Undershoot Overshoot Voltage Magnitude Undershoot Voltage Magnitude Overshoot Voltage Magnitude Undershoot Voltage Magnitude Max 1.89 V 2.5 V -0.6 V 2.35 -0.45 2.25 -0.35 Time Duration N/A N/A N/A <300 ps <300 ps <600 ps <600 ps Notes 1 2 2 3,4,5 3,4,5 3,4,5 3,4,5

NOTES: 1. Vccx is the voltage at which the time duration for the overshoot voltage is measured 2. The signal voltage must not exceed the absolute maximum OS/US voltage at any time. 3. Activity Factor = 0.25, i.e., 1 out of 4 receive cycles will have the OS/US. 4. Tj = 95C. 5. Below information is based on constraining per pad DPM to <2DPM; Realistic waveforms may have different amount of OS/US.

Table 4-60.LVDS Interface AC Characteristics at Various Frequencies (Sheet 1 of 4)
Symbol LLHT LHLT Parameter LVDS Low-to-High Transition Time LVDS High-to-Low Transition Time Min 0.25 0.25 Nom 0.5 0.5 Max 0.75 0.75 Unit ns ns Figures Figure 4-22 Notes 1, Across receiver termination 1, Across receiver termination

Frequency = 40-MHz

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Table 4-60.LVDS Interface AC Characteristics at Various Frequencies (Sheet 2 of 4)
Symbol TxPPos0 TxPPos1 TxPPos2 TxPPos3 TxPPos4 TxPPos5 TxPPos6 TxJCC Parameter Transmitter Output Pulse for Bit 0 Transmitter Output Pulse for Bit 1 Transmitter Output Pulse for Bit 2 Transmitter Output Pulse for Bit 3 Transmitter Output Pulse for Bit 4 Transmitter Output Pulse for Bit 5 Transmitter Output Pulse for Bit 6 Transmitter Jitter Cycle-to-Cycle Min -0.25 3.32 6.89 10.46 14.04 17.61 21.18 0 3.57 7.14 10.71 14.29 17.86 21.43 350 Nom Max 0.25 3.82 7.39 10.96 14.54 18.11 21.68 370 Unit ns ns ns ns ns ns ns ps Figures Notes

Figure 4-23

Figure 4-23

Frequency = 65-MHz TxPPos0 TxPPos1 TxPPos2 TxPPos3 TxPPos4 TxPPos5 TxPPos6 TxJCC Transmitter Output Pulse for Bit 0 Transmitter Output Pulse for Bit 1 Transmitter Output Pulse for Bit 2 Transmitter Output Pulse for Bit 3 Transmitter Output Pulse for Bit 4 Transmitter Output Pulse for Bit 5 Transmitter Output Pulse for Bit 6 Transmitter Jitter Cycle-to-Cycle -0.20 2.00 4.20 6.39 8.59 10.79 12.99 0 2.20 4.40 6.59 8.79 10.99 13.19 0.20 2.40 4.60 6.79 8.99 11.19 13.39 250 ns ns ns ns ns ns ns ps

Figure 4-23

Frequency = 85–MHz

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Table 4-60.LVDS Interface AC Characteristics at Various Frequencies (Sheet 3 of 4)
Symbol TxPPos0 TxPPos1 TxPPos2 TxPPos3 TxPPos4 TxPPos5 TxPPos6 TxJCC Parameter Transmitter Output Pulse for Bit 0 Transmitter Output Pulse for Bit 1 Transmitter Output Pulse for Bit 2 Transmitter Output Pulse for Bit 3 Transmitter Output Pulse for Bit 4 Transmitter Output Pulse for Bit 5 Transmitter Output Pulse for Bit 6 Transmitter Jitter Cycle-to-Cycle Min -0.20 1.48 3.16 4.84 6.52 8.20 9.88 0 1.68 3.36 5.04 6.72 8.40 10.08 Nom Max 0.20 1.88 3.56 5.24 6.92 8.60 10.28 250 Unit ns ns ns ns ns ns ns ps Figure 4-23 Figures Notes

Frequency = 108–MHz TxPPos0 TxPPos1 TxPPos2 TxPPos3 TxPPos4 TxPPos5 TxPPos6 TxJCC Transmitter Output Pulse for Bit 0 Transmitter Output Pulse for Bit 1 Transmitter Output Pulse for Bit 2 Transmitter Output Pulse for Bit 3 Transmitter Output Pulse for Bit 4 Transmitter Output Pulse for Bit 5 Transmitter Output Pulse for Bit 6 Transmitter Jitter Cycle-to-Cycle -0.20 1.12 2.46 3.76 5.09 6.41 7.74 0 1.32 2.66 3.96 5.29 6.61 7.94 0.20 1.52 2.86 4.16 5.49 6.81 8.14 250 ns ns ns ns ns ns ns ps

Figure 4-23

Frequency = 112 - MHz

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Table 4-60.LVDS Interface AC Characteristics at Various Frequencies (Sheet 4 of 4)
Symbol TxPPos0 TxPPos1 TxPPos2 TxPPos3 TxPPos4 TxPPos5 TxPPos6 TxJCC Parameter Transmitter Output Pulse for Bit 0 Transmitter Output Pulse for Bit 1 Transmitter Output Pulse for Bit 2 Transmitter Output Pulse for Bit 3 Transmitter Output Pulse for Bit 4 Transmitter Output Pulse for Bit 5 Transmitter Output Pulse for Bit 6 Transmitter Jitter Cycle-to-Cycle Min -0.20 1.08 2.35 3.63 4.90 6.18 7.46 0 1.28 2.55 3.83 5.10 6.38 7.66 Nom Max 0.20 1.48 2.75 4.03 5.30 6.58 7.86 250 Unit ns ns ns ns ns ns ns ps Figures Notes

Figure 4-23

4.9.4.5.2

DDI Main Transmitter AC specification

Table 4-61.DDI Main Transmitter AC specification (Sheet 1 of 2)
Symbol UI_High_Rate UI_Low_Rate Down_Spread_A mplitude Down_Spread_F requency TTX-EYE_CHIP _High_Rate TTX-EYE-MEDIANto- MAX-JITTER _CHIP__High_Rate

Parameter Unit Interval for high bit rate (2.7 Gbps / lane) Unit Interval for high bit rate (1.62 Gbps / lane) Link clock down Spreading Link Clock down Spreading Frequency Minimum TX Eye Width at Tx package pins Maximum time between the jitter median and maximum deviation from the median at Tx package pins Minimum TX Eye Width at Tx package pins Maximum time between the jitter median and maximum deviation from the median at Tx package pins D+/D- TX Output Rise/Fall Time at Tx package pins
TX Short Circuit Current Limit

Min

Typ 370 617

Max

Units ps ps

Notes 1 1 2 3 4

0 30 0.726

0.5 33

% kHz UI

0.137

UI

4

TTX-EYE_CHIP
_Low_Rate

0.82

UI

5

TTX-EYE-MEDIANto- MAX-JITTER CHIP Low_Rate

0.09
50 130

UI
ps

5
6

TTX-RISE_CHIP, TTX-FALL_CHIP ITX-SHORT

50

mA

7

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Table 4-61.DDI Main Transmitter AC specification (Sheet 2 of 2)
Symbol LTX-SKEWINTER_
PAIR

Parameter Lane-to-Lane Output Skew at Tx package pins Lane Intra-pair Output Skew at Tx package pins Lane Intra-pair Rise-fall Time Mismatch at Tx package pins. Clock Jitter Rejection Bandwidth TX AC Common Mode Voltage AC Coupling Capacitor Rise time/ Fall time (20%-80%) Undershoot, max

Min

Typ

Max 2 20

Units UI ps

Notes

LTX-SKEWINTRA_
PAIR

TTX-RISE_FALL
_MISMATCH _CHIPDIFF

5

%

8

FTX-REJECTION-BW VTX-AC-CM CTX Trise/ Tfall Vundershoot

4 20 75 75 200 0.4 UI 0.25 of full differen tial amplitu de 0.15 UI 1.212 40 50 60 0.25

MHz mV nF ps V

9 2 11

LTX-SKEWINTER_
PAIR

Intra-Pair skew at source connector Intra-Pair skew at source connector Clock duty cycle, min/average/max TMDS differential Clock Jitter

ps ps % UI 11

LTX-SKEWINTRA_
PAIR

NOTES: 1. High limit = +300ppm; Low limit = -5300ppm 2. Range: 0% ~ 0.5% when downspread enabled 3. Range: 30 KHz ~33 KHz when downspread enabled. 4. For High Bit Rate. 5. For Reduced Bit Rate. 6. At 20 to 80 7. Total drive current of the transmitter when it is shorted to its ground. 8. Informative. D+ rise to D- fall mismatch and D+ fall to D- rise mismatch. 9. Informative. Transmitter jitter must be measured at source connector pins using a signal analyzer that has a 2nd order PLL with tracking bandwidth of 20MHz (for D10.2 pattern) and damping factor of 1.428. 10. Measured at 1.62 GHz and 2.7GHz (if supported), within the frequency tolerance range. Timedomain measurement using a spectrum analyzer. 11. 0.20 Tcharacter @ 165MHz. Tcharacter is the symbol clock Equivalent which 10 times the UI. 12. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the transmitter side. Placement of AC coupling capacitors on the receiver side is optional.

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.

Table 4-62.DDI AUX Channel AC Specification
Symbol UI TAUX-BUS-PARK TCYCLE-to-CYCLE
Jitter

Parameter AUX Unit Interval AUX CH bus park time Maximum allowable UI variation within a single transaction at connector pins of a transmitting Device Maximum allowable UI variation within a single transaction at connector pins of a receiving Device

Min 0.4 10

Typ 0.5

Max 0.6

Units ?s ns

Notes1 1 2 3

0.04

UI

0.05

UI

4

IAUX_SHORT CAUX

AUX Short Circuit Current Limit AC Coupling Capacitor 75

90 200

mA nF

5

NOTES: 1. Results in the bit rate of 1Mbps including the overhead of ManchesterII coding. 2. Period after the AUX CH STOP condition for which the bus is parked 3. Equal to 24 ns maximum. The transmitting Device is a Source Device for a Request transaction and a Sink Device for a Reply Transaction 4. Equal to 30 ns maximum. The transmitting Device is a Source Device for a Request transaction and a Sink Device for a Reply Transaction. 5. Total drive current of the transmitter when it is shorted to its ground. 6. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the transmitter side. Placement of AC coupling capacitors on the receiver side is optional.

4.9.4.5.3

R, G and B / CRT DAC Display Interface Timing The DAC (digital-to-analog converter) consists of three identical 8-bit DACs to provide red, green, and blue color components. Each DAC can output a current from 0 to 255 units of current, where one unit of current (LSB) is defined based on the VESA video signal standard.

Table 4-63.R,G,B / CRT DAC Display AC Specification (Sheet 1 of 2)
Symbol Parameter Min Nom Max Unit Notes

Pixel Clock Frequency = 300-MHz Trise Tfall Tsettling Vo R,G,B Video Rise TIme R,G,B Video Fall TIme Settling time Video Channel-toChannel output skew 0.33 0.33 1.0 0.833 1.67 1.67 ns ns ns ns 1,2,8 (10-90% of “black”-to”white” video transition) 1,3,8 (90-10% of “black”-to”white” video transition) 1,4,8 1,5,8

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Table 4-63.R,G,B / CRT DAC Display AC Specification (Sheet 2 of 2)
Symbol Parameter Overshoot/ Undershoot Noise Injection Ratio Pixel Clock Frequency = 350-MHz Trise Tfall Tsettling Vo R,G,B Video Rise TIme R,G,B Video Fall TIme Settling time Video Channel-toChannel output skew Overshoot/ Undershoot Noise Injection Ratio -0.084 2.5 0.286 0.286 0.857 0.714 1.43 1.43 ns ns ns ns 1,2,8 (10-90% of “black”-to”white” video transition) 1,3,8 (90-10% of “black”-to”white” video transition) 1,4,8 1,5,8 Min -0.084 2.5 Nom Max +0.084 V % Unit Notes 1,6,8 (0.7V full-scale voltage step)

+0.084

V %

1,6,8 (0.7V full-scale voltage step)

NOTES: 1. Measured at each R,G,B termination according to the VESA Test Procedure - Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). 2. R,G,B Max Video Rise/Fall Time: 50% of minimum pixel clock period 3. R,G,B Min Video Rise./Fall Time: 10% of minimum pixel clock period 4. Max settling time: 30% of minimum pixel clock period 5. Video channel-to-channel output skew: 25% of minimum pixel clock period 6. Overshoot/Undershoot: ±12% of “black”-to-”white” video step function 7. Noise Injection Ratio: 2.5% of maximum luminance voltage (dc to max pixel clock frequency) 8. R,G,B AC parameters are strongly dependent on the board design & implementation: actual performance may differ from values noted above depending on board implementation.

Table 4-64.CRT_HSYNC and CRT_VSYNC AC Specification
Symbol
Tf Tr ---

Parameter Fall Time Rise Time Overshoot/Undershoot Jitter (measured between Hsync pulses)

Min
-----

Max 80% of minimum pixel clock period 80% of minimum pixel clock period 30% of high level signal voltage range One half of the difference between max and min interval <15% of the pixel clock, DC to max.

Units ns ns mA V

Notes1

1 2

NOTES: 1. No signal non-monotonicity / excursions allowed in the 0.5 to 2.4V range 2. Measured over 100,000 intervals. Horizontal refresh rate at all image format, worse-case screen patterns.

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Table 4-65.LDDC_DATA, LDDC_CLK, LCTLA_CLK, LCTLB_DATA, CRT_DDC_DATA, and CRT_DDC_CLK Timing Specification
Standard mode 100kbits/s Min FSCL TLOW THIGH TR TF
THD:DAT TSU:DAT

Symbol

Parameter

Units

Figures

Max 100
--

SCL Clock Frequency Low Period of SCL Clock High Period of SCL Clock Rise Signals Time1
1

0 4.7 4 --0 250

kHz ?s ?s ns 4-24 ns ?s ns

-1000 300 ---

of Both SDA and SCL

Fall Time of Both SDA and SCL Signals Data Hold Time3 Data Setup Time

NOTES: 1. Measurement point for rise and fall time: VIL(min) - VIL(max) 2. tHD:DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

4.9.4.6

DMI DC & AC Specification

Table 4-66.DMI Interface Timing (Sheet 1 of 2)
Symbol Transmitter Timings VIH UI VTX-DIFFPP_LOW (half swing)

Parameter

Min

Typ

Max

Unit

Notes

Input High Voltage Unit Interval Low Power Differential p-p Tx voltage swing Tx de-emphasis level Tx AC common mode voltage (2.5 GT/s) DC differential Tx impedance Minimum Transmission Eye Width D+/D- TX Out put Rise/Fall time

0.987 399.88 0.4

1.1031 400.12 1.2

V ps V

6 5

VTx-DE-Ratio3.5dB

3.0 20 80 0.70 0.125

4.0

dB mV

VTX-CM-AC-P ZTx-Diff-DC TTX-EYE TTX-RISE/Fall

120 -

Ohm UI UI 1,2 1,2

Receiver Timings UI Unit Interval – DMI 399.88 400.12 ps 5

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Table 4-66.DMI Interface Timing (Sheet 2 of 2)
Symbol VRX-DIFFPP_CC

Parameter Differential Rx peak-peak voltage for common clock architecture Common Mode Rx return Loss Rx DC common mode impedance DC Differential impedance Rx AC common mode voltage Minimum Receiver Eye Width

Min 0.175 6.0 40 80

Typ

Max 1.2

Unit V dB

Notes

RLRX-CM ZRX-DC ZRX-DIFF-DC VRX_CM_AC_P TRX-EYE

60 120 150

Ohm Ohm mVP UI 3,4

0.40



NOTES: 1. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. 2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. Specified at the measurement point and measured over any 250 consecutive UIs. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 5. Nominal UI Interval for DMI is 400 ps. 6. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value

4.9.4.7

DDR3 AC Specification
This table good for DDR3 electrical characteristic and AC Timing at 1066 MT/s and VDDQ = 1.5 V ±0.075 V

Table 4-67.DDR3 Interface Timing Specification (Sheet 1 of 3)
Symbol Parameter Min Max Unit Figure Notes

DDR3 Electrical Characteristic and AC timings at 1066 MT/s. VDDQ = 1.5 V±0.075 V TSLR_D DQ[63:0], DQS[7:0], DQS#[7:0] Input Slew Rate

System Memory Clock Timings

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Table 4-67.DDR3 Interface Timing Specification (Sheet 2 of 3)
Symbol TCK(AVG) TCH TCL TSKEW Parameter Average CK Period Average CK High Time Average CK Low Time Skew between any System Memory Differential Clock Pair (CK/CK#) 0.45 0.45 100 Min Max 1.875 Unit ns tCKA VG tCKA VG ps Figure Notes

System Memory Command Signal Timings TCMD
(tCMDVB+tCMDVA)

Total CMD Buffer window available for command buffers (RAS#,CAS#, WE#, BS, MA)

1545

ps

1

System Memory Control Signal Timings TCTL
(tCTLVB + tCTLVA)

Total Control buffer Window available for Control buffers (CA#, CKE)

1576

ps

2

System Memory Data and Strobe Signal Timings Data, DQ[63:0] and DM[7:0] timing window available at the interface output for write commands. tDVB is data available before strobe and tDVA is data available after corresponding slope. Data, DQ[63:0] Input Setup Plus Hold Time requirement for successful Read operation. These Setup and Hold numbers are measured w.r.t. corresponding strobe. or Falling Edge TDQSS TWPRE TWPST DQS Preamble duration (one dummy cycle) DQS Postamble Duration 0.9 0.4 tCKA VG tCKA VG 699 ps 3

TDVB+TVDA

332

ps

4

TSU + THD

DDR3 - 800MT/s AC Specification Table DDR3 Electrical Characteristic and AC timings at 800 MT/s. VDDQ = 1.5 V +/- 0.075 V TSLR_D DQ[63:0], DQS[7:0], DQS#[7:0] Input Slew Rate System Memory Clock Timings TCK(AVG) TCH TCL TSKEW Average CK Period Average CK High Time Average CK Low Time Skew between any System Memory Differential Clock Pair (CK/CK#) 100 ps 2.5 ns

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Table 4-67.DDR3 Interface Timing Specification (Sheet 3 of 3)
Symbol Parameter Min Max Unit Figure Notes

System Memory Command Signal Timings TCMD
(tCMDVB+tCMDVA)

Total CMD Buffer window available for command buffers (RASB,CASB, WEB, BS, MA)

2162

ps

1

System Memory Control Signal Timings TCTL
(tCTLVB + tCTLVA)

Total Control buffer Window available for Control buffers (CAB, CKE)

2194

ps

2

System Memory Data and Strobe Signal Timings TDVB+TVDA Data, DQ[63:0] and DM[7:0] timing window available at the interface output for write commands. tDVB is data available before strobe and tDVA is data available after correspo

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