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tms320c6678


TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform

to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS691B August 2011

TMS320C6678 Data Manual
SPRS691B—August 2011
www.ti.com

Release History
Revision Date Description/Comments ? Updated the timing and electrical sections of several peripherals ? Updated the core-specific and general-purpose timer numbers ? Updated the connection matrix tables in chapter 4 “System Interconnection” ? Updated device boot configuration tables and figures ? Updated DDR3 and PASS PLL timing figures ? Removed section 7.1 “Parameter Information” ? Added sections: NMI and LRSET ? Added Pin Map diagrams ? Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers ? Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL ? Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns ? Corrected items in the Memory Map Summary table ? Changed all occurrences of PA_SS to Network Coprocessor ? Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR

SPRS691B August 2011

SPRS691A July 2011

SPRS691

November 2010 Initial release

For detailed revision information, see ‘‘Revision History’’ on page A-211.

2

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011

Contents
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.5.3 PLL Boot Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.7.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.7.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.9 Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.10 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.1 2.2 2.3 2.4 2.5

3

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.3.2 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.3.11 NMI Even Generation to CorePac (NMIGRx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.3.12 IPC Generation (IPCGRx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4

System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.1 Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.2 Switch Fabric Connections Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4.3 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5

C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Copyright 2011 Texas Instruments Incorporated

3

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 5.2 5.3 5.4 5.5 5.6
www.ti.com

5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 103 104 109 109 110 111 111 112 113 115 116 117 118 119 119 119 120 122 123 125 131 132 134 135 136 136 137 137 138 139 140 140 141 141 145 145 162 168 169 170 171 174 179 184 184

6

Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.1 6.2 6.3 6.4

7

Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.1 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.7 Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 DDR3 PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.3 EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.4 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.2 INTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7.11.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.2 I2C Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17 TSIP Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17.1 TSIP Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.1 EMIF16 Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.21 Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.22 Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.24 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.26 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.27 Emulation Features and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.27.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.27.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.27.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
B.1 B.2 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

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List of Figures
Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 4-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DSP Core Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 No Boot/ EMIF16 Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Serial Rapid I/O Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Ethernet (SGMII) Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PCI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I2C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CYP 841-Pin BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Upper Left Quadrant—A (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Upper Right Quadrant—B (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Lower Right Quadrant—C (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Lower Left Quadrant—D (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 C66x DSP Device Nomenclature (including the TMS320C6678). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 NMI Generation Register (NMIGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 IPC Acknowledgement Registers (IPCARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Reset Mux Register RSTMUXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 CorePac Revision ID Register (MM_REVID) Address - 0181 2000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Soft/Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

6

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Main PLL Control Register 0 (MAINPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Main PLL Control Register 1 (MAINPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Main PLL Clock Input Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 DDR3 PLL Control Register 0 (DDR3PLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 PASS PLL Control Register 0 (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 TMS320C6678 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 SPI Additional Timings for 4 Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 UART RTS (Request-to-Send Output) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 TSIP 2x Timing Diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 TSIP 1x Timing Diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 EMIF16 Asynchronous Memory Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 EMIF16 Asynchronous Memory Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 EMIF16 EM_WAIT Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 EMIF16 EM_WAIT Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 CPTS_RFTCLK_SEL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-31 Figure 7-32 Figure 7-33 Figure 7-34 Figure 7-35 Figure 7-36 Figure 7-37 Figure 7-38 Figure 7-39 Figure 7-40 Figure 7-41 Figure 7-42 Figure 7-43 Figure 7-44 Figure 7-45 Figure 7-46 Figure 7-47 Figure 7-48 Figure 7-49 Figure 7-50 Figure 7-51 Figure 7-52 Figure 7-53 Figure 7-54 Figure 7-55 Figure 7-56 Figure 7-57 Figure 7-58 Figure 7-59 Figure 7-60 Figure 7-61

Copyright 2011 Texas Instruments Incorporated

7

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011
www.ti.com

List of Tables
Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 5-2 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Characteristics of the TMS320C6678 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 No Boot / EMIF16 Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Serial Rapid I/O Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PCI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 C66x DSP System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Terminal Functions — Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Terminal Functions — By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 TMS320C6678 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 IPC Generation Registers (IPCGRH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Switch Fabric Connection Matrix Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Switch Fabric Connection Matrix Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Power Supply Rails on TMS320C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

8

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Reset Configuration Register (RSTCFG) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 DDR3 PLL Control Register 0 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 DDR3 PLL Control Register 1 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 PASS PLL Control Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 PASS PLL Control Register 1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 TPCC0 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 TPCC1 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 TPCC2 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 INTC1 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 INTC0/INTC1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 INTC2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 INTC3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 NMI and Local Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 9

Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 7-28 Table 7-29 Table 7-30 Table 7-31 Table 7-32 Table 7-33 Table 7-34 Table 7-35 Table 7-36 Table 7-37 Table 7-38 Table 7-39 Table 7-40 Table 7-41 Table 7-42 Table 7-43 Table 7-44 Table 7-45 Table 7-46 Table 7-47 Table 7-48 Table 7-49 Table 7-50 Table 7-51 Table 7-52 Table 7-53 Table 7-54 Table 7-55 Table 7-56 Table 7-57 Table 7-58 Table 7-59

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 7-60 Table 7-61 Table 7-62 Table 7-63 Table 7-64 Table 7-65 Table 7-66 Table 7-67 Table 7-68 Table 7-69 Table 7-70 Table 7-71 Table 7-72 Table 7-73 Table 7-74 Table 7-75 Table 7-76 Table 7-77 Table 7-78 Table 7-79 Table 7-80 Table 7-81 Table 7-82 Table 7-83 Table 7-84 Table 7-85 Table 7-86 Table 7-87 Table B-1
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Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions . . . . . . . . . . . .181 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .183 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 Timing Requirements for TSIP 2x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 Timing Requirements for TSIP 1x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 EMIF16 Asynchronous Memory Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 CPTS_RFTCLK_SEL Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Thermal Resistance Characteristics (PBGA Package) [CYP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

10

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011

1 Features
? Eight TMS320C66x? DSP Core Subsystems (C66x CorePacs), Each with – 1.25 GHz C66x Fixed/Floating-Point CPU Core ? 40 GMAC/Core for Fixed Point @ 1.25 GHz ? 20 GFLOP/Core for Floating Point @ 1.25 GHz – Memory ? 32K Byte L1P Per Core ? 32K Byte L1D Per Core ? 512K Byte Local L2 Per Core ? Multicore Shared Memory Controller (MSMC) – 4096 KB MSM SRAM Memory Shared by Eight DSP C66x CorePacs – Memory Protection Unit for Both MSM SRAM and DDR3_EMIF ? Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue Manager – Packet-Based DMA for Zero-Overhead Transfers ? Network Coprocessor – Packet Accelerator Enables Support for ? Transport Plane IPsec, GTP-U, SCTP, PDCP ? L2 User Plane PDCP (RoHC, Air Ciphering) ? 1 Gbps Wire-Speed Throughput at 1.5M Packets Per Second – Security Accelerator Engine Enables Support for ? IPSec, SRTP, 3GPP, WiMAX Air Interface, and SSL/TLS Security ? ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 ? Up to 2.8 Gbps Encryption Speed ? Peripherals – Four Lanes of SRIO 2.1 ? 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane ? Supports Direct I/O, Message Passing ? Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations – PCIe Gen2 ? Single port supporting 1 or 2 lanes ? Supports Up To 5 GBaud Per Lane – HyperLink ? Supports Connections to other KeyStone Architecture Devices Providing Resource Scalability ? Supports up to 50 Gbaud – Gigabit Ethernet (GbE) Switch Subsystem ? Two SGMII Ports ? Supports 10/100/1000 Mbps operation – 64-Bit DDR3 Interface (DDR3-1600) ? 8G Byte Addressable Memory Space – 16-Bit EMIF ? Support For Up To 256MB NAND Flash and 16MB NOR Flash ? Support For Asynchronous SRAM up to 1MB – Two Telecom Serial Ports (TSIP) ? Supports 1024 DS0s Per TSIP ? Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps Per Lane – UART Interface – I2C Interface – 16 GPIO Pins – SPI Interface – Semaphore Module – Sixteen 64-Bit Timers – Three On-Chip PLLs ? Commercial Temperature: – 0°C to 85°C ? Extended Temperature: – - 40°C to 100°C

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011
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1.1 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink. Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access. HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

1.2 Device Description
The TMS320C6678 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and automation, and other applications requiring high performance, TI's TMS320C6678 DSP offers 10 GHz cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs. TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity. For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per core raw computational performance is an industry-leading 32 MACS/cycle and 16 flops/cycle. It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware. The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.

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SPRS691B—August 2011

This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I2C, UART, Telecom Serial Interface Port (TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding to the network awareness of this device is a network co-processor that includes both packet and optional security acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for the entire multicore C6678 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities. The C6678 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger interface for visibility into source code execution.

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320C6678 device.
Figure 1-1 Functional Block Diagram

Memory Subsystem
64-Bit DDR3 EMIF
4MB MSM SRAM

MSMC

Debug & Trace

Boot ROM

Semaphore Power Management PLL

C66x CorePac
32KB L1 P-Cache 32KB L1 D-Cache

?3
EDMA

512KB L2 Cache

?3
HyperLink

8 Cores @ up to 1.25 GHz

TeraNet
Multicore Navigator

Queue Manager

Packet DMA

?2

?2

?4

Ethernet Switch

EMIF 16

UART

GPIO

SPI

I2C

Switch

SRIO

PCIe

TSIP

Security Accelerator Packet Accelerator

SGMII ?2

Network Coprocessor

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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the TMS320C6678 DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the DSP frequency, and the package and pin count.
Table 2-1 Characteristics of the TMS320C6678 Processor
HARDWARE FEATURES DDR3 Memory Controller (64-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P) EDMA3 (16 independent channels) [DSP/2 clock rate] EDMA3 (64 independent channels) [DSP/3 clock rate] High-speed 1×/2x/4× Serial RapidIO Port (4 lanes) PCIe (2 lanes) 10/100/1000 Ethernet Management Data Input/Output (MDIO) Peripherals HyperLink EMIF16 TSIP SPI UART IC 64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) General-Purpose Input/Output Port (GPIO) Accelerators Packet Accelerator Security Accelerator Size (Bytes)
(1) 2

TMS320C6678 1 1 2 1 1 2 1 1 1 2 1 1 1 Sixteen 64-bit (each configurable as two32-bit timers) 16 1 1 8832KB 256KB L1 Program Memory [SRAM/Cache] 256KB L1 Data Memory [SRAM/Cache]

On-Chip Memory

Organization

4096KB L2 Unified Memory/Cache 4096KB MSM SRAM 128KB L3 ROM

C66x CorePac Revision ID JTAG BSDL_ID Frequency

CorePac Revision ID Register (address location: 0181 2000h) JTAGID register (address location: 0262 0018h) MHz

See Section 5.5 ‘‘C66x CorePac Revision’’ on page 98. See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register Description’’ on page 71 1250 (1.25 GHz) 1000 (1.0 GHz) 0.8 ns (1.25 GHz) 1 ns (1.0 GHz) SmartReflex variable supply 1.0 V, 1.5 V, and 1.8 V 0.040 μm 841-Pin Flip-Chip Plastic BGA (CYP) PD

Cycle Time

ns Core (V) I/O (V) μm 24 mm × 24 mm
(2)

Voltage Process Technology BGA Package Product Status

Product Preview (PP), Advance Information (AI), or Production Data (PD)

End of Table 2-1
1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

2.2 DSP Core Description
The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler. The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data. 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3 upper registers. The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions that multiply a complex number with a complex conjugate of another number with rounding capability. Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability. A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix. Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one the following floating-point operations each clock cycle: one, two, or four single-precision multiplies or a complex single-precision multiply.

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The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number. The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall until the completion of all the DSP-triggered memory transactions, including: ? Cache line fills ? Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints ? Victim write backs ? Block or global coherence operations ? Cache mode changes ? Outstanding XMC prefetch requests This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations. For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following documents: ? C66x CPU and Instruction Set Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64. ? C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64. ? C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

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Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1 DSP Core Data Paths
Note: Default bus width is 64 bits (i.e. a register pair)
src1

.L1

src2

dst ST1 src1

Register File A (A0, A1, A2, ...A31)

.S1

src2 dst

Data Path A
.M1

src1 src1_hi src2 src2_hi dst2 dst1
LD1

src1 DA1
32

32

.D1

dst
src2
32

32

32

2? 1?

src2
DA2
32

32 32 32 32 32

.D2

dst src1

Register File B (B0, B1, B2, ...B31)

LD2 dst1 dst2 src2_hi

.M2

src2 src1_hi src1

Data Path B
dst

.S2

src2 src1

ST2 dst

.L2

src2

src1

32

Control Register

32

18

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SPRS691B—August 2011

2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the TMS320C6678 device.
Table 2-2
Start 00000000 00800000 00880000 00E00000 00E08000 00F00000 00F08000 01800000 01C00000 01D00000 01D00080 01D08000 01D08080 01D10000 01D10080 01D18000 01D18080 01D20000 01D20080 01D28000 01D28080 01D30000 01D30080 01D38000 01D38080 01D40000 01D40080 01D48000 01D48080 01D50000 01D50080 01D58000 01D58080 01D60000 01D60080 01D68000 01D68080 01D70000 01D70080 01D78000

Memory Map Summary (Part 1 of 7)
Physical 36-bit Address Start 0 00000000 0 00800000 0 00880000 0 00E00000 0 00E08000 0 00F00000 0 00F08000 0 01800000 0 01C00000 0 01D00000 0 01D00080 0 01D08000 0 01D08080 0 01D10000 0 01D10080 0 01D18000 0 01D18080 0 01D20000 0 01D20080 0 01D28000 0 01D28080 0 01D30000 0 01D30080 0 01D38000 0 01D38080 0 01D40000 0 01D40080 0 01D48000 0 01D48080 0 01D50000 0 01D50080 0 01D58000 0 01D58080 0 01D60000 0 01D60080 0 01D68000 0 01D68080 0 01D70000 0 01D70080 0 01D78000 End 0 007FFFFF 0 0087FFFF 0 00DFFFFF 0 00E07FFF 0 00EFFFFF 0 00F07FFF 0 017FFFFF 0 01BFFFFF 0 01CFFFFF 0 01D0007F 0 01D07FFF 0 01D0807F 0 01D0FFFF 0 01D1007F 0 01D17FFF 0 01D1807F 0 01D1FFFF 0 01D2007F 0 01D27FFF 0 01D2807F 0 01D2FFFF 0 01D3007F 0 01D37FFF 0 01D3807F 0 01D3FFFF 0 01D4007F 0 01D47FFF 0 01D4807F 0 01D4FFFF 0 01D5007F 0 01D57FFF 0 01D5807F 0 01D5FFFF 0 01D6007F 0 01D67FFF 0 01D6807F 0 01D6FFFF 0 01D7007F 0 01D77FFF 0 01D7807F Bytes 8M 512K 5M+512K 32K 1M-32K 32K 9M-32K 4M 1M 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 Description Reserved Local L2 SRAM Reserved Local L1P SRAM Reserved Local L1D SRAM Reserved C66x CorePac Registers Reserved Tracer 0 Reserved Tracer 1 Reserved Tracer 2 Reserved Tracer 3 Reserved Tracer 4 Reserved Tracer 5 Reserved Tracer 6 Reserved Tracer 7 Reserved Tracer 8 Reserved Tracer 9 Reserved Tracer 10 Reserved Tracer 11 Reserved Tracer 12 Reserved Tracer 13 Reserved Tracer 14 Reserved Tracer 15 End 007FFFFF 0087FFFF 00DFFFFF 00E07FFF 00EFFFFF 00F07FFF 017FFFFF 01BFFFFF 01CFFFFF 01D0007F 01D07FFF 01D0807F 01D0FFFF 01D1007F 01D17FFF 01D1807F 01D1FFFF 01D2007F 01D27FFF 01D2807F 01D2FFFF 01D3007F 01D37FFF 01D3807F 01D3FFFF 01D4007F 01D47FFF 01D4807F 01D4FFFF 01D5007F 01D57FFF 01D5807F 01D5FFFF 01D6007F 01D67FFF 01D6807F 01D6FFFF 01D7007F 01D77FFF 01D7807F

Logical 32-bit Address

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-2
Start 01D78080 01D80000 01D80080 01E00000 01E40000 01E80000 01EC0000 02000000 02100000 02200000 02200080 02210000 02210080 02220000 02220080 02230000 02230080 02240000 02240080 02250000 02250080 02260000 02260080 02270000 02270080 02280000 02280080 02290000 02290080 022A0000 022A0080 022B0000 022B0080 022C0000 022C0080 022D0000 022D0080 022E0000 022E0080 022F0000 022F0080 02300000
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Memory Map Summary (Part 2 of 7)
Physical 36-bit Address Start 0 01D78080 0 01D80000 0 01D80080 0 01E00000 0 01E40000 0 01E80000 0 01EC0000 0 02000000 0 02100000 0 02200000 0 02200080 0 02210000 0 02210080 0 02220000 0 02220080 0 02230000 0 02230080 0 02240000 0 02240080 0 02250000 0 02250080 0 02260000 0 02260080 0 02270000 0 02270080 0 02280000 0 02280080 0 02290000 0 02290080 0 022A0000 0 022A0080 0 022B0000 0 022B0080 0 022C0000 0 022C0080 0 022D0000 0 022D0080 0 022E0000 0 022E0080 0 022F0000 0 022F0080 0 02300000 End 0 01D7FFFF 0 01D8007F 0 01DFFFFF 0 01E3FFFF 0 01E7FFFF 0 01EBFFFF 0 01FFFFFF 0 020FFFFF 0 021FFFFF 0 0220007F 0 0220FFFF 0 0221007F 0 0221FFFF 0 0222007F 0 0222FFFF 0 0223007F 0 0223FFFF 0 0224007F 0 0224FFFF 0 0225007F 0 0225FFFF 0 0226007F 0 0226FFFF 0 0227007F 0 0227FFFF 0 0228007F 0 0228FFFF 0 0229007F 0 0229FFFF 0 022A007F 0 022AFFFF 0 022B007F 0 022BFFFF 0 022C007F 0 022CFFFF 0 022D007F 0 022DFFFF 0 022E007F 0 022EFFFF 0 022F007F 0 022FFFFF 0 0230FFFF Bytes 32K-128 128 512K-128 256K 256K 256K 1M +256K 1M 1M 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 64K Description Reserved Tracer 16 Reserved Telecom Serial Interface Port (TSIP) 0 Reserved Telecom Serial Interface Port (TSIP) 1 Reserved Network Coprocessor (Packet Accelerator, Gigabit Ethernet Switch Subsystem and Security Accelerator) Reserved Timer0 Reserved Timer1 Reserved Timer2 Reserved Timer3 Reserved Timer4 Reserved Timer5 Reserved Timer6 Reserved Timer7 Reserved Timer8 Reserved Timer9 Reserved Timer10 Reserved Timer11 Reserved Timer12 Reserved Timer13 Reserved Timer14 Reserved Timer15 Reserved Reserved End 01D7FFFF 01D8007F 01DFFFFF 01E3FFFF 01E7FFFF 01EBFFFF 01FFFFFF 020FFFFF 021FFFFF 0220007F 0220FFFF 0221007F 0221FFFF 0222007F 0222FFFF 0223007F 0223FFFF 0224007F 0224FFFF 0225007F 0225FFFF 0226007F 0226FFFF 0227007F 0227FFFF 0228007F 0228FFFF 0229007F 0229FFFF 022A007F 022AFFFF 022B007F 022BFFFF 022C007F 022CFFFF 022D007F 022DFFFF 022E007F 022EFFFF 022F007F 022FFFFF 0230FFFF

Logical 32-bit Address

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Memory Map Summary (Part 3 of 7)
Physical 36-bit Address Start 0 02310000 0 02310200 0 02320000 0 02320100 0 02330000 0 02330400 0 02350000 0 02351000 0 02360000 0 02360400 0 02368000 0 02368400 0 02370000 0 02370400 0 02378000 0 02378400 0 02380000 0 02440000 0 02444000 0 02450000 0 02454000 0 02460000 0 02464000 0 02470000 0 02474000 0 02480000 0 02484000 0 02490000 0 02494000 0 024A0000 0 024A4000 0 024B0000 0 024B4000 0 024C0000 0 02530000 0 02530080 0 02540000 0 02540400 0 02550000 0 02600000 0 02602000 0 02604000 0 02606000 End 0 023101FF 0 0231FFFF 0 023200FF 0 0232FFFF 0 023303FF 0 0234FFFF 0 02350FFF 0 0235FFFF 0 023603FF 0 02367FFF 0 023683FF 0 0236FFFF 0 023703FF 0 02377FFF 0 023783FF 0 0237FFFF 0 0243FFFF 0 02443FFF 0 0244FFFF 0 02453FFF 0 0245FFFF 0 02463FFF 0 0246FFFF 0 02473FFF 0 0247FFFF 0 02483FFF 0 0248FFFF 0 02493FFF 0 0249FFFF 0 024A3FFF 0 024AFFFF 0 024B3FFF 0 024BFFFF 0 0252FFFF 0 0253007F 0 0253FFFF 0 0254003F 0 0254FFFF 0 025FFFFF 0 02601FFF 0 02603FFF 0 02605FFF 0 02607FFF Bytes 512 64K-512 256 64K-256 1K 127K 4K 64K-4K 1K 31K 1K 31K 1K 31K 1K 31K 768K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 448K 128 64K-128 64 64K-64 704K 8K 8K 8K 8K Description PLL Controller Reserved GPIO Reserved SmartReflex Reserved Power Sleep Controller (PSC) Reserved Memory Protection Unit (MPU) 0 Reserved Memory Protection Unit (MPU) 1 Reserved Memory Protection Unit (MPU) 2 Reserved Memory Protection Unit (MPU) 3 Reserved Reserved DSP trace formatter 0 Reserved DSP trace formatter 1 Reserved DSP trace formatter 2 Reserved DSP trace formatter 3 Reserved DSP trace formatter 4 Reserved DSP trace formatter 5 Reserved DSP trace formatter 6 Reserved DSP trace formatter 7 Reserved Reserved I C data & control Reserved UART Reserved Reserved Secondary Interrupt Controller (INTC) 0 Reserved Secondary Interrupt Controller (INTC) 1 Reserved
2

Table 2-2
Start 02310000 02310200 02320000 02320100 02330000 02330400 02350000 02351000 02360000 02360400 02368000 02368400 02370000 02370400 02378000 02378400 02380000 02440000 02444000 02450000 02454000 02460000 02464000 02470000 02474000 02480000 02484000 02490000 02494000 024A0000 024A4000 024B0000 024B4000 024C0000 02530000 02530080 02540000 02540400 02550000 02600000 02602000 02604000 02606000

Logical 32-bit Address End 023101FF 0231FFFF 023200FF 0232FFFF 023303FF 0234FFFF 02350FFF 0235FFFF 023603FF 02367FFF 023683FF 0236FFFF 023703FF 02377FFF 023783FF 0237FFFF 0243FFFF 02443FFF 0244FFFF 02453FFF 0245FFFF 02463FFF 0246FFFF 02473FFF 0247FFFF 02483FFF 0248FFFF 02493FFF 0249FFFF 024A3FFF 024AFFFF 024B3FFF 024BFFFF 0252FFFF 0253007F 0253FFFF 0254003F 0254FFFF 025FFFFF 02601FFF 02603FFF 02605FFF 02607FFF

Copyright 2011 Texas Instruments Incorporated

21

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-2
Start 02608000 0260A000 0260C000 0260E000 02620000 02620800 02640000 02640800 02650000 02700000 02708000 02720000 02728000 02740000 02748000 02760000 02760400 02768000 02768400 02770000 02770400 02778000 02778400 02780000 02780400 02788000 02788400 02790000 02790400 02798000 02798400 027A0000 027A0400 027A8000 027A8400 027B0000 027D0000 027D1000 027E0000 027E1000 027F0000 027F1000 02800000
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Memory Map Summary (Part 4 of 7)
Physical 36-bit Address Start 0 02608000 0 0260A000 0 0260C000 0 0260E000 0 02620000 0 02620800 0 02640000 0 02640800 0 02650000 0 02700000 0 02708000 0 02720000 0 02728000 0 02740000 0 02748000 0 02760000 0 02760400 0 02768000 0 02768400 0 02770000 0 02770400 0 02778000 0 02778400 0 02780000 0 02780400 0 02788000 0 02788400 0 02790000 0 02790400 0 02798000 0 02798400 0 027A0000 0 027A0400 0 027A8000 0 027A8400 0 027B0000 0 027D0000 0 027D1000 0 027E0000 0 027E1000 0 027F0000 0 027F1000 0 02800000 End 0 02609FFF 0 0260BFFF 0 0260DFFF 0 0261FFFF 0 026207FF 0 0263FFFF 0 026407FF 0 0264FFFF 0 026FFFFF 0 02707FFF 0 0271FFFF 0 02727FFF 0 0273FFFF 0 02747FFF 0 0275FFFF 0 027603FF 0 02767FFF 0 027683FF 0 0276FFFF 0 027703FF 0 02777FFF 0 027783FF 0 0277FFFF 0 027803FF 0 02787FFF 0 027883FF 0 0278FFFF 0 027903FF 0 02797FFF 0 027983FF 0 0279FFFF 0 027A03FF 0 027A7FFF 0 027A83FF 0 027AFFFF 0 027CFFFF 0 027D0FFF 0 027DFFFF 0 027E0FFF 0 027EFFFF 0 027F0FFF 0 027FFFFF 0 02800FFF Bytes 8K 8K 8K 72K 2K 126K 2K 64K-2K 704K 32K 96K 32K 96K 32K 96K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 128K 4K 60K 4K 60K 4K 60K 4K Description Secondary Interrupt Controller (INTC) 2 Reserved Secondary Interrupt Controller (INTC) 3 Reserved Chip-Level Registers Reserved Semaphore Reserved Reserved EDMA Channel Controller (TPCC) 0 Reserved EDMA Channel Controller (TPCC) 1 Reserved EDMA Channel Controller (TPCC) 2 Reserved EDMA TPCC0 Transfer Controller (TPTC) 0 Reserved EDMA TPCC0 Transfer Controller (TPTC) 1 Reserved EDMA TPCC1 Transfer Controller (TPTC) 0 Reserved EDMA TPCC1 Transfer Controller (TPTC) 1 Reserved EDMA TPCC1 Transfer Controller (TPTC) 2 Reserved EDMA TPCC1Transfer Controller (TPTC) 3 Reserved EDMA TPCC2 Transfer Controller (TPTC) 0 Reserved EDMA TPCC2 Transfer Controller (TPTC) 1 Reserved EDMA TPCC2 Transfer Controller (TPTC) 2 Reserved EDMA TPCC2 Transfer Controller (TPTC) 3 Reserved Reserved TI embedded trace buffer (TETB) - CorePac0 Reserved TI embedded trace buffer (TETB) - CorePac1 Reserved TI embedded trace buffer (TETB) - CorePac2 Reserved TI embedded trace buffer (TETB) - CorePac3 End 02609FFF 0260BFFF 0260DFFF 0261FFFF 026207FF 0263FFFF 026407FF 0264FFFF 026FFFFF 02707FFF 0271FFFF 02727FFF 0273FFFF 02747FFF 0275FFFF 027603FF 02767FFF 027683FF 0276FFFF 027703FF 02777FFF 027783FF 0277FFFF 027803FF 02787FFF 027883FF 0278FFFF 027903FF 02797FFF 027983FF 0279FFFF 027A03FF 027A7FFF 027A83FF 027AFFFF 027CFFFF 027D0FFF 027DFFFF 027E0FFF 027EFFFF 027F0FFF 027FFFFF 02800FFF

Logical 32-bit Address

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SPRS691B—August 2011 Memory Map Summary (Part 5 of 7)
Physical 36-bit Address Start 0 02801000 0 02810000 0 02811000 0 02820000 0 02821000 0 02830000 0 02831000 0 02840000 0 02841000 0 02850000 0 02858000 0 02860000 0 02900000 0 02921000 0 02A00000 0 02C00000 0 08000000 0 08010000 0 0BC00000 0 0BD00000 0 0C000000 0 0C400000 0 10800000 0 10880000 0 10900000 0 10E00000 0 10E08000 0 10F00000 0 10F08000 0 11800000 0 11880000 0 11900000 0 11E00000 0 11E08000 0 11F00000 0 11F08000 0 12800000 0 12880000 0 12900000 0 12E00000 0 12E08000 0 12F00000 0 12F08000 End 0 0280FFFF 0 02810FFF 0 0281FFFF 0 02820FFF 0 0282FFFF 0 02830FFF 0 0283FFFF 0 02840FFF 0 0284FFFF 0 02857FFF 0 0285FFFF 0 028FFFFF 0 02920FFF 0 029FFFFF 0 02BFFFFF 0 07FFFFFF 0 0800FFFF 0 0BBFFFFF 0 0BCFFFFF 0 0BFFFFFF 0 0C3FFFFF 0 107FFFFF 0 1087FFFF 0 108FFFFF 0 10DFFFFF 0 10E07FFF 0 10EFFFFF 0 10F07FFF 0 117FFFFF 0 1187FFFF 0 118FFFFF 0 11DFFFFF 0 11E07FFF 0 11EFFFFF 0 11F07FFF 0 127FFFFF 0 1287FFFF 0 128FFFFF 0 12DFFFFF 0 12E07FFF 0 12EFFFFF 0 12F07FFF 0 137FFFFF Bytes 60K 4K 60K 4K 60K 4K 60K 4K 60K 32K 32K 640K 132K 1M-132K 2M 84M 64K 60M-64K 1M 3M 4M 68 M 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 9M-32K Description Reserved TI embedded trace buffer (TETB) - CorePac4 Reserved TI embedded trace buffer (TETB) - CorePac5 Reserved TI embedded trace buffer (TETB) - CorePac6 Reserved TI embedded trace buffer (TETB) - CorePac7 Reserved TI embedded trace buffer (TETB) — system Reserved Reserved Serial RapidIO (SRIO) configuration Reserved Queue manager subsystem configuration Reserved Extended memory controller (XMC) configuration Reserved Multicore shared memory controller (MSMC) config Reserved Multicore shared memory (MSM) Reserved CorePac0 L2 SRAM Reserved Reserved CorePac0 L1P SRAM Reserved CorePac0 L1D SRAM Reserved CorePac1 L2 SRAM Reserved Reserved CorePac1 L1P SRAM Reserved CorePac1 L1D SRAM Reserved CorePac2 L2 SRAM Reserved Reserved CorePac2 L1P SRAM Reserved CorePac2 L1D SRAM Reserved End 0280FFFF 02810FFF 0281FFFF 02820FFF 0282FFFF 02830FFF 0283FFFF 02840FFF 0284FFFF 02857FFF 0285FFFF 028FFFFF 02920FFF 029FFFFF 02BFFFFF 07FFFFFF 0800FFFF 0BBFFFFF 0BCFFFFF 0BFFFFFF 0C3FFFFF 107FFFFF 1087FFFF 108FFFFF 10DFFFFF 10E07FFF 10EFFFFF 10F07FFF 117FFFFF 1187FFFF 118FFFFF 11DFFFFF 11E07FFF 11EFFFFF 11F07FFF 127FFFFF 1287FFFF 128FFFFF 12DFFFFF 12E07FFF 12EFFFFF 12F07FFF 137FFFFF

Table 2-2
Start 02801000 02810000 02811000 02820000 02821000 02830000 02831000 02840000 02841000 02850000 02858000 02860000 02900000 02921000 02A00000 02C00000 08000000 08010000 0BC00000 0BD00000 0C000000 0C400000 10800000 10880000 10900000 10E00000 10E08000 10F00000 10F08000 11800000 11880000 11900000 11E00000 11E08000 11F00000 11F08000 12800000 12880000 12900000 12E00000 12E08000 12F00000 12F08000

Logical 32-bit Address

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-2
Start 13800000 13880000 13900000 13E00000 13E08000 13F00000 13F08000 14800000 14880000 14900000 14E00000 14E08000 14F00000 14F08000 15800000 15880000 15900000 15E00000 15E08000 15F00000 15F08000 16800000 16880000 16900000 16E00000 16E08000 16F00000 16F08000 17800000 17880000 17900000 17E00000 17E08000 17F00000 17F08000 20000000 20100000 20B00000 20B20000 20BF0000 20BF0400 20C00000 20C00100
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Memory Map Summary (Part 6 of 7)
Physical 36-bit Address Start 0 13800000 0 13880000 0 13900000 0 13E00000 0 13E08000 0 13F00000 0 13F08000 0 14800000 0 14880000 0 14900000 0 14E00000 0 14E08000 0 14F00000 0 14F08000 0 15800000 0 15880000 0 15900000 0 15E00000 0 15E08000 0 15F00000 0 15F08000 0 16800000 0 16880000 0 16900000 0 16E00000 0 16E08000 0 16F00000 0 16F08000 0 17800000 0 17880000 0 17900000 0 17E00000 0 17E08000 0 17F00000 0 17F08000 0 20000000 0 20100000 0 20B00000 0 20B20000 0 20BF0000 0 20BF0400 0 20C00000 0 20C00100 End 0 1387FFFF 0 138FFFFF 0 13DFFFFF 0 13E07FFF 0 13EFFFFF 0 13F07FFF 0 147FFFFF 0 1487FFFF 0 148FFFFF 0 14DFFFFF 0 14E07FFF 0 14EFFFFF 0 14F07FFF 0 157FFFFF 0 1587FFFF 0 158FFFFF 0 15DFFFFF 0 15E07FFF 0 15EFFFFF 0 15F07FFF 0 167FFFFF 0 1687FFFF 0 168FFFFF 0 16DFFFFF 0 16E07FFF 0 16EFFFFF 0 16F07FFF 0 177FFFFF 0 1787FFFF 0 178FFFFF 0 17DFFFFF 0 17E07FFF 0 17EFFFFF 0 17F07FFF 0 1FFFFFFF 0 200FFFFF 0 20AFFFFF 0 20B1FFFF 0 20BEFFFF 0 20BF03FF 0 20BFFFFF 0 20C000FF 0 20FFFFFF Bytes 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 9M-32K 512K 512K 5M 32K 1M-32K 32K 129M-32K 1M 10M 128K 832K 1K 63K 256 12M - 256 Description CorePac3 L2 SRAM Reserved Reserved CorePac3 L1P SRAM Reserved CorePac3 L1D SRAM Reserved CorePac4 L2 SRAM Reserved Reserved CorePac4 L1P SRAM Reserved CorePac4 L1D SRAM Reserved CorePac5 L2 SRAM Reserved Reserved CorePac5 L1P SRAM Reserved CorePac5 L1D SRAM Reserved CorePac6 L2 SRAM Reserved Reserved CorePac6 L1P SRAM Reserved CorePac6 L1D SRAM Reserved CorePac7 L2 SRAM Reserved Reserved CorePac7 L1P SRAM Reserved CorePac7 L2 SRAM Reserved System trace manager (STM) configuration Reserved Boot ROM Reserved SPI Reserved EMIF16 config Reserved End 1387FFFF 138FFFFF 13DFFFFF 13E07FFF 13EFFFFF 13F07FFF 147FFFFF 1487FFFF 148FFFFF 14DFFFFF 14E07FFF 14EFFFFF 14F07FFF 157FFFFF 1587FFFF 158FFFFF 15DFFFFF 15E07FFF 15EFFFFF 15F07FFF 167FFFFF 1687FFFF 168FFFFF 16DFFFFF 16E07FFF 16EFFFFF 16F07FFF 177FFFFF 1787FFFF 178FFFFF 17DFFFFF 17E07FFF 17EFFFFF 17F07FFF 1FFFFFFF 200FFFFF 20AFFFFF 20B1FFFF 20BEFFFF 20BF03FF 20BFFFFF 20C000FF 20FFFFFF

Logical 32-bit Address

24

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SPRS691B—August 2011 Memory Map Summary (Part 7 of 7)
Physical 36-bit Address Start 0 21000000 0 21000100 0 21400000 0 21400400 0 21800000 0 21808000 0 34000000 0 34200000 0 40000000 0 50000000 0 60000000 0 70000000 0 74000000 0 78000000 0 7C000000 8 80000000 End 0 21000123 0 213FFFFF 0 214003FF 0 217FFFFF 0 21807FFF 0 33FFFFFF 0 341FFFFF 0 3FFFFFFF 0 4FFFFFFF 0 5FFFFFFF 0 6FFFFFFF 0 73FFFFFF 0 77FFFFFF 0 7BFFFFFF 0 7FFFFFFF 8 FFFFFFFF Bytes 292 4M-256 1K 4M-1K 32K 296M-32K 2M 190M 256M 256M 256M 64M 64M 64M 64M 2G Description DDR3 EMIF configuration Reserved HyperLink config Reserved PCIe config Reserved Queue manager subsystem data Reserved HyperLink data Reserved PCIe data EMIF16 CS2 data space, supports NAND, NOR or SRAM memory EMIF16 CS3 data space, supports NAND, NOR or SRAM memory
(1) (1)

Table 2-2
Start 21000000 21000100 21400000 21400400 21800000 21808000 34000000 34200000 40000000 50000000 60000000 70000000 74000000 78000000 7C000000 80000000

Logical 32-bit Address End 21000123 213FFFFF 214003FF 217FFFFF 21807FFF 33FFFFFF 341FFFFF 3FFFFFFF 4FFFFFFF 5FFFFFFF 6FFFFFFF 73FFFFFF 77FFFFFF 7BFFFFFF 7FFFFFFF FFFFFFFF

EMIF16 CS4 data space, supports NAND, NOR or SRAM memory(1) EMIF16 CS5 data space, supports NAND, NOR or SRAM memory DDR3 EMIF data
(1)

End of Table 2-2
1 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. More than 32MB allowed by NAND flash

2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section 7.4 ‘‘Reset Controller’’ on page 115. The C6678 supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

2.5 Boot Modes Supported and PLL Settings
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes: ? Public ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base 2 address. After performing the boot process (e.g., from I C ROM, Ethernet, or RapidIO), C66x CorePac0 then begins execution from the provided boot entry point, other C66x CorePac’s are released from reset and begin executing an IDLE from the L3 ROM. They are then released from IDLE based on interrupts generated by C66x CorePac0. See the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 for more details.

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?

Secure ROM Boot - On secure devices, the C66x CorePac0 is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which C66x CorePac0 initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].
Figure 2-2 Boot Mode Pin Decoding
Boot Mode Pins 12
2

11

10

9

8

7

6 Device Configuration

5

4

3

2

1 Boot Device

0

PLL Mult I C /SPI Ext Dev Cfg

2.5.1 Boot Device Field The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot modes.
Table 2-3
Bit 2-0 Field Boot Device

Boot Mode Pins: Boot Device Values
Description Device boot mode 0 = EMIF16 / No Boot 1 = Serial Rapid I/O 2 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as CORECLK(P|N); BOOTMODE[12:10] values drive the PASS PLL configuration during boot. 3 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as SRIOSGMIICLK(P|N); BOOTMODE[9:8] values drive the PASS PLL configuration during boot. 4 = PCIe 5 = I2C 6 = SPI 7 = HyperLink

End of Table 2-3

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SPRS691B—August 2011

2.5.2 Device Configuration Field The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode
2.5.2.1 No Boot/ EMIF16 Boot Device Configuration
Figure 2-3
9 Sub-Mode

No Boot/ EMIF16 Configuration Fields
8 7 Wait Enable 6 5 Reserved 4 3

Table 2-4
Bit 9-8 Field

No Boot / EMIF16 Configuration Field Descriptions
Description Sub mode selection. 0 = No boot 1 = EMIF16 boot 2 -3 = Reserved Extended Wait mode for EMIF16. 0 = Wait enable disabled (EMIF16 sub mode) 1 = Wait enable enabled (EMIF16 sub mode) Reserved

Sub-Mode

7

Wait Enable

6-3

Reserved

End of Table 2-4

2.5.2.2 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 2-4
9 Lane Setup

Serial Rapid I/O Device Configuration Fields
8 Data Rate 7 6 Ref Clock 5 4 Reserved 3

Table 2-5
Bit 9 Field

Serial Rapid I/O Configuration Field Descriptions
Description SRIO port and lane configuration 0 = Port Configured as 4 ports each 1 lane wide (4 -1× ports) 1 = Port Configured as 2 ports 2 lanes wide (2 – 2× ports) SRIO data rate configuration 0 = 1.25 GBaud/s 1 = 2.5 GBaud/s 2 = 3.125 GBaud/s 3 = 5.0 GBaud/s SRIO reference clock configuration 0 = 156.25 MHz 1 = 250 MHz 2 = 312.5 MHz 3 = Reserved Reserved

Lane Setup

8-7

Data Rate

6-5

Ref Clock

4-3

Reserved

End of Table 2-5

In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.
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2.5.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 2-5
9 SerDes Clock Mult

Ethernet (SGMII) Device Configuration Fields
8 7 Ext connection 6 5 4 Device ID 3

Table 2-6
Bit 9-8 Field

Ethernet (SGMII) Configuration Field Descriptions
Description SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs. 0 = ×8 for input clock of 156.25 MHz 1 = ×5 for input clock of 250 MHz 2 = ×4 for input clock of 312.5 MHz 3 = Reserved External connection mode 0 = MAC to MAC connection, master with auto negotiation 1 = MAC to MAC connection, slave, and MAC to PHY 2 = MAC to MAC, forced link 3 = MAC to fiber connection This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.

SerDes Clock Mult

7-6

Ext connection

5

Device ID

End of Table 2-6

2.5.2.4 PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.
Figure 2-6
9 Reserved

PCI Device Configuration Fields
8 7 BAR Config 6 5 4 Reserved 3

Table 2-7
Bit 9 8-5 4-3 Field

PCI Device Configuration Field Descriptions
Description Reserved PCIe BAR registers configuration This value can range from 0 to 0xf. See Table 2-8. Reserved Reserved

Reserved BAR Config

End of Table 2-7

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SPRS691B—August 2011 BAR Config / PCIe Window Sizes
32-Bit Address Translation 64-Bit Address Translation BAR5 Clone of BAR4 BAR2/3 BAR4/5

Table 2-8

BAR cfg 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111

BAR0 PCIe MMRs

BAR1 32 16 16 32 16 16 32 32 64 4 4 4

BAR2 32 16 32 32 16 32 32 32 64 128 128 128

BAR3 32 32 32 32 64 64 64 64 128 128 128 256

BAR4 32 64 64 64 64 64 64 128 256 128 256 256

256 512 1024 2048

256 512 1024 2048

End of Table 2-8

2.5.2.5 I C Boot Device Configuration
2.5.2.5.1 I2C Master Mode

2

In master mode, the I C device configuration uses ten bits of device configuration instead of seven as used in other 2 boot modes. In this mode, the device will make the initial read of the I C EEPROM while the PLL is in bypass mode. The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
Figure 2-7
12 Reserved

2

I2C Master Mode Device Configuration Bit Fields
11 Speed 10 Address 9 Reserved 8 Mode 7 6 5 Parameter Index 4 3

Table 2-9
Bit 12 11 Field

I2C Master Mode Device Configuration Field Descriptions
Description Reserved I C data rate configuration 2 0 = I C data rate set to approximately 20 kHz 2 1 = I C fast mode. Data rate set to approximately 400 kHz (will not exceed) I2C bus address configuration 2 2 0 = Boot from I C EEPROM at I C bus address 0x50 2 1 = Boot from I C EEPROM at I2C bus address 0x51 Reserved I C operation mode 0 = Master mode 2 1 = Passive mode (see section 2.5.2.5.2 ‘‘I C Passive Mode’’) Identifies the index of the configuration table initially read from the I2C EEPROM This value can range from 0 to 31.
2 2

Reserved Speed

10

Address

9 8

Reserved Mode

7-3

Parameter Index

End of Table 2-9

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In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
Figure 2-8
9 Reserved

I2C Passive Mode Device Configuration Bit Fields
8 Mode 7 6 Receive I C Address
2

5

4 Reserved

3

Table 2-10
Bit 9 8 Field

I2C Passive Mode Device Configuration Field Descriptions
Description Reserved I2C operation mode 2 0 = Master Mode (See section 2.5.2.5.1 ‘‘I C Master Mode’’) 1 = Passive Mode
2

Reserved Mode

7-5

Receive I C Address

I C bus address configuration 0 - 7 = The I2C Bus address the device will listen to for data The actual value on the bus is 0x19 plus the value in bits [8:5]. For Ex. if bits[8:5] = 0 then the device will listen to I C bus address 0x19.
2

2

4-3

Reserved

Reserved

End of Table 2-10

2.5.2.6 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.
Figure 2-9
12 Mode

SPI Device Configuration Bit Fields
11 10 4, 5 Pin 9 Addr Width 8 Chip Select 7 6 5 4 3

Parameter Table Index

Table 2-11
Bit 12-11 Field Mode

SPI Device Configuration Field Descriptions
Description Clk Pol / Phase 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge. 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK. 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge. 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK. SPI operation mode configuration 0 = 4-pin mode used 1 = 5-pin mode used SPI address width configuration 0 = 16-bit address values are used 1 = 24-bit address values are used The chip select field value Specifies which parameter table is loaded

10

4, 5 Pin

9

Addr Width

8-7 6-3

Chip Select Parameter Table Index

End of Table 2-11

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SPRS691B—August 2011

2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
9 Reserved

HyperLink Boot Device Configuration Fields
8 Data Rate 7 6 Ref Clock 5 4 Reserved 3

Table 2-12
Bit 9 8-7 Field

HyperLink Boot Device Configuration Field Descriptions
Description Reserved HyperLink data rate configuration 0 = 1.25 GBaud/s 1 = 3.125 GBaud/s 2 = 6.25 GBaud/s 3 = Reserved HyperLink reference clock configuration 0 = 156.25 MHz 1 = 250 MHz 2 = 312.5 MHz 3 = Reserved Reserved

Reserved Data Rate

6-5

Ref Clocks

4-3

Reserved

End of Table 2-12

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2.5.3 PLL Boot Configuration Settings The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 2-13 shows settings for various input clock frequencies. OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=2, by default). CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1)) The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See Table 2-3 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip divider (=3), feeds 350 MHz to the NETCP. The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are controlled by chip level MMRs. For details on how to set up the PLL see section 7.5 ‘‘Main PLL and PLL Controller’’ on page 122. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
Table 2-13
BOOTMODE [12:10] 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111

C66x DSP System PLL Configuration
Input Clock Freq (MHz) 50.00 66.67 80.00 100.00 156.25 250.00 312.50 122.88 1000 MHz Device PLLD 0 0 0 0 4 0 4 28 PLLM 39 29 24 19 63 7 31 471 1000 1000.05 1000 1000 1000 1000 1000 999.989 DSP ? PLLD 0 1 3 0 24 4 24 31 1250 MHz Device PLLM 49 74 124 24 399 49 199 650 1250 1250.06 1250 1250 1250 1250 1200 1249.92 DSP ? PLLD 0 1 3 0 24 4 24 11 PASS PLL = 350 MHz PLLM 41 62 104 20 335 41 167 204
(1)

DSP ? (2) 1050 1050.053 1050 1050 1050 1050 1050 1049.6

End of Table 2-13
1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator. 2 ? represents frequency in MHz.

2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

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SPRS691B—August 2011

2.7 Terminals
2.7.1 Package Terminals Figure 2-11 shows the TMS320C6678CYP ball grid area (BGA) package (bottom view).
Figure 2-11 CYP 841-Pin BGA Package (Bottom View)
AJ AG AE AC AA
W U R P N M L K H F D B G E C A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 J

AH AF AD AB Y
V T

2.7.2 Pin Map Figure 2-13 through Figure 2-16 show the TMS320C6678 pin assignments in four quadrants (A, B, C, and D).
Figure 2-12 Pin Map Quadrants (Bottom View)

A D

B C

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Figure 2-13
1

Upper Left Quadrant—A (Bottom View)
2 3 4 5 6 7 8 9 10 11 12 13 14 15

AJ

VSS

DVDD18

RSV05

PASSCLKN

PASSCLKP

SRIOSGMII CLKN

VSS

PCIERXP1

PCIERXN1

VSS

RIORXN0

RIORXP0

VSS

RIORXP3

RIORXN3

AH

DVDD18

RSV04

RSV25

RSV24

PCIECLKN

VSS

PCIERXN0

PCIERXP0

VSS

RIORXN1

RIORXP1

VSS

RIORXP2

RIORXN2

VSS

AG

SPISCS0

SPISCS1

CORECLKP CORECLKN

PCIECLKP

SRIOSGMII CLKP

VSS

PCIETXP1

PCIETXN1

VSS

RIOTXN1

RIOTXP1

VSS

RIOTXP2

RIOTXN2

AF

RSV22

CORESEL0

RSV20

VSS

DVDD18

VSS

PCIETXP0

PCIETXN0

VSS

RIOTXN0

RIOTXP0

VSS

RIOTXP3

RIOTXN3

VSS

AE

SPICLK

BOOT COMPLETE SYSCLKOUT PACLKSEL

CORESEL3

CORESEL2

VSS

VSS

VSS

VDDR2

VSS

RSV15

VSS

VDDR4

VSS

AD

UARTRXD

SPIDIN

SCL

CORESEL1

AVDDA3

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

AC

UARTTXD

VSS

DVDD18

SDA

VSS

AVDDA2

VSS

VDDT2

RSV16

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

AB

SPIDOUT

UARTRTS

UARTCTS

VSS

DVDD18

VSS

DVDD18

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

AA

MCMTX FLCLK

MCMTX PMCLK

MCMTX FLDAT

MCMTX PMDAT

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

Y

MCMREF CLKOUTP

MCMCLKN

MCMRX PMCLK

MCMRX PMDAT

RSV12

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

W

MCMREF CLKOUTN

MCMCLKP

MCMRX FLCLK

MCMRX FLDAT

RSV13

RSV14

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

V

VSS

VSS

VSS

VSS

VDDR1

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

U

VSS

MCMRXN0

VSS

MCMTXP1

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

T

MCMRXN1

MCMRXP0

VSS

MCMTXN1

MCMTXP2

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

A

34

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011

Figure 2-14
16 17

Upper Right Quadrant—B (Bottom View)
18 19 20 21 22 23 24 25 26 27 28 29

VSS

SGMII0RXP

SGMII0RXN

VSS

TR15

TR13

FSB1

CLKA1

TX02

TR01

FSA0

EMU16

DVDD18

VSS

AJ

SGMII1RXP

SGMII1RXN

VSS

RSV08

TX16

TR16

TR14

CLKB1

TX04

TR05

TR00

EMU18

RSV01

DVDD18

AH

VSS

SGMII0TXP

SGMII0TXN

VSS

TX14

TR17

DVDD18

FSA1

TX03

CLKB0

FSB0

EMU15

EMU14

EMU12

AG

SGMII1TXP

SGMII1TXN

VSS

RSV09

TX17

TX10

VSS

TX07

TX05

CLKA0

DVDD18

EMU17

EMU11

EMU09

AF

VDDR3

VSS

VDDT2

VSS

TX15

TX13

TR10

TX06

TX00

TR07

VSS

EMU10

EMU08

EMU07

AE

VSS

VDDT2

VSS

RSV17

HOUT

TR11

TX11

TR02

TR03

TX01

EMU13

EMU06

EMU05

EMU04

AD

VDDT2

VSS

VDDT2

VSS

POR

TR12

TX12

TR04

TR06

EMIFD15

EMU03

EMU02

EMU01

EMU00

AC

VSS

VDDT2

VSS

DVDD18

VSS

DVDD18

VSS

EMIFD12

EMIFD13

EMIFD09

EMIFD14

EMIFD05

DVDD18

EMIFD01

AB

CVDD

VSS

CVDD

VSS

RSV0B

RSV0A

CVDD

VSS

EMIFD10

EMIFD07

EMIFD06

EMIFD04

VSS

EMIFD02

AA

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

EMIFD11

EMIFD08

EMIFD03

EMIFD00

EMIFA22

EMIFA21

Y

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFA20

EMIFA19

EMIFA18

EMIFA17

EMIFA15

EMIFA14

EMIFA16

W

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

EMIFA13

EMIFA12

EMIFA11

EMIFA10

EMIFA08

EMIFA09

V

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFA23

EMIFA07

EMIFA06

DVDD18

EMIFA04

EMIFA05

EMIFA02

U

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

EMIFA01

EMIFA03

VSS

EMIFA00

EMIFWAIT1 EMIFWAIT0

T

B

Copyright 2011 Texas Instruments Incorporated

35

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011
www.ti.com

Figure 2-15

Lower Right Quadrant—C (Bottom View)

C

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFBE1

EMIFBE0

EMIFCE3

EMIFOE

EMIFCE1

EMIFCE2

TDO

R

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

EMIFWE

EMIFCE0

EMIFRW

TDI

TRST

TMS

P

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

RSV03

RSV02

RESETFULL

LRESET

RESETSTAT

DVDD18

TCK

N

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

RSV26

RSV27

NMI

TIMO1

LRESET NMIEN

VSS

RESET

M

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VCNTL0

TIMI0

TIMO0

TIMI1

GPIO15

GPIO11

GPIO12

L

VSS

CVDD

VSS

CVDD

VSS

CVDD

RSV10

VCNTL1

GPIO14

GPIO13

GPIO09

GPIO07

GPIO08

GPIO10

K

CVDD

VSS

CVDD

VSS

CVDD

VSS

RSV11

VCNTL2

GPIO06

GPIO04

GPIO03

GPIO05

GPIO01

GPIO02

J

VSS

CVDD

VSS

CVDD

VSS

CVDD

AVDDA1

VCNTL3

DVDD18

GPIO00

MDCLK

DDRSL RATE1

RSV06

DDRCLKN

H

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

PTV15

DVDD15

VSS

RSV21

MDIO

DDRSL RATE0

RSV07

DDRCLKP

G

VSS

DVDD15

VSS

DVDD15

DDRD25

DDRD27

DDRD17

DDRD16

DDRD08

DDRD07

DVDD15

VSS

DVDD15

VSS

F

DDRA10

DDRA12

DDRCKE1

DDRCB00

VSS

DDRD26

DDRD23

DDRD19

DDRD09

DDRD10

DDRD06

DDRD02

DDRD00

DDRDQM0

E

DDRA11

DDRA14

VSS

DDRCB02

DVDD15

DDRD24

DDRD28

DVDD15

DDRD18

DDRD11

DDRD12

DDRD04

DDRD03

DDRD01

D

DDRA13

DDRA15

DDRCB05

DDRCB04

DDRCB01

DDRD29

DDRD31

VSS

DDRD22

DVDD15

DDRD13

DDRDQM1

DDRDQS0P DDRDQS0N

C

DDRCLK OUTN1

VSS

DDRCB06

DDRDQS8N

DDRCB03

DDRDQS3N

DDRD30

DDRD21

DDRDQS2N

VSS

DDRD14

DDRDQS1N

DDRD05

DVDD15

B

DDRCLK OUTP1

DVDD15

DDRCB07

DDRDQS8P

DDRDQM8

DDRDQS3P

DDRDQM3

DDRD20

DDRDQS2P

DDRDQM2

DDRD15

DDRDQS1P

DVDD15

VSS

A

16

17

18

19

20

21

22

23

24

25

26

27

28

29

36

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011

Figure 2-16

Lower Left Quadrant—D (Bottom View)

D

R

MCMRXP1

VSS

VSS

VSS

MCMTXN2

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

P

VSS

MCMRXN3

VSS

MCMTXP3

VSS

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

N

MCMRXP2

MCMRXP3

VSS

MCMTXN3

MCMTXP0

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

M

MCMRXN2

VSS

VSS

VSS

MCMTXN0

VSS

VDDT1

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

L

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

K

VSS

VSS

VSS

VSS

VSS

VSS

CVDD1

VSS

CVDD1

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

J

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

H

VSS

VSS

VSS

VSS

VSS

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

G

VSS

DVDD15

VSS

DVDD15

VSS

VSS

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

F

DDRD63

DDRD60

DDRD61

DDRD56

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DDRA03

DDRA02

DDRA08

E

DDRD62

DDRD58

DVDD15

DDRD53

VSS

DDRD45

DDRD42

DDRD39

DDRD36

DDRD32

DDRRESET

DDRWE

DDRODT1

VREFSSTL

DDRA09

D

DDRDQS7P

DDRD57

VSS

DDRD52

DVDD15

DDRD46

DDRD41

DVDD15

DDRD35

DDRD33

DDRCKE0

DDRCAS

DDRODT0

VSS

DDRA07

C

DDRDQS7N

DDRD59

DDRD55

DDRD54

DDRD48

DDRD47

DDRD43

VSS

DDRD37

DDRRAS

DDRCE0

DDRCE1

DDRBA2

DVDD15

DDRA05

B

DVDD15

DDRDQM7 DDRDQS6P

DDRD50

DDRDQM6 DDRDQS5P

DDRD44

DDRD38

DDRDQS4N

DDRD34

VSS

DDRCLK OUTN0

DDRBA1

DDRA01

DDRA06

A

VSS

DVDD15

DDRDQS6N

DDRD51

DDRD49

DDRDQS5N

DDRD40

DDRDQM5 DDRDQS4P DDRDQM4

DVDD15

DDRCLK OUTP0

DDRBA0

DDRA00

DDRA04

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Copyright 2011 Texas Instruments Incorporated

37

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011
www.ti.com

2.8 Terminal Functions
The terminal functions table (Table 2-15) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table (Table 2-16) lists the various power supply pins and ground pins and gives functional pin descriptions. Table 2-17 shows all pins arranged by signal name. Table 2-18 shows all pins arranged by ball number. There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (?). For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 86. Use the symbol definitions in Table 2-14 when reading Table 2-15.
Table 2-14
Functional Symbol

I/O Functional Symbol Definitions
Definition Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 64. Analog signal Ground Input terminal Output terminal Supply voltage Three-state terminal or high impedance Table 2-15 Column Heading

IPD or IPU

IPD/IPU

A GND I O S Z

Type Type Type Type Type Type

End of Table 2-14

Table 2-15
Signal Name

Terminal Functions — Signals and Control by Function (Part 1 of 12)
Ball No. Type IPD/IPU Description Boot Configuration Pins

LENDIAN ? BOOTMODE00 ? BOOTMODE01? BOOTMODE02 ? BOOTMODE03 ? BOOTMODE04 ? BOOTMODE05 ? BOOTMODE06 ? BOOTMODE07 ? BOOTMODE08 ? BOOTMODE09 ? BOOTMODE10 ? BOOTMODE11 ? BOOTMODE12 ?

H25 J28 J29 J26 J25 J27 J24 K27 K28 K26 K29 L28 L29 K25

IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ

UP Down Down Down Down Down Down Down Down Down Down Down Down Down

Endian configuration pin (Pin shared with GPIO[0])

See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 25 for more details (Pins shared with GPIO[1:13])

38

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 2 of 12)
Ball No. Type K24 L27 L24 IOZ IOZ I IPD/IPU Down Down Down Description PCIe Mode selection pins (Pins shared with GPIO[14:15]) PCIe module enable (Pin shared with TIMI0) Clock / Reset

Table 2-15
Signal Name PCIESSMODE0 ? PCIESSMODE1 ? PCIESSEN ?

CORECLKP CORECLKN SRIOSGMIICLKP SRIOSGMIICLKN DDRCLKP DDRCLKN PCIECLKP PCIECLKN MCMCLKP MCMCLKN PASSCLKP PASSCLKN AVDDA1 AVDDA2 AVDDA3 SYSCLKOUT PACLKSEL HOUT NMI LRESET LRESETNMIEN CORESEL0 CORESEL1 CORESEL2 CORESEL3 RESETFULL RESET POR RESETSTAT BOOTCOMPLETE PTV15

AG3 AG4 AG6 AJ6 G29 H29 AG5 AH5 W2 Y2 AJ5 AJ4 H22 AC6 AD5 AE3 AE4 AD20 M25 N26 M27 AF2 AD4 AE6 AE5 N25 M29 AC20 N27 AE2 G22

I I I I I I I I I I I I P P P OZ I OZ I I I I I I I I I I O OZ A UP Down Down Down UP UP UP UP Down Down Down Down UP UP

Core Clock Input to main PLL.

RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes

DDR Reference Clock Input to DDR PLL (

PCIe Clock Input to drive PCIe SerDes

HyperLink Reference Clock to drive the HyperLink SerDes

Network Coprocessor (PASS PLL) Reference Clock SYS_CLK PLL Power Supply Pin DDR_CLK PLL Power Supply Pin PASS_CLK PLL Power Supply Pin System Clock Output to be used as a general purpose output clock for debug purposes PA clock select to choose between core clock and PASSCLK pins Interrupt output pulse created by IPCGRH Non-maskable Interrupt Warm Reset Enable for core selects

Select for the target core for LRESET and NMI. For more details see Table 7-48‘‘NMI and Local Reset Timing Requirements’’ on page 170

Full Reset Warm Reset of non isolated portion on the IC Power-on Reset Reset Status Output Boot progress indication output PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50ohms. Presently the recommended value for this 1% resistor is 45.3 ohms.

Copyright 2011 Texas Instruments Incorporated

39

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-15
Signal Name
www.ti.com

Terminal Functions — Signals and Control by Function (Part 3 of 12)
Ball No. Type IPD/IPU Description DDR

DDRDQM0 DDRDQM1 DDRDQM2 DDRDQM3 DDRDQM4 DDRDQM5 DDRDQM6 DDRDQM7 DDRDQM8 DDRDQS0P DDRDQS0N DDRDQS1P DDRDQS1N DDRDQS2P DDRDQS2N DDRDQS3P DDRDQS3N DDRDQS4P DDRDQS4N DDRDQS5P DDRDQS5N DDRDQS6P DDRDQS6N DDRDQS7P DDRDQS7N DDRDQS8P DDRDQS8N DDRCB00 DDRCB01 DDRCB02 DDRCB03 DDRCB04 DDRCB05 DDRCB06 DDRCB07

E29 C27 A25 A22 A10 A8 B5 B2 A20 C28 C29 A27 B27 A24 B24 A21 B21 A9 B9 B6 A6 B3 A3 D1 C1 A19 B19 E19 C20 D19 B20 C19 C18 B18 A18

OZ OZ OZ OZ OZ OZ OZ OZ OZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR EMIF Check Bits DDR EMIF Data Strobe DDR EMIF Data Masks

40

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 4 of 12)
Ball No. Type E28 D29 E27 D28 D27 B28 E26 F25 F24 E24 E25 D25 D26 C26 B26 A26 F23 F22 D24 E23 A23 B23 C24 E22 D21 F20 E21 F21 D22 C21 B22 C22 E10 D10 B10 D9 E9 C9 B8 E8 A7 D7 IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR EMIF Data Bus DDR EMIF Data Bus IPD/IPU Description

Table 2-15
Signal Name DDRD00 DDRD01 DDRD02 DDRD03 DDRD04 DDRD05 DDRD06 DDRD07 DDRD08 DDRD09 DDRD10 DDRD11 DDRD12 DDRD13 DDRD14 DDRD15 DDRD16 DDRD17 DDRD18 DDRD19 DDRD20 DDRD21 DDRD22 DDRD23 DDRD24 DDRD25 DDRD26 DDRD27 DDRD28 DDRD29 DDRD30 DDRD31 DDRD32 DDRD33 DDRD34 DDRD35 DDRD36 DDRD37 DDRD38 DDRD39 DDRD40 DDRD41

Copyright 2011 Texas Instruments Incorporated

41

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-15
Signal Name DDRD42 DDRD43 DDRD44 DDRD45 DDRD46 DDRD47 DDRD48 DDRD49 DDRD50 DDRD51 DDRD52 DDRD53 DDRD54 DDRD55 DDRD56 DDRD57 DDRD58 DDRD59 DDRD60 DDRD61 DDRD62 DDRD63 DDRCE0 DDRCE1 DDRBA0 DDRBA1 DDRBA2 DDRA00 DDRA01 DDRA02 DDRA03 DDRA04 DDRA05 DDRA06 DDRA07 DDRA08 DDRA09 DDRA10 DDRA11 DDRA12 DDRA13 DDRA14 DDRA15 DDRCAS
www.ti.com

Terminal Functions — Signals and Control by Function (Part 5 of 12)
Ball No. Type E7 C7 B7 E6 D6 C6 C5 A5 B4 A4 D4 E4 C4 C3 F4 D2 E2 C2 F2 F3 E1 F1 C11 C12 A13 B13 C13 A14 B14 F14 F13 A15 C15 B15 D15 F15 E15 E16 D16 E17 C16 D17 C17 D12 IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ DDR EMIF Column Address Strobe DDR EMIF Address Bus DDR EMIF Bank Address DDR EMIF Chip Enables DDR EMIF Data Bus IPD/IPU Description

42

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com

SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 6 of 12)
Ball No. Type C10 E12 D11 E18 A12 B12 A16 B16 D13 E13 E11 G27 H27 E14 OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ I I P Down Down DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs DDR Reset signal DDR Slew rate control Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2) EMIF16 DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM) IPD/IPU Description DDR EMIF Row Address Strobe DDR EMIF Write Enable DDR EMIF Clock Enable DDR EMIF Clock Enable

Table 2-15
Signal Name DDRRAS DDRWE DDRCKE0 DDRCKE1 DDRCLKOUTP0 DDRCLKOUTN0 DDRCLKOUTP1 DDRCLKOUTN1 DDRODT0 DDRODT1 DDRRESET DDRSLRATE0 DDRSLRATE1 VREFSSTL

EMIFRW EMIFCE0 EMIFCE1 EMIFCE2 EMIFCE3 EMIFOE EMIFWE EMIFBE0 EMIFBE1 EMIFWAIT0 EMIFWAIT1

P26 P25 R27 R28 R25 R26 P24 R24 R23 T29 T28

O O O O O O O O O I I

UP UP UP UP UP UP UP UP UP Down Down EMIF16 Control Signals

Copyright 2011 Texas Instruments Incorporated

43

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-15
Signal Name EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15 EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15
www.ti.com

Terminal Functions — Signals and Control by Function (Part 7 of 12)
Ball No. Type T27 T24 U29 T25 U27 U28 U25 U24 V28 V29 V27 V26 V25 V24 W28 W27 W29 W26 W25 W24 W23 Y29 Y28 U23 Y27 AB29 AA29 Y26 AA27 AB27 AA26 AA25 Y25 AB25 AA24 Y24 AB23 AB24 AB26 AC25 O O O O O O O O O O O O O O O O O O O O O O O O IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IPD/IPU Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down EMIF16 Data EMIF16 Address Description

44

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 8 of 12)
Ball No. Type IPD/IPU Description EMU

Table 2-15
Signal Name

EMU00 EMU01 EMU02 EMU03 EMU04 EMU05 EMU06 EMU07 EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18

AC29 AC28 AC27 AC26 AD29 AD28 AD27 AE29 AE28 AF29 AE27 AF28 AG29 AD26 AG28 AG27 AJ27 AF27 AH27

IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ

UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP General Purpose Input/Output (GPIO) Emulation and Trace Port

GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15

H25 J28 J29 J26 J25 J27 J24 K27 K28 K26 K29 L28 L29 K25 K24 L27

IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ

UP Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down General Purpose Input/Output These GPIO pins have secondary functions assigned to them as mentioned in the ‘‘Boot Configuration Pins’’ on page 38.

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45

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-15
Signal Name
www.ti.com

Terminal Functions — Signals and Control by Function (Part 9 of 12)
Ball No. Type IPD/IPU Description HyperLink

MCMRXN0 MCMRXP0 MCMRXN1 MCMRXP1 MCMRXN2 MCMRXP2 MCMRXN3 MCMRXP3 MCMTXN0 MCMTXP0 MCMTXN1 MCMTXP1 MCMTXN2 MCMTXP2 MCMTXN3 MCMTXP3 MCMRXFLCLK MCMRXFLDAT MCMTXFLCLK MCMTXFLDAT MCMRXPMCLK MCMRXPMDAT MCMTXPMCLK MCMTXPMDAT MCMREFCLKOUTP MCMREFCLKOUTN

U2 T2 T1 R1 M1 N1 P2 N2 M5 N5 T4 U4 R5 T5 N4 P4 W3 W4 AA1 AA3 Y3 Y4 AA2 AA4 Y1 W1

I I I I I I I I O O O O O O O O O O I I I I O O O O Down Down Down Down Down Down Down Down HyperLink Reference clock output for daisy chain connection I C
2

Serial HyperLink Receive Data

Serial HyperLink Transmit Data

Serial HyperLink Sideband Signals

SCL SDA

AD3 AC4

IOZ IOZ

I C Clock I2C Data JTAG

2

TCK TDI TDO TMS TRST

N29 P27 R29 P29 P28

I I OZ I I

UP UP UP UP Down

JTAG Clock Input JTAG Data Input JTAG Data Output JTAG Test Mode Input JTAG Reset MDIO

MDIO MDCLK

G26 H26

IOZ O

UP Down

MDIO Data MDIO Clock

46

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 10 of 12)
Ball No. Type IPD/IPU Description PCIe

Table 2-15
Signal Name

PCIERXN0 PCIERXP0 PCIERXN1 PCIERXP1 PCIETXN0 PCIETXP0 PCIETXN1 PCIETXP1

AH7 AH8 AJ9 AJ8 AF8 AF7 AG9 AG8

I I I I O O O O Serial RapidIO PCIexpress Transmit Data (2 links) PCIexpress Receive Data (2 links)

RIORXN0 RIORXP0 RIORXN1 RIORXP1 RIORXN2 RIORXP2 RIORXN3 RIORXP3 RIOTXN0 RIOTXP0 RIOTXN1 RIOTXP1 RIOTXN2 RIOTXP2 RIOTXN3 RIOTXP3

AJ11 AJ12 AH10 AH11 AH14 AH13 AJ15 AJ14 AF10 AF11 AG11 AG12 AG15 AG14 AF14 AF13

I I I I I I I I O O O O O O O O SGMII Serial RapidIO Transmit Data (2 links) Serial RapidIO Transmit Data (2 links) Serial RapidIO Receive Data (2 links) Serial RapidIO Receive Data (2 links)

SGMII0RXN SGMII0RXP SGMII0TXN SGMII0TXP SGMII1RXN SGMII1RXP SGMII1TXN SGMII1TXP

AJ18 AJ17 AG18 AG17 AH17 AH16 AF17 AF16

I I O O I I O O

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data SmartReflex

VCNTL0 VCNTL1 VCNTL2 VCNTL3

L23 K23 J23 H23

OZ OZ OZ OZ Voltage Control Outputs to variable core power supply

Copyright 2011 Texas Instruments Incorporated

47

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-15
Signal Name
www.ti.com

Terminal Functions — Signals and Control by Function (Part 11 of 12)
Ball No. Type IPD/IPU Description SPI

SPISCS0 SPISCS1 SPICLK SPIDIN SPIDOUT

AG1 AG2 AE1 AD2 AB1

OZ OZ OZ I OZ

UP UP Down Down Down

SPI Interface Enable 0 SPI Interface Enable 1 SPI Clock SPI Data In SPI Data Out Timer

TIMI0 TIMI1 TIMO0 TIMO1

L24 L26 L25 M26

I I OZ OZ

Down Down Down Down

Timer Inputs

Timer Outputs TSIP

CLKA0 CLKB0 FSA0 FSB0 TR00 TR01 TR02 TR03 TR04 TR05 TR06 TR07 TX00 TX01 TX02 TX03 TX04 TX05 TX06 TX07 CLKA1 CLKB1 FSA1 FSB1 TR10 TR11 TR12 TR13 TR14 TR15 TR16 TR17

AF25 AG25 AJ26 AG26 AH26 AJ25 AD23 AD24 AC23 AH25 AC24 AE25 AE24 AD25 AJ24 AG24 AH24 AF24 AE23 AF23 AJ23 AH23 AG23 AJ22 AE22 AD21 AC21 AJ21 AH22 AJ20 AH21 AG21

I I I I I I I I I I I I OZ OZ OZ OZ OZ OZ OZ OZ I I I I I I I I I I I I

Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down

TSIP0 external clock A TSIP0 external clock B TSIP0 frame sync A TSIP0 frame sync B

TSIP0 receive data

TSIP0 transmit data

TSIP1 external clock A TSIP1 external clock B TSIP1 frame sync A TSIP1 frame sync B

TSIP1 receive data

48

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — Signals and Control by Function (Part 12 of 12)
Ball No. Type AF21 AD22 AC22 AE21 AG20 AE20 AH20 AF20 OZ OZ OZ OZ OZ OZ OZ OZ IPD/IPU Down Down Down Down Down Down Down Down UART TSIP1 transmit data Description

Table 2-15
Signal Name TX10 TX11 TX12 TX13 TX14 TX15 TX16 TX17

UARTRXD UARTTXD UARTCTS UARTRTS

AD1 AC1 AB3 AB2

I OZ I OZ

Down Down Down Down

UART Serial Data In UART Serial Data Out UART Clear To Send UART Request To Send Reserved

RSV01 RSV02 RSV03 RSV04 RSV05 RSV06 RSV07 RSV08 RSV09 RSV10 RSV11 RSV12 RSV13 RSV14 RSV15 RSV16 RSV17 RSV20 RSV21 RSV22 RSV24 RSV25 RSV26 RSV27 RSV0A RSV0B End of Table 2-15

AH28 N24 N23 AH2 AJ3 H28 G28 AH19 AF19 K22 J22 Y5 W5 W6 AE12 AC9 AD19 AF3 G25 AF1 AH4 AH3 M23 M24 AA21 AA20

IOZ OZ OZ O O O O A A A A A A A A A A OZ OZ OZ O O IOZ IOZ A A

Down Down Down

Reserved - Pullup to DVDD18 Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - Connect to GND Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected

Down Down Down

Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected Reserved - leave unconnected

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49

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-16
Supply AVDDA1 AVDDA2 AVDDA3 CVDD
www.ti.com

Terminal Functions — Power and Ground
Ball No. H22 AC6 AD5 Volts Description 1.8 1.8 1.8 PLL Supply - CORE_PLL PLL Supply - DDR3_PLL PLL Supply - PASS_PLL SmartReflex core supply voltage

H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16, 0.9 to L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, 1.1 V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12, AA14, AA16, AA18, AA22 J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16, V13, V15, W12, W14, W16 1.0

CVDD1 DVDD15 DVDD18 VDDR1 VDDR2 VDDR3 VDDR4 VDDT1 VDDT2 VREFSSTL VSS

Fixed core supply voltage DDR IO supply IO supply HyperLink SerDes regulator supply PCIe SerDes regulator supply SGMII SerDes regulator supply SRIO SerDes regulator supply HyperLink SerDes termination supply SGMII/SRIO/PCIe SerDes termination supply DDR3 reference voltage Ground

A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28, 1.5 G2, G4, G8, G10, G12, G14, G16, G18, G20, G23 H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26, AG22, AH1, AH29, AJ2, AJ28 V5 AE10 AE16 AE14 M7, N6, P7, R6, T7, U6, V7 AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13, AD15, AD17, AE18 E14 1.8 1.5 1.5 1.5 1.5 1.0 1.0 0.75

A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1, GND G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24, H1, H2, H3, H4, H5, H6, H8, H10, H12, H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6, K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2, M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17, N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13, R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11, U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9, W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15, AF18, AF22, AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10, AJ13, AJ16, AJ19, AJ29

End of Table 2-16

50

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — By Signal Name (Part 1 of 12)
Ball Number H22 AC6 AD5 AE2 J28 J29 J26 J25 J27 J24 K27 K28 K26 K29 L28 L29 K25 AF25 AJ23 AG25 AH23 AG4 AG3 AF2 AD4 AE6 AE5 H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16, L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12, AA14, AA16, AA18, AA22 DDRA00 DDRA01 DDRA02 DDRA03 DDRA04 DDRA05 DDRA06 DDRA07 DDRA08 DDRA09 DDRA10 DDRA11 DDRA12 DDRA13 DDRA14 DDRA15 DDRBA0 DDRBA1 DDRBA2 DDRCAS DDRCB00 DDRCB01 DDRCB02 DDRCB03 DDRCB04 DDRCB05 DDRCB06 DDRCB07 DDRCE0 DDRCE1 DDRCKE0 DDRCKE1 DDRCLKN DDRCLKOUTN0 DDRCLKOUTN1 DDRCLKOUTP0 DDRCLKOUTP1

Table 2-17

Table 2-17

Terminal Functions — By Signal Name (Part 2 of 12)
Ball Number J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16, V13, V15, W12, W14, W16 A14 B14 F14 F13 A15 C15 B15 D15 F15 E15 E16 D16 E17 C16 D17 C17 A13 B13 C13 D12 E19 C20 D19 B20 C19 C18 B18 A18 C11 C12 D11 E18 H29 B12 B16 A12 A16

Table 2-17

Terminal Functions — By Signal Name (Part 3 of 12)
Ball Number G29 E28 D29 E27 D28 D27 B28 E26 F25 F24 E24 E25 D25 D26 C26 B26 A26 F23 F22 D24 E23 A23 B23 C24 E22 D21 F20 E21 F21 D22 C21 B22 C22 E10 D10 B10 D9 E9 C9 B8 E8 A7

Signal Name AVDDA1 AVDDA2 AVDDA3 BOOTCOMPLETE BOOTMODE00 ? BOOTMODE01? BOOTMODE02 ? BOOTMODE03 ? BOOTMODE04 ? BOOTMODE05 ? BOOTMODE06 ? BOOTMODE07 ? BOOTMODE08 ? BOOTMODE09 ? BOOTMODE10 ? BOOTMODE11 ? BOOTMODE12 ? CLKA0 CLKA1 CLKB0 CLKB1 CORECLKN CORECLKP CORESEL0 CORESEL1 CORESEL2 CORESEL3 CVDD

Signal Name CVDD1

Signal Name DDRCLKP DDRD00 DDRD01 DDRD02 DDRD03 DDRD04 DDRD05 DDRD06 DDRD07 DDRD08 DDRD09 DDRD10 DDRD11 DDRD12 DDRD13 DDRD14 DDRD15 DDRD16 DDRD17 DDRD18 DDRD19 DDRD20 DDRD21 DDRD22 DDRD23 DDRD24 DDRD25 DDRD26 DDRD27 DDRD28 DDRD29 DDRD30 DDRD31 DDRD32 DDRD33 DDRD34 DDRD35 DDRD36 DDRD37 DDRD38 DDRD39 DDRD40

CVDD

CVDD

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-17 Terminal Functions — By Signal Name (Part 4 of 12)
Ball Number D7 E7 C7 B7 E6 D6 C6 C5 A5 B4 A4 D4 E4 C4 C3 F4 D2 E2 C2 F2 F3 E1 F1 E29 C27 A25 A22 A10 A8 B5 B2 A20 C29 C28 B27 A27 B24 A24 B21 A21 B9 A9 EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15 EMIFA16 DVDD18
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Table 2-17

Terminal Functions — By Signal Name (Part 5 of 12)
Ball Number A6 B6 A3 B3 C1 D1 B19 A19 D13 E13 C10 E11 G27 H27 E12 A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28, G2, G4, G8, G10, G12, G14, G16, G18, G20, G23 H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26, AG22, AH1, AH29, AJ2, AJ28 T27 T24 U29 T25 U27 U28 U25 U24 V28 V29 V27 V26 V25 V24 W28 W27 W29

Table 2-17

Terminal Functions — By Signal Name (Part 6 of 12)
Ball Number W26 W25 W24 W23 Y29 Y28 U23 R24 R23 P25 R27 R28 R25 Y27 AB29 AA29 Y26 AA27 AB27 AA26 AA25 Y25 AB25 AA24 Y24 AB23 AB24 AB26 AC25 R26 P26 T29 T28 P24 AC29 AC28 AC27 AC26 AD29 AD28 AD27 AE29

Signal Name DDRD41 DDRD42 DDRD43 DDRD44 DDRD45 DDRD46 DDRD47 DDRD48 DDRD49 DDRD50 DDRD51 DDRD52 DDRD53 DDRD54 DDRD55 DDRD56 DDRD57 DDRD58 DDRD59 DDRD60 DDRD61 DDRD62 DDRD63 DDRDQM0 DDRDQM1 DDRDQM2 DDRDQM3 DDRDQM4 DDRDQM5 DDRDQM6 DDRDQM7 DDRDQM8 DDRDQS0N DDRDQS0P DDRDQS1N DDRDQS1P DDRDQS2N DDRDQS2P DDRDQS3N DDRDQS3P DDRDQS4N DDRDQS4P

Signal Name DDRDQS5N DDRDQS5P DDRDQS6N DDRDQS6P DDRDQS7N DDRDQS7P DDRDQS8N DDRDQS8P DDRODT0 DDRODT1 DDRRAS DDRRESET DDRSLRATE0 DDRSLRATE1 DDRWE DVDD15

Signal Name EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMIFBE0 EMIFBE1 EMIFCE0 EMIFCE1 EMIFCE2 EMIFCE3 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 EMIFOE EMIFRW EMIFWAIT0 EMIFWAIT1 EMIFWE EMU00 EMU01 EMU02 EMU03 EMU04 EMU05 EMU06 EMU07

52

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — By Signal Name (Part 7 of 12)
Ball Number AE28 AF29 AE27 AF28 AG29 AD26 AG28 AG27 AJ27 AF27 AH27 AJ26 AG23 AG26 AJ22 H25 J28 J29 J26 J25 J27 J24 K27 K28 K26 K29 L28 L29 K25 K24 L27 AD20 H25 M27 N26 Y2 W2 W1 Y1 W3 W4 U2

Table 2-17

Table 2-17

Terminal Functions — By Signal Name (Part 8 of 12)
Ball Number T1 M1 P2 T2 R1 N1 N2 Y3 Y4 AA1 AA3 M5 T4 R5 N4 N5 U4 T5 P4 AA2 AA4 H26 G26 M25 AE4 AJ4 AJ5 AH5 AG5 AH7 AJ9 AH8 AJ8 K24 L27 L24 AF8 AG9 AF7 AG8 AC20 G22

Table 2-17

Terminal Functions — By Signal Name (Part 9 of 12)
Ball Number N25 N27 M29 AJ11 AH10 AH14 AJ15 AJ12 AH11 AH13 AJ14 AF10 AG11 AG15 AF14 AF11 AG12 AG14 AF13 AH28 N24 N23 AH2 AJ3 H28 G28 AH19 AF19 AA21 AA20 K22 J22 Y5 W5 W6 AE12 AC9 AD19 AF3 G25 AF1 AH4

Signal Name EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18 FSA0 FSA1 FSB0 FSB1 GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 HOUT LENDIAN ? LRESETNMIEN LRESET MCMCLKN MCMCLKP MCMREFCLKOUTN MCMREFCLKOUTP MCMRXFLCLK MCMRXFLDAT MCMRXN0

Signal Name MCMRXN1 MCMRXN2 MCMRXN3 MCMRXP0 MCMRXP1 MCMRXP2 MCMRXP3 MCMRXPMCLK MCMRXPMDAT MCMTXFLCLK MCMTXFLDAT MCMTXN0 MCMTXN1 MCMTXN2 MCMTXN3 MCMTXP0 MCMTXP1 MCMTXP2 MCMTXP3 MCMTXPMCLK MCMTXPMDAT MDCLK MDIO NMI PACLKSEL PASSCLKN PASSCLKP PCIECLKN PCIECLKP PCIERXN0 PCIERXN1 PCIERXP0 PCIERXP1 PCIESSMODE0 ? PCIESSMODE1 ? PCIESSEN ? PCIETXN0 PCIETXN1 PCIETXP0 PCIETXP1 POR PTV15

Signal Name RESETFULL RESETSTAT RESET RIORXN0 RIORXN1 RIORXN2 RIORXN3 RIORXP0 RIORXP1 RIORXP2 RIORXP3 RIOTXN0 RIOTXN1 RIOTXN2 RIOTXN3 RIOTXP0 RIOTXP1 RIOTXP2 RIOTXP3 RSV01 RSV02 RSV03 RSV04 RSV05 RSV06 RSV07 RSV08 RSV09 RSV0A RSV0B RSV10 RSV11 RSV12 RSV13 RSV14 RSV15 RSV16 RSV17 RSV20 RSV21 RSV22 RSV24

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53

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-17 Terminal Functions — By Signal Name (Part 10 of 12)
Ball Number AH3 AD3 AC4 AJ18 AJ17 AG18 AG17 AH17 AH16 AF17 AF16 AE1 AD2 AB1 AG1 AG2 AJ6 AG6 AE3 N29 P27 R29 L24 L26 L25 M26 P29 AH26 AJ25 AD23 AD24 AC23 AH25 AC24 AE25 AE22 AD21 AC21 AJ21 AH22 AJ20 AH21 VREFSSTL VSS VDDT2
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Table 2-17

Terminal Functions — By Signal Name (Part 11 of 12)
Ball Number AG21 P28 AE24 AD25 AJ24 AG24 AH24 AF24 AE23 AF23 AF21 AD22 AC22 AE21 AG20 AE20 AH20 AF20 AB3 AB2 AD1 AC1 L23 K23 J23 H23 V5 AE10 AE16 AE14 M7, N6, P7, R6, T7, U6, V7 AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13, AD15, AD17, AE18 E14 A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1, G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24,

Table 2-17

Terminal Functions — By Signal Name (Part 12 of 12)
Ball Number H1, H2, H3, H4, H5, H6, H8, H10, H12, H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6, K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2, M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17, N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13, R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11, U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9, W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15, AF18, AF22AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10, AJ13, AJ16, AJ19, AJ29

Signal Name RSV25 SCL SDA SGMII0RXN SGMII0RXP SGMII0TXN SGMII0TXP SGMII1RXN SGMII1RXP SGMII1TXN SGMII1TXP SPICLK SPIDIN SPIDOUT SPISCS0 SPISCS1 SRIOSGMIICLKN SRIOSGMIICLKP SYSCLKOUT TCK TDI TDO TIMI0 TIMI1 TIMO0 TIMO1 TMS TR00 TR01 TR02 TR03 TR04 TR05 TR06 TR07 TR10 TR11 TR12 TR13 TR14 TR15 TR16

Signal Name TR17 TRST TX00 TX01 TX02 TX03 TX04 TX05 TX06 TX07 TX10 TX11 TX12 TX13 TX14 TX15 TX16 TX17 UARTCTS UARTRTS UARTRXD UARTTXD VCNTL0 VCNTL1 VCNTL2 VCNTL3 VDDR1 VDDR2 VDDR3 VDDR4 VDDT1

Signal Name VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

End of Table 2-17

54

Copyright 2011 Texas Instruments Incorporated

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — By Ball Number (Part 1 of 21)
Signal Name VSS DVDD15 DDRDQS6N DDRD51 DDRD49 DDRDQS5N DDRD40 DDRDQM5 DDRDQS4P DDRDQM4 DVDD15 DDRCLKOUTP0 DDRBA0 DDRA00 DDRA04 DDRCLKOUTP1 DVDD15 DDRCB07 DDRDQS8P DDRDQM8 DDRDQS3P DDRDQM3 DDRD20 DDRDQS2P DDRDQM2 DDRD15 DDRDQS1P DVDD15 VSS DVDD15 DDRDQM7 DDRDQS6P DDRD50 DDRDQM6 DDRDQS5P DDRD44 DDRD38 DDRDQS4N DDRD34 VSS DDRCLKOUTN0 DDRBA1

Table 2-18

Table 2-18

Terminal Functions — By Ball Number (Part 2 of 21)
Signal Name DDRA01 DDRA06 DDRCLKOUTN1 VSS DDRCB06 DDRDQS8N DDRCB03 DDRDQS3N DDRD30 DDRD21 DDRDQS2N VSS DDRD14 DDRDQS1N DDRD05 DVDD15 DDRDQS7N DDRD59 DDRD55 DDRD54 DDRD48 DDRD47 DDRD43 VSS DDRD37 DDRRAS DDRCE0 DDRCE1 DDRBA2 DVDD15 DDRA05 DDRA13 DDRA15 DDRCB05 DDRCB04 DDRCB01 DDRD29 DDRD31 VSS DDRD22 DVDD15 DDRD13

Table 2-18

Terminal Functions — By Ball Number (Part 3 of 21)
Signal Name DDRDQM1 DDRDQS0P DDRDQS0N DDRDQS7P DDRD57 VSS DDRD52 DVDD15 DDRD46 DDRD41 DVDD15 DDRD35 DDRD33 DDRCKE0 DDRCAS DDRODT0 VSS DDRA07 DDRA11 DDRA14 VSS DDRCB02 DVDD15 DDRD24 DDRD28 DVDD15 DDRD18 DDRD11 DDRD12 DDRD04 DDRD03 DDRD01 DDRD62 DDRD58 DVDD15 DDRD53 VSS DDRD45 DDRD42 DDRD39 DDRD36 DDRD32

Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

Ball Number B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26

Ball Number C27 C28 C29 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-18 Terminal Functions — By Ball Number (Part 4 of 21)
Signal Name DDRRESET DDRWE DDRODT1 VREFSSTL DDRA09 DDRA10 DDRA12 DDRCKE1 DDRCB00 VSS DDRD26 DDRD23 DDRD19 DDRD09 DDRD10 DDRD06 DDRD02 DDRD00 DDRDQM0 DDRD63 DDRD60 DDRD61 DDRD56 DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DDRA03 DDRA02 DDRA08 VSS DVDD15 VSS DVDD15 DDRD25 DDRD27 DDRD17 DDRD16
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Table 2-18

Terminal Functions — By Ball Number (Part 5 of 21)
Signal Name DDRD08 DDRD07 DVDD15 VSS DVDD15 VSS VSS DVDD15 VSS DVDD15 VSS VSS VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS PTV15 DVDD15 VSS RSV21 MDIO DDRSLRATE0 RSV07 DDRCLKP VSS VSS VSS VSS VSS VSS CVDD

Table 2-18

Terminal Functions — By Ball Number (Part 6 of 21)
Signal Name VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA1 VCNTL3 DVDD18 GPIO00 LENDIAN ? MDCLK DDRSLRATE1 RSV06 DDRCLKN VSS VSS VSS VSS VSS VSS VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS

Ball Number E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23

Ball Number F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 H1 H2 H3 H4 H5 H6 H7

Ball Number H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H25 H26 H27 H28 H29 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
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SPRS691B—August 2011 Terminal Functions — By Ball Number (Part 7 of 21)
Signal Name CVDD VSS RSV11 VCNTL2 GPIO06 BOOTMODE05 ? GPIO04 BOOTMODE03 ? GPIO03 BOOTMODE02 ? GPIO05 BOOTMODE04 ? GPIO01 BOOTMODE00 ? GPIO02 BOOTMODE01? VSS VSS VSS VSS VSS VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD RSV10 VCNTL1 GPIO14 PCIESSMODE0 ? GPIO13

Table 2-18

Table 2-18

Terminal Functions — By Ball Number (Part 8 of 21)
Signal Name BOOTMODE12 ? GPIO09 BOOTMODE08 ? GPIO07 BOOTMODE06 ? GPIO08 BOOTMODE07 ? GPIO10 BOOTMODE09 ? VSS VSS VSS VSS VSS VSS VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VCNTL0 TIMI0 PCIESSEN ? TIMO0 TIMI1 GPIO15 PCIESSMODE1 ? GPIO11 BOOTMODE10 ? GPIO12 BOOTMODE11 ?

Table 2-18

Terminal Functions — By Ball Number (Part 9 of 21)
Signal Name MCMRXN2 VSS VSS VSS MCMTXN0 VSS VDDT1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS NMI TIMO1 LRESETNMIEN VSS RESET MCMRXP2 MCMRXP3 VSS MCMTXN3 MCMTXP0 VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

Ball Number J20 J21 J22 J23 J24 J24 J25 J25 J26 J26 J27 J27 J28 J28 J29 J29 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K24 K25

Ball Number K25 K26 K26 K27 K27 K28 K28 K29 K29 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L24 L25 L26 L27 L27 L28 L28 L29 L29

Ball Number M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M25 M26 M27 M28 M29 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-18 Terminal Functions — By Ball Number (Part 10 of 21)
Signal Name CVDD VSS CVDD VSS CVDD1 VSS CVDD1 RSV03 RSV02 RESETFULL LRESET RESETSTAT DVDD18 TCK VSS MCMRXN3 VSS MCMTXP3 VSS VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFWE EMIFCE0 EMIFRW TDI TRST
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Table 2-18

Terminal Functions — By Ball Number (Part 11 of 21)
Signal Name TMS MCMRXP1 VSS VSS VSS MCMTXN2 VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFBE1 EMIFBE0 EMIFCE3 EMIFOE EMIFCE1 EMIFCE2 TDO MCMRXN1 MCMRXP0 VSS MCMTXN1 MCMTXP2 VSS VDDT1 VSS CVDD VSS CVDD VSS

Table 2-18

Terminal Functions — By Ball Number (Part 12 of 21)
Signal Name CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFA01 EMIFA03 VSS EMIFA00 EMIFWAIT1 EMIFWAIT0 VSS MCMRXN0 VSS MCMTXP1 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFA23 EMIFA07 EMIFA06

Ball Number N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28

Ball Number P29 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

Ball Number T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25

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SPRS691B—August 2011 Terminal Functions — By Ball Number (Part 13 of 21)
Signal Name DVDD18 EMIFA04 EMIFA05 EMIFA02 VSS VSS VSS VSS VDDR1 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFA13 EMIFA12 EMIFA11 EMIFA10 EMIFA08 EMIFA09 MCMREFCLKOUTN MCMCLKP MCMRXFLCLK MCMRXFLDAT RSV13 RSV14 VSS CVDD VSS

Table 2-18

Table 2-18

Terminal Functions — By Ball Number (Part 14 of 21)
Signal Name CVDD VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFA20 EMIFA19 EMIFA18 EMIFA17 EMIFA15 EMIFA14 EMIFA16 MCMREFCLKOUTP MCMCLKN MCMRXPMCLK MCMRXPMDAT RSV12 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

Table 2-18

Terminal Functions — By Ball Number (Part 15 of 21)
Signal Name DVDD18 EMIFD11 EMIFD08 EMIFD03 EMIFD00 EMIFA22 EMIFA21 MCMTXFLCLK MCMTXPMCLK MCMTXFLDAT MCMTXPMDAT VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS RSV0B RSV0A CVDD VSS EMIFD10 EMIFD07 EMIFD06 EMIFD04 VSS EMIFD02 SPIDOUT UARTRTS UARTCTS VSS DVDD18 VSS

Ball Number U26 U27 U28 U29 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 W1 W2 W3 W4 W5 W6 W7 W8 W9

Ball Number W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22

Ball Number Y23 Y24 Y25 Y26 Y27 Y28 Y29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AB1 AB2 AB3 AB4 AB5 AB6

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TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691B—August 2011 Table 2-18 Terminal Functions — By Ball Number (Part 16 of 21)
Signal Name DVDD18 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS DVDD18 VSS DVDD18 VSS EMIFD12 EMIFD13 EMIFD09 EMIFD14 EMIFD05 DVDD18 EMIFD01 UARTTXD VSS DVDD18 SDA VSS AVDDA2 VSS VDDT2 RSV16 VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS
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Table 2-18

Terminal Functions — By Ball Number (Part 17 of 21)
Signal Name POR TR12 TX12 TR04 TR06 EMIFD15 EMU03 EMU02 EMU01 EMU00 UARTRXD SPIDIN SCL CORESEL1 AVDDA3 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS RSV17 HOUT TR11 TX11 TR02 TR03 TX01 EMU13 EMU06 EMU05 EMU04 SPICLK BOOTCOMPLETE SYSCLKOUT

Table 2-18

Terminal Functions — By Ball Number (Part 18 of 21)
Signal Name PACLKSEL CORESEL3 CORESEL2 VSS VSS VSS VDDR2 VSS RSV15 VSS VDDR4 VSS VDDR3 VSS VDDT2 VSS TX15 TX13 TR10 TX06 TX00 TR07 VSS EMU10 EMU08 EMU07 RSV22 CORESEL0 RSV20 VSS DVDD18 VSS PCIETXP0 PCIETXN0 VSS RIOTXN0 RIOTXP0 VSS RIOTXP3 RIOTXN3 VSS SGMII1TXP

Ball Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19

Ball Number AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AE1 AE2 AE3

Ball Number AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16

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SPRS691B—August 2011 Terminal Functions — By Ball Number (Part 19 of 21)
Signal Name SGMII1TXN VSS RSV09 TX17 TX10 VSS TX07 TX05 CLKA0 DVDD18 EMU17 EMU11 EMU09 SPISCS0 SPISCS1 CORECLKP CORECLKN PCIECLKP SRIOSGMIICLKP VSS PCIETXP1 PCIETXN1 VSS RIOTXN1 RIOTXP1 VSS RIOTXP2 RIOTXN2 VSS SGMII0TXP SGMII0TXN VSS TX14 TR17 DVDD18 FSA1 TX03 CLKB0 FSB0 EMU15 EMU14 EMU12

Table 2-18

Table 2-18

Terminal Functions — By Ball Number (Part 20 of 21)
Signal Name DVDD18 RSV04 RSV25 RSV24 PCIECLKN VSS PCIERXN0 PCIERXP0 VSS RIORXN1 RIORXP1 VSS RIORXP2 RIORXN2 VSS SGMII1RXP SGMII1RXN VSS RSV08 TX16 TR16 TR14 CLKB1 TX04 TR05 TR00 EMU18 RSV01 DVDD18 VSS DVDD18 RSV05 PASSCLKN PASSCLKP SRIOSGMIICLKN VSS PCIERXP1 PCIERXN1 VSS RIORXN0 RIORXP0 VSS

Table 2-18

Terminal Functions — By Ball Number (Part 21 of 21)
Signal Name RIORXP3 RIORXN3 VSS SGMII0RXP SGMII0RXN VSS TR15 TR13 FSB1 CLKA1 TX02 TR01 FSA0 EMU16 DVDD18 VSS

Ball Number AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29

Ball Number AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13

Ball Number AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29

End of Table 2-18

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SPRS691B—August 2011
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2.9 Development and Support
2.9.1 Development Support In case the customer would like to develop their own features and software on the C6678 device, TI offers an extensive line of development tools for the TMS320C6000? DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio? Integrated Development Environment (IDE). The following products support development of C6000? DSP-based applications: ? Software Development Tools: – Code Composer Studio? Integrated Development Environment (IDE), including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools. – Scalable, Real-Time Foundation Software (DSP/BIOS?), which provides the basic run-time target software needed to support any DSP application. ? Hardware Development Tools: – Extended Development System (XDS?) Emulator (supports C6000? DSP multiprocessor system debug) – EVM (Evaluation Module) 2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: ? TMX: Experimental device that is not necessarily representative of the final device's electrical specifications ? TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification ? TMS: Fully qualified production device Support tool development evolutionary flow: ? TMDX: Development-support product that has not yet completed Texas Instruments internal qualification testing. ? TMDS: Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CYP), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]). For device part numbers and further ordering information for TMS320C6678 in the CYP package type, see the TI website www.ti.com or contact your TI sales representative. Figure 2-17 provides a legend for reading the complete device name for any C66x KeyStone device.
Figure 2-17 C66x DSP Device Nomenclature (including the TMS320C6678)
TMX PREFIX TMX = Experimental device TMS = Qualified device DEVICE FAMILY 320 = TMS320 DSP family DEVICE C66x DSP: C6678 SILICON REVISION Blank = Initial Silicon 1.0 320 C6678 ( ) ( ) CYP ( ) ( ) DEVICE SPEED RANGE Blank = 1 GHz 25 = 1.25 GHz TEMPERATURE RANGE Blank = 0°C to +85°C (default case temperature) A = Extended temperature range (-40°C to +100°C) PACKAGE TYPE CYP = 841-pin plastic ball grid array, with Pb-free solder balls ENCRYPTION Blank = Encryption NOT enabled X = Encryption enabled

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SPRS691B—August 2011
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2.10 Related Documentation from Texas Instruments
These documents describe the TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com
64-bit Timer (Timer 64) for KeyStone Devices User Guide Bootloader for the C66x DSP User Guide C66x CorePac User Guide C66x CPU and Instruction Set Reference Guide C66x DSP Cache User Guide DDR3 Design Guide for KeyStone Devices DDR3 Memory Controller for KeyStone Devices User Guide DSP Power Consumption Summary for KeyStone Devices Embedded Trace for KeyStone Devices User Guide Emulation and Trace Headers Technical Reference Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide External Memory Interface (EMIF16) for KeyStone Devices User Guide General Purpose Input/Output (GPIO) for KeyStone Devices User Guide Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide Hardware Design Guide for KeyStone Devices HyperLink for KeyStone Devices User Guide Inter Integrated Circuit (I C) for KeyStone Devices User Guide Interrupt Controller (INTC) for KeyStone Devices User Guide Memory Protection Unit (MPU) for KeyStone Devices User Guide Multicore Navigator for KeyStone Devices User Guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide Network Coprocessor (NETCP) for KeyStone Devices User Guide Packet Accelerator (PA) for KeyStone Devices User Guide Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide Power Sleep Controller (PSC) for KeyStone Devices User Guide Security Accelerator (SA) for KeyStone Devices User Guide Semaphore2 Hardware Module for KeyStone Devices User Guide Serial Peripheral Interface (SPI) for KeyStone Devices User Guide Serial RapidIO (SRIO) for KeyStone Devices User Guide Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs Using IBIS Models for Timing Analysis
2

SPRUGV5 SPRUGY5 SPRUGW0 SPRUGH7 SPRUGY8 SPRABI1 SPRUGV8 SPRABL4 SPRUGZ2 SPRU655 SPRUGS5 SPRUGZ3 SPRUGV1 SPRUGV9 SPRABI2 SPRUGW8 SPRUGV3 SPRUGW4 SPRUGW5 SPRUGR9 SPRUGW7 SPRUGZ6 SPRUGS4 SPRUGS6 SPRUGV2 SPRUGV4 SPRUGY6 SPRUGS3 SPRUGP2 SPRUGW1 SPRUGY4 SPRUGP1 SPRA387 SPRA753 SPRA839

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SPRS691B—August 2011

3 Device Configuration
On the TMS320C6678 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.

3.1 Device Configuration at Device Reset
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP can be taken out of reset. Also, please note that most of the device configuration pins are shared with other function pins (LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0), some time must be given following the rising edge of reset in order to drive these device configuration input pins before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.

Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 86. Table 3-1
(1) (2)

TMS320C6678 Device Configuration Pins
Pin No. H25 IPD/IPU IPU
(1)

Configuration Pin LENDIAN

Functional Description Device endian mode (LENDIAN). 0 = Device operates in big endian mode 1 = Device operates in little endian mode Method of boot. Some pins may not be used by bootloader and can be used as general purpose config pins. Refer to the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 for how to determine the device enumeration ID value.

BOOTMODE[12:0]

(1) (2)

J28, J29, J26, J25, J27, J24, K27, K28, K26, K29, L28, L29, K25 L27, K24

IPD

PCIESSMODE[1:0]

(1) (2)

IPD

PCIe Subsystem mode selection. 00 = PCIe in end point mode 01 = PCIe legacy end point (support for legacy INTx) 10 = PCIe in root complex mode 11 = Reserved PCIe subsystem enable/disable. 0 = PCIE Subsystem is disabled 1 = PCIE Subsystem is enabled Network Coprocessor (PASS PLL) input clock select. 0 = CORECLK is used as the input to PASS PLL 1 = PASSCLK is used as the input to PASS PLL

PCIESSEN

(1) (2)

L24

IPD

PACLKSEL

(1)

AE4

IPD

End of Table 3-1
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 86. 2 These signal names are the secondary functions of these pins.

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TMS320C6678

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