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mt9v022


MT9V022I77ATM (mono) MT9V022I77ATC (color)

1/3-Inch, Wide-VGA CMOS Digital Image Sensor
Rugged Specs and High Quality for Scene-Understanding and Smart Imaging Applications Micron’s MT9V022 has specifically been designed to support the demanding interior and exterior needs of automotive imaging, which makes it ideal for a wide variety of scene understanding and smart imaging applications in realworld environments. This wide-VGA CMOS image sensor features DigitalClarity?, Micron’s breakthrough, low-noise CMOS imaging technology that achieves CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.

Applications
? ? ? ? Automotive Unattended surveillance Stereo vision Security ? ? ? ? Smart vision Automation Video as input Machine vision

Key Parameters
Optical format Active imager size Active pixels Pixel size Color filter array Shutter type Maximum data rate Master clock Full resolution Frame rate ADC resolution Responsivity Dynamic range 1/3-inch 4.51mm(H) x 2.88mm(V) 5.35mm Diagonal 752H x 480V 6.0?m x 6.0?m Monochrome or color RGB Bayer pattern Double-Buffered global shutter TrueSNAP? 26.6 Mp/s 26.6 MHz 752 x 480 60 fps (at full resolution) 10-bit 4.8 V/lux-sec (550nm) >55dB linear; >80dB–100dB in HiDy Mode 3.3V +0.3V (all supplies) <320mW at maximum data rate; 100?W standby current –40°C to +85°C 52-ball IBGA, automotivequalified; wafer or die

Features
? Micron’s DigitalClarity? CMOS imaging technology ? Double-buffered global shutter photodiode pixels ? Simultaneous integration and readout ? Enhanced Near-IR performance (NIR QE >35%) ? Progressive or interlaced readout modes ? Linear or high dynamic range pixel response ? >99% global shutter efficiency ? Register lock capability ? User-Programmable window size within frame ? 2 x 2 and 4 x 4 pixel averaging of the full resolution ? ADC On-Chip (10-bit linear or 12-bit to 10-bit companding mode) ? Auto exposure control (AEC) ? Auto gain control (AGC) ? Black level calibration (BLC) ? User-Programmable regional gain and exposure weighting (25 regions) ? Support for 4 unique serial control register IDs to control multiple imagers on the same bus ? Master/Slave dual sensor operation for stereoscopic, foveal, or hyperspectral operation ? On-Chip digital thermometer ? Data output formats: – Single sensor mode: 10-bit parallel/stand-alone or 8bit or 10-bit serial LVDS – Dual sensor mode: Interspersed 8-bit serial LVDS

Supply voltage Power consumption

Operating temperature Packaging

Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor General Description

General Description
The MT9V022 active imaging pixel array is 752H x 480V. It incorporates sophisticated camera functions on-chip, such as averaging 2 x 2 and 4 x 4, to improve SNR when operating in smaller resolutions, as well as windowing and column and row mirroring. It is programmable through a simple two-wire serial interface. The MT9V022 pixel response can be configured for either linear light response with >55dB of dynamic range or for high dynamic range response with as much as 100dB of dynamic range. The MT9V022 can be operated in its default mode or be programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-sized image at 60 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. The user can alternatively enable 12-bit resolution companded to 10 bits for small signals, enabling more accurate digitization for darker areas in the image. In addition to a traditional, parallel logic output, the MT9V022 also features a serial lowvoltage differential signaling (LVDS) output. The sensor can be operated in stereo-camera mode, where the sensor, designated as a stereo-master, is able to merge the data from itself and the stereo-slave sensor into one serial LVDS stream. The sensor is designed to operate in a wide temperature range (–40°C to +85°C). A builtin digital thermometer allows the host to read the temperature through the two-wire serial interface. Figure 1: Block Diagram
Serial Register I/O

Control Register Active-Pixel Sensor (APS) Array 752H x 480V Timing and Control

Analog Processing
Parallel Video Data Out

ADCs

Digital Processing

Slave Video LVDS In Serial Video (for stereo applications only) LVDS Out

Operational Modes
The MT9V022 works in master, snapshot, or slave mode. In master mode, the sensor generates the readout timing. There are two possible operation methods for master mode: simultaneous and sequential. In simultaneous master mode, the exposure period occurs during readout. The exposure and readout occur in parallel rather than sequentially, making this the fastest mode of operation. In sequential master mode, the exposure period is followed by readout, and the frame rate changes as the integration time changes. In snapshot mode, the start of the integration period is determined by the externallyapplied EXPOSURE pulse that the user inputs to the MT9V022. The sensor in snapshot mode can capture a single image or a sequence of images.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Pixel Data Format and Pixel Array Structure
In slave mode, the sensor accepts both external integration and readout controls. The integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled via an externally generated control signal during slave mode.

LVDS Serial Output (Stand-Alone and Stereoscopic Operation)
The LVDS interface allows for the streaming of sensor data serially to a standard off-the shelf deserializer up to 8 meters away from the sensor. The LVDS serial output could either be data from a single sensor (stand-alone) or stream-merged data from a pair (master and slave) of synchronized MT9V022 devices. The pixels (and controls) are packeted—12-bit packets for stand-alone mode and 18-bit packets (2 frame bits and 8 data bits from each sensor) for stereoscopic mode. All serial signals (clock and data) is LVDS. An LVDS connection overview for a single MT9V022 and for stereoscopic pair of MT9V022 devices is shown in Figure 2. Figure 2: LVDS Stereoscopic Topology
SLAVE MASTER
26.6 MHz Osc.
LVDS SER_DATAIN

SENSOR SENSOR

LVDS SER_DATAIN

SENSOR

LVDS BYPASS_CLKIN
X 1 8/X 1 2 PL L

LVDS BYPASS_CLKIN

LVDS SER_DATAOUT

LVDS SHIFT_CLKOUT

LVDS SER_DATAOUT

LVDS SHIFT_CLKOUT

5m (maximum)
1. PLL in non-bypass mode 2. PLL in x 18 mode (stereoscopy) 1. PLL in bypass mode

DS92LV16
8 PIXEL FROM SLAVE 8 PIXEL FROM MASTER

26.6 MHz Osc.

LV and FV are embedded in the data stream

Pixel Data Format and Pixel Array Structure
The MT9V022 pixel array is configured of 782 columns by 492 rows, as shown in Figure 3. The left 26 columns and the top 8 rows of pixels are optically black and can be used to monitor the black level. The black row data is used internally for the automatic black level adjustment.

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Format
Figure 3: Pixel Array Description and Color Pattern Detail
8 dark, 1 light dummy rows
Column Readout Direction

(0,0)
Dummy Pixel Row Readout Direction Pixel (2,9)

G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G

26 dark, 1 light dummy columns

2 dummy columns

Dummy Pixel

(782,492)

2 dummy rows

Output Data Format
The MT9V022 image data can be read out in a progressive scan or in interlaced scan mode. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 4. Figure 4: Spatial Illustration of Image Readout: Interlaced Scan (left) and Progressive Scan (right)
00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00

P4,1 P4,2 P4,3.....................................P4,n-1 P4,n P6,0 P6,1 P6,2.....................................P6,n-1 P6,n VALID IMAGE - Even Field Pm-2,0 Pm-2,2.....................................Pm-2,n-2 Pm-2,n Pm,2 Pm,2.....................................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 P5,1 P5,2 P5,3.....................................P5,n-1 P5,n P7,0 P7,1 P7,2.....................................P7,n-1 P7,n VALID IMAGE - Odd Field Pm-3,1 Pm-3,2.....................................Pm-3,n-1 Pm-3,n Pm,1 Pm,1.....................................Pm,n-1 Pm,n

HORIZONTAL BLANKING
VALID IMAGE

HORIZONTAL BLANKING

FIELD BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00

VERTICAL BLANKING 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00

00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Timing

Output Data Timing
The data output of the MT9V022 is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period. Figure 5: Row Timing and FRAME_VALID/LINE_VALID Signals
...

FRAME_VALID
...

LINE_VALID
...

Number of master clocks

P1

A

Q

A

Q

A

P2

Figure 6:

Timing Example of Pixel Data
....

LINE_VALID
....

PIXCLK
Blanking P0 (9:0) P1 (9:0) Valid Image Data P2 (9:0) P3 (9:0) P4 (9:0)

....

Blanking Pn-1 (9:0) Pn (9:0)

DOUT(9:0)

....

Note:

The parameters P1, A, Q, and P2 are defined in Table 1 on page 5.

Table 1:

Frame Time
Description Active data time Frame start blanking Frame end blanking Horizontal blanking Row time Vertical blanking Frame valid time Total frame time Pixel Clock 752 71 23 94 846 38,074 406,080 444,154 Master Clocks 752 71 23 94 846 38,074 406,080 444,154 Time 28.02 2.66 0.86 3.52 31.72 1.43 15.23 16.66 Units ?s ?s ?s ?s ?s ms ms ms

Parameter A P1 P2 Q A+Q V Nrows F

Serial Bus Description
The MT9V022 control registers are written to and read from the two-wire serial interface bus. The MT9V022 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0, and 0xB8) determined by S_CTRL_ADR0 and S_CTRL_ADR1 inputs. Data is transferred into the MT9V022 and out through the serial data (SDATA) line. The SDATA line is pulled up to VDD off-chip by a 1. 5kΩ resistor. Either the slave or master device can pull the SDATA line down. The serial interface protocol determines which device is allowed to pull the SDATA line down at any given time.

Register Lock
A register lock feature is included in the MT9V022 to help reduce the probability of an inadvertent, noise-triggered two-wire serial interface WRITE to the sensor. The user may lock all registers or only the read mode register. The read mode register controls the image orientation, and an unintended flip to the image can cause serious results.

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Timing High Dynamic Range
The MT9V022 pixel light response can be optionally configured to achieve intra-scene dynamic range as high as 100dB. High dynamic range is achieved by controlling the slopes of a three-segment, piecewise, linear pixel response, as illustrated in Figure 7. The slope of the three segments can be programmed via the serial interface. Figure 7: High Dynamic Range

Linear Response

High Dynamic Range Response

Output

Light

Variable ADC Resolution
By default, the MT9V022 ADC has a linear response with 10-bit resolution. The ADC can also be configured to have a 12- to 10-bit companding response, as illustrated in Figure 7. This mode allows higher ADC resolution (12 bits) for low-level signals (shadow details) and lower ADC resolution (9 bits) for high-level signals (highlight details. ) Figure 8: 12- to 10-Bit ADC Companding Chart
10-Bit Codes 1,024 768 512 256 12-Bit Resolution (0:255 256 1,024 2,048 0:255) 4,096 12-Bit Codes 9-Bit Resolution (2048:4095 10-Bit Resolution (512:2047 11-Bit Resolution (256:511 256:383) 384:767) 768:1,023)

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Timing Automatic Gain Control (AGC) and Automatic Exposure Control (AEC)
The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. When the AGC or AEC are enabled, the MT9V022 measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel values while reading out a frame. The desired exposure and gain are then calculated and applied for the subsequent frame.

Pixel Clock Speed
The pixel clock speed is same as the master clock of 26.66 MHz by default. However, when column binning 2 or 4 is enabled, the pixel clock speed will be reduced by half or one-fourth of the master clock speed, respectively.

Gain Settings
Analog Gain Digital Gain The analog gain range supported in the MT9V022 is 1X–4X with a step size of 6.25 percent. In the MT9V022, the user either may apply a single gain value for the entire array or they may divide the image into 25 tiles (Figure 9) through the two-wire serial interface and apply digital gain individually to each tile. The coordinates and digital gain (0.25 - 3.75X) of each tile may be individually programmed via the two-wire serial interface. This feature should help improve pulling detail out of regions of an image that are either dark, or lighter than the rest of the scene without affecting the rest of the scene. Figure 9: Digital Gain Tiled Sample
X0/5 X1/5 X2/5 Y0/5 x0_y0 x1_y0 Y1/5 x0_y1 Y2/5 x0_y2 Y3/5 x0_y3 Y4/5 x0_y4 x1_y4 x4_y4 x1_y3 x4_y3 x1_y2 x4_y2 x1_y1 x4_y1 X3/5 X5/5 X5/5 x4_y0

Y5/5

Read Mode Options
Column and Row Flip To ease mounting orientation issues, the MT9V022 column and row readout order can be independently reversed via the two-wire serial interface. The image will then be represented correctly regardless of camera orientation.

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Pixel Binning In addition to windowing mode— in which smaller resolution (CIF, QCIF, user-selected size frame) is obtained by selecting a small window from the sensor array—the MT9V022 provides the ability to show the entire image captured by the pixel array with smaller resolution by pixel binning. Pixel binning is performed by combining signals from adjacent pixels by averaging. There are two options: binning 2 and binning 4. When binning 2 is on, 4 pixel signals from 2 adjacent rows and columns are combined. In the case of binning 4 mode, 16 pixels are combined from 4 adjacent rows and columns. Binning may be used in conjunction with image flip. The binning operation increases SNR but decreases resolution. Enabling row bin2 and row bin4 improves frame rate by 2x and 4x, respectively. Column binning does not increase the frame rate.

Power Reduction Modes
Standby Control The user may set the sensor in standby mode by setting STANDBY HIGH. Once the MT9V022 detects that STANDBY is asserted, it completes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. To release the sensor out from the standby mode, reset STANDBY back to LOW. Monitor Mode Control In this mode, the MT9V022 first captures a programmable number of frames and then goes into a sleep period for five minutes. During the sleep period, all of the analog circuitry of the MT9V022 is powered-down and only a small portion of the digital circuitry remains powered.

Thermometer
The MT9V022 thermometer circuit provides a digital output vs. temperature that is accessible via the serial interface. The resolution of the thermometer is approximately 1 LSB per degree Celsius.

Electrical Specifications
Table 2:
Symbol VIH VIL IIN VOH VOL IOH IOL VAA IPWRA VDD IPWRD VAAPIX IPIX

DC Electrical Characteristics
VPWR = 3.3V ±0.3V; TA = Ambient = 25°C Definition Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Output high current Output low current Analog power supply Analog supply current Digital power supply Digital supply current Pixel array power supply Pixel supply current Condition Min VPWR -0.5 -0.3 -15.0 VPWR -0.7 – -9.0 – 3.0 – 3.0 — 3.0 0.5 Typ – – – – – – – 3.3 35.0 3.3 35.0 3.3 1.4 Max VPWR +0.3 0.8 15.0 – 0.3 – 9.0 3.6 60.0 3.6 60 3.6 3.0 Unit V V μA V V mA mA V mA V mA V mΑ

No pull-up resistor; VIN = VPWR or VGND IOH = -4.0mA IOL = 4.0mA VOH = VDD - 0.7 VOL = 0.7 Default settings Default settings Default settings Default settings, CLOAD= 10pF Default settings Default settings

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Table 2:
Symbol VLVDS ILVDS IPWRA Standby IPWRD Standby Clock Off IPWRD Standby Clock On |VOD| |DVOD| VOS DVOS IOS IOZ

DC Electrical Characteristics (continued)
VPWR = 3.3V ±0.3V; TA = Ambient = 25°C Definition LVDS power supply LVDS supply current Analog standby supply current Digital standby supply current with clock off Digital standby supply current with clock on Condition Default settings Default settings STDBY = VDD STDBY = VDD, CLKIN = 0 MHz Min 3.0 11.0 2 1 Typ 3.3 13.0 3 2 Max 3.6 15.0 4 4 Unit V mA μA μA

STDBY= VDD, CLKIN = 27 MHz



1.05



mA

LVDS Driver DC Specifications Output differential voltage Change in VOD between complementary output states Output offset voltage Change in VOS between complementary output states Output current when driver shorted to ground Output current when driver is tri-state Input differential Input current 250 – RLOAD = 100 1.0 – – – 1.2 – 400 50 1.4 35 mV mV mV mV mA μA

Ω ±1%

±10 ±1

±12 ±10

LVDS Receiver DC Specifications VIDTH+ Iin | VGPD| <925mV -100 – – –

±20

100

mV μA

Table 3:
Symbol
tR tF t t

AC Electrical Characteristics
VPWR = 3.3V ±0.3V; TA = Ambient = 25°C; Output Load = 10pF Definition Clock duty cycle Input clock rise time Input clock fall time SYSCLK to PIXCLK propagation delay PIXCLK to valid DOUT(9:0) propagation delay Data setup time Data hold time PIXCLK to LINE_VALID propagation delay PIXCLK to FRAME_VALID propagation delay Condition Min 45.0 1 1 3 -2 14 14 -2 -2 Typ 50.0 2 2 7 0 16 16 0 0 Max 55.0 5 5 11 2 – – 2 2 Unit % ns ns ns ns ns ns ns

PLHP PD tSD tHD tPFLR t PFLF

CLOAD = 10pF CLOAD = 10pF

CLOAD = 10pF CLOAD = 10pF

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Table 4: Absolute Maximum Ratings
Symbol VSUPPLY ISUPPLY IGND VIN VOUT TSTGNote: Note: Parameter Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature Min -0.3 – – -0.3 -0.3 -40 Max 4.5 200 200 VDDQ + 0.3 VDDQ + 0.3 +125 Unit V mA mA V V °C

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Figure 10:

Propagation Delays for PIXCLK and Data Out Signals
tF tR

SYSCLK
tPLHP

PIXCLK
tPD tSD tHD

DOUT(9:0)

Figure 11:

Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPFLR tPFLF

PIXCLK FRAME_VALID LINE_VALID

PIXCLK FRAME_VALID LINE_VALID

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Figure 12: Quantum Efficiency – Color and Monochrome

60

Quantum Efficiency (%)

50

Blue Green (B) Green (R) Red MONO

40

30

20

10

0 350

450

550

650

750

850

950

1,050

Wavelength (nm)

Figure 13:

Typical Configuration (Connection) – Parallel Output Mode
VDD VAA VAA VAAPIX VAAPIX DOUT(9:0) LINE_VALID FRAME_VALID PIXCLK LED_OUT ERROR

1.5KΩ
Master Clock STANDBY from Controller or Digital GND Two-Wire Serial Interface 0.1μF

10KΩ

VDDLVDS

VDD

SYSCLK OE RESET# EXPOSURE STANDBY S_CTRL_ADR0 S_CTRL_ADR1 SCLK SDATA

To Controller

To LED output

RSVD

DGND LVDSGND

AGND

Note:

LVDS signals are to be left floating.

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Figure 14: 52-Ball IBGA Package
1 2 3 4 5 6 7 8

A

VDD LVDS

SER_ SER_ DATAOUT DATAOUT _P _N SHFT_ CLKOUT _P BYPASS _CLKIN _N SER_ DATAIN _N VDD SHFT_ CLKOUT _N LVDS GND

VDD LVDS

SYSCLK

DOUT0

DOUT2

DOUT3

B

LVDS GND

VDD

PIXCLK

DOUT1

DOUT4

VAAPIX

C

BYPASS _CLKIN _P SER_ DATAIN _P DOUT5

DGND

AGND

VAA

D

NC

NC

E

NC

NC

F

DOUT6

DOUT7

DGND

AGND

VAA

STANDBY

G

DOUT8

FRAME _VALID

STLN_ OUT EXPOSURE

SDATA

STFRM_ OUT

LED_ OUT

S_CTRL_ ADR0

RESET#

H

DOUT9

LINE_ VALID

SCLK

ERROR

OE

RSVD

S_CTRL _ADR1

Top View (Ball Down)

Table 5:

Ball Descriptions
Only pins DOUT0 through DOUT9 may be tri-stated.

52-Ball IBGA Numbers H7 D2 D1 C2 C1 H3 H4

Symbol RSVD SER_DATAIN_N SER_DATAIN_P BYPASS_CLKIN_N BYPASS_CLKIN_P EXPOSURE SCLK

Type Input Input Input Input Input Input Input

Description Connect to DGND. Serial data in for stereoscopy (differential negative). Tie to 1KΩ pull-up (to 3.3V) in non-stereoscopy mode. Serial data in for stereoscopy (differential positive). Tie to DGND in non-stereoscopy mode. Input bypass shift-CLK (differential negative). Tie to 1KΩ pull-up (to 3.3V) in non-stereoscopy mode. Input bypass shift-CLK (differential positive). Tie to DGND in non-stereoscopy mode. Rising edge starts exposure in slave mode. Two-wire serial interface clock. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. DOUT enable pad, active HIGH. Two-wire serial interface slave address bit 3. Two-wire serial interface slave address bit 5. Asynchronous reset. All registers assume defaults. Shut down sensor operation for power saving.

Notes 1

H6 G7 H8 G8 F8

OE S_CTRL_ADR0 S_CTRL_ADR1 RESET# STANDBY

Input Input Input Input Input

2

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Table 5: Ball Descriptions (continued)
Only pins DOUT0 through DOUT9 may be tri-stated. 52-Ball IBGA Numbers A5 G4 Symbol SYSCLK SDATA Type Input I/O Description Master clock (26.6 MHz). Two-wire serial interface data. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. Output in master mode—start line sync to drive slave chip in-phase; input in slave mode. Output in master mode—start frame sync to drive a slave chip in-phase; input in slave mode. Asserted when DOUT data is valid. Asserted when DOUT data is valid. Parallel pixel data output 5. Parallel pixel data output 6. Parallel pixel data output 7. Parallel pixel data output 8 Parallel pixel data output 9. Error detected. Directly OR with STEREO ERROR FLAG and PIXEL ERROR FLAG. LED strobe output. Parallel pixel data output 4. Parallel pixel data output 3. Parallel pixel data output 2. Parallel pixel data output 1. Parallel pixel data output 0. Pixel clock out. DOUT is valid on rising edge of this clock. Output shift CLK (differential negative). Output shift CLK (differential positive). Serial data out (differential negative). Serial data out (differential positive). Digital power 3.3V. Analog power 3.3V. Pixel power 3.3V. Dedicated power for LVDS pads. Dedicated GND for LVDS pads. Digital GND. Analog GND. No connect. Notes

G3 G5 H2 G2 E1 F1 F2 G1 H1 H5 G6 B7 A8 A7 B6 A6 B5 B3 B2 A3 A2 B4, E2 C8, F7 B8 A1, A4 B1, C3 C6, F3 C7, F6 E7, E8, D7, D8

STLN_OUT STFRM_OUT LINE_VALID FRAME_VALID DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 ERROR LED_OUT DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK SHFT_CLKOUT_N SHFT_CLKOUT_P SER_DATAOUT_N SER_DATAOUT_P VDD VAA VAAPIX VDDLVDS LVDSGND DGND AGND NC

I/O I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Supply Supply Supply Supply Ground Ground Ground NC

3

Notes: 1. Pin H7 (RSVD) must be tied to GND. 2. Output Enable (OE) tri-states signals DOUT0-DOUT9. No other signals are tri-stated with OE. 3. No connect. These pins must be left floating for proper operation.

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications
Figure 15: 52-Ball IBGA Package Outline Drawing
0.90 (FOR REFERENCE ONLY) 1.50 MAX B SEATING PLANE 0.10 A A 0.40 (FOR REFERENCE ONLY) 0.125 (FOR REFERENCE ONLY) 0.525 ±0.050 0.375 ±0.075 7.00 52X ?0.55
DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW DIAMETER IS 0.50.

1.00 TYP BALL A8

BALL A1 BALL A1 ID

BALL A1 CORNER

4.500 ±0.075 OPTICAL CENTER 1.849 1.999 FUSES FIRST CLEAR PIXEL

4.50 ±0.05 3.50

4.500 ±0.075 OPTICAL CENTER

7.00

C L

9.000 ±0.075

4.90

1.00 TYP

C L 4.50 ±0.05 9.000 ±0.075 SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3% Ag, 0.5% Cu NON SOLDER MASK DEFINED BALL PADS: ?0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE ENCAPSULANT: EPOXY 3.50

OPTICAL AREA

5.50

MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1? MAXIMUM TILT OF OPTICAL AREA RELATIVE TO PACKAGE EDGE B : 50 MICRONS. MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 50 MICRONS. LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS IMAGE SENSOR DIE

Note:

All dimensions in millimeters.

PDF:09005aef8201ffc3/Source: 09005aef81ff2525 MT9V022_Product_Brief - Rev. A 1/06 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Ordering Information

Ordering Information
Production Parts
MT9V022I77ATM MT9V022IA7ATM MT9V022I77ATC MT9V022IA7ATC Monochrome Pb packaged parts Monochrome Pb-Free packaged parts Color Pb packaged parts Color Pb-Free packaged parts

Demo Kits
A demonstration kit is also available for evaluation purposes and consists of: ? ? ? ? ? Micron Imaging Demo2 Camera Board Micron Sensor Head with lens USB2.0 Cable Software CD Demo User Manual picture from Demo Kit
Monochrome Demo Kit Color Demo Kit

MT9V022I77ATMD ES MT9V022I77ATCD ES

Headboards
MT9V022I77ATMH ES MT9V022I77ATCH ES Note: Monochrome Headboard Color Headboard

For customers who already have a demo kit with the demo 2 camera board (USB2.0), only order the head board.

?

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF:09005aef8201ffc3/Source: 09005aef81ff2525 MT9V022_Product_Brief - Rev. A 1/06 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice. ?2006 Micron Technology, Inc. All rights reserved.


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