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vlsi circuit design 03 static cmos logic


VLSI Circuits Design
Static CMOS Logic

Harbin Institute of Technology Microelectronics Center

CMOS Circuit Styles
?

HIT Microelectronics

>Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path
?

high noise margins
- full rail to rail swing - VOH and VOL are at VDD and GND, respectively

?
? ? ?

low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions)

?

Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes
? ?

simpler, faster gates increased sensitivity to noise

Static CMOS Logic - 2

Static Complementary CMOS
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HIT Microelectronics

Pull-up network (PUN) and pull-down network (PDN)
VDD PMOS transistors only In1 In2 PUN pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1 F(In1,In2,…InN) PDN pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0

InN
In1 In2 InN

NMOS transistors only

PUN and PDN are dual logic networks
Static CMOS Logic - 2

Threshold Drops
PUN VDD
S

HIT Microelectronics

VDD
D

VDD
D

0 ? VDD

VGS

S

0 ? VDD - VTn

CL

CL

PDN
D

VDD ? 0 CL

VGS

VDD ? |VTp|
S

VDD
S

CL

D

Static CMOS Logic - 2

Construction of PDN
?

HIT Microelectronics

NMOS devices in series implement a NAND function
A?B

A
B

?

NMOS devices in parallel implement a NOR function
A+B A B

Static CMOS Logic - 2

Dual PUN and PDN
?

HIT Microelectronics

PUN and PDN are dual networks
?

DeMorgan’s theorems
A+B=A?B [!(A + B) = !A ? !B or !(A | B) = !A & !B]

A?B=A+B
?

[!(A ? B) = !A + !B or !(A & B) = !A | !B]

a parallel connection of transistors in the PUN corresponds to a series connection of the PDN

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Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)
Number of transistors for an N-input logic gate is 2N

?

Static CMOS Logic - 2

CMOS NAND

HIT Microelectronics

A

B

F

0
A B 0 1

0
1 0 1

1
1 1 0

A?B
A B A B

1

Static CMOS Logic - 2

CMOS NOR

HIT Microelectronics

A

B

F

B
A

0
0

0
1 0

1
0 0

A+B
A B

1

1

1

0

A B

Static CMOS Logic - 2

Complex CMOS Gate

HIT Microelectronics

B
A C D OUT = !(D + A ? (B + C)) A

D
B C

Static CMOS Logic - 2

Standard Cell Layout Methodology

HIT Microelectronics

Routing channel VDD

signals

GND

What logic function is this?
Static CMOS Logic - 2

VTC is Data-Dependent
3

HIT Microelectronics

0.5?/0.25? NMOS 0.75? /0.25? PMOS

A

M3 B

M4
2

F= A ? B
D

A,B: 0 -> 1 B=1, A:0 -> 1 A=1, B:0->1

A
VGS2 = VA –VDS1

M2 M1
S

1
Cint

weaker PUN

S D

B
VGS1 = VB

0 0 1 2

?

The threshold voltage of M2 is higher than M1 due to the body effect (?)
VTn1 = VTn0 VTn2 = VTn0 + ?(?(|2?F| + Vint) - ?|2?F|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint

Static CMOS Logic - 2

Static CMOS Full Adder Circuit
!Cout = !Cin & (!A | !B) | (!A & !B)

HIT Microelectronics

!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)

B
A B B A Cin A A B Cin A Cin !Sum Cin

!Cout

A

B

B

A

B

Cin

A B

Cout = Cin & (A | B) | (A & B)
Static CMOS Logic - 2

Sum = !Cout & (A | B | Cin) | (A & B & Cin)

Next Time: Pass Transistor Circuits

HIT Microelectronics

A

A?B

B

Static CMOS Logic - 2


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