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vlsi circuit design 10 multipliers


VLSI Circuits Design
Multiplier Design
Wang Yong-sheng
yswang@hit.edu.cn

Harbin Institute of Technology Microelectronics Center

Review: Basic Building Bl

ocks
?

HIT Microelectronics

Datapath
?

Execution units
- Adder, multiplier, divider, shifter, etc.

? ?

Register file and pipeline registers Multiplexers, decoders

?

Control
?

Finite state machines (PLA, ROM, random logic)

?

Interconnect
?

Switches, arbiters, buses

?

Memory
?

Caches (SRAMs), TLBs, DRAMs, buffers

Multiplier Design - 2

WANG Yong-sheng

2013-7-20

Multiply Operation
?

HIT Microelectronics

Multiplication as repeated additions

N multiplicand multiplier partial product array

N

can be formed in parallel

double precision product 2N

Multiplier Design - 3

WANG Yong-sheng

2013-7-20

Shift & Add Multiplication
?

HIT Microelectronics

Right shift and add
? ? ?

Partial product array rows are accumulated from top to bottom on an N-bit adder After each addition, right shift (by one bit) the accumulated partial product to align it with the next row to add Time for N bits Tserial_mult = O(N Tadder) = O(N2) for a RCA Use a faster adder Use higher radix (e.g., base 4) multiplication
- Use multiplier recoding to simplify multiple formation

?

Making it faster
? ?

?

Form partial product array in parallel and add it in parallel Use an array multiplier
- Very regular structure with only short wires to nearest neighbor cells. Thus, very simple and efficient layout in VLSI - Can be easily and efficiently pipelined

?

Making it smaller (i.e., slower)
?

Multiplier Design - 4

WANG Yong-sheng

2013-7-20

Array Multiplier
X3 X2 X1

HIT Microelectronics

X0 Z0

Y0

X3

X2

X1

X0

Y1

HA
X3 X2

FA
X1

FA
X0 Y2

HA
Z1

FA
X3 X2

FA
X1

FA
X0 Y3

HA
Z2

Multiplicand: X, M bits Multiplier: Y, N bits

FA
Z7 Z6

FA
Z5

FA
Z4

HA
Z3

Tmul=[(M-1)+(N-2)]tcarry+(N-1)tsum+tand
Multiplier Design - 5 WANG Yong-sheng 2013-7-20

Carry-Save Multiplier
X3 X2 X1

HIT Microelectronics

X0 Z0

Y0

X3

X2

X1

X0

Y1

HA
X3 X2

HA
X1

HA
X0 Y2

HA
Z1

HA
X3 X2

FA
X1

FA
X0 Y3

FA
Z2

Multiplicand: X, M bits Multiplier: Y, N bits

HA

FA

FA

FA
Z3

HA
Z7

FA
Z6

FA
Z5

HA
Z4

Vector Merging Adder

Multiplier Design - 6

Tmul=(N-1)tcarry+tmerge+tand

WANG Yong-sheng

2013-7-20

Wallace Tree Multiplier Structure
0 D 0 D multiple forming circuits partial product array reduction tree fast carry propagate adder (CPA) 0 D

HIT Microelectronics

Q (?ier)

0 D (?icand)

mux + reduction tree (log N) + CPA (log N)
P (product)
WANG Yong-sheng 2013-7-20

Multiplier Design - 7

4x4 Multiply Operation (review)

HIT Microelectronics

multiplicand multiplier partial product array

partial product array

Multiplier Design - 8

WANG Yong-sheng

2013-7-20

(3,2) Counter
?

HIT Microelectronics

(3,2) counters (just FA?s!)

(3,2)

?

HA operation

(HA)

Multiplier Design - 9

WANG Yong-sheng

2013-7-20

4x4 Partial Product Array Reduction
?

HIT Microelectronics

Fast 4x4 multiplication using (3,2) counters
multiplicand multiplier partial product array

double precision product
Multiplier Design - 10 WANG Yong-sheng 2013-7-20

(4,2) Counter
?
? ?

HIT Microelectronics

Built out of two (3,2) counters (just FA?s!)
all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position) the internal output is carried to the next higher weight position (indicated by the )

(3,2)

(3,2)

Note: Two carry outs - one “internal” and one “external”

Multiplier Design - 11

WANG Yong-sheng

2013-7-20

Tiling (4,2) Counters

HIT Microelectronics

(3,2)

(3,2)

(3,2)

(3,2)

(3,2)

(3,2)

?

Reduces columns four high to columns only two high
? ?

Tiles with neighboring (4,2) counters Internal carry in at same “level” (i.e., bit position weight) as the internal carry out

Multiplier Design - 13

WANG Yong-sheng

2013-7-20

4x4 Partial Product Array Reduction
?

HIT Microelectronics

Fast 4x4 multiplication using (4,2) counters
multiplicand multiplier partial product array reduced pp array (to CPA) double precision product

Multiplier Design - 15

WANG Yong-sheng

2013-7-20

8x8 Partial Product Array Reduction
How many (4,2) counters minimum are needed to reduce it to 2 rows?

HIT Microelectronics

‘icand ‘ier

partial product array

Answer: 24
reduced partial product array

Multiplier Design - 17

WANG Yong-sheng

2013-7-20

More (4,2) counters, so what is the advantage?

Alternate 8x8 Partial Product Array HIT Microelectronics Reduction ‘icand
‘ier

partial product array

reduced partial product array

Multiplier Design - 18

WANG Yong-sheng

2013-7-20

Next Lecture and Reminders
?

HIT Microelectronics

Next lecture
?

Shifters, decoders, and multiplexers

Multiplier Design - 19

WANG Yong-sheng

2013-7-20


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