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?

V+

R5

VBIAS1

Q6 Q4

? ???? ?????

????? ??????????
VIN Q1 Q2

R2 R4 VOUT R3

? ???? ???? ????
V

BIAS2 Q5

R1 Q3

R6

V–

??

??? ?? ?? ?? ?? ??? ?? ?? ?? ??? ?? ?? ??? ?? ?? ?? ??? ?? ?? ?? ??
?

?

? ????? ??? ???

? ? ???? ??? ? ???

?

???

1 991 Burr-Brown Corporation

AB-027A

Printed in U.S.A. June, 199 1

V+

R1

R2

VIN

– VGS +

Q1 R1 + Q2 VBE – R3 VOUT Q3 Q7 R4 Q6 VIN A1 Op Amp A2 Buffer VOUT

FIGURE 3. High Current Op Amp.

Q4 + VBE –

???
Q5 R2

?? ? ?? ?? ?

??

??? ?? ??

V–

? ?? ??? ???? ???

?? ?? ??? ??? ??

?? ???

? ? ???? ???? ????? ?????? ? ?? ? ? ?

?

? ??? ?? ?? ?? ??

?? ???

????? ??? ?? ??

?

?????

?????? ?????

?????

? ????
V+ RG Q1 VIN CL RL VOUT

??? ??

Z OUT = re + ( )=

RG + rb ( ) (o)

1.4 1.2 1.0 0.8 k = 0.44, T = 4.7ns k = 0.35, T = 5.6ns

1+j =
t

(o) Z OUT = re + RG + rb (o) LEQ + j (RG + rb)
t

0.6 k = 0.51, T = 1.9ns 0.4 0.2 0

Z OUT = REQ + j

FIGURE 4. Output Impedance of Emitter Follower. ??

0

1

2

3

4 5 Time (ns)

6

7

8

9

VOUT VIN

=1–

[

1 1 k t t sin 2 (1 – k2) 2 + cos 2 (1 – k2) 2 e–2 (1 – k2)1/2 T T

]

FIGURE 7. Results. ? ?
k(t/T)

1

RO VOUT VOUT VIN

where: T = 2 (LEQ ? CL ) 2 k=

[

REQ LEQ

+

1 RL CL

]

T 4

VIN

RO

REQ = re + LEQ =

RG + rb (o) VIN VIN Cable Input V

RG + rb T V

?? FIGURE 5. Time Response.

VOUT T

V

V/2

V/2

Received fT = 1GHz RG = 50 rb = 50 re = 5 CL = 50pF (o) = 100 k = 0.35 T = 5.6ns fT = 5GHz RG = 50 rb = 50 re = 5 CL = 50pF (o) = 100 k = 0.44 T = 4.7ns fT = 5GHz RG = 50 rb = 50 re = 5 CL = 50pF (o) = 100 k = 0.51 T = 1.9ns T VOUT Reflected

V/2

V/2

V T

?? ??

?

V+ R5 R6 R7

Q4

Q5 Q6 R9 C1 C2 To V–

Q8

Q9 Q7 To V–

+In

Q2 R2

Pole-Zero Comp

C3 Q3 R3 Q11 Q12 Q10 Integrator Compensation Q14 R11 VOUT R10 Q15 VBIAS Q13

–In

Q1

R1

R8

R9 V–

??

? ??? ?? ?? ?? ?? ?? ??? ?? ?? ?? ?? ?? ??? ? ??? ?? ?? ?? ?? ?? ?? ?? ?? ??? ??? ???? ??? ??? ??? ?? ????? ??

? ?? ???? ???? ????

???

??????

?

V+ I1 I2 C2 Q3 C1 A1 Q4 VOUT

G=

1
2

1 1– A(o) 1
2

+j
1 2

A(o)

(

1
1

+

1
2

)

G=

1 1– n2

+2

( )
n
1 2 1

where

n = A(o) + =

2 1 2

–In

Q1

Q2

+In Step Response: e0(t) = 1 e1(t) 1 –

2 A(o)

[

t– 1–

nt
2

sin ( n

1–

2

t + cos–1 )

]

V– 1 A 1+A A(o)

FIGURE 11. Transient Response Integrator Compensation. ???

G=

A( ) =

(

1+j

1

) (1 + j )
2

Case 2 Case 1

Pole Due to Integrator

Second Pole A

Case 1 = 0.2 Case 2 = 0.8

???
f11 f1 2 f GT f2

Case 1 Case 2

??
f eO(t) Case 2 Case 1

FIGURE 12. Open Loop Gain, Closed Loop Gain, and Tran??? sient Response Integrator Compensation. ?? ?? ????

??

?? ?? ?? ?? ?? ????? ?

?? ??

?? ??

??

?

V+ I1 I2

G=

1

A 1+A A(o)

R1

C1 A1 VOUT

A( ) =

(

1+

S
1

)(

1+

S
2

( ) (
0

1+ 1+
2.

S
1'

S
0

) )

For simplicity assume A(o)

>>

–In

Q1

Q2

+In

A( ) =

A(o)

(

1+

S
1

( ) ( (

1+ 1+

S
1'

S
0

) )
S
1'

If

1

1' :

V– G= 1 A 1+A A(o) S S 1+ 1+
1

G=

1

A 1+A

1+

S
1'

( )(

1+ 1+

)
0

S (1 + A )

)
0t

A( ) =

(

)(

1

(1 + S') ) (1 + S )
1 0

Step Response: eOUT eIN (t) = 1 A 1+A

[

1–

1'


1

1

e–

1t

– e–(1 + A

]

2-Pole Amplifier

Pole-Zero Network

FIGURE 15. Pole-Zero Transient Response. ??? ??? FIGURE 13. Pole-Zero Compensation in Op Amp.

1

>

1'

A

A

1

<

1'

A

A

0

1

2

0

1

2

???

????

?

“Tail”
1'


1

1

e–

1t

?

?

(

1–e

–(1 + A

0t

)

eOUT eIN

(t) =

1

A 1+A

[

1 – e–(1 + A

0t



1'


1

1

e–

1t

]

? ??

????

???

?

?? ? ?

?? ??? ??? ?? ???

?? ????

??

??

???

V+ R1 R2

Q4 VBIAS

Q5

Q6

Q10 R8

–In

Q1

R3

R4

Q2

+In Q7 R9 Q11

VOUT

Q3

VBIAS

Q8 VBIAS

Q9

CCOMP

R5

R6

R7

V–

FIGURE 17. Folded Cascode.

?

V+

R6 R11 R3 R4 R5 R10 R9 Q16 R1 R2 Q5 VBIAS Q3 Q4 Q7 Q8 Q6 R7 R8 Q13 Q 14 Q9 Q11 Q 12 Q10 I5 Q15 Logic Out

+In

Q1

Q2

–In

To V+

I1

I2

I3

I6

I4 V–

FIGURE 18. High Speed Comparator.
V+

R1 Q3 Q4

R2

Offset 0.4mV

???

VBIAS

20?s Q1 Q2 VIN 0

–1 1mA t

?? ?????

V– At t < 0 At t > 0 Power in Q1 = 2mW Power in Q2 = 0 Power in Q1 = Q2 = 1mW

???? ?????

Due to thermal time constant, temp. of Q1 and Q2 doesn’t change quickly. TempQ2 = VBE =
JA

X P = 100°C/W X 0.001W = 0.1°C X T = 2mV/°C X 0.1°C = 0.1mV

dVBE dT

FIGURE 19. Thermal Offset.

?

CS

Rg A1 VIN A2 A3 A4 VOUT

G = G 1 X G2 X G3 X G4 = 7 X 7 X 7 X 35 = 12,000

82dB

B /STAGE = 225MHz 82dB ?SHIFT = 4 X 45°C = 180°C

70dB GT

Open Loop Gain = Loop – Gain

Insertion Gain 1 2 Rg f CS

70dB – 20 log 100MHz 70dB – 20 log 0° f 225MHz 70dB – 27dB = 43dB When

1 2 (300)(225 X 106) X (0.1 X 10–12)

= 0°, oscillation occurs.

96° 180°

f (Hz)

???
V+ VL RL VO VIN A1 A2 A3 Q1 Q2

??

??

7

7 RL re RL 0.026 I

7 VL 0.026 V– I

Gain* =

=

=

* 3rd Stage

Since the gain is proportional to I, a 43dB gain reduction occurs when: I @ Balance = 141 I @ Unbalance I @ Balance VBE = 26 ln = 129mV I @ Unbalance Overdrive for 43dB gain reduction:

??

?? ? ? ? ??

???? ?? ?? ??

VOVERDRIVE =

VBE 73

=

129 73

= 375?V

FIGURE 21. Gain Reduction to Stop Comparator Oscillation.

?

??

?? ? ?

? ?

??

????

V+

R3

R1 VBIAS Q7 Q5 To Output Stage Q I1 +In Q1 Q3 Q4 Q6

R2 Q8

To Output Stage Q –In Q2 I2

Latch Enable (–)

Q9

Q10

Latch Enable (+)

I3

V–

???

??

???
e(t) = EFS sin 2 ft 2

?

EFS = Full Scale ADC Range d e(t) = f EFS dt d e(t) dt EFS cos 2 ft, d e(t) = f EFS dt

?? ?? ??????? ??? ?????? ???

f=

??? ??? ?????? ??? ???????

Assume maximum allowable change during ADC conversion time. T = 1/2LSB and EFS = 2NLSB where N is the number of bit ADC. f= 1/2LSB T 2NLSB = 1 2(N + 1) T

As an example, let N = 12 and T = 1?s: fMAX = 1/2LSB T 2NLSB = 38.9Hz

With a sample/hold, the maximum frequency would be 500kHz.

??

??

???

?

???

??

??? ? ??? ???

eIN

??? ?

eOUT

V

eIN

T/H

eOUT

??? ??

fs

Fourier Transform of Output tfS T EO(f) = o Vej2 ft dt = V (ej2 ft) j2 f o V ej2 fT – 1 Vej fT (ej fT – e–j fT) = f 2j f 2j Vej fT sin f Magnitude fT T

?

????????

??? ???

???

=

= EO(f) EO(o)

sin = ej fT

fT = e j (f/fs) fT Phase

(

)

( )
sin f fs f fs

?? ?????? ?? ??????? ?? ????????? ?? ????????? ?? ????????? ?? ????????? ??? ??? ?????

???

?

??

0dB –3.9dB A(f)

Input Signal Track/Hold Output

fs/2

fs

Frequency

sin |A(f)| = f fs

f fs

Sampling Signal

???

? FIGURE 27. Track/Holds Wave Forms.

+5 VIN –5 A1 VOUT G VG VON On Sampling Signal 10V VOFF Off –7.5V Allowed Error = V IN X 0.01% = 10V X 0.01% = 1mV S D C A1 VO

S

D C A1 VO

???

?
G

CGD

10

VOFFSET –7.5 Track Track Hold CGD C + CGD

?? ?? ?? ?? ?? ?? ?? ?? ??

VGATE

VOFFSET =

X VGATE, if CGD = 0.5pF C = 0.009?F

VOFFSET =

0.5 X 10–12 0.009 X 10–6

X 17.5 = 1mV

??? ?? ??? ????? ????? ??? ?? ?? ????????????????????????????? ???

??? ??? ??? ?

??

VIN C1 A1 VOUT

+5V In

VG On

VG +10

+ 5V –

C1

A1

VO

VOFF = Off RON VIN C1 A1 VOUT –5V In – 5V + –7.5

15 X 0.5 X 10–12 0.009 X 10–6

= 0.83mV

C1

A1

VO

VG +10

VOFF = Small Signal Bandwidth = 1 2 RON C 1 2 (50) 0.009 X 10–6 I –7.5

5 X 0.5 X 10–12 0.009 X 10–6

= 0.28mV

=

= 354kHz

Vt = 2.5

?????? ?????????????
? ?????? ????????

(

???

???????

)
???

? ???

?????? ?????? ?? ????? ??

???

? ?
???

???

??????????????? ???????????? ????

??? ??????

??????????????????????????? ???

??????

????????

???? ??
???????? ?? ?? ??? ? ??????? ?????????????? ????????

??? ?? ??? ??? ???? ?? ??? ?? ????????????????????????????????????????????????? ? ? ? ?????????

??

CDS VFT C1 A1 VOUT Q3 –7.5V Logic Input Q1 Q2 Logic Threshold D1 D2 R1 R4 V– = 0.1 X 10–12 0.009 X 10–6 + 0.1 X 10–12 X 10 = 111?Vp-p Logic Noise = Noise X Density 50nV Hz X BW 300 X 106 = 0.87mV R2 R3 Q4 To T/H Gate Circuits

10V

VIN

VFEEDTHROUGH =

CDS C + CDS

X VIN

???

=

???

Threshold Variation Logic Input

Logic Output

Aperture Jitter =

Threshold Noise Logic Rate of Change 0.87mV = 2.2ps 0.4V/ns

?????????? ?????? ?? ????????? ?????????????? ???????? ?? ?? ????? ???? ?? ??? ???

=

????????????????????????????

???????????????????? ????? ????? ???? ?

???????? ?

?? ? ? ? ??????? ? ?????? ? ??????? ? ????? ??? ???????

??????????? ??????? ?

??

??????? ?? ??

?????

???

??? ?? ?? ????

???

????????????????? ????????????? ?? ???? ???
Input

??? ??????

?? ??? ??????

Sampling Signal

Jitter

Noise Output

???

Input Input to Sample/Hold

Input to Switch Driver

Sampling Signal

Aperture Jitter

Gate Signal

Aperture Delay Output Range of Outputs Due to Aperture Jitter

Aperture Induced Noise = Signal Rate of Change ? Aperture Time = E FS ? ? f ? ta = 4096 ? ? 10 X 106 ? 2.2 X 10–12 = 0.28LSB For f = 10MHz EFS = 212 ? ta = 2.2ps

???

???

??

+5 VIN –5 +15V Q3 C1 A1 VO

Track/Hold Signal In
1 6

R1 Q1 7417 6.8V

VBIAS

Q2

V–

?? ????
ID IG C VGATE ID + IG A1 VO

VIN

?? ???? ?????????????????? ?????? ?? ?

????????????
S/H Output

????????????????????????? ???????????????????????????????????

Sample Pulse ID + IG I 50pA + 50pA = = = 0.011?V/?s C 0.009?F C

Droop Rate =

????????????????????????????????????????

??? ??? ??

????? ???

??? ??

???

???????????????? ??? ? ?????????????????????????

??

??

?????? ?? ??? ??? ????????? ??? ????? ????? ????? ???????????????? ?????

???

??

V=

1 C

I dt =

1 It C

V I = t C IDSS VIN I IDSS VO

VDS

VGATE

???

V2
VOUT = 5 sin 2 ft

V1

Linear Settling Slew Time IDSS C
–3

Slew Rate =

dVOUT dt Max

= 5.2 f cos 2 ft Max = 89.1kHz

Slew Rate =

=

25 X 10

0.009 X 10–6

= 2.8V/?s
f =

Linear Response V1 = V2 1 – e –t/RONC

Slew Rate 2.8V/?s = (5) (2 ) 10

(

)

V2 e–t/RONC de = dt RON C

When de/dt = Slew Rate, response follows exponential: IDSS C = V2 RON C V2 = IDSS RON = 25 X 10–3 X 50 = 1.25V

???

??? 40. Acquisition Time. FIGURE ?? ????????????? ????????? ? ??? ???? ??

Slew Time = Linear:

(10 – 1.25) = 3.1?s 2.8V/?s

–6 1.249 = 1.25 1 – e–t/(50)(0.009 X 10 )

(

)

?????????????? ??????? ????? ???? ???

t = (50) (0.009 ? 10–6) ln

1.25 0.001

= 3.2?s

Acquisition Time = Slew Time + Linear = 3.1 + 3.2 = 6.3?s

FIGURE 41. Acquisition Time. ???

????

??

?????
VIN Q1 S D C1 C2 A1 VOUT

?? ?? ????? ???
S

??

Q2 D

??

??

?? ??? ????

Track/Hold Signal

? ???????? ?

???? ?

?

???? ? ? ???? ?

?

???

?

??????????????????????????????????????

????? ???? ???? ????? ????? ?? ?? ???? ??? ???? ??? ?????

????

VIN RS

Q1 A1 C1 C1SS CRSS1 C2 VOUT

Q2 CRSS2

VGATE CRSS C

VOUT = VG

= 17.5

( ( )
0.5 450

CRSS CRSS

+

C C

)

(0.05 + 0.05) = 1.9mV

FIGURE 44. Capacitance Mismatch.

??

VIN

Q1 A1 C1 C2 VOUT

Q2

??? ?? ????? ?????
VG

VIN

?? ???
VC 300ns

VOUT 424ns

??

?? ????? ??????? ??????? ????? ?????

????? ??? ?????

FIGURE 45. Difference in Acquisition Time Between Buffer and Hold Cap.

??? ???

?????

?? ????? ??? ???

?? ??? ?? ????? ???? ??? ???

????? ?? ???

???

???? ?????

??? ??? ????

??? ???? ????????????

????

??

R1

C1

R VIN Q1 VOUT R/2

Q2

C

Sampling Signal (a)

R

C

R VIN RON VO

t = (2RON + R)C (b)

???

?
Amplifier will slew until slew rate = E T

??? ????? ??

?????? ????

T = (2 RON + RF) C = (2 ? 50 + 300) 60pF = 24ns E = T ? Slew Rate = 24 ? 10–9 ? 200V 10–6 = 4.8V

Acquisition Time = =

Input – E E + T ln Slew Rate Error 10 – 4.8 200V/?s + 24ns ln 4V 0.001V

???????????????????????????? ?????? ???? ?????? ?? ??? ?? ?? ??? ?????? ????? ?? ?? ???? ?? ???? ??

= 26ns + 203ns = 229ns Feedthrough Capacitance Feedthrough = 0.6Vp-p ? 0.1pF = 1mVp-p 60pF Feedback Capacitance

????

Input Clamped by Diode

?? ?

?

??

V+

I

Q1

Q2 R1

CR1 VIN Buffer CR3

CR2

High Speed Op Amp A1 VOUT

CR4

C

R2 Q3 Q4

I

V–

???

???

?? ?

??? ??? ?? ? ??? ??? ?? ?? ?? ? ?

??

??? ???

??? ?? ??? ? ??? ?? ???? ??? ?? ?? ???? ??? ?? ???

??

??

???
V+ VG

??? ???? ? ???

I1

??

CD1

???? ??????????????????????????????
VOFF C1

VIN

CD2 I2

VG V–

???

VOFF = VG X

(CD1 – CD2) C

=

2(0.025) 40

= 1.3mV

??

???

V+ VG1 I1 VG2

Q1

Q2 VG1

T

?? ???? ??????????? ???????? ????????
VG2 VIN C1 VOFF

??

??

?????? ?? ????

Q3

Q4

???? ????????????????????? ???
V–

I2

VOFF = =

I?T C 5

? 10–3 ? 50 ? 10–12 40 ? 10–12

???

= 6.3mV

???

??

R C1 VC1 VC2 R VOUT R/2 C2 Track to Hold Settling VOUT = Ve–t/RC

VIN VOUT C3 VOUT = V (1 – e–t/RC)

Track to Hold Settling

???

5mA R1 200

?????? ?? ???????????? ??????????? ???????????? ?????
VIN

CC VOUT

C1

R2

??? ???

???
VFEEDTHROUGH =

200 2(0.01) = 0.5mV 40

??? ??? ??? ?????????? ????????? ?? ? ????????? ???

??

?? ????? ?? ?? ??????

????? ?????

?? ?? ??? ??? ?? ???
Amplifier will slew until slew rate = 1 2 B 1 = 1.99ns 2 80 X 106 E T

???? ???? ????? ???

???

?? ???? ???

T=

=

??? ??? ?? ??? ??? ???? ?? ????? ??? ??? ??? ?? ??? ????? ???

E = T ? Slew Rate = 1.99 X 10–9 ? 300V/?s = 0.6V

Acquisition Time =

Input – E Slew Rate 2 – 0.6 300V/?s

+ T ln

E Error 0.6 0.0002

=

+ 1.99ns ln

= 4.7ns + 15.9ns = 20.6ns Slew Rate (VPEAK)(2 ) 300V/?s (1)(2 ) = 47.7MHz

Full Power Bandwidth =

=

???

?

Track/Hold T/H Gate

VOUT

VIN

VOFFSET

T/H Gate

Delay Line VIN Comparator

VOUT

???

??

IOUT

IOUT

Bit 1 Q1 Q2

Bit 2 Q3 Q4

Bit 3 Q5 Q6

Bit 4 Q7 Q8

Bit 11

Bit 12

VLOGIC REF 10mA 5mA 2.5mA 1.25mA 9.8?A 4.9?A VBIAS

R1

R2

R3

R4

???

?? ?? ?? ?? ??? ??? ?? ?? ???? ??? ??? ????? ??? ?? ? ?? ???? ?? ?? ?? ??? ??? ??? ?? ?? ?? ?? ?? ?? ?? ??

??

??

???

??

??

V+

DAC Out 2R IREF R R 2R R R 2R R R

Q1 Bit 1 Bit 2 Bit 3 Bit 11 Bit 12 Logic Ref

RC

RC

RC

RC

RC

RC

???

???

V+

IOUT I1 = IREF I2 = Q1 Bit Input VBIAS I1 Q2 + VBE1 – R1 I2 Q3 + VBE2 – R2 I3 I4 I4 = VBIAS Q4 Q5 +1 IREF
2

IREF

( )
+1

IREF

VBE1 + I2R1 = VBE2 + I 3R2 If VBE1 = VBE2 and R1 = R2, I2 = I3

IOUT = IOUT =

( ) ( ) ( ) ( ) ( ) ( ) ( )
+1 I3
2

2

+1

I4 = I2 =

+1

I3 = ?

+1

I2 IREF

2

2

+1

2

+1

+1

IOUT = IREF V–

?? ????

??

I1

I2 Input Output

Q1 CTE

Q2 CTE COB I Set Properly

CSUB Q3

I3

I Set Too Low

Circuit Fragment

I=C

V 1V = 1pF = 1mA T ns

??????

???

??? ?? ?????????? ?? ?? ?? ?? ??? ?? ????? ??? ?? ??? ? ? ????? ????????????????

??

???

?????? ??? ??? ? ????? ? ?? ?????? ? ? ?? ???? ? ?

?

?? ?? ??? ? ?????? ?? ??? ??? ???? ?????

??

V1 –0.8 –1.7 6.8 –7.6 –8.5 I1

V0 VREF –1.3V Logic Reference

6.8V Q1 –8.8V Q2

–8.1V

1k –10V Q3 –10.7V

I2

VBIAS R 1.25mA

5mA Transistor

1.25mA Transistor

–13.5V 13.5 – 10.7 R= = 2.24k 1.25mA

??? ??????
VBIAS2

VBIAS1

Q7

Q3 Q4 7.5V R1

Q5 Q6 DAC Out R4 1.25k 250 125 125 125 125

Q1 Bit 1 5mA Bit 2 2.5mA Bit 3 1.25mA Bit 4 1.25mA Bit N VBIAS3 Q2 1.25mA

R2

R3

–15V

???

???

??

??? ??? ???? ??? ????? ?? ?? ?? ?????
V+ VO IREF

I

? ????? ???

?? ?? ??

?? ?? ????

VBIAS Q1 Q4

?????? ?? ??????
R1

Q2 Q3

R2

?????? ???? ?????? ???? ???? ???? ???? ? ?????? ????? ?? ??? ???
DAC Error = R R + VRE IR

V– + 2 ? B B

= 0.5ppm/°C + 0.36ppm/°C + 0.47ppm/°C = 1.33ppm/°C

FIGURE 62. Trimmable DAC Errors. ?????? ??? ??? ????? ??? ??????? ??? ??? ?? ? ? ?? ?????????????? ??????? ?? ???????? ???? ? ? ?? ????? ???? ??????????????????????????? ???????????????????? ??????????? ??? ?? ??????? ??? ??? ?? ? ??? ??? ????

???

???????

??????? ? ? ????????????????? ???????????????????????

???? ???

???

?????? ??????

???

???? ???

??

??

??
V+ RL = 250 VO ROUT V1 Q1 Q2 V2 ROUT = I VBIAS R1 Q2 On ROUT = Q2 Off VA 200 = 150 = 3M I 10mA

???

??? ???? ???? ???? ???? ??? ??? ???? ????? ????? ???? ????? ??? ?? ? ????

V–

FIGURE 63. Error Due to ROUT.

???

???? ?? ???

??? ??? ???

??? ????? ?? ????

Improper Connection

R

I = I 1 + I2 + I3 + I4 + … + I12 Resistance in Ground Line

Proper Connection

VOUT R

2R R

2R R

2R

R

I1

I2

I3

I4

I12

VMSB = R(I/2) + RI VMSB – 1 = R

Offset for Single Current Source – I 2048

( 2I

) + R (11) I

Offset for Multiple Current Source

???

??

V+ Q3 Q4 VBIAS Q5 Q6 RL R4 R1 0.01 CL

VREF Bias Q1 CL Digital Delay Q2 0.01 R2 R3

V– Settling Time = Digital Delay + Ladder Response = 3ns + RL CL ln = 26ns 1 ( 0.01% ) = 3ns + (250 )(10pF) ln (+0.01%)

??? ????? ?????? ???? ??? ?????? ?? ??? ??? ????? ?????????????? ??? ?????? ?????? ? ?? ??? ?????? ??? ????? ?????

??? ??? ?? ??? ????

??? ??????????????? ???

????????????????

???????????????

?? ?????? ???? ??????? ??? ??? ??? ??? ???? ??? ??? ??? ??? ??? ???

??

Data Skew DAC Out

??? ???
Digital Input

??

Data Skew

??? ???

??

??? ?? ?????

??

0111 1111 1111 Before Change

1111 1111 1111 During Glitch

1000 0000 0000 After Change

?????? FIGURE 66. Skew. ???
VP Data Skew VP i (t) C1 R1 VOUT

?????? ??

???
eO (t) T

eO (t) =

VP R VP T RC

T C

t–(T/RC) = (VP T) ? 2 fO e –2

fO t

Clock ? RC (1 – e–(T/RC)) = VP T o Counter ROM DAC

eO (t) dt = o

Track Hold

Filter

?? ?
Glitch

??? ?? ??? ??? ????? ????? ???????

DAC Output

Track/Hold Command

Hold Track

????? ??

Register

DAC

Track Hold T/H Signal

Deglitched Output at Track/Hold Output

Clock

???

???

??

Word M – 1 Word M Word M + 1 Word 4 Word 3 Word 2 Word 1

???
1234 Clock M–1 M M+1

FIGURE 70. Arbitrary Waveform. ? ?? ??? ??? ??? ?? ?? ?????? ???? ????? ?????? ??

???

???

R1 –Ref

R2

R3

Analog Input R(2M – 2)

R(2M – 1)

R(2M) +Ref

1 Clock

2

Comparator Stages

2M – 2

2M – 1

Linear to Binary Encoder

Output Stages (Output Register)

B1

BN – 1

BN

FIGURE 71. Block Diagram of a Flash Encoder.

??

?? ?? ??? ??? ??? ???? ?????? ???? ????

??

???

???? ????? ????

Ref

Analog Q3 VOFF ?2 CM VIN Q1 A1 ?1 CM + 1 Q2 CMOS Comparator VOFF VOFF Digital Out

R

R

VOFF

R

?2

Comparator Reference = VLADDER ± VOFF

??

??

??

? ? ????

??????

R VIN Buffer

Flash Encoder

?? ??

??? ??

??? ??

?? ?? ?? ??? ??

???? ????????????????

?? ?????????????? ????? ???????? ???????? ????p? ???? ????? ??????? ????? ????? ??????
Analog Input Flash ADC

+VREF

???
Strobe Input R R

Flash ADC

??? ? ?? ? ?? ?? ? ? ?

??

??

??

???? ???

????

??

??? ???? ??? ???? ??? ????

Convert Command

????

????

Clock

Shift Register

Latches Digital Output

Comparator

Digital Analog Converter Analog Input

??? ? ??? ? ??? ?? ? ?? ? ? ?? ??? ???

???

?

? ????? ????

??

?

???

???

?? ?? ??? ????? ???? ???? ???

??? ?????

??? ???? ???

??

???
VIN = 2.120V

??? ???

DAC

Comparator

VO

????
Logic DAC Full Scale = 4.096V COMPARATOR INPUT 0.072 –0.952 –0.440 –0.184 –0.056 +0.008 –0.024 –0.008 +0.000 –0.004 –0.002 –0.001 DIGITAL OUTPUT 1 0 0 0 0 1 0 0 1 0 0 0

TRIAL 1 2 3 4 5 6 7 8 9 10 11 12 Analog In Digital Out

DAC 2.048 + 2.048 + 2.048 + 2.048 + 2.048 + 2.112 + 2.112 + 2.112 + 2.120 + 2.120 + 2.120 + 2.048 1.024 0.512 0.256 0.128 0.064 0.032 0.016 0.008 0.004 0.002 0.001

???

VIN = 2.120V 1000 0100 1000

?? ?
Start

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12

DAC

Comparator

???

??

Analog DAC Comparator

??? ??? ???

1% Analog Input

0.1%

0.01% Error

DAC Output

Comparator Output

??? ??? ??? ?? ??? ??? ?? ??? ??? ??? ?? ???

Input

R1 2.5 DAC

Comparator VO

2.0 Sub-Ranging 1.5 DAC 1.0 Successive Approximation 0.5 VO

Comparator

Input

0.8

1.0

1.2

1.4

1.6

1.8

???????????

Conversion Time (?s)

???

??

eIN

Sample and Hold

MSB Flash Encoder M Bits

Amp DAC

LSB Flash Encoder L Bits

Digital Error Corrector (Adder)

Digital Output

???

???

???

?????

??

?? ? ?? ?? ??? ??? ???? ?? ??? ?? ??? ??? ?? ?? ? ?? ??? ?? ?? ??? ??? ??? ? ??? ??????? ?? ???

Amp From S/H e IN MSB Flash Encoder DAC eIN + em (Analog) eIN + em (Digital) System Input MSB Flash Out Input to LSB Flash eIN eIN + em, em = MSB Flash Error eIN – (eIN + em) = – em eIN + em + (– em + ed ) = eIN – ed
+

LSB Flash Encoder

Digital Error Corrector (Adder)

Digital Output

Output from LSB Flash – em + ed, ed = LSB Flash Error Digital Output

FIGURE 83. Error Correction.

??

Integrator Comparator Device Under Test Strobe R1 C1 A1

???

Test Signal Generator

Digitally Programmable Delay

DVM

??
Computer

?? FIGURE 84. Waveform Digitizer.

??

???

? ?

???

??? ?? ?? ?????

Input

dV dT

Delay Line

Device Under Test Strobe

En

Oscilloscope

Aperture Jitter = Original Waveform

En dV dT

Sampled Waveform

???

???

??

?? ?? ??????????????

Analog Input ADC f 2 Oscilloscope Sampling Signal ÷2 f+ f Register DAC

?? ?????????

FIGURE 87. Block Diagram of Beat Frequency Testor. ??? ??
fS

???????

?? ??? ??????? ???

???

f

Resampling Signal (fS + f)

??? FIGURE 88. Beat Frequency Waveforms.

C1

?????????? ???

??????
Analog In

ADC Under Test

Digital Comparator

R1 A1

?? ??

?? ???

Computer

DVM

??? ??? ??? ??? ?

???

???

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

??

???? ???? ????? ??

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? ? ? ?

???? ??????

??? ??? ??????????????? ?? ?? ???????

????? ??

????? ? ??????????????????????????????? ??????????????

?????????????????????

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? ? ? ? ? ? ? ? ? ? ? ? ?

??????

????????????????????????????? ???????????????????????????? ???????????????????????????? ??????

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?

??????????????????????????

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? ?

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? ? ? ? ?

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? ? ? ?

???????

???? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??

?? ?? ?? ?? ??? ?? ??

??????????????????????????????? ??????????????????????????????????? ??? ???????????????????????? ?????????????????????????????? ?????????????????????????? ?????????????????????????? ????????????????????????????????????? ?????????????????????????? ??????????????????????????????? ?????????????????????????????? ???????????????????????????? ??????????????????????????????????? ????????????????????????????? ???????????????????????????? ?????????????????????????? ????????????????????????????? ????? ???????????? ???? ?????? ??? ??????? ??????? ????? ????? ????????? ? ????? ????? ??????????? ????????????


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