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Tri-mode


10_100_1000 Mbps Tri-mode Ethernet MAC Specification
Author: Jon Gao gaojon@yahoo.com

Rev. 0.1 January 25, 2006

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Revision History
Rev. 0.1 Date 11/28/0 5 Author Jon Gao Description First Draft

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Contents
INTRODUCTION......................................................................................................... 1
BLOCK DIAGRAM .......................................................................................................... 3 CLOCK DISTRIBUTION ................................................................................................... 4

OPERATION ................................................................................................................ 5 CONFIG OPTAIONAL MODULES ...................................................................................... 5 VERIFICATION .............................................................................................................. 5 REG DESCRIPTION ................................................................................................. 10 REGISTER LIST .......................................................................................................... 10 W ATER MARK ............................................................................................................ 11 FLOW CONTROL......................................................................................................... 11 IFG ........................................................................................................................... 13 FULL DUPLEX............................................................................................................. 13 TARGET MAC ADDRESS............................................................................................ 13 BROADCAST_FILTER.................................................................................................. 14 RX_APPEND_CRC.................................................................................................. 14 CRC_CHK_EN............................................................................................................ 15 PACKET LENGTH RESTRICT ......................................................................................... 15 STATISTIC COUNTERS(NEED ADD ONE ADDRESS FOR 32BIT WIDTH DOUT) ..................... 15 CLOCKS ..................................................................................................................... 18 IO PORTS ................................................................................................................... 19 PHY INTERFACE ....................................................................................................... 19 Gigabit Media Independent Interface (GMII/MII) ............................................. 19 USER INTERFACE ........................................................................................................ 21 HOST INTERFACE........................................................................................................ 22 APPENDIX A.............................................................................................................. 23 INDEX.......................................................................................................................... 24

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1
Introduction
10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. functional description: Implements the full 802.3 specification. half-duplex support for 10 100 Mbps mode FIFO interface to user application support pause frame generation and termination transmitting frames source MAC address insertion(optional) receiving frames destination MAC address filter(optional) receiving broadcast frames throughout constraint(optional) support Jumbo frame 9.6K RMON MIB statistic counter Before you start to use this IP core, you need to make your working enviroment ready. At fist, you need to install WIN2K operation system(recommend) or other stable operation system.In addtion, Cygwin is needed to run some bash scripts.Tcl/tk is also needed for many GUI scripts. Finally, the cadence LDV nc-sim is needed for simualtion. If you are using

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worksation, you need Tcl/tk of your platform for GUI scripts and LDV nc-sim. I recommend WIN2K + Cygwin0528 + LDV5.0 +Tcl/tk.

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Architecture
block diagram
CRC_g en MAC_tx_add r_add Ramdon _gen

MAC_tx_f ifo

MAC_tx_ctrl

GMII

Flow_ctrl

MII

MAC_rx_f ifo

MAC_rx_ctrl

MUX

Host

REG_int

MAC_rx_addr_ filter

CRC_ch eck

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clock distribution
FPGA MAC_rx_clk sw Rx_clk

div MAC_core

MAC_rx Tx_clk MAC_tx div Gtx_clk MAC_tx_clk sw 125 Mhz PHY GMII/MII

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Operation
Config optaional modules
There are three optional modules can be removed frome IP core to reduce area. You can start a GUI configuration tools to customize this IP core. Type the following command in root directory to run a tcl/tk script. #vish start.tcl if the tcl/tk was installed correctly, a GUI windows will appear on your screen. It's looks like that:

To click the checkbutton will enable the corresponding module of IP core.By the way, the Fifo depth can be set in this window.The default setting of Fifo depth is 9,which means that the fifo can contain 512 words. Because of the fifo width of user side is 32bit, the actual capacity of fifo is 512*4=2K bytes. After you changed the setting, don't forget to save the new configuration.

Verification
To click the "verify"button of above window, a new window will appear for verification.

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the first button "set_stimulus" is used to config the parameters used for automatically generate stimulus for simulation.

If you select "Random" mode , the generated packet length will be random in the range of "Packet begin length " and "Packet begin length". The generated packet number will be equal to "Total Gen Packet number".If you want to generate broadcast packets , just click the "broadcast" slectbutton. The "save" button will save current configuration to "config.ini" file.Furthermore, you can use "save as" button to save the configuration as another file which can be used for "batch_mode" "set_cpu_data" button of main window is used to config internal registers.All the registers will be list in following forms:

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the "save" button will save current configuration to file "CPU.dat".Also, you can use "save as" button to save register setting to any others files you like. Some complex operation of register such as reading statistic counters need to edit "CPU.dat" file manually.

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The "start_verify" of main window will start simulation. The compiling and simulation output will be printed in the following windows:

At first , a bash script will be invoked to compile the source file .If no any error occurred , the nc-simulator will be invoked to start simulation. When any error packet received , the simulator will stop and print the data of received error packet. The "batch_mode" button of main windwos will invoke following windows:

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this window will be used to perform verify the IP core with several testcase.In this window, you can change the description , stimulus and regvector of a testcase.

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Reg Description
Register list
Reg Name Tx_Hwmark Tx_Lwmark pause_frame_send_en pause_quanta_set IFGset FullDuplex MaxRetry MAC_tx_add_en MAC_tx_add_prom_data MAC_tx_add_prom_add MAC_tx_add_prom_wr tx_pause_en xoff_cpu xon_cpu MAC_rx_add_chk_en MAC_rx_add_prom_data MAC_rx_add_prom_add MAC_rx_add_prom_wr broadcast_filter_en broadcast_bucket_depth broadcast_bucket_interval RX_APPEND_CRC Rx_Hwmark Operaion R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w R/w Address 7'd000 7'd001 7'd002 7'd003 7'd004 7'd005 7'd006 7'd007 7'd008 7'd009 7'd010 7'd011 7'd012 7'd013 7'd014 7'd015 7'd016 7'd017 7'd018 7'd019 7'd020 7'd021 7'd022 Default Value 16'h001e 16'h0019 16'h0000 16'h0000 16'h0012 16'h0001 16'h0002 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h001a

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Rx_Lwmark CRC_chk_en RX_IFG_SET RX_MAX_LENGTH RX_MIN_LENGTH CPU_rd_addr CPU_rd_apply CPU_rd_grant CPU_rd_dout_l CPU_rd_dout_h Line_loop_en Speed

R/w R/w R/w R/w R/w R/w R/w R R R R/w R/w

7'd023 7'd024 7'd025 7'd026 7'd027 7'd028 7'd029 7'd030 7'd031 7'd032 7'd033 7'd034

16'h0010 16'h0000 16'h0012 16'h2710 16'h0040 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000 16'h0004

Water mark
Tx_Hwmark Tx_Lwmark R/w R/w 7'd000 7'd001 16'h001e 16'h0019

This two registers are used to set transmit Fifo high water mark and low water hark.When the packet data stored in transmit Fifo meet low water,transmit control logic will begin to read packet data from Fifo and send it to Phy through GMII/MII interface. In addition,hight water mark and low water mark setting is correlated with Tx_mac_wr signal. When the transmit Fifo meet high water mark , Tx_mac_wr will be asserted 0 to tell user application to hold packet transmitting. When the transmit Fifo under low water mark, the Tx_mac_wr signal will be disasserted and the user application can proceed to transmit packet data. Rx_Hwmark Rx_Lwmark R/w R/w 7'd022 7'd023 16'h001a 16'h0010

This two registers are used to set receive Fifo water mark. When Fifo received one full packet or stored packet data meet hight water mark,the Rx_mac_ra will be asserted.The Rx_mac_ra will be disasserted while Fifo below low water mark. If there is one full packet received from PHY, The Rx_mac_ra will disasserted when the whole packet is read out from Fifo.

Flow control
pause_frame_send_en R/w 7'd002 16'h0000

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pause_quanta_set xoff_cpu xon_cpu

R/w R/w R/w

7'd003 7'd012 7'd013

16'h0000 16'h0000 16'h0000

pause_frame_send_en register is used to enable transmit logic to send PAUSE frame. pause_quanta_set register is used to setting quanta value in send PAUSE frame. The rising pulse of xon_cpu signal is used to start transmit one PAUSE frame with quanta value of pause_quanta_set when the transmit in idle state. The rising pulse of xoff_cpu signal is used to start transmit one PAUSE frame when the transmit in idle state with quanta zero, asking remote ethernet controller jump out from pause state.
Rising edge of xoff_gen/xon_gen

pause_frame_s end_en=1?

Yes

xon_gen

Wait transmit state idle

xoff_gen

Send Pause frame with quanta= pause_quanta_set

Send Pause frame with quanta= zero

No

End

tx_pause_en

R/w

7'd011

16'h0000

When this register is "1", this core will respond to received pause frame.The transmit state machine will enter PAUSE state according to quanta value in received packet . One quanta time is equal to the time of transmit 512bit data.

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IFG
IFGset RX_IFG_SET R/w R/w 7'd004 7'd025 16'h0012 16'h0012

According to IEEE802.3 ,The minimum IfG value is 96bit. If the system clock is 125Mhz with 8bit data width, the interval time between packet is at least 18 clock cycles RX_IFG_SET is used to set received frame gap. If the gap between two received packets is less than RX_IFG_SET,the second packet will be drop as an invalid frame.

Full duplex
FullDuplex R/w 7'd005 16'h0001 This config register is only used in 100Mbps and 10Mbps. When FullDuplex register is equal to "1" , the transmit state machine will be FullDuplex mode.Otherwise,the transmit state machine will detect collision ,perform random slot time back off , retransmit collision packet and some other half-duplex operations. MaxRetry R/w 7'd006 16'h0002 When collision occurred in half duplex mode, the transmit state machine will try to transmit this collision packet again. If one packet collide MaxRetry times, this packet will be drop and never try again.

Target MAC address
MAC_tx_add_en MAC_tx_add_prom_data MAC_tx_add_prom_add MAC_tx_add_prom_wr R/w R/w R/w R/w 7'd007 7'd008 7'd009 7'd010 16'h0000 16'h0000 16'h0000 16'h0000

Those registers are used to set mac address which will replace the target mac address of transmit packet. This function will be enable one when register MAC_tx_add_en set to "1". At the rising edge of signal MAC_tx_add_prom_wr, the value of MAC_tx_add_prom_data will be write to prom address MAC_tx_add_prom_add . You need repeat six times to write six bytes length target mac to prom.

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Broadcast_filter
broadcast_filter_en broadcast_bucket_depth broadcast_bucket_interval "1".
Interval time

R/w R/w R/w

7'd018 7'd019 7'd020

16'h0000 16'h0000 16'h0000

The broadcast packet filter will enable only when broadcast_filter_en is set

The bucket wil be periodically refilled after broadcast_bucket_interval time. broadcast_bucket_depth register is used to setting the bucket depth. When a byte of broadcast packet is received, the bucket will decrease 1. If the bucket is empty, the received packet will be drop until the bucket is refilled next time. The radio of broadcast_bucket_depth to broadcast_bucket_interval will determine maximal broadcast packets throughput in on second. For example, if the radio is 0.1, the broadcast flow will be restricted to 10Mbps when MAC in 100Mbps mode. The broadcast_bucket_depth will determine the burst number of broadcast packets.

RX_APPEND_CRC
RX_APPEND_CRC R/w 7'd021 16'h0000 In some condition, the user application need MAC to retain FCS of ethernet frame. When RX_APPEND_CRC signal is equal "1" , the FCS of ethernet frame will transmit to user application.

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CRC_chk_en
CRC_chk_en R/w 7'd024 16'h0000 By default, the receive logic will drop any packet with FCS checksum error. By setting CRC_chk_en register to zero, you can disable received packet FCS checking.

Packet length restrict
RX_MAX_LENGTH RX_MIN_LENGTH R/w R/w 7'd026 7'd027 16'h2710 16'h0040

The length of Received packet beyond minimal length and maximal length will be droped in receive Fifo. if the packet is already trasmitting in user interface , a error flag will enclosed at end of packet .

Statistic counters
CPU_rd_addr CPU_rd_apply CPU_rd_grant CPU_rd_dout_l CPU_rd_dout_h R/w R/w R R R 7'd028 7'd029 7'd030 7'd031 7'd032 16'h0000 16'h0000 16'h0000 16'h0000 16'h0000

All statistic counters are stored in a blockram. When you read a counter,you need to write the corresponding address to CPU_rd_addr register and assert CPU_rd_apply signal. When the counter data register CPU_rd_dout is available , the signal CPU_rd_grant will be "1". CPU_rd_addr 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0a Statistic counter RxPacketLengthBytesCounter RxPacketCounter RxBroadcastCounter RxMulticastCounter RxUnicastCounter RxCRCErrCounter RxFifoFullErrCounter RxTooShortTooLongCounter RxPacketLength<64 RxPacketLength_64 RxPacketLength_64_127

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6'h0b 6'h0c 6'h0d 6'h0e 6'h0f 6'h10 CPU_rd_addr 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2a 6'h2b 6'h2c 6'h2d 6'h2e 6'h2f 5'h30

RxPacketLength_128_255 RxPacketLength_256_511 RxPacketLength_512_1023 RxPacketLength_1024_1517 RxPacketLength>1518 RxPuaseFrameCounter Statistic counter TxPacketLengthBytesCounter TxPacketCounter TxBroadcastCounter TxMulticastCounter TxUnicastCounter TxJamDropCounter TxFifoUnderflowCounter TxFifoOverflowCounter TxPacketLength<64 TxPacketLength_64 TxPacketLength_64_127 TxPacketLength_128_255 TxPacketLength_256_511 TxPacketLength_512_1023 TxPacketLength_1024_1517 TxPacketLength>1518 TxPuaseFrameCounter

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Write CPU_rd_addr

Write CPU_rd_apply=1

=0

CPU_rd_grant

=1

read CPU_rd_dout_l

read CPU_rd_dout_h

End

line side loopback
Line_loop_en R/w 7'd033 16'h0000 If Line_loop_en =1 , the packet transmited to Phy will loopback to receive side. This function is used for test purpose.

Speed level
Speed R/w 3'b100: 1000Mbps mode 3'b010: 100Mbps mode 3'b001: 10Mbps mode 7'd034 16'h0004 This register is used to set speed level of ethernet mac core.

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Clocks
This section specifies all the clocks. All clocks, clock domain passes and the clock relations should be described. Name Sourc e Input Pad Input Pad Input port Rates (MHz) Max Min Resolutio n 125 66 80 50 Remarks Description

Clk_125M Clk_user Clk_reg

For GMII interface User clock Host interface cock

Table 1: List of clocks

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5
IO Ports
PHY interface
Gigabit Media Independent Interface (GMII/MII) signal mapping
88E1111 Device Pins
GTX_CLK TX_CLK TX_ER TX_EN TXD[7:0] RX_CLK RX_ER RX_DV RXD[7:0] CRS COL

GMII
GTX_CLK TX_ER TX_EN TXD[7:0] RX_CLK RX_ER RX_DV RXD[7:0] CRS COL

MII
TX_CLK TX_ER TX_EN TXD[3:0] RX_CLK RX_ER RX_DV RXD[3:0] CRS COL

gmii signal diagram

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mii diagram

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user interface
output input output output output output output output input input input input input [31:0] [1:0] [31:0] [1:0] Rx_mac_ra Rx_mac_rd Rx_mac_data Rx_mac_BE Rx_mac_pa Rx_mac_sop Rx_mac_eop // Tx_mac_wa Tx_mac_wr Tx_mac_data Tx_mac_BE Tx_mac_sop Tx_mac_eop // //

Clk_user Tx_mac_w a Tx_mac_w r Tx_mac_sop Tx_mac_eop Tx_mac_data Tx_mac_BE

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Clk_user Rx_mac_ra Rx_mac_rd Rx_mac_pa Rx_mac_sop Rx_mac_eop Rx_mac_data Rx_mac_BE

Host interface
input input input output input [15:0] [15:0] [7:0] CSB WRB CD_in CD_out CA

clk_reg CD_in CD_out CA WRB CSB w rite read

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Appendix A
Name
This section may be added to outline different specifications.

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Index

This section contains an alphabetical list of helpful document entries with their corresponding page numbers.

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