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笙科A9108 Datasheet v0.5(Preliminary)


A9108
Sub1GHz FSK/GFSK Transceiver SOC Document Title
A9108 Data Sheet, sub1GHz Transceiver SOC

Revision History
Rev. No.
0.0 0.1 0.2 0.3 0.4 0.5

His

tory
Initial issue. Modified package information. Update pin definition and specifications Update register table, package, pin definition and specifications Update pin definition and specifications Update specifications and revise RSSI curve

Issue Date
May, 2012 March, 2013 June, 2013 Nov., 2013 July, 2014

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Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer.

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Objective Objective Objective Preliminary Preliminary Preliminary

A9108
Sub1GHz FSK/GFSK Transceiver SOC Table of Contents
1. General Description ....................................................................................................................................................... 6 2. Typical Applications ....................................................................................................................................................... 6 3. Feature ......................................................................................................................................................................... 6 4. Pin Configurations ......................................................................................................................................................... 7 5. Pin Description (I: input; O: output, I/O: input or output)................................................................................................... 8 6. Chip Block Diagram ....................................................................................................................................................... 9 7. Absolute Maximum Ratings...........................................................................................................................................10 8. Electrical Specification .................................................................................................................................................. 11 9. SFR & RFR(Radio Frequency Register) ........................................................................................................................14 9.1 SFR Overview ............................................................................................................................................................14 9.2 RFR Overview ............................................................................................................................................................15 9.2.0 RSTCTL (Address: 0x800h) .....................................................................................................................18 9.2.1 MODEC1 (Address: 0x801h) ....................................................................................................................19 9.2.2 MODEC2 (Address: 0x802h) ....................................................................................................................19 9.2.3 CALC (Address: 0x803h) .........................................................................................................................20 9.2.4 FIFO1 (Address: 0x804h).........................................................................................................................20 9.2.5 FIFO2 (Address: 0x805h).........................................................................................................................20 9.2.6 RCOSC1 (Address: 0x806h) ....................................................................................................................21 9.2.7 RCOSC2 (Address: 0x807h) ....................................................................................................................21 9.2.8 RCOSC3 (Address: 0x808h) ....................................................................................................................21 9.2.9 RCOSC4 (Address: 0x809h) ....................................................................................................................21 9.2.10 RCOSC5 (Address: 0x80Ah) ..................................................................................................................22 9.2.11 RCOSC6 (Address: 0x80Bh) ..................................................................................................................22 9.2.12 RCOSC7 (Address: 0x80Ch)..................................................................................................................22 9.2.13 RCOSC8 (Address: 0x80Dh)..................................................................................................................22 9.2.14 CKO (Address: 0x80Eh).........................................................................................................................22 9.2.15 GPIO1 (Address: 0x80Fh) ......................................................................................................................23 9.2.16 GPIO2 (Address: 0x810h) ......................................................................................................................23 9.2.17 CLOCK (Address: 0x811h) .....................................................................................................................24 9.2.18 PLL1 (Address: 0x812h) ........................................................................................................................25 9.2.19 PLL2 (Address: 0x813h) ........................................................................................................................25 9.2.20 PLL3 (Address: 0x814h) ........................................................................................................................25 9.2.21 PLL4 (Address: 0x815h) ........................................................................................................................25 9.2.22 PLL5 (Address: 0x816h) ........................................................................................................................26 9.2.23 PLL6 (Address: 0x817h) ........................................................................................................................26 9.2.24 PLL7 (Address: 0x818h) ........................................................................................................................26 9.2.25 CHG1 (Address: 0x819h) .......................................................................................................................26 9.2.26 CHG2 (Address: 0x81Ah).......................................................................................................................26 9.2.27 CHG3 (Address: 0x81Bh).......................................................................................................................26 9.2.28 TX1 (Address: 0x81Ch)..........................................................................................................................27 9.2.29 TX2 (Address: 0x81Dh)..........................................................................................................................27 9.2.30 DELAY1 (Address: 0x81Eh) ...................................................................................................................27 9.2.31 DELAY2 (Address: 0x81Fh) ...................................................................................................................27 9.2.32 RX (Address: 0x820h)............................................................................................................................28 9.2.33 ADCC (Address: 0x821h) .......................................................................................................................28 9.2.34 RXAGC1 (Address: 0x822h) ..................................................................................................................29 9.2.35 RXAGC2 (Address: 0x823h) ..................................................................................................................29 9.2.36 RSSI (Address: 0x824h) ........................................................................................................................29 9.2.37 AGCHT (Address: 0x825h).....................................................................................................................30 9.2.38 AGCLT (Address: 0x826h) .....................................................................................................................30 9.2.39 CODE1 (Address: 0x827h).....................................................................................................................30 9.2.40 CODE2 (Address: 0x828h).....................................................................................................................30 9.2.41 CODE3 (Address: 0x829h).....................................................................................................................31 9.2.42 IFC1 (Address: 0x82Ah).........................................................................................................................31 9.2.43 IFC2 (Address: 0x82Bh).........................................................................................................................31 9.2.44 VCOCC (Address: 0x82Ch)....................................................................................................................31 9.2.45 VCOBC1 (Address: 0x82Dh) ..................................................................................................................32 9.2.46 VCOBC2 (Address: 0x82Eh) ..................................................................................................................32

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Sub1GHz FSK/GFSK Transceiver SOC
9.2.47 PM (Address: 0x82Fh) ...........................................................................................................................33 9.2.48 RFI (Address: 0x830h) ...........................................................................................................................33 9.2.49 XTST (Address: 0x831h) ........................................................................................................................33 9.2.50 BD (Address: 0x832h)............................................................................................................................33 9.2.51 TXT1 (Address: 0x833h) ........................................................................................................................34 9.2.52 TXT2 (Address: 0x834h) ........................................................................................................................34 9.2.53 RXDEM1 (Address: 0x835h) ..................................................................................................................35 9.2.54 RXDEM2 (Address: 0x836h) ..................................................................................................................35 9.2.55 RXDEM3 (Address: 0x837h) ..................................................................................................................35 9.2.56 DRCK (Address: 0x838h) .......................................................................................................................35 9.2.57 RTC (Address: 0x839h) .........................................................................................................................36 9.2.58 ID0 (Address: 0x83Ah) ...........................................................................................................................36 9.2.59 ID1 (Address: 0x83Bh) ...........................................................................................................................36 9.2.60 ID2 (Address: 0x83Ch)...........................................................................................................................36 9.2.61 ID3 (Address: 0x83Dh)...........................................................................................................................36 9.2.62 ID4 (Address: 0x83Eh) ...........................................................................................................................36 9.2.63 ID5 (Address: 0x83Fh) ...........................................................................................................................37 9.2.64 ID6 (Address: 0x840h) ...........................................................................................................................37 9.2.65 ID7 (Address: 0x841h) ...........................................................................................................................37 9.2.66 DID0 (Address: 0x842h).........................................................................................................................37 9.2.67 DID1 (Address: x843h)...........................................................................................................................37 9.2.68 DID2 (Address: x844h)...........................................................................................................................37 9.2.69 DID3 (Address: x845h)...........................................................................................................................37 9.2.70 ADCCTL (Address: x858h) .....................................................................................................................38 9.2.71 ADCAVG1 (Address: x859h) ..................................................................................................................38 9.2.72 ADCAVG2 (Address: x85Ah) ..................................................................................................................38 9.2.73 ADCAVG3 (Address: x85Bh) ..................................................................................................................38 9.2.74 TMRINV (Address: 0x85Ch) ...................................................................................................................38 9.2.75 TMRCTL (Address: 0x85Dh) ..................................................................................................................39 9.2.76 EXT1 (Address: 0x85Eh)........................................................................................................................39 9.2.77 EXT2 (Address: 0x85Fh) ........................................................................................................................39 9.2.78 EXT3 (Address: 0x860h) ........................................................................................................................39 9.2.79 EXT4 (Address: 0x861h) ........................................................................................................................40 9.2.80 EXT5 (Address: 0x862h) ........................................................................................................................40 9.2.81 PWRCTL (Address: 0x863h) ..................................................................................................................40 9.2.82 INTSW (Address: 0x864h) .....................................................................................................................40 9.2.83 TX5DY (Address: 0x865h) ........................................................................................................................41 10.SOC Architectural Overview .........................................................................................................................................42 10.1 Pipeline 8051 CPU ...................................................................................................................................................42 10.2 Memory Organization................................................................................................................................................42 10.2.1 Program memory .....................................................................................................................................42 10.2.2 Data memory ...........................................................................................................................................43 10.2.3 General Purpose Registers.......................................................................................................................43 10.2.4 Bit Addressable Locations ........................................................................................................................43 10.2.5 Special Function Registers .......................................................................................................................43 10.2.6 Stack .......................................................................................................................................................43 10.2.7 Data Pointer Register ...............................................................................................................................43 10.2.8 RF Registers, RF FIFO.............................................................................................................................45 10.2.9 CODEC Registers ....................................................................................................................................45 10.3 Instruction set ...........................................................................................................................................................45 10.4 External interrupt handler ..........................................................................................................................................48 10.4.1 FUNCTIONALITY.....................................................................................................................................48 10.5 Reset Circuit ............................................................................................................................................................51 10.6 Clock source ............................................................................................................................................................53 11. I/O Ports .....................................................................................................................................................................53 11.2 FUNCTIONALITY .....................................................................................................................................................54 12 Timer 0 & 1 &2 ............................................................................................................................................................57 12.1 Timer 0 & 1 PINS DESCRIPTION..............................................................................................................................57 12.2 Timer 0 & 1 FUNCTIONALITY...................................................................................................................................57 12.2.1 OVERVIEW .............................................................................................................................................57 12.2.2 Timer 0 & 1 Registers ...............................................................................................................................57

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Sub1GHz FSK/GFSK Transceiver SOC
12.2.3 Timer 0 – Mode 0 .....................................................................................................................................58 12.2.4 Timer 0 – Mode 1 .....................................................................................................................................59 12.2.5 Timer 0 – Mode 2 .....................................................................................................................................59 12.2.6 Timer 0 – Mode 3 .....................................................................................................................................60 12.2.7 Timer 1 – Mode 0 .....................................................................................................................................60 12.2.8 Timer 1 – Mode 1 .....................................................................................................................................60 12.2.9 Timer 1 – Mode 2 .....................................................................................................................................61 12.2.10 Timer 1 – Mode 3 ...................................................................................................................................61 12.3 Timer2 PINS DESCRIPTION.....................................................................................................................................61 12.4 Timer2 FUNCTIONALITY..........................................................................................................................................61 12.4.1 OVERVIEW .............................................................................................................................................61 12.4.2 Timer 2 Registers .....................................................................................................................................62 13. UART 0,1 ...................................................................................................................................................................65 13.1 UART0 PINS DESCRIPTION ....................................................................................................................................65 13.2 FUNCTIONALITY .....................................................................................................................................................65 13.3 OPERATING MODES ...............................................................................................................................................67 13.3.1 UART0 MODE 0, SYNCHRONOUS ..........................................................................................................67 13.3.2 UART0 MODE 1, 8-BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE ...................................67 13.3.3 UART0 MODE 2, 9‐BIT UART, FIXED BAUD RATE ..................................................................................67 13.3.4 UART0 MODE 3, 9‐BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE ...................................67 14. IIC interface................................................................................................................................................................69 14.1 Master mode I2C.......................................................................................................................................................69 14.1.1 I2C REGISTERS ......................................................................................................................................69 14.2.4 I2C MASTER MODULE AVAILABLE SPEED MODES ...............................................................................72 14.2.5 I2C MASTER MODULE AVAILABLE COMMAND SEQUENCES ................................................................73 14.3 I2C MASTER MODULE INTERRUPT GENERATION.................................................................................................80 2 14.5 Slave mode I C.........................................................................................................................................................80 14.5.1 I2C MODULE INTERNAL REGISTERS.....................................................................................................80 14.7 AVAILABLE I2C MODULE TRANSMISSION MODES ................................................................................................82 2 14.7.1 I C module SINGLE RECEIVE..................................................................................................................82 14.7.2 I2C module SINGLE SEND .......................................................................................................................82 2 14.7.3 I C module BURST RECEIVE...................................................................................................................82 14.7.4 I2C module BURST SEND ........................................................................................................................83 2 14.7.5 AVAILABLE I C module COMMAND SEQUENCES FLOWCHART ............................................................84 14.8 I2C MODULE INTERRUPT GENERATION ................................................................................................................84 15. SPI interface...............................................................................................................................................................86 15.1 KEY FEATURES.......................................................................................................................................................86 15.2 SPI PINS DESCRIPTION..........................................................................................................................................87 15.3 SPI HARDWARE DESCRIPTION..............................................................................................................................87 15.3.1 BLOCK DIAGRAM ...................................................................................................................................87 15.3.2 INTERNAL REGISTERS ..........................................................................................................................88 15.4 MASTER OPERATIONS ...........................................................................................................................................89 15.4.1 MASTER MODE ERRORS.......................................................................................................................90 15.5 SLAVE OPERATIONS ..............................................................................................................................................91 15.5.1 SLAVE MODE ERRORS ..........................................................................................................................91 15.6 CLOCK CONTROL LOGIC .......................................................................................................................................92 15.6.1 SPI CLOCK PHASE AND POLARITY CONTROLS ...................................................................................92 15.6.2 SPI MODULE TRANSFER FORMATS ......................................................................................................92 15.6.3 CPHA EQUALS ZERO TRANSFER FORMAT ...........................................................................................92 15.6.4 CPHA EQUALS ONE TRANSFER FORMAT .............................................................................................93 15.7 SPI DATA TRANSFER ..............................................................................................................................................93 15.7.1 TRANSFER BEGINNING PERIOD ( INITIATION DELAY ) .........................................................................93 15.7.2 TRANSFER ENDING PERIOD .................................................................................................................93 15.8 TIMING DIAGRAMS .................................................................................................................................................93 15.8.1 MASTER TRANSMISSION.......................................................................................................................93 15.8.2 SLAVE TRANSMISSION ..........................................................................................................................94 15.9 SPI MODULE INTERRUPT GENERATION................................................................................................................94 16. PWM..........................................................................................................................................................................96 16.1 PWM FUNCTIONALITY ............................................................................................................................................96 16.1.1 PWM Registers ........................................................................................................................................96 17. ADC (Analog to Digital Converter) ...............................................................................................................................98

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Sub1GHz FSK/GFSK Transceiver SOC
9.2.2 MODEC2 (Address: 0x802h) ....................................................................................................................98 9.2.32 RX (Address: 0x820h)............................................................................................................................98 9.2.33 ADCC (Address: 0x821h) .......................................................................................................................98 9.2.36 RSSI (Address: 0x824h) ........................................................................................................................98 17.1 RSSI Measurement ..................................................................................................................................................98 17.1 Temperature Measurement .......................................................................................................................................98 17.2 RSSI Measurement ..................................................................................................................................................99 17.2 Carrier Detect ...........................................................................................................................................................99 17.3 Battery Detect...........................................................................................................................................................99 9.2.50 BD (Address: 0x832h).......................................................................................................................... 100 18. Power Management.................................................................................................................................................. 101 19. A9108 RF ................................................................................................................................................................. 103 19.1 Strobe Command ...................................................................................................................................... 103 19.1.1 Strobe Command - Sleep Mode .............................................................................................................. 103 19.1.2 Strobe Command - Idle Mode ................................................................................................................. 103 19.1.3 Strobe Command - Standby Mode .......................................................................................................... 103 19.1.4 Strobe Command - PLL Mode................................................................................................................. 103 19.1.5 Strobe Command - RX Mode .................................................................................................................. 103 19.1.6 Strobe Command - TX Mode .................................................................................................................. 103 19.2 RF Reset Command ............................................................................................................................................... 103 19.3 FIFO Accessing Command ..................................................................................................................................... 103 20. Flash memory controller ........................................................................................................................................... 104 21. In Circuit Emulator (ICE) ........................................................................................................................................... 106 21.2 PIN define .......................................................................................................................................................... 106 21.2 ICE Key feature ...................................................................................................................................................... 107 22. Application circuit ...................................................................................................................................................... 108 23. Abbreviations............................................................................................................................................................ 109 24. Ordering Information ................................................................................................................................................. 109 25. Package Information ................................................................................................................................................. 110 26. Top Marking Information............................................................................................................................................ 111 27. Reflow Profile ........................................................................................................................................................... 112 28. Tape Reel Information ............................................................................................................................................... 113 29. Product Status .......................................................................................................................................................... 114

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
1. General Description
A9108 is a high performance and low cost Sub1GHz ISM band system-on-chip (SOC) wireless transceiver. This device integrates high speed pipeline 8051 MCU, 16KBytes In-system programmable flash memory, 2KB SRAM, various powerful functions and excellent performance of Sub1GHz GFSK/FSK transceiver. A9108 has various operating modes, making it highly suited for systems where ultra-low power consumption is required. A9108 has a 8bit ADC for RSSI and 4 channel 12bit ADC for general purpose. Three kinds of serial communication port (SPI, I2C and UART) can interact with other device(s). A9108 is one of AMICCOM sub1GHz family. It integrates AMICCOM sub1GHz transceiver well and offers a low cost solution with advanced radio features such as high output power amplifier up to 20 dBm (433MHz band, excluding LPF and HPF) and low noise receiver (- 114 dBm @ 10Kbps, -110dBm @50Kbps). Therefore, A9108 is very suitable for long LOS (line-of-sight) applications without the need to add an external LNA or PA. The on-chip data rate divider supports programmable on-air data rates from 2K to 250Kbps to satisfy different system requirements. For a battery powered system, A9108 supports fast PLL settling time (35 us), Xtal settling time (500 us) and on-chip Regulator settling time (450 us) to reduce average power consumption.

2. Typical Applications
? Wireless sensor networks ? Industrial monitoring and control ? Wireless alarm and security system

3. Feature
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

? ? ? ? ? ? ? ?

Small Package size (QFN5 X5, 40 pins). High performance pipeline complicated 8051 Operation clock: 1, 1/2, 1/4, 1/8, 1/16, 1/32 of crystal oscillator. 16KB Flash memory, 2KB SRAM AMICCOM Agent:www.koryosz.com UART, I2C, SPI serial communication Three 16/8-bit counter/timers Zed:13641400981 Two channel PWM Watchdog timer Sleep timer In-Circuit Debugger In-System programming/ In-Application programming 24 GPIO Four channel 12bit SAR ADC One channel 8 bit ADC for RSSI and battery detect Programmable threshold of carrier detect. Frequency band: 315/433/470/868/915 MHz. FSK and GFSK modulation. Programmable data rate from 2Kbps to 250Kbps. RX Current consumption (AGC Off) 915MHz: 16mA. TX Current consumption 915MHz: 90mA @ 17dBm. Deep sleep current (1uA) Low sleep current (3.5uA) On chip regulator, support input voltage 2.0 ~ 3.6 V. High RX sensitivity 915MHz. ? -104dBm at 50Kbps on-air data rate. ? -101dBm at 100Kbps on-air data rate. ? -99dBm at 150Kbps on-air data rate. ? -97dBm at 250Kbps on-air data rate. Support low cost crystal 12.8 MHz /16 MHz). Support RTC clock 32.678KHz Fast PLL settling time (35 us). 9-bits Digital RSSI and Auto RSSI measurement Auto Calibrations. Auto FCS (CRC) and Filtering. On-chip full range VCO and Fractional-N PLL synthesizer. On-chip low power RC oscillator for WOR (Wake on RX) function.

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? Wireless ISM band data communication ? Remote control ? Home and building automation

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
? ? AFC (Auto Frequency Compensation) for frequency drift due to Xtal aging. Separated 64 bytes FIFO for RX and TX.

4. Pin Configurations

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Fig 4-1. A9108 QFN 5x5 Package Top View

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Sub1GHz FSK/GFSK Transceiver SOC
5. Pin Description (I: input; O: output, I/O: input or output)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol REGI VPAI VPAO BP_BG BP_RSSI VDD_A RFI RFO VDD_VCO GND_PLL VDD_PLL XO XI P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESETN VDD_D VDD_S I/O I I O O O O I O I I O O I DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO I O I G Function Description Regulator input. Connect to bypass capacitor. Supply voltage input for PA. Connect to bypass capacitor. Supply voltage output. Connect to PA output stage. Band-gap bypass. Connect to bypass capacitor. O: RSSI bypass. Connect to bypass capacitor. Analog supply voltage output. Connect to bypass capacitor. RF input. Connect to matching circuit. RF output. Connect to matching circuit. (recommend powered by VDD directly). VCO supply voltage input. Connect to bypass capacitor. PLL ground. PLL supply voltage pin. Connect to bypass capacitor. Crystal oscillator output. Connect to tank capacitor. Crystal oscillator input. Connect to tank capacitor. SPI_SCLK SPI_MOSI SPI_MISO SPI_SSEL GPIO/ ICE mode I2C_SCL I2C_SDA INT2 /GIO1 Timer2_T2/IN1 Timer2_T2EX/CS1 INT3 /GIO2/RS1 INT4/ CKO/RT1 TTAG_TTDIO TTAG_TTCK PWM0 PWM1 UART0_RX UART0_TX INT0/ADC0 INT1/ADC1 Timer0_T0/ADC2 Timer1_T1/ADC3 RTC_I RTC_O Reset input Digital supply voltage output. Connect to bypass capacitor. Digital supply voltage output. Connect to bypass capacitor. Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance.

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Sub1GHz FSK/GFSK Transceiver SOC
6. Chip Block Diagram

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Fig 6-1. A9108 Block Diagram

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Sub1GHz FSK/GFSK Transceiver SOC
7. Absolute Maximum Ratings
Parameter Supply voltage range (VDD) Digital IO pins range Voltage on the analog pins range Input RF level Storage Temperature range ESD Rating HBM MM With respect to GND GND GND Rating -0.3 ~ 3.6 -0.3 ~ VDD+0.3 -0.3 ~ 2.1 14 -55 ~ 125 ± 2K ± 100 Unit V V V

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*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. *Device is Moisture Sensitivity Level III (MSL 3).

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*Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
8. Electrical Specification
(Ta=25℃, VDD=3.3V, data rate= 250Kbps, FXTAL =16MHz, On Chip Regulator = 1.8V, PN9 pattern, with matching network and low pass filter, unless otherwise noted.)

Parameter General
Operating Temperature Supply Voltage Current Consumption (Regulator on, X’TAL OSC on)

Description

Min.
-40 2.0

Typ.

Max.
85

Unit
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PM3 mode without Sleep timer PM3 mode with Sleep timer PM2 mode with Sleep timer PM1 mode with Sleep timer Normal PLL mode(CG off) RX mode (AGC Off) RX mode (AGC ON) TX 10.5dBm (TBG=1, TDC=2, PAC=0) TX 12.5dBm (TBG=3, TDC=0, PAC=0) TX 17.3dBm (TBG=7, TDC=3, PAC=3) PLL mode(CG off) RX mode (AGC Off) RX mode (AGC ON) TX 10.5dBm (TBG=1, TDC=2, PAC=0) TX 12.5dBm (TBG=3, TDC=0, PAC=0) TX 17.3dBm (TBG=7, TDC=3, PAC=3) PLL mode(CG off) RX mode (AGC Off) RX mode (AGC ON) TX 19.5dBm (TBG=7, TDC=2, PAC=1)

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2 TBD TBD 5.5 12.5 17.2 TBD 40 43 80 12.5 17.2 TBD 40 43 80 12.5 17.2 TBD 85 12 18 TBD 100 13 18 TBD 100 0.5 12.8/16 16 12.582912 19.6608 100 20 90 110

Current Consumption 315MHz band

Current Consumption 433MHz band

Current Consumption 490MHz band

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Current Consumption 868Hz band

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PLL mode(CG off)

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RX mode (AGC Off) RX mode (AGC ON)
(TBG=7, TDC=2, PAC=1)

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Current Consumption 915MHz band

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TX 19.5dBm

PLL mode(CG off) RX mode (AGC Off) RX mode (AGC ON) TX 17.5dBm
(TBG=7, TDC=2, PAC=1)

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Phase Locked Loop
X’TAL Settling Time 2 X’TAL frequency Idle to standby, 49US type General case Data rate = 250Kbps Data rate = 32.768K or 16.384Kbps Data rate = 38.4Kbps Recommended PN @100k offset PN @500k offset ms MHz MHz MHz MHz Ohm pF dBc/Hz dBc/Hz

X’TAL ESR X’TAL Capacitor Load (Cload) 433MHz PLL Phase noise
(loop component:

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
R1=820,C1=33nF,C2=2.2nF)

915MHz PLL Phase noise
(loop component: R1=560,C1=47nF,C2=3.3nF)

PLL Settling Time @settle to 25kHz Reference spur

PN @1M offset PN @100k offset PN @500K offset PN @1M offset Standby to PLL

115 80 100 105 35 65 -12 -15 20 20

dBc/Hz dBc/Hz dBc/Hz dBc/Hz us dBc

Transmitter
TX Power Range TX Settling Time TX Spurious Emission
1. Pout = 12 dBm 2. With LPF and HPF

Receiver
IF Frequency

IF Filter Bandwidth

315MHz RX Sensitivity 3
@BER=0.1% high gain mode

433MHz RX Sensitivity

3

@BER=0.1% high gain mode

490MHz RX Sensitivity

3

@BER=0.1% high gain mode

868MHz RX Sensitivity

3

@BER=0.1% high gain mode

915MHz RX Sensitivity

3

50K Mode 100K Mode 150K Mode 250K Mode 50K Mode (10 ppm Xtal needed) 100K Mode 150K Mode 250K Mode 2kbps(Fdev = 8KHz, IFBW=50KHz) 10kbps (Fdev = 18.75KHz IFBW=50KHz) 50kbps (Fdev = 18.75KHz IFBW=50KHz) 100kbps (Fdev = 37.5KHz) 150kbps (Fdev = 56.25KHz) 250kbps (Fdev = 93.75KHz) ,16MHz Xtal 2kbps(Fdev = 8KHz, IFBW=50KHz) 10kbps (Fdev = 18.75KHz IFBW=50KHz) 50kbps (Fdev = 18.75KHz IFBW=50KHz) 100kbps (Fdev = 37.5KHz) 150kbps (Fdev = 56.25KHz) 250kbps (Fdev = 93.75KHz) ,16MHz Xtal 50kbps (Fdev = 18.75KHz) 100kbps (Fdev = 37.5KHz) 150kbps (Fdev = 56.25KHz) 250kbps (Fdev = 93.75KHz) ,16MHz Xtal 50kbps (Fdev = 18.75KHz) 100kbps (Fdev = 37.5KHz) 150kbps (Fdev = 56.25KHz) 250kbps (Fdev = 93.75KHz),16MHz Xtal 50kbps (Fdev = 18.75KHz)

FI D

433MHz (excluding LPF and HPF) 868MHz (excluding LPF and HPF) PLL to TX f < 1GHz (RBW =100kHz) 47MHz< f <74MHz 87.5MHz< f <118MHz 174MHz< f <230MHz 470MHz< f <862MHz (RBW =100kHz) Above 1GHz (RBW = 1MHz) nd 2 Harmonic 3rd Harmonic

TI A
30 -36 -54 -30 -30 -30 100 200 300 500 50 100 150 250 -117 -114 -109 -107 -105 -102 -117 -114 -109 -107 -105 -102 -109 -106 -104 -100 -106 -103 -101 -97 -107

EN

C O

N

M

IC

C

O

A

M

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dBm dBm ?s dBm dBm

dBm dBm dBm

KHz

KHz

dBm

dBm

dBm

dBm

A9108
Sub1GHz FSK/GFSK Transceiver SOC
@BER=0.1% high gain mode

100kbps (Fdev = 37.5KHz) 150kbps (Fdev = 56.25KHz) 250kbps (Fdev = 93.75KHz),16MHz Xtal Co-channel ACR1 (C/Ich1) ACR2 (C/Ich2) Offset ± 10MHz 25MHz ~ 1GHz Above 1GHz AGC on @ RF input (BER = 0.1%) PLL to RX Standby to RX

Image rejection Interference (915MHz, 100Kbps)

RSSI Range Max Operation Input Power RX Settling Time

-110

12Bit SAR ADC
Input voltage range External reference voltage Input capacitor Bandwidth Conversion time Current consumption

EN
0 1.8 25.6 TBD 33 0.25 450 1.2 1.8 1.8 0.8*VDD 0 VDD-0.4 0

TI A
30 250 VDDA 2.1 VDD 0.2*VDD VDD 0.4

RX Spurious

CLK=1MHz

Regulator
Regulator settling time Band-gap reference voltage Regulator output voltage(VDDA)

N

FI D
13

Digital IO DC characteristics
High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL)

C O

Pin 3 connected to 1nF

A

M

IC

C

O

M

@IOH= -0.5mA @IOL= 0.5mA

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-57 -47 -30 10 ?s V V V V V V

-104 -99 -97 20 -14 21 37 50

dBm

dB dB dB dB dB

dBm dBm dBm dBm us us V V pF KHz uS mA

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9. SFR & RFR(Radio Frequency Register)
A9108 contains standard 8051 SFRs(special function registers) and RFR (RF control registers). A9108’s SFR location is almost the same as the standard 8052 SFR location. RFR is Radio Frequency Registers are located in XDATA spaces and located in 0x0800 ~ 0x08FF. For more detail information, please reference Section 9.2.

9.1 SFR Overview
0/8 0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80 IP P3 IE P2 SOCN0 P1 TCON P0 SBUF0 EIF TMOD SP PCONE PWM1CON PWM0CON RSFLAG PWM1H PWM0H EIP B EIE ACC WDCON PSW T2CON P3OE P1OE P0OE T2IF P3PUN P1PUN P0PUN RLDL P3WUN P1WUN P0WUN RLDH 1/9 OSCCON I2CSADR I2CSCR I2CSBUF I2CMSA SPCR SPCR1 2/A 3/B 4/C 5/D 6/E

I2CMCR SPSR

EN
SPSR1 TH2 FLSHTER TH1 DPH1 RS2 OV F1

FI D
TL2 FLSHTPG TH0 DPL1 F0 RS1

IOSEL

C O

FL]SHCTRL FLSHTMR

N

PWM1L PWM0L

M

TL0

TL1 DPH0

: It means bit-addressable : It means reserved. Following are description of SFRs related to the operation of A9108 System Controller. Detailed descriptions of the remaining SFRs are including the sections of the datasheet associated with their corresponding system function. The arithmetic section of the processor performs extensive data manipulation and is comprised of the 8-bit arithmetic logic unit (ALU), an ACC(0xE0) register, B(0xF0) register and PSW(0xD0) register.

A

PSW (Address: D0h) Address/Name D0h PSW Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W CY AC P

0 0 0 0 0 0 0 0 Program Status Word register The ALU performs typical arithmetic operations as: addition, subtraction, multiplication, division and additional operations such as: increment, decrement, BCD-decimal-add-adjust and compare. Within logic unit are performance: AND, OR, Exclusive OR, complement and rotation. The Boolean processor performance the bit operations as: set, clear, complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry.

M

IC

C

O

DPL0

Table 9.1 A9108 Special Function Registers (SFRs) table

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TI A
I2CMBUF SPDR SPDR1 USBADDR CKCON DPS

L
7/F I2CMTP SSCR SSCR1 DEVICR USBDATA DMAIR PCON

A9108
Sub1GHz FSK/GFSK Transceiver SOC
CY - Carry flag AC - Auxiliary carry F0 - General purpose flag 0 RS[1:0] - Register bank select bits

OV - Overflow flag F1 - General purpose flag 1 P - Parity flag The PSW contains several bits that reflect the current state of the CPU. ACC (Address: E0h) Address/Name E0h ACC Reset R/W R/W Bit 7 Bit 6 Bit 5 Bit 4

0 0 0 0 0 Accumulator ACC Register

FI D
Bit 4 ADC12RN CER STRB4 -DFCD Bit 3

EN
Bit 3 Bit 2 Bit 1 0 0
Bit 2 FIFORN XER STRB3 -WOR_EN VCC -FMT VBC TPSA[5:0]

9.2 RFR Overview
Address / Name 0x800h RSTCTL

C

IC

R/W
W R W R W/R W/R W W W

O

Bit 7

M

0 0 0 0 0 0 0 B Register The B register is used during multiply and divide operations. In other cases may be used as normal SFR.

Address/Name F0h B Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

C O

0

Bit 6 FWPRN FECF STRB6 P_IRQ1O ARSSI

N
Bit 5 FRPRN CRCF STRB5 P_IRQ2O FIFO_REV

B (Address: F0h)

TI A
Bit 0 0
Bit 1 RCADCRN TRSR STRB1 -FMS FBC Bit 0 -TRER STRB0 -ADCM RSSCR BFCRN PLLER STRB2 FEP[7:0] WORDLY[7:0]

RESETN -STRB7 P_CKO STRR

A

M

0x801h MODEC1 0x802h MODEC2 0x803h CALC 0x804h FIFO1 0x805h FIFO2 0x806h RCOSC1

WORS[3:0]

FPM[1:0]

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
0x807h RCOSC2 0x808h RCOSC3 0x809h RCOSC4
W W W R W R W R WORDLY[9:8] SPSS RCOT2 NUMLH11 MRCT9 NUMLH7 MRCT7 RCOC7 -RCOT1 NUMLH10 MRCT8 NUMLH6 MRCT6 RCOC6 -RCOT0 NUMLH9 -NUMLH5 MRCT5 RCOC5 -WSEL1 NUMLH8 -NUMLH4 MRCT4 RCOC4 WRDLY[5:0] -WSEL0 --NUMLH3 MRCT3 RCOC3 TMRE MVS1 RCOC9 -NUMLH2 MRCT2 TSEL MVS0 RCOC8 MAN TWOR ENCAL ENCAL MCALS

0x80Ah RCOSC5

TI A
MRCT1 RCOC2 RCOC1

0x80Bh RCOSC6 0x80Ch RCOSC7 0x80Dh RCOSC8 0x80Eh CKO 0x80Fh GPIO1 0x810h GPIO2 0x811h CLOCK 0x812h PLL1 0x813h PLL2 0x814h PLL3 0x815h PLL4 0x816h PLL5 0x817h PLL6 0x818h PLL7 0x819h CHG1 0x81Ah CHG2 0x81Bh CHG3 0x81Ch TX1 0x81Dh TX2 0x81Eh DELAY1 0x81Fh DELAY2 0x820h RX 0x821h ADCC

W W
W W W W/R W W W W W

--

--

--

--

TGNUM[7:0]
PRS HWCKS WRCKS CKOS[3:0]

FI D

EN
CKOI SDPW MC[14:8] GS RXDI -MVS[1:0] --

TGNUM[11:8]

L
NUMLH1 -GIO1I GIO2I CGS NSDO FDP[2:0] PDLY[2:0] RS_DLY[2:0] -XADSR

NUMLH0 MRCT0 RCOC0

-GIO1OE GIO2OE XS

GIO1S[3:0] GIO2S[3:0]

MCNT[1:0] GRS CPS CKX2

C O
CPC[1:0] MD[1:0]

N

GRC[4:0] MDIV VCS[1:0] IP[7:0]

RRC[3:0] EDI

M
AFC FPH[3:0] MCNTR BT[1:0] TME

FP[15:8] FP[7:0]

C
W/R W/R W/R W/R W/R W W W W W R W R --

O

IC

MC[7:0] IPL[7:0] IPH[7:0] FPL[3:0]

A

M

FD[7:0] DPRY[2:0] WSEL[2:0] AGCE -RADC -AVS[1:0] ADCO[7:0] BW[1:0] -TDLY[1:0] AGC_DLY[1:0]

DMG[1:0]

ULS -CDM

ADCO[8] MXD

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
0x822h RXAGC1 0x823h RXAGC2 0x824h RSSI 0x825h AGCHT 0x826h AGCLT 0x827h CODE1 0x828h CODE2 0x829h CODE3 0x82Ah IFC1 0x82Bh IFC2 0x82Ch VCOCC 0x82Dh VCOBC1 0x82Eh VCOBC2 0x82Fh PM 0x830h RFI 0x831h XTST 0x832h BD 0x833h TXT1 0x834h TXT2 0x835h RXDEM1 0x836h RXDEM2 0x837h RXDEM3 0x838h DRCK 0x839h RTC 0x83Ah ID0 0x83Bh ID1 0x83Ch ID2 0x83Dh ID3
W R W R W R W R W W W W W R W R W R W R W W W W W R MCS ETH2 MSCRC BGS -STS -SWT ---QDP -RF23D1 QCLIM CA1 -WHTS ETH1 WS6 CRCDNP -TRT2 -RGC[1] ---INTXC RSAGC1 RF23D0 -CA0 -FECS ETH0 WS5 CRCINV -TRT1 -VRSEL -HDM ERSSM -EXRSI LGM[1:0] LGC[1:0] MS RHM[7:0] RTH[7:0] ADC[7:0] IRTH[7:0] RLM[7:0] MGM[1:0] MGC[1:0] MSCL[4:0] IGM[1:0] IGC[1:0]

IDL1 WS4 MFBS FBCF TRT0 FCD4

IDL0 WS3 MFB3 FB3

TI A
-PMD1 WS1 WS2 MFB2 FB2 MFB1 FB1 ASMV0 FCD1 VCOC0 VCB1 MVB1 VB1 VTH1 XCL1 RMP1 XCP1 BVT0 -TBG1 TXIB1 SLF0 CSC1 DCV1 SDR1 RTCI ID1 ID9 ID17 ID25 ASMV1 FCD2 VCOC1 VCB2 MVB2 VB2 VTH2 XCL2 PRIC0 XCC BVT1 -TBG2 LODV0 SLF1 CSC2 DCV2 SDR2 RTC0 ID2 ID10 ID18 ID26

CRCS

--

--

EN
ASMV2 FCD3 VCOC2 VCB3 MVBS VBCF VTL0 XCL3 PRIC1 RXCP0 BVT2 -TDC0 LODV1 SLF2 DCM0 DCV3 SDR3 RTC1 ID3 ID11 ID19 ID27

RGC[0] --DVT1 VTL2

FI D

VCOC3 VCCF VBS DVT0 VTL1

N

C O

RSAGC0 PRRC1 RXCC RGV1 -PAC0 RFT1 MLP1 DCL0 DCV5 SDR5 -ID5 ID13 ID21 ID29

XCL4 PRRC0 RXCP1 RGV0 VBD TDC1 RFT0 MLP0 DCM1 DCV4 SDR4 RTCOE ID4 ID12 ID20 ID28

M

W W W

O

TXDI --

PAC1 RFT2 DMT DCL1 DCV6 SDR6 -ID6 ID14 ID22 ID30

C

IC

CST DCL2 DCV7 --ID7 ID15 ID23 ID31

M

W/R W W/R W W/R W/R W/R W/R

A

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PML[1:0] PMD0 WS0 MFB0 FB0 AMVS FCD0 MVCS VCB0 MVB0 VB0 VTH0 XCL0 RMP0 XCP0 BDS BODF TBG0 TXIB0 DMOS CSC0 DCV0 SDR0 RTCE ID0 ID8 ID16 ID24

IRTL[7:0]

A9108
Sub1GHz FSK/GFSK Transceiver SOC
0x83Eh ID4 0x83Fh ID5 0x840h ID6 0x841h ID7 0x842h DID0 0x843h DID1 0x844h DID2 0x845h DID3 0x858h ADCCTL 0x859h ADCAVG1 0x85Ah ADCAVG2 0x85Bh ADCAVG3 0x85Ch TMRINV 0x85Dh TMRCTL 0x85Eh EXT1 0x85Fh EXT2 0x860h EXT3 0x851h EXT4 0x862h EXT5 0x863h PWRCTL 0x864h INTSW 0x865h TX5DY
W/R W/R W/R W/R R R R R W R R R R W W R W/R W/R W W W W W ID39 ID47 ID55 ID63 DID31 DID23 DID15 DID7 --ID38 ID46 ID54 ID62 DID30 DID22 DID14 DID6 CKS1 -ID37 ID45 ID53 ID61 DID29 DID21 DID13 DID5 CKS0 -MVADC[9] MVADC[5] ADC[5] ID36 ID44 ID52 ID60 DID28 DID20 DID12 DID4 MODE MODE ID35 ID43 ID51 ID59 DID27 DID19 DID11 DID3 MVS[2] MVS[2] ID34 ID42 ID50 ID58 DID26 DID18 DID10 DID2 ID33 ID41 ID49 ID57 DID25 DID17 DID9 DID1 ID32 ID40 ID48 ID56 DID24 DID16 DID8 DID0 ADCE ADCE ADC[8] MVADC[0] ADC[0]

EN
ADC[11] MVADC[3] ADC[3] CTR3 FBG[0] STM[3] -XEC QDSD SWINT50 CTR2 CBG2 -CEL

MVADC[11] MVADC[10] MVADC[7] ADC[7] MVADC[6] ADC[6]

MVADC[8] MVADC[4] ADC[4]

FI D
--CTR4 FBG[1] STM[4] -PDNS ENDV --

-FBG[4] --

C O

TMRON TMRIE

TMRIE TMRIF --

N

TMR_INV[7] TMR_INV[6] TMR_INV[5] TMR_INV[4] TMR_INV[3] TMR_INV[2] TMR_INV[1] TMR_INV[0] TMRIF -CTR5 TMRCKS[2] TMRCKS[1] TMRCKS[0] ---CTR1 CBG1 STM[1] -ENDL[1] SVREF TMR_CE -CTR0 CBG0 STM[0] RGS ENDL[0] CELA

FBG[3] --

FBG[2]

M

STM[5] INTLP -QDSA --

O

CSLP --

RSLP --

C

EBOD --

ENAV --

IC

A

9.2.0 RSTCTL (Address: 0x800h)
Name R/W
W R

M

W/R

Bit 7
RESETN --

Bit 6
FWPRN FECF

Bit 5
FRPRN CRCF

Bit 4
ADC12RN CER

Bit 3
FIFORN XER

TI A
MVS[1] MVS[1] MVS[0] MVS[0] ADC[9] MVADC[1] ADC[1] ADC[10] MVADC[2] ADC[2] STM[2] ENDL[2] SWINTT0

TX5DY[5:0]

Bit 2
BFCRN PLLER

Bit 1
-TRSR

RSTCTL Reset

0

0

0

0

0

0

RESETN: Software reset for baseband FWPRN: Software reset for TX FIFO pointer. FRPRN: Software reset for RX FIFO pointer. FIFORN: Software reset for RX FIFO. BFCRN: Software Reset for IF Filter Bank Calibration. ADC12RN: Software reset for 12-bits ADC.

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Bit 0
-TRER

SWINTT1 SWTMRINT

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
CER: Chip Enable Status . (Read Only). [0]: Disable. [1]: Enable. XER: Crystal Status. (Read Only). [0]: Disable. [1]: Enable. PLLER: PLL Status. (Read Only). [0]: Disable. [1]: Enable. TRSR: TRX Mode Status. (Read Only). [0]: RX mode. [1]: TX mode. TRER: TRX Status. (Read Only). [0]: Disable. [1]: Enable.

CRCF: CRC latch error flag. (CRCF is read clear.) [0]: CRC pass. [1]: CRC error.

9.2.1 MODEC1 (Address: 0x801h)
Name MODEC1 Reset R/W
W

Bit 7
STRB7

Bit 6
STRB6

Bit 5 0

N
Bit 4 0

FI D
Bit 3
STRB3

FECF: FEC latch error flag. (FECF is read clear.) [0]: FEC pass. [1]: FEC error.

EN
Bit 2
STRB2

TI A
Bit 1
STRB1

0

C O

STRB5

STRB4

0

0

0

9.2.2 MODEC2 (Address: 0x802h)
Name R/W
W/R

IC

C

Strobe Command STRB STRB STRB STRB STRB STRB STRB STRB Description 7 6 5 4 3 2 1 0 1 0 0 0 0 x x x Sleep mode 1 0 0 1 x x x x Idle mode 1 0 1 0 x x x x Standby mode 1 0 1 1 x x x x PLL mode 1 1 0 0 x x x x RX mode 1 1 0 1 x x x x TX mode

O

Bit 7 0

M

Bit 6
ARSSI

Bit 5
FIFOREV

Bit 4
DFCD

Bit 3
WOR_EN

Bit 2
FMT

Bit 1
FMS

M

MODEC2 Reset

STRR

0

0

0

0

0

A

STRR: Direct mode modem data can be accessed via GPIO pin. [0]: P_DTDM. [1]: Direct mode TX Data (DTD = 0). ARSSI: Auto RSSI measurement enable. [0]: Disable. [1]: Enable. FIFOREV: Reverse TX and RX FIFO. [0]: Disable. [1]: Enable.

DFCD (Data Filter by CD): The received package will be filtered out if Carrier Detector signal is inactive. [0]: Disable. [1]: Enable.

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AMICCOM Electronics Corporation

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Bit 0
STRB0

0

0

Bit 0
ADCM

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
WOR_EN: WOR or WOT function enable. [0]: Disable. [1]: Enable.
FMT: FIFO mode test. [0]: [1]: Enable Test mode. FMS: FIFO mode select. [0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement (Auto clear when done). [0]: Disable. [1]: Enable.

9.2.3 CALC (Address: 0x803h)
Name CALC Reset R/W
W/R

Bit 7
WORS3

Bit 6
WORS2

Bit 5
WORS1

Bit 4
WORS0

EN
Bit 3
VCC

TI A
Bit 2
VBC

Bit 1
FBC

0

0

0

0

0

0

WORS[3:0]: WOR wake up time.

VCC: VCO Current Calibration. (Write only, Shall be set to [1].)

[0]: Disable. [1]: Enable.
VBC: VCO Bank Calibration enable (Auto clear when done).

[0]: Disable. [1]: Enable. [0]: Disable. [1]: Enable. [0]: Disable. [1]: Enable.

FBC: IF Filter Bank Calibration enable (Auto clear when done).

RSSCR: RSSI Calibration. (Auto clear when done)

9.2.4 FIFO1 (Address: 0x804h)
Name FIFO1 Reset R/W
W

Bit 7
FEP7

M

Bit 6 0

C O

Bit 5
FEP5

N

FI D
Bit 4
FEP4

Bit 3
FEP3

Bit 2
FEP2

Bit 1
FEP1

O

FEP6

0

0

0

0

0

M

9.2.5 FIFO2 (Address: 0x805h)
Name R/W
W

IC

FEP[7:0]: FIFO end pointer in byte for TX FIFO and RX FIFO. FIFO Length Setting = FEP[7:0] + 1 ; For example if FEP = 0x3F, it means FIFO length is 64 bytes.

C

Bit 7
FPM1

Bit 6
FPM0

Bit 5
TPSA5

Bit 4
TPSA4

Bit 3
TPSA3

Bit 2
TPSA2

Bit 1
TPSA1

A

FIFO2 Reset

0

0

0

0

0

0

FPM[1:0]: FIFO pointer margin. Used in FIFO extension mode

FPM[1:0] 00 01 10 11

Bytes in TX FIFO 4 8 12 16

Bytes in RX FIFO 60 56 52 48

TPSA[5:0]: TX payload start address in byte. Used for segment FIFO.

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Bit 0
RSSCR

0

0

Bit 0
FEP0

0

0

Bit 0
TPSA0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.6 RCOSC1 (Address: 0x806h)
Name RCOSC1 Reset R/W
W

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

Bit 0 0

WORDLY7 WORDLY6 WORDLY5 WORDLY4 WORDLY3 WORDLY2 WORDLY1 WORDLY0

WORDLY[7:0]: WOR sleep periods

RCOSC2 Reset

W

WORDLY9 WORDLY8

WRDLY5

WRDLY4

WRDLY3

WRDLY2

0

0

0

0

0

TI A
WRDLY1

Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 0

Bit 1 0

WORDLY[9:8]: WOR sleep periods WRDLY[5:0]: WOR active periods

9.2.8 RCOSC3 (Address: 0x808h)
Name RCOSC3 Reset R/W
W

SPSS

--

--

FI D
---

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

EN
Bit 3 0 Bit 2 0
TMRE

Bit 1
TSEL

TMRE: WOR timer enable bit [0]: Disable [1]: Enable

TWOR: WOR timer select

9.2.9 RCOSC4 (Address: 0x809h)

IC

Name

C

R/W
W R

O

[0]: WWS mode [1]: Timer mode

Bit 7

M

TSEL: TWOR Duty select. [0]: Use WOR_AC [5:0]. (where WOR_AC is located in 08h, page 1) [1]: Use WOR_SL [9:0]. (where WOR_SL is located in 08h, page 1)

Bit 6
RCOT1 NUMLH10

C O

Bit 5
RCOT0 NUMLH9

N

SPSS: Mode back select if WOR is enabled. Recommend SPSS = [0]. [0]: STBY [1]: PLL

Bit 4
WSEL1 NUMLH8

Bit 3
WSEL0 --

Bit 2
MVS1 RCOC9

Bit 1
MVS0 RCOC8

RCOSC4 Reset

RCOT2 NUMLH11

ENCAL: Enable RC-OSC Calibration.

A

RCOT [2:0]: RC Oscillator current setting.

MVS[1:0]: Main clock divider. [00]: MSCK [01]: MSCK / 2 [10]: MSCK / 3 [11]: MSCK / 4 WSEL[1:0]: RC-OSC Calibration Source Clock Selection. [00]: 16 MHz. [01]: 8 MHz. [10]: 4 MHz. [11]: 2 MHz.

M

0

0

0

0

0

0

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Bit 0 0
WRDLY0

9.2.7 RCOSC2 (Address: 0x807h)

Bit 0
TWOR

0

0

Bit 0
ENCAL ENCAL

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
RCOC[9:0]: RC-OSC calibration value. NUMLH[11:0]: RC-OSC calibration latch number.

9.2.10 RCOSC5 (Address: 0x80Ah)
Name RCOSC5 Reset R/W
W R

Bit 7
MRCT9 NUMLH7

Bit 6
MRCT8 NUMLH6

Bit 5
-NUMLH5

Bit 4
-NUMLH4

Bit 3
-NUMLH3

Bit 2
-NUMLH2

Bit 1
MAN NUMLH1

Bit 0
MCALS NUMLH0

0

0

0

0

0

0

MCALS: Enable Continuous RC-OSC Calibration. MAN: Enable Manual RC-OSC Calibration. MRCT[9:0]: Manual RC-OSC calibration value setting. NUMLH[11:0]: RC-OSC calibration latch number.

9.2.11 RCOSC6 (Address: 0x80Bh)
Name RCOSC6 Reset R/W
W R

Bit 7
MRCT7 RCOC7

Bit 6
MRCT6 RCOC6

Bit 5
MRCT5 RCOC5

FI D
Bit 4 Bit 3
MRCT4 RCOC4 MRCT3 RCOC3

EN
Bit 2
MRCT2 RCOC2

TI A
Bit 1
MRCT1 RCOC1

0

0

0

0

0

0

MRCT[9:0]: Manual RC-OSC calibration value setting. RCOC[9:0]: RC-OSC calibration value.

9.2.12 RCOSC7 (Address: 0x80Ch)
Name RCOSC7 Reset R/W
W

Bit 7
--

Bit 6
--

C O

Bit 5
--

N

Bit 4
--

Bit 3
TGNUM11

Bit 2
TGNUM10

Bit 1
TGNUM9

--

M

--

--

--

0

0

9.2.13 RCOSC8 (Address: 0x80Dh)
Name RCOSC8 Reset

C

R/W
W

O

TGNUM[11:0]: Target Number for RC OSC Calibration.

Bit 7 0

Bit 6
TGNUM6

Bit 5
TGNUM5

Bit 4
TGNUM4

Bit 3
TGNUM3

Bit 2
TGNUM2

Bit 1
TGNUM1

IC

TGNUM7

0

0

0

0

0

TGNUM[11:0]: Target Number for RC OSC Calibration.

9.2.14 CKO (Address: 0x80Eh)

M

A

Name CKO Reset

R/W
W

Bit 7
PRS

Bit 6
CKOS3

Bit 5
CKOS2

Bit 4
CKOS1

Bit 3
CKOS0

Bit 2
CKOI

Bit 1
--

0

0

0

0

0

0

PRS: Read frequency mode when AFC=1. Recommend PRS= [0].

[0]: no frequency compensation. [1]: frequency offset in AFC mode.
CKOS[3:0]: CKO select. [0000]: BCK. ( Bit clock) [0001]: MRCK. ( Modulation rate clock) [0010]: FPF.( FIFO pointer flag. 1: Touch margin.) [0011]: EOP | EOVBC | EOFBC | EOADC | OKADC . [0100]: BBCK.

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0 0 Bit 0
MRCT0 RCOC0

0

0

Bit 0
TGNUM8

0

0

Bit 0
TGNUM0

0

0

Bit 0
--

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
[0101]: BBCK. [0110]: BBCK. [0111]: RTCIN. (RTC timer input). [1000]: WCK. [1001]: FP8M. [1010]: TMRCK. [1011]: EOADC. [1100]: OKADCN. [1101]: 0. [1110]: RTCO. (RTC timer output). [1111]: 0. CKOI: CKO pin Output signal invert [0]: Non-inverted output. [1]: Invert

Name GPIO1 Reset

R/W
W

Bit 7
HWCKS

Bit 6
WRCKS

Bit 5
GIOS3

Bit 4
GIOS2

EN
Bit 3 0 Bit 2 0
GIOS1 GIOS0

9.2.15 GPIO1 (Address: 0x80Fh)

TI A
Bit 1
GIO1I

HWCKS: WOR Clock Select. Recommend HWCKS = [0]. [0]: 4KHz [1]: 1.2KHz WRCKS: WOR Reference clock select. [0]: WOR Ref clock when PF8M is equal or close to 6.4MHz. [1]: WOR Ref clock when PF8M is equal or close to 8MHz. GIO1S[3:0]: GIO1 pin function select.

GIO1S[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

TX State RX state WTR ( Wait until TX or RX finished ) EOAC(end of access code) FSYNC(frame sync) TMEO(TX modulation enable) CD(carrier detect) Preamble Detect Output (PMDO) MCU wakeup signal (TWOR) In phase demodulator input(DMII) or DVT[0](AGC) SDO (4 wires SPI data out) TRXD In/Out (Direct mode) RXD (Direct mode) TXD (Direct mode) PDN_RX External FSNYC input in RX direct mode * In phase demodulator output (DMOI) FPF (FIFO pointer flag for FIFO extension) PDN_TX FMTDO (FIFO mode TX Data Output testing)

A

GIO1I: GIO1 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output GIO1OE: GIO1pin output enable.

[0]: High Z. [1]: Enable.

9.2.16 GPIO2 (Address: 0x810h)
Name GPIO2 R/W
W

M

IC

C

O

Bit 7
MCNT1

M

Bit 6
MCNT0

C O

Bit 5
GIO2S3

N

FI D
Bit 4
GIO2S2

0

0

0

0

Bit 3
GIO2S1

Bit 2
GIO2S0

Bit 1
GIO2I

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Bit 0
GIO1OE

0

0

Bit 0
GIO2OE

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Reset
MCNT[1:0]: Main Clock Divider. [00]: MSCK [01]: MSCK / 2 [10]: MSCK / 3 [11]: MSCK / 4 GIO2S[3:0]: GIO2 pin function select..

0

0

0

0

0

0

0

0

0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

GIO2I: GIO2 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output GIO2OE: GIO2 pin output enable. [0]: High Z. [1]: Enable.

9.2.17 CLOCK (Address: 0x811h)
CLOCK Reset

C

Name

R/W
W/R

O

Bit 7
GRS

M

Bit 6 0

C O

Bit 5
GRC3

N
Bit 4
GRC2

FI D
Bit 3
GRC1

EN
Bit 2
GRC0

TI A
Bit 1
CGS

GIO2S[3:0] 0000 0001 0010

TX State RX state WTR ( Wait until TX or RX finished ) EOAC(end of access code) FSYNC(frame sync) TMEO(TX modulation enable) CD(carrier detect) External sync input(for direct mode) (only in SWT=0) Preamble Detect Output (PMDO) (only in SWT=1) MCU wakeup signal (TWOR) Quadrature phase demodulator input(DMIQ) or DVT[1](AGC) SDO (4 wires SPI data out) TRXD In/Out (Direct mode) RXD (Direct mode) TXD (Direct mode) PDN_TX External FSNYC input in RX direct mode * Quadrature phase demodulator output (DMOQ) FPF (FIFO pointer flag for FIFO extension) Battery Detect flag (BDF) FMRDI (FIFO mode RX input for internal test)

GRC4

GRS: Reference Clock Selection for the internal PLL CLK Generator.

A

GRC[4:0]: Clock generation PLL R counter.

GRC [4:0] is used to divide crystal frequency to obtain reference clock.

fCGRF ?

CGS: Clock Generation Selection.

XS: Crystal Oscillator Selection. Recommend XS = [1]. [0]: disable, use external clock source from XI pin. [1]: enable, use Xtal from XI and XO pin.

M

[0]: PLL CLK Gen. = FCGRF x 48 [1]: PLL CLK Gen. = FCGRF x 32 Where FCGRF is from below GRC divider.

f xtal GRC[4 : 0] ? 1

IC

0

0

0

0

0

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Bit 0
XS

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.18 PLL1 (Address: 0x812h)
Name PLL1 Reset R/W
W

Bit 7
CPS

Bit 6
CPC1

Bit 5
CPC0

Bit 4
MDIV

Bit 3
RRC3

Bit 2
RRC2

Bit 1
RRC1

Bit 0
RRC0

0

0

0

0

0

0

0

0

CPS: Charge Pump tri-state setting. Recommend CPS = [1] .

[0]: Tri-state.[1]: Normal operation.

MDIV: RF Divider Range setting.

[0]: Range of IP[7:0] is 32~67. [1]: Range of IP[7:0] is 68 ~ 255.
RRC[3:0]: RF PLL Reference Counter.

RRC [3:0] is the clock divider to generate a PFD clock for RF_PLL to lock the wanted LO frequency.

f PFD ?

f xtal RRC[3 : 0] ? 1

9.2.19 PLL2 (Address: 0x813h)
Name PLL2 Reset R/W
W

Bit 7
CKX2

Bit 6
MD1

Bit 5
MD0

FI D
Bit 4 0 Bit 3 0
VCS1 VCS0

EN
Bit 2
SDPW

TI A
Bit 1
NSDO

0

0

0

N

0

CKX2: Reserved. CKX2 shall be [0]. MD[1:0]: RF Band select, [Bit12, Bit8]. [00]: RF in 868MHz and 915MHz Band. [01]: RF in 868MHz and 915MHz Band. [10]: RF in 433MHz / 510MHz Band. [11]: RF in 315MHz Band.

SDPW: Pulse Width of sigma-delta modulator.

O

VCS[1:0]: VCO Current setting. Recommend VCS = [01]. SDPW shall be [1].

EDI: Dither Noise setting. Recommend EDI = [0]. [0]: Disable. [1]: Enable.

M

9.2.20 PLL3 (Address: 0x814h)
Name PLL3 Reset R/W
W

IC

C

NSDO: Mash sigma delta order setting. Recommend NSDO = [0]. [0]: order 2. [1]: order 3.

Bit 7
IP7

M

Bit 6
IP6

C O

Bit 5
IP5

Bit 4
IP4

Bit 3
IP3

Bit 2
IP2

Bit 1
IP1

A

0

0

0

0

0

0

IP[7:0]: final PLL integer part output.

9.2.21 PLL4 (Address: 0x815h)
Name PLL4 Reset R/W
W

Bit 7
FP15

Bit 6
FP14

Bit 5
FP13

Bit 4
FP12

Bit 3
FP11

Bit 2
FP10

Bit 1
FP9

0

0

0

0

0

0

FP[15:8]: LO Frequency Fractional Part setting.

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Bit 0
EDI

CPC[1:0]: Charge Pump Current setting. [00]: 0.5mA. [01]: 1mA. [10]: 1.5mA. [11]: 2mA.

0

0

Bit 0
IP0

0

0

Bit 0
FP8

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.22 PLL5 (Address: 0x816h)
Name PLL5 Reset R/W
W

Bit 7
FP7

Bit 6
FP6

Bit 5
FP5

Bit 4
FP4

Bit 3
FP3

Bit 2
FP2

Bit 1
FP1

Bit 0
FP0

0

0

0

0

0

0

0

0

FP[7:0]: LO Frequency Fractional Part setting.

9.2.23 PLL6 (Address: 0x817h)
Name PLL6 Reset R/W
W/R

Bit 7
AFC

Bit 6
MC14

Bit 5
MC13

Bit 4
MC12

Bit 3
MC11

Bit 2
MC10

Bit 1
MC9

0

0

0

0

0

TI A
0 0 Bit 2
MC2

MC[14:8]: PLL Fractional Part Compensation value (Manual frequency compensation value)

9.2.24 PLL7 (Address: 0x818h)
Name PLL7 Reset R/W
W/R

Bit 7
MC7

Bit 6
MC6

Bit 5
MC5

FI D
Bit 4
MC4

[Write]:Manual setting to LO fractional part compensation value when AFC = [0]. [Read]:Frequency offset value when AFC = [1].

EN
Bit 3
MC3

AFC: Auto Frequency Compensation selection. Recommend AFC = [1]. [0]: manual [1]: auto

Bit 1
MC1

0

0

0

N

0

0

0

[Write]:Manual setting to LO fractional part compensation value when AFC = [0]. [Read]:Frequency offset value when AFC = [1].

9.2.25 CHG1 (Address: 0x819h)
Name CHG1 Reset R/W
W/R

IPL7

M

Bit 7 0

Bit 6
IPL6

C O

MC[7:0]: PLL Fractional Part Compensation value

Bit 5
IPL5

Bit 4
IPL4

Bit 3
IPL3

Bit 2
IPL2

Bit 1
IPL1

Name

IC

9.2.26 CHG2 (Address: 0x81Ah)
R/W
W/R

C

IPL [7:0]: VCO Calibration Integer Part Setting for Low Boundary Channel Group. Please refer to A9108’s reference code for the wanted RF band.

O

0

0

0

0

0

Bit 7
IPH7

Bit 6
IPH6

Bit 5
IPH5

Bit 4
IPH4

Bit 3
IPH3

Bit 2
IPH2

Bit 1
IPH1

M

CHG2 Reset

0

0

0

0

0

0

A

IPH [7:0]: VCO Calibration Integer Part Setting for High Boundary Channel Group. Please refer to A9108’s reference code for the wanted RF band.

9.2.27 CHG3 (Address: 0x81Bh)
Name CHG3 Reset R/W
W/R

Bit 7
FPH3

Bit 6
FPH2

Bit 5
FPH1

Bit 4
FPH0

Bit 3
FPL3

Bit 2
FPL2

Bit 1
FPL1

0

0

0

0

0

0

FPH [3:0]: VCO Calibration Fractional Part Setting for High Boundary Channel Group. Please refer to A9108’s reference code for the wanted RF band. FPL [3:0]: VCO Calibration Fractional Part Setting for Low Boundary Channel Group. Please refer to A9108’s reference code for the wanted RF band.

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Bit 0
MC8

0

Bit 0
MC0

0

0

Bit 0
IPL0

0

0

Bit 0
IPH0

0

0

Bit 0
FPL0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.28 TX1 (Address: 0x81Ch)
Name TX1 Reset R/W
W

Bit 7
MCNTR

Bit 6
BT1

Bit 5
BT0

Bit 4
TME

Bit 3
GS

Bit 2
FDP2

Bit 1
FDP1

Bit 0
FDP0

0

0

0

0

0

0

0

0

[1]: PF8M = f MCNT where f
MCNT

located in 0x06 page 8.

TME: TX modulation enable. [0]: Disable. (Test Mode to check single tone). [1]: Enable. (Normal Operation).

TME shall be set no matter in FIFO mode or Direct mode, Then, the TX modulator will be active automatically after PDL and TDL delay timer.

FDP[2:0]: Frequency Deviation Exponential Coefficient setting For both Gaussian filter is enabled (GS =1) or disabled(GS = 0):

f dev ? 2 ? f PFD ? FD[7 : 0] ?
where

f PFD ? f Xtal
R/W
W

9.2.29 TX2 (Address: 0x81Dh)
Name TX2 Reset Bit 7
FD7

O

M

2 FDP[ 2:0] (unit: Hz) 219 ? ( RFC [3 : 0] ? 1) , is the comparison frequency of RF_PLL.

C

Bit 6
FD6

C O

GS: Gaussian select. [0]: Disable [1]: Select.

Bit 5
FD5

N
Bit 4
FD4

FI D
Bit 3
FD3

BT [1:0]: Data Shaper. If GS = [0],Gaussian filter is disabled, BT = [00]: not average. [01]: 2 bit average. [10]: 4 bit average. [11]: 8 bit average That means BT is used to smooth TX data transition. If GS = [1],Gaussian filter is enabled, BT = [00]: 2.0. [01]: 1.0. [10]: 0.5. [11]: 0.5 That means BT is used to configure shape of Gaussian filter.

EN
Bit 2
FD2

TI A
Bit 1
FD1

= f MSCK /( MCNT [1: 0]),

FD[7:0]: TX Frequency Deviation setting.

9.2.30 DELAY1 (Address: 0x81Eh)

M

A

Name

IC

0

0

0

0

0

0

R/W
W

Bit 7
DPRY2

Bit 6
DPRY1

Bit 5
DPRY0

Bit 4
TDLY1

Bit 3
TDLY0

Bit 2
PDLY2

Bit 1
PDLY1

DELAY1 Reset

0

0

0

0

0

0

DPRY[2:0]: TDLY[1:0]: PDLY[2:0]: PLL wait time.

9.2.31 DELAY2 (Address: 0x81Fh)
Name DELAY2 Reset R/W
W

Bit 7
WSEL2

Bit 6
WSEL1

Bit 5
WSEL0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1
RS_DLY1

AGC_DLY1 AGC_DLY0 RS_DLY2

0

0

0

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Bit 0
FD0

MCNTR: Divided by 2 select. [0]: PF8M = f MCNT / 2, where PF8M is one of baseband clock sources.

0

0

Bit 0
PDLY0

0

0

Bit 0
RS_DLY0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
WSEL[2:0]: Crystal Settling Delay setting (200us ~ 2.5ms). Recommend WSEL = [001].
AGC_DLY[1:0]: RSSI calibration switching time. (10us ~ 40us). Recommend AGC_D = [00].

[00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. RS_DLY [2:0]: RSSI Measurement Delay while in RX mode. Recommend RS_DLY = [000].
[000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us. [100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us.

9.2.32 RX (Address: 0x820h)
Name RX Reset R/W
W R

Bit 7
-ADCO8

Bit 6
AGCE --

Bit 5
BW1 --

Bit 4
BW0 --

Bit 3
RXDI --

Bit 2
DMG1 --

Bit 1

0

0

0

0

0

TI A
0 0 Bit 2
MVS0 ADCO2

DMG0 --

DMG[1:0]: Demodulator gain select.

ULS: RX Up/Low side band select. Recommend ULS = [0]. [0]: Up side band, TX A-terminal frequency – IF = RX B-terminal frequency [1]: Low side band, TX A-terminal frequency + IF = RX B-terminal frequency ADCO[8:0]: Digital RSSI, 9-bits, output when AGC is enabled. (Read Only).

Name ADCC Reset

R/W
W R

O

9.2.33 ADCC (Address: 0x821h)
Bit 7

M

Bit 6

C O

RXDI: RX data invert. [0]: Not inverterd. [1]: Invert.

Bit 5
AVS1 ADCO5

N

[00]: x1. [01]: x3. [1x]: x5.

FI D
Bit 4
AVS0 ADCO4

BW [1:0]: IF Band Pass Filter select. [00]: 50KHz. data rate ≦50Kbps. (Xtal shall be chosen ± 10 ppm stability in case of RX sensitivity degradation.) [01]: 100KHz. 50K < data rate ≦100Kbps. [10]: 150KHz. 100K < data rate ≦150Kbps. [11]: 250KHz. 150K < data rate ≦250Kbps.

EN
Bit 3
MVS1 ADCO3

AGCE: Auto Gain Control enable. [0]: Disable. [1]: Enable.

Bit 1
XADSR ADCO1

C

MXD ADCO7

RADC ADCO6

IC

0

0

0

0

0

0

A

RADC: ADC Read Out Average Mode. [0]: 1, 2, 4, 8 average mode. If RADC = 0, ADC average is set by AVSEL[1:0] (0Ah). [1]: 8, 16, 32, 64 average mode. If RADC = 1, ADC average is set by MVSEL[1:0] (0Ah). XADSR: ADC input signal source select. [0]: internal temperature sensor or RSSI signal. [1]: external signal source. CDM: RSSI measurement mode [0]: Single mode. [1]: Continuous mode. AVS[1:0]: ADC average mode [00]: No average. [01]: 2. [10]: 4. [11]: 8. MVS[1:0]: ADC average mode for VCO calibration and RSSI.
Dec. 2014, Version 0.5(Preliminary)

M

MXD: Mixer Bias Select enable. Recommend MXD = [1]. [0]: Disable. [1]: Enable.

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AMICCOM Electronics Corporation

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Bit 0
ULS --

0

Bit 0
CDM ADCO0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
[00]: 8. [01]: 16. [10]: 32. [11]: 64. ADCO[7:0]: ADCO[8:0]: Digital RSSI, 9-bits, output when AGC is enabled. (Read Only)

9.2.34 RXAGC1 (Address: 0x822h)
Name RXAGC1 Reset R/W
W R

Bit 7
VRSEL --

Bit 6
ERSSM --

Bit 5
LGM1 LGC1

Bit 4
LGM0 LGC0

Bit 3
MGM1 MGC1

Bit 2
MGM0 MGC0

Bit 1
IGM1 IGC1

Bit 0
IGM0 IGC0

VRSEL: AGC Function select. Recommend VRSEL = [1]. [0]: Reserved. [1]: AGC transition by an internal wideband amplify and detector. ERSSM : Ending for RSSI measurement. Recommend ERSSM = [0]. [0]: RSSI value frozen before leaving RX. [1]: RSSI value frozen when valid frame sync (ID and header check ok). MGM [1:0]: Mixer Gain select. Recommend MGM = [11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. LGM [1:0]: LNA Gain select. Recommend LGM = [11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. LGC[1:0]: LNA Gain Check (Read Only). MGC[1:0]: Mixer Gain Check (Read Only). IGC[1:0]: IF Amplifier Gain Check (Read Only).

9.2.35 RXAGC2 (Address: 0x823h)
Name RXAGC2 Reset R/W
W R

Bit 7
HDM RHM7

Bit 6

C O

Bit 5

N

FI D
Bit 4 Bit 3
MSCL3 RHM3

EN
Bit 2
MSCL2 RHM2

TI A
Bit 1
MSCL1 RHM1

0

M

EXRSI RHM6

MS RHM5

MSCL4 RHM4

0

0

0

0

0

A

MSCL[4:0]: AGC Manual Scale setting. Reserved, shall set MSCL = [00000]. RHM [7:0]: RSSI calibration high threshold level (Read Only).

9.2.36 RSSI (Address: 0x824h)
Name RSSI Reset R/W
W R

M

MS: AGC Manual Scale select. Recommend MS = [0]. [0]: Auto(RL-RH). [1]: MSCL(Manual).

IC

EXRSI: Reserved. Shall be [0].

C

HDM: AGC HOLD select. Recommend HDM = [0]. [0]: No hold. [1]: Hold Gain Switching when ID is sync

O

Bit 7
RTH7 ADC7

Bit 6
RTH6 ADC6

Bit 5
RTH5 ADC5

Bit 4
RTH4 ADC4

Bit 3
RTH3 ADC3

Bit 2
RTH2 ADC2

Bit 1
RTH1 ADC1

0

0

0

0

0

0

RTH[7:0]: Threshold value of Carrier Detect (Active in RX mode only). CD (Carrier Detect) =1 when RSSI < RTH. CD (Carrier Detect) =0 when RSSI ≧ RTH. 29

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Bit 0
MSCL0 RHM0

0

0

0

0

0

0

0

0

0

0

Bit 0
RTH0 ADC0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
ADC[7:0]: ADC value (Read Only).

9.2.37 AGCHT (Address: 0x825h)
Name AGCHT Reset R/W
W R

Bit 7
IRTH7 RLM7

Bit 6
IRTH6 RLM6

Bit 5
IRTH5 RLM5

Bit 4
IRTH4 RLM4

Bit 3
IRTH3 RLM3

Bit 2
IRTH2 RLM2

Bit 1
IRHT1 RLM1

Bit 0
IRTH0 RLM0

0

0

0

0

0

0

0

0

IRTH[7:0]: AGC high Threshold. Recommend IRTH = [0x05]. RLM [7:0]: RSSI calibration low threshold (Read Only).

9.2.38 AGCLT (Address: 0x826h)
Name AGCLT Reset R/W
W

Bit 7
IRTL7

Bit 6
IRTL6

Bit 5
IRTL5

Bit 4
IRTL4

Bit 3
IRTL3

TI A
Bit 2 0 Bit 1 0
IRTL2 IRTL1

EN
0 Bit 3
--

0

0

0

0

IRTL[7:0]: AGC low Threshold. Recommend IRTL = [0x03].

9.2.39 CODE1 (Address: 0x827h)
Name CODE1 Reset R/W
W

Bit 7
MCS

Bit 6
WHTS

Bit 5
FECS

FI D
Bit 4 0
CRCS

Bit 2
--

Bit 1
PML1

PML[1:0]: Preamble length in byte = PML+1.

[00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes.

9.2.40 CODE2 (Address: 0x828h)

M

A

Name

IC

CRCS: CRC selector. [0]: Bypass [1]: CRC enable.

C

R/W
W

O

FECS: FEC selector. [0]: Bypass [1]: FEC enable.

Bit 7
ETH2

M

WHTS: WHT selector. [0]: Bypass [1]: WHT enable.

Bit 6
ETH1

C O

MCS: Manchester code select. [0]: disable. [1]: Select.

Bit 5
ETH0

N

0

0

0

0

0

Bit 4
IDL1

Bit 3
IDL0

Bit 2
--

Bit 1
PMD1

CODE2 Reset

0

0

0

0

0

0

IDL[1:0]: ID length . [0]: 16 bits. [1]: 32 bits.

ETH[2:0]: Sync word error threshold. [000]: 0 bit. [001]: 1bit. [010]: 2 bits. [011]: 3 bits. [100]: 4 bits. [101]: 5 bits. [110]: 6 bits. [111]: 7 bits.
PMD[1:0]: Preamble pattern detection.

[00]: 0 bit [01]: 4 bits [10]: 8 bits [11]: 16 bits When DCM[1:0] = 01, 10, 11, PMD setting is active. 30

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Bit 0 0
IRTL0

Bit 0
PML0

0

0

Bit 0
PMD0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.41 CODE3 (Address: 0x829h)
Name CODE3 Reset R/W
W

Bit 7
MSCRC

Bit 6
WS6

Bit 5
WS5

Bit 4
WS4

Bit 3
WS3

Bit 2
WS2

Bit 1
WS1

Bit 0
WS0

0

0

0

0

0

0

0

0

WS [6:0]: Data Whitening Seed (data encryption key).
MSCRC: CRC data filtering enable. [0]: Disable. [1]: Enable.

9.2.42 IFC1 (Address: 0x82Ah)
Name IFC1 Reset R/W
W R

Bit 7
BGS --

Bit 6
CRCDNP --

Bit 5
CRCINV --

Bit 4
MFBS FBCF

Bit 3
MFB3 FB3

TI A
Bit 2 Bit 1
MFB2 FB2 MFB1 FB1

EN
0 0 Bit 3
ASMV2 FCD3

0

0

0

0

MFBS: IF Filter Calibration Select. Recommend MFBS = [0]. [0]: Auto. [1]: Manual.

MFB[3:0]: IF filter Manual Setting. Recommend MFB = [0000]. CRCDNP: CRC Mode. Shall be [0] CRCINV: CRC Inverted Select.

FBCF: IF Filter Auto Calibration Flag (Read Only). [0]: Pass. [1]: Fail.

9.2.43 IFC2 (Address: 0x82Bh)
Name IFC2 Reset R/W
W R

O

Bit 7
STS --

M

FB[3:0]: IF Filter Auto Calibration Result (Read Only).

Bit 6

C O

Bit 5
TRT1 --

N

FI D
Bit 4
TRT0 FCD4

BGS: Reserved for internal usage

Bit 2
ASMV1 FCD2

Bit 1
ASMV0 FCD1

C

TRT2 --

0

0

0

0

0

0

STS: Reserved. Shall be [0].

TRT [2:0]: TX Ramp down discharge current select. Recommend TRT =[000].

A

ASMV [2:0]: TX Ramp up Timing Select. Recommend ASMV =[111]. [000]: 2us, [001]: 4us. [010]: 6us. [011]: 8us. [100]: 10us, [101]: 12us. [110]: 14us. [111]: 16us. AMVS : PA Ramp Up Enable. Recommend AMVS = [1]. [0]: Disable. [1]: Enable. FCD [4:0]: IF Filter Auto Calibration Deviation from Goal (read only).

9.2.44 VCOCC (Address: 0x82Ch)
Name VCOCC R/W
W R

M

IC

Bit 7
SWT --

Bit 6
RGC[0] --

Bit 5
RGC[0] --

Bit 4
VCOC3 VCCF

Bit 3
VCCO2 VCB3

Bit 2
VCOC1 VCB2

Bit 1
VCOC0 VCB1

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Bit 0
MFB0 FB0

0

0

Bit 0
AMVS FCD0

0

0

Bit 0
MVCS VCB0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Reset 0 0 0 0 0 0 0 0

SWT: Reserved. Recommend SWT= [1]

RGC[1:0]: Reserved. Recommend RGC = [01]. VCOC [3:0]: VCO Current Bank Calibration result. If SWT = [0]: VCOC= [1000]. If SWT = [1]: VCOC[3:0] = Manual setting. Recommend VCOC = [0000]. Note: SWT is located at 0Fh. MVCS: VCO current calibration select. Recommend MVCS = [0]. [0]: Auto. [1]: Manual. VCO band calibration result can be read from VCB [3:0]. VCCF: VCO Current Auto Calibration Flag (Read Only). [0]: Pass. [1]: Fail. VCB [3:0]: VCO Current Bank Calibration Value (Read Only). If MVCS= 0 (bit 0), VCB [3:0] is auto calibration value. If MVCS= 1 (bit 0), VCB [3:0] is manual calibration value.

9.2.45 VCOBC1 (Address: 0x82Dh)
Name VCOBC1 Reset R/W
W R

Bit 7
---

Bit 6
---

Bit 5
-DVT1

FI D
Bit 4 Bit 3
VBS DVT0 MVBS VBCF

EN
Bit 2
MVB2 VB2

TI A
Bit 1
MVB1 VB1

0

0

0

N

0

0

0

VBS: VCO Band adjustment for 433MHz and 868MHz. [0]: For 315MHz / 470MHz / 915MHz band [1]: For 433MHz / 868MHz band

A

VB[2:0]: VCO Bank Auto Calibration Result (Read Only).

9.2.46 VCOBC2 (Address: 0x82Eh)
Name VCOBC2 Reset R/W
W

M

VBCF: VCO Band Auto Calibration Flag (Read Only). [0]: Pass. [1]: Fail.

IC

DVT[1:0]: VT output (Read Only). [00]: VT< VTL< VTH. [01]: VTL< VT< VTH. [10]: No used. [11]: VTL< VTH< VT.

C

O

MVB[2:0]: VCO bank manual setting. VCO frequency increases when MVB decreases. Recommend MVB = [000].

Bit 7
QDP

M

MVBS: VCO band calibration select. Recommend MVBS = [0]. [0]: Auto. [1]: Manual

Bit 6
INTXC

C O

Bit 5
VTL2

Bit 4
VTL1

Bit 3
VTL0

Bit 2
VTH2

Bit 1
VTH1

0

0

0

0

0

0

QDP: Reserved.

INTXC: Internal Crystal Load selection. Recommend INTXC = [1]. [0]: Use external capacitors. [1]: Use on-chip capacitors

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Bit 0
MVB0 VB0

0

0

Bit 0
VTH0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
VTL[2:0]: VT low threshold setting for VCO calibration. Recommend VTL = [100]. VTH[2:0]: VT high threshold setting for VCO calibration. Recommend VTH = [100].

9.2.47 PM (Address: 0x82Fh)
Name PM Reset R/W
W

Bit 7
--

Bit 6
RGAGC1

Bit 5
RGAGC0

Bit 4
XCL4

Bit 3
XCL3

Bit 2
XCL2

Bit 1
XCL1

Bit 0
XCL0

0

0

0

0

0

0

0

0

9.2.48 RFI (Address: 0x830h)
Name RFI Reset R/W
W

RF23D1

RF23D0

PRRC1

FI D
PRRC0 PRIC1

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

EN
Bit 3 0 Bit 2 0
PRIC0

XCL[4:0]: On-chip Crystal Capacitor Load setting. Set XCL = [10000] as the first value to fine tune the carrier frequency and minimize the frequency drift if Xtal Cload = 20pF. XCL is active when INTXC=1 and Each XCL step is typical 1.68 pF. XCL is the on-chip capacitor for Xtal oscillator to fine tune offset frequency of the wanted RF carrier. Please refer to chapter 11 or contact AMICCOM’s FAE.

TI A
Bit 1
RMP1

RXAGC[1:0]: Reserved. RSAGC shall be [00].

RF23D [1:0]: Reserved. PRRC [1:0]: RF divider by 2/3 current setting. PRIC [1:0]: Reserved.

RMP [1:0]: PA Ramp up/down Timing Scale setting. Recommend RMP = [00]. [00]: 1. [01]: 2. [10]: 4. [11]: 8.

Name XTST Reset

R/W
W

Bit 7 0

M

9.2.49 XTST

(Address: 0x831h)
QCLIM

Bit 6
--

C O

Bit 5
RXCC

N

Bit 4
RXCP1

Bit 3
RXCP0

Bit 2
XCC

Bit 1
XCP1

O

0

0

0

0

0

QCLIM: Reserved. Shall be [0].

A

XCP[1:0]: Crystal Regulating Couple setting. Recommend XCP = [00].

9.2.50 BD (Address: 0x832h)
Name BD Reset R/W
W R

M

XCC: Crystal Current setting. Recommend XCC = [0]. [0]: Low current. [1]: High current.

IC

RXCC: 32.768KHz Crystal Current setting. Recommend XCC = [0]. RXCP[1:0]: 32.768KHz Crystal Regulating Couple setting. Recommend XCP = [00].

C

Bit 7
CA1 --

Bit 6
CA0 --

Bit 5
RGV1 --

Bit 4
RGV0 VBD

Bit 3
BVT2 --

Bit 2
BVT1 --

Bit 1
BVT0 --

0

0

0

0

0

0

CA[1:0]: Reserved. Should be [00].

BVT [2:0]: Battery Voltage Threshold select.
[000]: 2.0V.

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Bit 0
RMP0

0

0

Bit 0
XCP0

0

0

Bit 0
BDS BODF

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
[001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.

9.2.51 TXT1 (Address: 0x833h)
Name TXT1 Reset R/W
W

Bit 7
TXDI

Bit 6
PAC1

Bit 5
PAC0

Bit 4
TDC1

Bit 3
TDC0

TI A
Bit 2 0 Bit 1 0
TBG2 TBG1

BDS: Battery Detection selection. [0]: Disable. [1]: Enable.

0

0

0

0

EN
0 Bit 3
LODV1

PAC[1:0]: PA current setting. Please refer to A9108 App. Note for programmable TX output power. TDC[1:0]: TX Driver current setting. Please refer to A9108 App. Note for programmable TX output power.

9.2.52 TXT2 (Address: 0x834h)
Name TXT2 Reset R/W
W

Bit 7
QDS

Bit 6 0

C O

TBG[2:0]: TX Buffer Gain setting. Please refer to A9108 App. Note for programmable TX output power.

Bit 5 0

N

FI D
Bit 4 0 Bit 2
LODV0

TXDI: TX data inverted. Recommend TXDI = [0]. [0]: normal. [1]: invert

Bit 1
TXIB1

0

M

RFT2

RFT1

RFT0

0

0

RFT [2:0]: RF Analog Pin Configuration. Recommend RFT= [000]. {XADS, RFT[2:0]} [0000] [0001] [0010] [0011] [0100] [0101] [0110] [0111] [1000] [1001] [1010] [1011] [1100] [1101] [1110] [1111]

C

O

BP_BG (Pin 19) Band-gap voltage Analog temperature voltage Band-gap voltage Analog temperature voltage BPF positive in phase output BPF positive quadrature phase output RSSI voltage RSSI voltage Band-gap voltage Analog temperature voltage Band-gap voltage Analog temperature voltage No connection No connection No connection No connection

RSSI (Pin 1) RSSI voltage RSSI voltage No connection No connection BPF negative in phase output BPF negative quadrature phase output No connection No connection External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source

A

LODV [1:0]: Reserved. Shall be [01]. TXIB[1:0]: Reserved.

M

IC

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Bit 0 0
TBG0

RGV [1:0]: Regulator Voltage select. Recommend RGV = [11]. [00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V.

Bit 0
TXIB0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.53 RXDEM1 (Address: 0x835h)
Name RXDEM1 Reset R/W
W

Bit 7
CST

Bit 6
DMT

Bit 5
MLP1

Bit 4
MLP0

Bit 3
SLF2

Bit 2
SLF1

Bit 1
SLF0

Bit 0
DMOS

0

0

0

0

0

0

0

0

MLP[1:0]: Symbol recovery loop setting after FSYNC. SLF[2:0]: Symbol recovery loop setting. DMOS: Demodulator over-sample select . [0]: x64. [1]: x32.

9.2.54 RXDEM2 (Address: 0x836h)
Name RXDEM2 Reset R/W
W/R

Bit 7
DCL2

Bit 6
DCL1

Bit 5
DCL0

FI D
Bit 4 0 Bit 3 0
DCM1 DCM0

EN
Bit 2
CSC2

TI A
Bit 1
CSC1

CST: DC average length selection. Shall be [0]. [0]: DC average length unchanged. [1]: DC average length halves.

DCL[2:0]: DC average length. Recommend DCL = [010].

DCM [1:0]: Demodulator DC estimation mode. Recommend DCM = [01]. [00]: DC average set by DCV[7:0],(09h). [01]: DC holds after preamble detected. [10]: DC holds after ID detected. [11]: DC value when chip receive specific data length (set by DCL[:2:0])..
CSC[1:0]: System Clock Divider setting.

FCSCK shall be set appropriately, otherwise, IF Filter calibration will be failure.

9.2.55 RXDEM3 (Address: 0x837h)

M

Name

IC

C

f CSCK ?

f MSCK CSC[2 : 0] ? 1

R/W
W

O

CSC is the clock divider of FMSCK to generate the wanted data clock and IF calibration clock where FMSCK is either from Xtal itself (CGS = 0) or from the internal CLK Generator (CGS = 1).

Bit 7
DCV7

M

Bit 6
DCV6

C O

Bit 5
DCV5

N

0

0

0

0

Bit 4
DCV4

Bit 3
DCV3

Bit 2
DCV2

Bit 1
DCV1

A

RXDEM3 Reset

0

0

0

0

0

0

DCV[7:0]: DC value setting.

This setting is only active when DCM (09h) = [00].

9.2.56 DRCK (Address: 0x838h)
Name DRCK Reset R/W
W/R

Bit 7
--

Bit 6
SDR6

Bit 5
SDR5

Bit 4
SDR4

Bit 3
SDR3

Bit 2
SDR2

Bit 1
SDR1

0

0

0

0

0

0

SDR[6:0]: System clock to 128*DCK ratio = SDR + 1.

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Bit 0
CSC0

DMT: Demodulator test bit. DMT shall be [0]. [0]: Normal mode. [1]: Test mode.

0

0

Bit 0
DCV0

0

0

Bit 0
SDR0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Data rate ? f system 1 ? 128 SDR[6 : 0] ? 1
R/W
W

where Fsystem is system clock.

9.2.57 RTC (Address: 0x839h)
Name DRCK Reset Bit 7
--

Bit 6
--

Bit 5
--

Bit 4
RTCOE

Bit 3
RTC1

Bit 2
RTC0

Bit 1
RTCI

Bit 0
RTCE

0

0

0

0

0

0

0

0

[0]: disable. [1]: enable.

RTCI: RTCO invert. Reserved. Shall be set to [0]. [0]: Non-inverted output.
[1]: Invert

RTC[1:0]: Reserved. Shall be set to [00]. [00]:250ms. [01]: 500ms [10]: 1sec. [11]:2sec RTCE: Internal / External 32.768k Hz oscillator selection. [0]: Internal. [1]: External.

9.2.58 ID0 (Address: 0x83Ah)
Name ID0 Reset
ID[63:0]: Device ID.

R/W
W/R

Bit 7
ID63

Bit 6
ID62

Bit 5
ID61

N
Bit 4
ID60

FI D
Bit 3
ID59

EN
Bit 2
ID58

TI A
Bit 1
ID57

RTCOE: RTC timer output enable. Reserved. Shall be set to [0].

0

C O

0

0

0

0

0

9.2.59 ID1 (Address: 0x83Bh)
Name ID1 Reset
ID[63:0]: Device ID.

R/W
W/R

Bit 7
ID55

M

Bit 6
ID54

Bit 5
ID53

Bit 4
ID52

Bit 3
ID51

Bit 2
ID50

Bit 1
ID49

Name ID2 Reset

IC

9.2.60 ID2 (Address: 0x83Ch)
R/W
W/R

C

O

0

0

0

0

0

0

Bit 7
ID47

Bit 6
ID46

Bit 5
ID45

Bit 4
ID44

Bit 3
ID43

Bit 2
ID42

Bit 1
ID41

A

ID[63:0]: Device ID.

9.2.61 ID3 (Address: 0x83Dh)
Name ID3 Reset R/W
W/R

M

0

0

0

0

0

0

Bit 7
ID39

Bit 6
ID38

Bit 5
ID37

Bit 4
ID36

Bit 3
ID35

Bit 2
ID34

Bit 1
ID33

0

0

0

0

0

0

ID[63:0]: Device ID.

9.2.62 ID4 (Address: 0x83Eh)
Name ID4 R/W
W/R

Bit 7
ID31

Bit 6
ID30

Bit 5
ID29

Bit 4
ID28

Bit 3
ID27

Bit 2
ID26

Bit 1
ID25

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Bit 0
ID56

0

0

Bit 0
ID48

0

0

Bit 0
ID40

0

0

Bit 0
ID32

0

0

Bit 0
ID24

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Reset
ID[63:0]: Device ID.

0

0

0

0

0

0

0

0

9.2.63 ID5 (Address: 0x83Fh)
Name ID5 Reset
ID[63:0]: Device ID.

R/W
W/R

Bit 7
ID23

Bit 6
ID22

Bit 5
ID21

Bit 4
ID20

Bit 3
ID19

Bit 2
ID18

Bit 1
ID17

Bit 0
ID16

0

0

0

0

0

0

0

0

9.2.64 ID6 (Address: 0x840h)
Name ID6 Reset
ID[63:0]: Device ID.

R/W
W/R

Bit 7
ID15

Bit 6
ID14

Bit 5
ID13

Bit 4
ID12

Bit 3
ID11

TI A
Bit 2
ID10

Bit 1
ID9

Name ID7 Reset
ID[63:0]: Device ID.

R/W
W/R

Bit 7
ID7

Bit 6
ID6

Bit 5
ID5

FI D
Bit 4
ID4

9.2.65 ID7 (Address: 0x841h)

EN
Bit 3
ID3

0

0

0

0

0

0

Bit 2
ID2

Bit 1
ID1

0

0

0

0

0

0

Name DID0 Reset
DID[31:0]: Device ID.

R/W
R

Bit 7
DID31

Bit 6 0

C O

9.2.66 DID0 (Address: 0x842h)

Bit 5 0

N

Bit 4 0

Bit 3
DID27

Bit 2
DID26

Bit 1
DID25

DID30

DID29

DID28

0

0

0

Name DID1 Reset

R/W
R

O

9.2.67 DID1 (Address: x843h)
Bit 7 0
DID23

M

Bit 6 0

Bit 5
DID21

Bit 4
DID20

Bit 3
DID19

Bit 2
DID18

Bit 1
DID17

C

DID22

0

0

0

0

DID[31:0]: Device ID.

M

9.2.68 DID2 (Address: x844h)
Name DID2 Reset R/W
R

IC

Bit 7
DID15

Bit 6
DID14

Bit 5
DID13

Bit 4
DID12

Bit 3
DID11

Bit 2
DID10

Bit 1
DID9

A

0

0

0

0

0

0

DID[31:0]: Device ID.

9.2.69 DID3 (Address: x845h)
Name DID3 Reset
DID[31:0]: Device ID.

R/W
R

Bit 7
DID7

Bit 6
DID6

Bit 5
DID5

Bit 4
DID4

Bit 3
DID3

Bit 2
DID2

Bit 1
DID1

0

0

0

0

0

0

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Bit 0
ID8

0

0

Bit 0
ID0

0

0

Bit 0
DID24

0

0

Bit 0
DID16

0

0

Bit 0
DID8

0

0

Bit 0
DID0

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.70 ADCCTL (Address: x858h)
Name ADCCTL Reset R/W
W R

Bit 7
---

Bit 6
CKS[1] --

Bit 5
CKS[0] --

Bit 4
MODE MODE

Bit 3
MVS[2] MVS[2]

Bit 2
MVS[1] MVS[1]

Bit 1
MVS[0] MVS[0]

Bit 0
ADCE ADCE

0

0

0

0

0

0

0

0

9.2.71 ADCAVG1 (Address: x859h)
Name ADCAVG1 Reset R/W
W R

Bit 7

Bit 6

C O

CKS[1:0]: ADC source clock select. [00]: 4 MHz. [01]: 2 MHz. [10]: 1 MHz. [11]: 500 KHz.

Bit 5

N
Bit 4 Bit 3
-ADC[11]

FI D
Bit 2
-ADC[10]

MODE: ADC mode select. [0]: Single mode. [1]: Continuous mode.

EN
Bit 1
-ADC[9]

MVS[3:0]: ADC average mode select. [000]: No moving average [001]: 2 times average mode. [010]: 4 times average mode. [011]: 8 times average mode. [100]: 16 times average mode. [101]: 32 times average mode. [110]: 64 times average mode. [111]: 128 times average mode.

TI A
Bit 0
-ADC[8] -MVADC[8]

0

M

---MVADC[11] MVADC[10] MVADC[9]

0

0

0

0

0

ADC[11:0]: ADC value. MVADC[11:0]: Moving average ADC value.

9.2.72 ADCAVG2 (Address: x85Ah)
Name

IC

C

R/W
W R

O

Bit 7

Bit 6
MVADC[6]

Bit 5
MVADC[5]

Bit 4
MVADC[4]

Bit 3
MVADC[3]

Bit 2
MVADC[2]

Bit 1
MVADC[1]

ADCAVG2 Reset

M

MVADC[7]

0

0

0

0

0

0

A

MVADC[11:0]: Moving average ADC value.

9.2.73 ADCAVG3 (Address: x85Bh)
Name ADCAVG3 Reset ADC[11:0]: ADC value. R/W
W R

Bit 7
-ADC[7]

Bit 6
-ADC[6]

Bit 5
-ADC[5]

Bit 4
-ADC[4]

Bit 3
-ADC[3]

Bit 2
-ADC[2]

Bit 1
-ADC[1]

0

0

0

0

0

0

9.2.74 TMRINV (Address: 0x85Ch)
Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

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0 0 Bit 0
MVADC[0]

ADCE: 12-bit ADC Enable. [0]: Disable. [1]: Enable. (auto clear when MODE = 0)

0

0

Bit 0
-ADC[0]

0

0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
TMRINV Reset
W/R TMR_INV[7:0]

0

0

0

0

0

0

0

0

9.2.75 TMRCTL (Address: 0x85Dh)
Name TMRCTL Reset R/W
W

Bit 7
TMRON

Bit 6
TMRIE

Bit 5
TMRIF

Bit 4
--

Bit 3 0

TI A
Bit 2 0 Bit 1 0
TMRCKS[2:0]

TMR_INV[7:0]: Timer interval setting. Timer interval can be set to be: TMRCKS[2:0] = 000: 7.808ms ~ 2s TMRCKS[2:0] = 001: 16.616ms ~ 4s TMRCKS[2:0] = 010: 31.232ms ~ 8s TMRCKS[2:0] = 011: 62.464ms ~ 1.6ms TMRCKS[2:0] = 100: 124.925ms ~ 3.18s TMRCKS[2:0] = 101: 249.856ms ~ 6.37s TMRCKS[2:0] = 110: 499.712ms ~ 12.74s TMRCKS[2:0] = 111: 1s ~ 254.8s

EN
Bit 3 0 Bit 2 0
CTR[5:0]

0

0

0

0

Name EXT1 Reset

R/W
W

O

9.2.76 EXT1 (Address: 0x85Eh)
Bit 7 0

M

TMRCE: Start Timer counting. [0]: Stop. [1]: Start.

Bit 6 0

C O

TMRON: TMRCK ON. TMRIE: Timer Interrupt Enable.(NO USE -> SWTMRINT) TMRIF: Timer Interrupt Flag. (Write to clear) TMRCKS[2:0]: Select Timer Source Clock [000]: 128Hz [001]: 64Hz [010]: 32Hz [011]: 16Hz [100]: 8Hz [101]: 4Hz [110]: 2Hz [111]: 1Hz

Bit 5 0

N

FI D
Bit 4 0 Bit 1 0 Bit 0 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1
CBG[2:0]

CTR [5:0]: ADC voltage fine trim setting.

M

9.2.77 EXT2 (Address: 0x85Fh)
Name EXT2 Reset R/W
W

IC

C

Bit 7 0

Bit 6 0

Bit 5
FBG[4:0]

A

0

FBG[4:0]: Bandgap voltage fine trim setting. CBG[2:0]: Reserved for internal usage.

9.2.78 EXT3 (Address: 0x860h)
Name EXT3 Reset R/W
W

Bit 7
--

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

STM[5:0]

0

STM [5:0]: Reserved. (no used)

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Bit 0 0
TMRCE

Bit 0 0

0

Bit 0 0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
9.2.79 EXT4 (Address: 0x861h)
Name EXT4 Reset R/W
W

Bit 7
CSLP

Bit 6
RSLP

Bit 5
INTLP

Bit 4
--

Bit 3
--

Bit 2
--

Bit 1
--

Bit 0
RGS

0

0

0

0

0

0

0

0

9.2.80 EXT5 (Address: 0x862h)
Name EXT5 Reset R/W
W

Bit 7 0

Bit 6 0

Bit 5 0

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Bit 4 0 Bit 3
XEC PDNS

RGS: VDD_D voltage setting in Sleep mode. [0]: 1.8V. [1]: 1.6V.

EN
Bit 2
ENDL[2]

NTLP: Internal loop filter enable [0]: Disable [1]: Enable

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Bit 1
ENDL[1]

CSLP[1:0]: Internal loop filter resister select [0 0]: C=4pF [0 1]: C=6pF [1 0]: C=8pF [1 1]: C=10pF RSLP: Internal loop filter resister select [0]: R=2k ohm [1]: R=1k ohm

N

0

0

PDNS: Power manager to turn on REGOD Recommend PDNS = [0] XEC: Reserved. Should set to [1]

ENDL[2:0]: Reserved for internal usage only

9.2.81 PWRCTL (Address: 0x863h)
Name PWRCTL Reset R/W
W

O

Bit 7 0

M

Bit 6 0

C O

Bit 5
QDSA

Bit 4
ENDV

Bit 3
QDSD

Bit 2
CEL

Bit 1
SVREF

EBOD

ENAV

EBOD: Reserved for internal usage.

ENAV: REGOA and REGOD connection. Reserved for internal usage. [1]: REGOA is connected to REGOD. QDSA: Reserved for internal usage.

A

ENDV: Reserved for internal usage.

QDSD: Reserved for internal usage. CEL: Digital voltage select in standby mode. Recommend CEL = [0]. SVREF: Reserved for internal usage. CELA: Reserved for internal usage.

9.2.82 INTSW (Address: 0x864h)
Name PWRCTL R/W
W

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IC

C

0

0

0

0

Bit 7
--

Bit 6
--

Bit 5
--

Bit 4
--

Bit 3
SWINT50

Bit 2
SWINTT0

Bit 1

SWINTT1 SWTMRINT

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Bit 0
ENDL[0]

0

0

Bit 0
CELA

0

0

Bit 0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Reset 0 0 0 0 0 0 0 0

SWINT50: switch adc12b interrupt Enable SWINTT0: switch A9108 baseband INTT0 interrupt Enable SWINTT1: switch A9108 baseband INTT1 interrupt Enable SWTMRINT: switch Timer interrupt Enable

9.2.83 TX5DY (Address: 0x865h)
Name TX5DY Reset R/W
W

Bit 7
--

Bit 6
--

Bit 5
--

Bit 4 0

Bit 3 0

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Bit 2 0 Bit 1 0

TX_5DLY[4:0]

0

0

0

TX_5DLY [4:0]: TX data output delay timing after PDN_TX enable.

A

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C

O

M

C O

N

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Bit 0 0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
10.SOC Architectural Overview
A9108 microcontroller is instruction set compatible with the industry standard 8051. Besides FSK/GFSK modulation RF transceiver, A9108 integrates many features, three 8/16bit counters/timers, watchdog timer, RTC, UART, SPI interface, I 2C interface, 2 channels PWM, 4 channels ADC, battery detector and CODEC function. The interrupt controller is extended to support 6 interrupt sources; watchdog timer, RTC, SPI, I2C, ADC, RF and AES engine. A9108 includes TTAG (2-wire) debug circuitry that provides full time, real-time, in-circuit debugging.

Clock to Execute Number of instructions

1 24

2 38

3 29

EN
4 5 8 11

A9108 microcontroller has pipelined RSIC architecture 10 times faster compared to standard 8051 architecture. The pipeline 8051 is fully compatible with the MCS-51TM instruction set. User can use standard 8051 assemblers and compilers to develop software. The pipelined architecture 8051 has greatly increases its instruction throughput over the standard 8051 architecture. A9108 has a total of 110 instructions. The table below shows the total number of instructions that require each execution time. For more detail information of instruction, please refer Table 10.1. 6 1

10.2 Memory Organization

0x3FFF

C O

Program /Data memory (FLASH) 2KBytes Data Storage
(In-System programmable in 512 bytes sector)

External Data address space

N

The memory organization of A9108 is similar to the standard 8051. The memory organization is shown as figure 10.1

FI D
0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00

0x3800 0x37FF

M

Special Function Registers
(Direct addressing only

C

O

0x09BF 0x0900 0x0800 0x07FF

RF FIFO
RX:0x980~9BF TX:0x900~93F

IC

RF Register XRAM 2KBytes
(accessable using MOVX instruction)

Direct and Indirect Addressing

M

Bit Addressable General Purpose Registers

A

0x0000

0x0000

Figure 10.1 Memory Organization

10.2.1 Program memory
The standard 8051 core has 64KB program memory space. A9108 implements 16KB flash in one 16x 8Kb flash macro. The last 2KB prhogram memory space (0x 3800 ~ 0x3FFF) supports IAP (In-Application Programming) function. The each block size in this area is 128Bytes. User has 16 blocks in 2KB program memory space to storage data. Program memory is normally assumed to be read-only. However, A9108 can write to program memory by IAP function call. Please reference xxxxx to write program memory.

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Internal Data Space

10.1 Pipeline 8051 CPU

L
Upper 128 RAM
(Indirect Adressing Only)

Low 128 Bytes RAM
(Direct and Indirect Addressing )

A9108
Sub1GHz FSK/GFSK Transceiver SOC
10.2.2 Data memory
The A9108 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 10.1 illustrates the data memory organization of the A9108.

10.2.3 General Purpose Registers

10.2.4 Bit Addressable Locations

10.2.6 Stack

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A9108 has 8-bit stack point called SP (0x81) located in the internal RAM space. It is incremented before data is stored during PUSH and CALL execution and decremented after data is popped during POP, RET and RETI execution. In the other words it always points to the last valid stack byte. The SP is accessed as any other SFRS. Address/Name 81h SP Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 1 1 1

A

C

O

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51? instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table xxx, for a detailed description of each register.

M

10.2.7 Data Pointer Register
A9108 are implemented dual data pointer registers, auto increment and auto decrement to speed up data block copying. DPTR0 and DPTR1 are located at four SFR addresses. Active DPTR register is selected by SEL bit (0x86.0). If SEL = 0 the DPTR0 is selected otherwise DPTR1. Address/Name 82h DPL0
Dec. 2014, Version 0.5(Preliminary)

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

C O

10.2.5 Special Function Registers

Stack pointer register

N
43

In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51? assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h ;moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.

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AMICCOM Electronics Corporation

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The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.4). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
Reset 0 0 0 0 0 0 0 0

Address/Name 83h DPH0 Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 Data Pointer Register DPTR0 0 0 0

R/W 0 0 0 0 0 0

Address/Name 85h DPH1 Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

A

Table DPTR0, DPTR1 operations Selected data pointer register in used in the following instructions: MOVX @DPTR,A MOVX A,@DPTR MOVC A,A+DPTR JMP @A+DPTR INC DPTR MOV DPTR,#data16
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AU ‐When set to '1' performs automatic increment(0)/ decrement(1) of selected DPTR according to IDx bits, after each MOVX @DPTR, MOVC @DPTR instructions SEL ‐ Select active data pointer – see table below ‐ ‐ Unimplemented bit. Read as 0 or 1.

C

O

ID[1:0] ‐ Increment/decrement function select. See table below. TSL ‐ Toggle select enable. When set, this bit allows the following DPTR related instruction to toggle the SEL bit following execution of the instruction: MOVC A, @A+DPTR INC DPTR MOVX @DPTR, A MOVX A, @DPTR MOV DPTR, #data16 When TSL=0, DPTR related instructions do not affect state of SEL bit.

M

C O

0 0 0 0 Data Pointers Select Register

N
44

Address/Name 86h DPS Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W ID1 ID0 TSL AU 0 SEL 0

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0 0 0 0 0 Data Pointer 1 Register DPTR1

EN
0 0 0

AMICCOM Electronics Corporation

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0 0 0

Address/Name 84h DPL1 Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

L

A9108
Sub1GHz FSK/GFSK Transceiver SOC
10.2.8 RF Registers, RF FIFO
RF registers are RF radio control registers and located in 0x0800 ~ 0x08ff. Please refer the section 9.2 and the related function setting in the datasheet. A9108 has 256 Bytes FIFO located from 0x0900 to 0x09FF. There are 128 bytes FIFO from 0x0900 ~ 0x097F for data transmitting. There are 128 bytes FIFO from 0x0980 ~ 0x09FF for data receiving.

10.2.9 CODEC Registers
A9108 integrates CODEC function and handle audio steaming transition. Please refer Chapter 9.3 and Chapter 17 for more detail.

A9108 use a high performance, pipeline 8051 core and it is fully compatible with the standard MCS-51TM instruction set. Standard 8051 development tools can used to develop software for A9108. All A9108 instruction sets are the binary and functional equivalent of the MCS-51TM. However, instruct timing is different with the standard 8051. All instruction timings are specified in the terms of clock cycles as shown in the table 10.1

Mnemonic ACALL addr11 ADD A,#data ADD A,@Ri ADD A,direct ADD A,Rn ADDC A,#data ADDC A,@Ri ADDC A,direct ADDC A,Rn AJMP addr11 ANL C,/bit ANL A,#data ANL A,@Ri

Description Absolute subroutine call

EN
Code

Add immediate data to accumulator Add indirect RAM to accumulator Add direct byte to accumulator Add register to accumulator

FI D

0x11‐0xF1 0x24 0x26‐0x27 0x25 0x28‐0x2F 0x34 0x36‐0x37 0x35 0x38‐0x3F

N

Add immediate data to A with carry flag Add indirect RAM to A with carry flag Add direct byte to A with carry flag

C O

M

Add register to accumulator with carry flag Absolute jump

0x01‐0xE1 0xB0 0x54 0x56‐0x57 0x55 0x58‐0x5F 0x82 0x53 0x52 0xB6‐0xB7 0xB4 0xB5 0xB8‐0xBF 0xE4 0xC2 0xC3

O

AND complement of direct bit to carry AND immediate data to accumulator AND indirect RAM to accumulator AND direct byte to accumulator AND register to accumulator AND direct bit to carry flag AND immediate data to direct byte AND accumulator to direct byte Compare immediate to ind. and jump if not equal Compare immediate to A and jump if not equal Compare direct byte to A and jump if not equal Compare immediate to reg. and jump if not equal Clear accumulator Clear direct bit Clear carry flag

C

IC

ANL A,direct ANL A,Rn ANL C,bit

M

ANL direct,#data ANL direct,A CJNE @Ri,#data CJNE A,#datare CJNE A,directre CJNE Rn,#datar CLR A CLR bit CLR C

A

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Bytes 2 2 1 2 1 2 1 2 1 2 2 2 1 2 1 2 3 2 3 3 3 3 1 2 1 Cycles 4 2 2 2 1 2 2 2 1 3 2 2 2 2 1 2 3 3 5 4 5 4 1 3 1

10.3 Instruction set

L

A9108
Sub1GHz FSK/GFSK Transceiver SOC
CPL A CPL bit CPL C DA A DEC @Ri DEC A DEC direct DEC Rn DIV A,B DJNZ direct,rel DJNZ Rn,rel INC @Ri INC A INC direct INC Rn INC DPTR JB bit,rel JBC bit,directre JC rel JMP@A+DPTR JNB bit,rel JNC JNZ rel JZ rel Complement accumulator Complement direct bit Complement carry flag Decimal adjust accumulator Decrement indirect RAM Decrement accumulator Decrement direct byte Decrement register Divide A by B Decrement direct byte and jump if not zero Decrement register and jump if not zero Increment indirect RAM Increment accumulator Increment directbyte Increment register Increment data pointer Jump if direct bit is set 0xF4 0xB2 0xB3 0xD4 0x16‐0x17 0x14 0x15 0x18‐0x1F 0x84 1 2 1 1 2 1 1 1 1 3 2 1 1 2 1 1 3 3 2 1 3 2 2 2 3 3 1 2 2 1 2 2 2 1 2 3 2 1 3 1 3 3 1 3 2 6 5 4 3 1 3 2 1 5 5 3 5 5 3 4 4 4 4 2 3 2 2 3 2 2 1 2 3 3

FI D
46

N

Jump if carry flag is set

C O

Jump if direct bit is set and clear bit

Jump indirect relative to the DPTR Jumpifdirectbitisnotset

M

Jump if carry flag is not set Jump if accumulator is not zero Jump if accumulator is zero Long subroutine call Long jump Move indirect RAM to accumulator Move carry flag to direct bit Move immediate data to indirect RAM Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to accumulator Move direct byte to accumulator Move register to accumulator Move direct bit to carry flag Move immediate data to direct byte Move indirect RAM to direct byte

O

LJMP addr16 MOV A,@Ri MOV bit,C

C

LCALL addr16

IC

M

MOV @Ri,#data MOV @Ri,A MOV @Ri,direct MOV A,#data MOV A,direct MOV A,Rn MOV C,bit MOV direct,#data MOV direct,@Ri

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0xD8‐0xDF 0x06‐0x07 0x04 0x05 0x08‐0x0F 0xA3 0x20 0x10 0x40 0x73 0x30 0x50 0x70 0x60 0x12 0x02 0xE6‐0xE7 0x92 0x76‐0x77 0xF6‐0xF7 0xA6‐0xA7 0x74 0xE5 0xE8‐0xEF 0xA2 0x75 0x86‐0x87

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0xD5

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
MOV direct,A MOV direct,Rn MOV direct1,direct2 MOV DPTR,#data16 MOV Rn,#data MOV Rn,A MOV Rn,direct MOVC A,@A+DPTR MOVC A,@A+PC MOVX @DPTR,A MOVX @Ri,A MOVX A,@DPTR MOVX A,@Ri MUL A,B NOP ORL direct,A ORL A,#data ORL A,@Ri ORL A,direct ORL A,Rn ORL C,/bit ORL C,bit ORL direct,#data POP direct PUSH direct RET RETI Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Load 16‐bit constant in to active DPTR Move immediate data to register Move accumulator to register Move direct byte to register Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move A to external SRAM (16‐bitaddress) Move A to external RAM (8‐bitaddress) Move external RAM (16‐bitaddress) to A Move external RAM (8‐bitaddress) to A Multiply A and B No operation 0xF5 0x88‐0x8F 0x85 0x90 0x78‐0x7F 0xF8‐0xFF 0xA8‐0xAF 0x93 0x83 2 2 3 3 2 1 2 1 1 1 1 1 1 1 1 2 2 1 2 1 2 2 3 2 2 1 1 1 1 1 1 1 2 2 1 2 2 2 2 3 3 2 1 3 5 4 1 2 2 2 2 1 3 2 2 2 1 2 2 3 2 3 4 4 1 1 1 1 1 3 3 2 2 2

FI D

OR accumulator to direct byte

OR immediate data to accumulator

N
47

OR direct byte to accumulator OR register to accumulator

C O

OR indirect RAM to accumulator

OR complement of direct bit to carry

M

OR direct bit to carry flag OR immediate data to direct byte Pop direct byte from internal ram stack Push direct byte on to internal ram stack Return from subroutine Return from interrupt Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Set carry flag Set direct bit Short jump (relative address) Subtract indirect RAM from A with borrow Subtract direct byte from A with borrow Subtract immediate data from A with borrow

O

C

IC

M

RL A

RLC A RR A

A

RRC A SETB C SETB bit SJMP rel SUBB A,@Ri SUBB A,direct SUBB A,#data

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EN
0xF2‐0xF3 0xE0 0xE2‐0xE3 0xA4 0x00 0x42 0x44 0x46‐0x47 0x45 0x48‐0x4F 0xA0 0x72 0x43 0xD0 0xC0 0x22 0x32 0x23 0x33 0x03 0x13 0xD3 0xD2 0x80 0x96‐0x97 0x95 0x94

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0xF0

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
SUBB A,Rn SWAP A XCH A,@Ri XCH A,direct XCH A,Rn XCHD A,@Ri XRL direct,#data XRL A,#data XRL A,@Ri XRL A,direct XRL A,Rn XRL direct,A Subtract register from A with borrow Swap nibbles within the accumulator Exchange indirect RAM with accumulator Exchange direct byte with accumulator Exchange register with accumulator Exchange low‐order nibble indirect RAM with A ExclusiveOR immediate data to direct byte ExclusiveOR immediate data to accumulator ExclusiveOR indirect RAM to accumulator ExclusiveOR direct byte to accumulator ExclusiveOR register to accumulator ExclusiveOR accumulator to direct byte 0x98‐0x9F 0xC4 0xC6‐0xC7 0xC5 0xC8‐0xCF 0xD6‐0xD7 0x63 0x64 1 1 1 2 1 1 3 2 1 2 1 2 1 1 3 3 2 3 3 2 2 2 1 3

0x66‐0x67 0x65

Table 10.1 Instruction set sorted by alphabet

10.4 External interrupt handler

10.4.1 FUNCTIONALITY

IC

C

All 8051 IP cores have implemented two levels interrupt priority control. Each external interrupt can be in high or low level priority group by setting or clearing a bit in the IP(0xB8), EIP(0xF8), and DEVICR(0xCF) registers. External interrupt pins are activated at low level or by a falling edge. Interrupt requests are sampled each system clock at the rising edge of CLK. Interrupt flag IE0 TF0 IE1 TF1 TI0 & RI0 TF2 INT2F INT3F INT4F RFINT KEYINT WDIF I2CMIF I2CSIF SPIIF Function Active level/edge Low/falling Low/falling Low Low Low Flag resets Hardware Hardware Hardware Hardware Software Software Hardware Hardware Hardware Software Software Software Software Software Vector 0x03 0x0B 0x13 0x1B 0x23 0x2B 0x3B 0x43 0x4B 0x53 0x5B 0x63 0x6B 0x73
1

O

M

Name ACTIVE TYPE DESCRIPTION int0(P3.2) low/falling Input External interrupt 0 line int1(P3.3) low/falling Input External interrupt 1 line int2(P0.7) low Input External interrupt 2 line RF_int failing Key_int failing Table 10.2 External interrupts pins description

C O

N

This section describes 8051 external interrupts and their functionality. For peripheral related interrupts, please refer to an appropriate peripheral section. The external interrupts symbol is shown in figure above. And the pins functionality is described in the following table. All pins are one directional. There are no three-state output pins and internal signals.

FI D

EN
0x68‐0x6F 0x62

Device pin INT0 Internal, Timer 0 Device pin INT1 Internal, Timer 1 Interrupt, UART0 Interrupt, Timer 2 Device pin INT2 Interrupt flag for VOX detected Interrupt flag for ADC and DAC Interrupt, RF Interrupt, Key Internal, Watchdog Internal, I2C MASTER MODULE Internal, DI2CS/ Internal, SPI

A

1-

Table10.3 8051 interrupts summary This is a default location when IRQ_INTERVAL = 8, in other case is equal to (IRQ_INTERVAL* n ) + 3, when n = (natural Priorit y - 1)

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Natural priority 1 2 3 4 5 6 8 9 10 11 12 13 14 15

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
Each interrupt vector can be individually enabled or disabled by setting or clearing a corresponding bit in the IE(0xA8), EIE(0xE8), DEVICR(0xCF). The IE contains global interrupt system disable(0) / enable(1) bit called EA. IE register (0xA8) Address/Name A8h IE Reset EA:Enable global interrupts EX0:Enable INT0 interrupts ET0:Enable Timer 0 interrupts EX1:Enable INT1 interrupts ET1:Enable Timer 1 interrupts ES0:Enable UART0 interrupts ET2:Enable Timer 2 interrupts R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EA 0 0 ET2 0 ES0 0 ET1 0 EX1 0 ET0 0 EX0

IP register (0xB8) Address/Name B8h IP Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W PT2 0 PS0 0 PT1 0 PX1 0 PT0 0 PX0 0

TCON register

M

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(0x88)

C

PX0:INT0 priority level control (at 1-high-level) PT0:Timer 0 priority level control (at 1-high-level) PX1:INT1 priority level control (at 1-high-level) PT1:Timer 1 priority level control (at 1-high-level) PS0:UART0 priority level control (at 1-high-level) PT2:Timer 2 priority level control (at 1-high-level)

A

Address/Name 88h TCON Reset

O

M

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W TF1 0 TR1 0 TF0 0 TR0 0 IE1 0 IT1 0 IE0 0 IT0 0

IT0:INT0 level (at 0) / edge (at 1) sensitivity IT1:INT1 level (at 0) / edge (at 1) sensitivity IE0:INT0 interrupt flag Cleared by hardware when processor branches to interrupt routine IE1:INT1 interrupt flag Cleared by hardware when processor branches to interrupt routine TF0:Timer 0 interrupt (overflow) flag Cleared by hardware when processor branches to interrupt routine TF1:Timer 1 interrupt (overflow) flag

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0

N
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All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The exceptions of this rule are the request flags IE0 and lE1. If the external interrupts 0 or 1 are programmed to be level activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request flag IE0 and/or lE1. The same exception is related to INT2F, INT3F, INT4F, INT5F, and INT6F – external interrupts number 2, 3, 4, 5, 6.

AMICCOM Electronics Corporation

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0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Cleared by hardware when processor branches to interrupt routine SCON0 register (0x98) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TI0 0 Bit 0 RI0 0

EIE register

(0xE8)

EIP register

(0xF8)

EIF register

A

Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 91h I2CSF R/W I2CMF INT6F INT5F INT4F INT3F INT2F EIF SPIF Reset 0 0 0 0 0 0 0 0 INT2F:INT2 interrupt flag Should be cleared by external hardware when processor branches to interrupt routine. This bit is a copy of INT2 pin updated every CLK period. It cannot be set by software. INT3F:Interrupt flag for VOX The signal for detect VOX and it is inverted than connected to INT3. If this bit is ‘1’ it means VOX occurred. INT4F*:Interrupt flag for ADC and DAC The signals of ADC and DAC are OR-wired and it is inverted than connected to INT4. If this bit is ‘1’, it means ADC or DAC occurred. Please check ADCSTAT and DACSTAT for

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Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F8h PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 EIP PSPI Reset 0 0 0 0 0 0 0 0 PINT2:INT2 priority level control (at 1-high-level) PINT3:INT3 (at 1-high-level) PINT4:INT4 (at 1-high-level) PRFINT:RFINT priority level control (at 1-high-level) PKEYINT:KEYINT priority level control (at 1-high-level) PWDI:Watchdog priority level control (at 1-high-level) PI2CM:I2C MASTER MODULE priority level control (at 1-high-level) PI2CS:I2C MODULE priority level control (at 1-high-level) PSPI:SPI MODULE priority level control (at 1-high-level) (0x91)

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Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E8h EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 EIE ESPI Reset 0 0 0 0 0 0 0 0 EINT2:Enable INT2 interrupts EINT3:Enable INT3 EINT4:Enable INT4 ERFINT:Enable RF INT EKEYINT:Enable KEY INT EWDI:Enable Watchdog interrupts EI2CM:Enable I2C MASTER MODULE interrupts EI2CS:Enable DI2CS interrupts ESPI:Enable SPI MODULE interrupts

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Address/Name R/W 98h R/W SCON0 Reset RI0:UART0 receiver interrupt flag TI0:UART0 transmitter interrupt flag

SM00 SM01 SM02 REN0 TB08 RB08 0 0 0 0 0 0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
RFINT:RFINT interrupt flag Must be cleared by software writing 0x08 when controlled by INT5 pin, else must be cleared by software writing 0x08 when Compare2 is enabled CCEN[5:4]=10. It cannot be set by software. KEYINT:KEYINT interrupt flag Must be cleared by software writing 0x10 when controlled by INT6 pin, else must be cleared by software writing 0x10 when Compare3 is enabled CCEN[7:6]=10. It cannot be set by software. I2CMIF:I2C MASTER MODULE interrupt flag. Must be cleared by software writing 0x40. It cannot be set by software I2CSIF:I2C MODULE interrupt flag SPIIF:SPI MODULE interrupt flag Software should determine the source of interrupt by checking both modules ’ interrupt related bits. Must be cleared by software writing 0x80. It cannot be set by software.
Note2: A peripheral related bit is available if this peripheral device is included in the system. Can be modified upon request. Please check your configuration.

Key interrupt

10.5 Reset Circuit
RSFLAG (0xBA): Address/Name BAh RSFLAG Reset PORF (power-on reset flag) = 1: Occurred Power-on Reset = 0: No Power-on Reset RESETNF (resetn flag) = 1: Occurred ResetN reset = 0: No ResetN resetno resetn reset BODF (Low voltage detect) flag = 1: Occurred Low Voltage Reset = 0: No Low Voltage reset R/W R Bit 7 -

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Bit 4 Bit 3 0 Bit 2 Bit 1 Bit 0 BODF RESETNF PORF 0 0 0 0 51

1. P0 / P1 ==> 1 個 wakeup bit, control 2 個 pin. 2. P3 ==> 1 個 wakeup bit, control 1 個 pin.

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Please refer the figure 10.3 and 10.4 for the timing diagram for stable power of reset signal and internal behavior of CPU.

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SPIIF:SPI MODULE interrupt flag Software should determine the source of interrupt by checking both modules ’ interrupt related bits. Must be cleared by software writing 0x80. It cannot be set by software.

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Sub1GHz FSK/GFSK Transceiver SOC

XOUT

T RST1 RESETN
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2046 Crystal Clock Cycles

T RST1 : According to RESETN’s RC delay (standard module is about 50ms)
Figure 10.3 Timing Diagram for stable power to the release of RESETN

CPU clock

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CPU OP Code Fetch

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T RST2
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Tstartup

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2046 Crystal Clock Cycles CPU Start Running

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CPU Stop Running

T RST2 : 2 Crystal Clock Cycles (min) Tstartup : 2046 Crystal Clock Cycles + RESETN’s RC delay (standard module is about 50ms)

Figure 10.4 Timing Diagram for RESETN control sequence

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Sub1GHz FSK/GFSK Transceiver SOC
10.6 Clock source
A9108 has three clock source, crystal oscillator (pin 13,14/ Xi, XO), RTC crystal (pin 1,2/ P3.6, P3.7/ RTC_I, RTC_O) and internal RC oscillator. In the MCU part (digital peripherals ), user choices the suitable clock source by power consumptions and performance. In the RF part, the clock source only comes from XO..
RF Clock Generator XO RTC IRC 1 0

CLKRUN 1 /1 /2 RTCS CLKSEL =7 /4 /8 /16 /32 /64

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CLKCTRL CLK PMM STOP

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Figure 10.5 Whole chip clock

WOR/TWOR timer

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A9108 has 24 Digital I/O Pins. There are separated to 3 Ports (Port0, Port1 and Port3) and each of the Port pin can be defined as general-purpose I/O (GPIO) or peripheral I/O signals connected to the timers, UART, I2C and SPI functions. Thus, each pin can also be used to wake A9108 up from sleep mode. User can select each pin function by setting register. Each port has itself port register like P0 (0x80), P1 (0x90) and P3 (0xB0) that are both byte addressable and bit addressable. When reading, the logic levels of the Port’s input pins are returned. Each port has three registers to setting Pull-up (PU), Output-enable (OE) and Wake-up enable (WUE). As shown the bellow block diagram, Fig. 11.1. Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a general-purpose I/O input with pull-up resistor.

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11. I/O Ports

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CLKSEL

CLKSEL = 0 ~6

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CLKPMM

MCU Core

A9108
Sub1GHz FSK/GFSK Transceiver SOC

PUN

OE DI

INT6

WUN

Table 11.1 OE and PUN setting and Output(P) and Input(DI)

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Address/Name 80h P0 Reset

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It has three 8-bit full bi-directional ports, P0, P1 and P3. Each port bit can be individually accessed by bit addressable instructions. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Port 0 register 0 0 0 0

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Address/Name 90h P1 Reset

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11.2 FUNCTIONALITY

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Port 1 register 0 0 0 0

Address/Name B0h P3 Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Port 3 register 0 0 0 0

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Table 11.2 WUN setting and INT6 source

WUN 0 1

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OE 0 0 1

PUN 0 1 X

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P 1 HZ DO

Figure11.1

Ports I/O block diagram

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
Read and write accesses to the I/O port are performed via their corresponding SFRs P0(0x80), P1(0x90), and P3(0xB0). Some port‐reading instructions read the data register and others read the port’s pin. The “Read‐Modify‐Write” instructions are directed to the data registers and are shown below. All the other instructions used to read a port exclusively read the port’s pin. Instruction ANL ORL XRL JBC CPL INC, DEC DJNZ MOV Px.y, C CLR Px.y SETB Px.y
Table11.2

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Address/Name B2h P0PU Reset

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R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Port 0 Pull Up Register 0 0 0 0

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Address/Name B3h P0OE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 Port 0 Output Enable Register 0 0 0

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Address/Name B4h P0WUE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 Port 0 Wake Up Enable Register 0 0 0

Address/Name B5h P1PU Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Port 1 Pull Up Register 0 0 0 0

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All Port pins can wake A9108 up when WUEN=1 and configured GPIO. All Port pins’ WEU signals connect one AND gate to INT2. It means pin wake up function needs INT2 ISR to take care this interrupt. WUEN WUNDI 1 1 0 DI

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OE 1 0 0

PU P DI X DO DO 1 Pull-up P 0 HZ Input

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According the Table 11.1, all Port pins can be configured as Output, Input with pull-up resistor( around 100 Kohm) or Input. Please refer the following truth table to know every function setting. When OE=1, this pin is configured as Output. Otherwise OE =0, this pin is configured as Input. User can set PU =1 or 0 depending on application. When OE =1, PU=0 is recommended for saving power..

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Read-modify-write instructions

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Function description Logic AND Logic OR Logic eXclusive OR Jump if bit is set and clear Complement bit Increment, decrement byte Decrement and jump if not zero Move carry bit to y of port x Clear bit y of port x Set bit y of port x

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Sub1GHz FSK/GFSK Transceiver SOC
Address/Name B6h P1OE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 Port 1 Output Enable Register 0 0 0

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0 0 0 Port 3Pull Up Register

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0 0 0 0 0 0 0

Address/Name AAh P3PU Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

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0 0 0 0 0 Port 3 Output Enable Register

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Address/Name ABh P3OE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

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Address/Name ACh P3WUE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 Port 3 Wake Up Enable Register

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URT0IOS (UART0 I/O select) [1]: Port 3.0 and Port3.1 are selected for UART0 mode0 (open drain I/O) [0]: Port 3.0 and Port3.1 are normal I/O I2CIOS (I2C I/O select) [1]: The pad is selected for I2C (open drain I/O) [0]: The pad is normal I/O BBIOS (Base band I/O select) [1]: Output [0]: Input RTCIOS (Real-time clock I/O select) [1]: The pad is for RTC clock [0]: The pad is normal I/O ADCIOS[2:0] (ADC I/O select) ADCIOS0 [1]: Enable ADC analog input [0]: Disable ADC analog input ADCIOS[2:1] [00]: Select P3.2 as the ADC analog input [01]: Select P3.3 as the ADC analog input [10]: Select P3.4 as the ADC analog input [11]: Select P3.5 as the ADC analog input

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Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BBh R/W ADCIOS2 ADCIOS1 ADCIOS0 RTCIOS BBIOS - I2CIOS URT0IOS IOSEL Reset 0 0 0 0 0 0 0 0

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IOSEL Register

(0xBB)

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Address/Name B7h P1WUE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 Port 1 Wake Up Enable Register 0 0 0

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Sub1GHz FSK/GFSK Transceiver SOC
12 Timer 0 & 1 &2
A9108 contains three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2. Timer 0 and Timer 1 in the “timer mode“, timer registers are incremented every 4/12/CLK periods depends on CKCON (0x8E) setting, when appropriate timer is enabled. In the “counter mode” the timer registers are incremented every falling transition on theirs corresponding input pins: T0 or T1. The input pins are sampled every CLK period.

12.1 Timer 0 & 1 PINS DESCRIPTION

The pins functionality is described in the following table. All pins are one directional. PIN T0(P3.4) GATE0(P3.2) T1(P3.5) GATE1(P3.3) ACTIVE Falling High Falling High TYPE Input Input Input Input

Table12.1 Timer 0, 1 pins description

12.2 Timer 0 & 1 FUNCTIONALITY
12.2.1 OVERVIEW

12.2.2 Timer 0 & 1 Registers
TMOD register (0x89)

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Address/Name 89h TMOD Reset

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M1 0 0 1 1

M0 0 1 0 1

Mode 0 1 2 3

Function description THx operates as 8-bit timer/counter with a divide by 32 prescaler served by lower 5-bit of TLx. 16-bit timer/counter. THx and TLx are cascaded. TLx operates as 8-bit timer/counter with 8-bit auto-reload by THx. TL0 is configured as 8-bit timer/counter controlled by the standard Timer 0 bits. TH0 is an 8-bit timer controlled by the Timer 1 controls bits. Timer 1 holds its count.
Table12.2 Timer 0 and 1 modes

R/W

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Bit 7

Bit 6 CT

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Timer 0 and Timer 1 are fully compatible with the standard 8051 timers. Each timer consists of two 8-bit registers TH0 (0x8C), TL0 (0x8A), TH1 (0x8D), TL1 (0x8B). Timers 0, 1 work in the same four modes. The modes are described below.

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Bit 4 M0 Bit 3 GATE0 0 TF0 0 TR0 0 IE1 0

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Bit 2 CT Bit 1 M1 Bit 0 M0 Timer 0 control bits 0 0 0 IT1 0 IE0 0 IT0 0

DESCRIPTION Timer 0 clock line Timer 0 clock line gate control Tiner 1 clock line Timer 1clock line gate control

R/W GATE1 0

GATE:Gating control =1, Timer x enabled while GATEx pin is high and TRx control bit is set. =0, Timer x enabled while TRx control bit is set. CT:Counter or timer select bit =1, Counter mode, Timer x clock from Tx pin. =0, Timer mode, internally clocked. M[1:0]:Mode select bits TCON register (0x88) Address/Name 88h TCON Reset TR0:Timer 0 run control bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W TF1 0 TR1 0

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Timer 1 control bits 0 0 0

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The Timer 2 is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc.

A9108
Sub1GHz FSK/GFSK Transceiver SOC
=1, enabled. =0, disabled. TR1:Timer 1 run control bit =1, enabled. =0, disabled. TF0:Timer 0 interrupt (overflow) flag. Cleared by hardware when processor branches to interrupt routine. TF1:Timer 1 interrupt (overflow) flag. Cleared by hardware when processor branches to interrupt routine. CKCON register (0x8E)

IE register (0xA8) Address/Name A8h IE Reset EA:Enable global interrupts. ET0:Enable Timer 0 interrupts. ET1:Enable Timer 1 interrupts. IP register (0xB8)

R/W

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ET2 0 0 Bit 5 PT2 0 -

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ES0 0 ET1 0 EX1 0 ET0 0 EX0 0

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Timer 0, 1 related bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Interrupt flag TF0 TF1 Function Internal, Timer 0 Internal, Timer 1 Active level/edge Flag resets Hardware Hardware Vector 0x0B 0x1B Natural priority 2 4

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Address/Name R/W Bit 7 B8h R/W IP Reset 0 PT0:Timer 0 priority level control (at 1-high level) PT1:Timer 1 priority level control (at 1-high level)

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Bit 4 PS0 0 Bit 3 PT1 0

T1M:This bit controls the division of the system clock that drives Timer 1. =1, Timer 1 uses a divided-by-4 of the system clock frequency. =0, Timer 1 uses a divided-by-12 of the system clock frequency.

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Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8Eh R/W T1M T0M MD2 MD1 MD0 CKCON Reset 0 0 0 0 0 0 0 0 T0M:This bit controls the division of the system clock that drives Timer 0. =1, Timer 0 uses a divided-by-4 of the system clock frequency. =0, Timer 0 uses a divided-by-12 of the system clock frequency.

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Table12.3

Timer 0, 1 interrupts

12.2.3 Timer 0 – Mode 0
In this mode, the Timer 0 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s. Timer 0 interrupt flag TF0 is set. The counted input is enabled to the Timer 0 when TCON.4 = 1 and either TMOD.3 = 1 or GATE0 = 1. (Setting TMOD.3 = 1 allows the Timer 0 to be controlled by external input GATE0, to facilitate pulse width measurement). The 13-bit register consists of all 8-bit of TH0 and lower 5 bits of TL0.The upper 3 bits of TL0 are indeterminate and should be ignored.

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Bit 1 PT0 Bit 0 PX0 0

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Sub1GHz FSK/GFSK Transceiver SOC

Figure12.1

Timer/Counter 0, Mode 0:13-Bit Timer/Counter

12.2.4 Timer 0 – Mode 1

Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure below.

12.2.5 Timer 0 – Mode 2

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Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reloads, as shown in figure below. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is loaded by software. The reload leaves TH0 unchanged.

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Figure12.3

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Figure12.2

Timer/Counter 0, Mode 2 :8-Bit Timer/Counter with Auto-Reload

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Timer/Counter 0, Mode 1 :16-Bit Timer/Counter

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Sub1GHz FSK/GFSK Transceiver SOC
12.2.6 Timer 0 – Mode 3
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in figure below. TL0 uses the Timer 0 control bits:C/T, GATE, TR0, GATE0 and TF0. TH0 is locked into a timer function and use the TR1 and TF1 flag from Timer1 and controls Timer1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer/counter. When Timer 0 is in Mode 3, Timer 1 can be turned off by switching it into its own Mode 3, or can still be used by the serial channel as a baud rate generator, or in any application where interrupt from Timer 1 is not required.

Figure12.4

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12.2.8 Timer 1 – Mode 1
Mode 1 is the same as Mode 0, except that timer register is running with all 16 bits. Mode 1 is shown in figure below.

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In this Mode, the Timer1 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, Timer1 interrupt flag TF1 is set. The counted input is enabled to the Timer1 when TCON.6 = 1 and either TMOD.6 = 0 or GATE1 = 1. (Setting TMOD.7 = 1 allows the Timer1 to be controlled by external input GATE1, to facilitate pulse width measurements). The 13‐bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored.

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12.2.7 Timer 1 – Mode 0

Figure12.5 Timer/Counter 1, Mode 0: 13-Bit Timers/Counters

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Timer/Counter 0, Mode 3 :Two 8-Bit Timers/Counters

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Sub1GHz FSK/GFSK Transceiver SOC

Figure12.6

Timer/Counter 1, Mode 0 :16-Bit Timers/Counter

Mode 2 configures the timer register as an 8-bit counter (TL1) with automatic reloads, as shown in figure below. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is loaded by software. The reload leaves TH1 unchanged.

Timer 1 in Mode 3 is held counting. The effect is the same as setting TR1=0.

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12.3 Timer2 PINS DESCRIPTION
The Timer 2 pins functionality is described in the following table. All pins are one directional. PIN t2(P1.0) t2ex(P1.1) ACTIVE falling high TYPE INPUT INPUT DESCRIPTION Timer 2 clock line Timer 2 control

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12.2.10 Timer 1 – Mode 3

12.4 Timer2 FUNCTIONALITY
12.4.1 OVERVIEW
Timer 2 is fully compatible with the standard 8052 Timer 2. It is up counter. Totally five SFRs control the Timer 2 operation: TH2/TL2(0xCD/0xCC) counter registers, RLDH/RLDL (0xCB/0xCA) capture registers and T2CON(0xC8) control register. Timer 2 works in the three modes selected by T2CON bits as shown in table below.

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Figure12.7

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Timer/Counter 1, Mode 2 :8-Bit Timer/Counter with Auto-Reload

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Table12.4 Compare/Capture pins description

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12.2.9 Timer 1 – Mode 2

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Sub1GHz FSK/GFSK Transceiver SOC
RCLK, TCLK 0 0 CPRL2 0 1 TR2 1 1 Function description 16-bit auto-reload mode. The Timer 2 overflow sets TF2 bit and the TH2,TL2 registers reloaded 16-bit value from RLDH, RLDL. 16-bit capture mode. The Timer 2 overflow sets TF2 bit. When the EXEN2 = 1, the TH2, TL2 register values are stored into RLDH, RLDL while falling edge is detected on T2EX pin. Baud rate generator for the UART0 interface. It auto-reloads its counter with RLDH, RLDL values each overflows. Timer 2 is off
Table12.5 Timer 2 modes

1 X

X X

1 0

12.4.2 Timer 2 Registers
T2CON register (0xC8)

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Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C8h R/W TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 APOL Reset 0 0 0 0 0 0 0 0 EXF2:Falling edge indicator on T2EX pin when EXEN = 1. Must be cleared by software. RCLK:Receive clock enable =1, UART0 receiver is clocked by Timer 2 overflow pulses =0, UART0 receiver is clocked by Timer 2 overflow pulses TCLK:Transmit clock enable =1, UART0 transmitter is clocked by Timer 2 overflow pulses =0, UART0 transmitter is clocked by Timer 2 overflow pulses EXEN2:Enable T2EX pin functionality. =1, Allows capture or reload as a result of T2EX pin falling edge. =0, ignore T2EX events TR2:Start / Stop Timer 2 =1, start =0, stop CT2:Timer / counter select =1, external event counter. Clock source is T2 pin. =0, timer 2 Internally clocked CPRL2:Capture / Reload select =1, T2EX pin falling edge causes capture to occur when EXEN2 = 1 =0, automatic reload occurs:on Timer 2 overflow or falling edge T2EX pin when EXEN2 = 1. When RCLK or TCLK is set this bit is ignored and automatic reload on Timer 2 overflow is forced.

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Sub1GHz FSK/GFSK Transceiver SOC

Figure12.9

Timer 2 block diagram in timer mode

CKCON register (0x8E) Address/Name 8Eh CKCON Reset R/W R/W Bit 7 Bit 6 -

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Bit 5 0 0

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Bit 4 T1M Bit 3 T0M 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 timer is in baud ET2 0 ES0 0 ET1 0 EX1 0 ET0 0 EX0 0 Bit 4 PS0 0 Bit 3 PT1 0 Bit 2 PX1 0 Bit 1 PT0 0 Bit 0 PX0 0 0

Timer 2 interrupt related bits are shown below. An interrupt can be turned on/off by IE (0xA8) register, and set into high/low priority group by IP register. IE register (0xA8)

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Address/Name A8h IE Reset EA:Enable global interrupts. ET2:Enable Timer 2 interrupts.

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T2M:This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the rate generator mode. =1, Timer 2 uses a divide-by-4 of the system clock frequency. =0, Timer 2 uses a divide-by-12 of the system clock frequency.

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EA 0 0

IP register (0xB8) Address/Name R/W B8h R/W IP Reset Bit 7 0 Bit 6 0 Bit 5 PT2

PT2:Timer 2 priority level control (at 1-high level) -:Unimplemented bit. Read as 0 or 1. T2CON register (0xC8)

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Sub1GHz FSK/GFSK Transceiver SOC
Address/Name R/W C8h R/W T2CON Reset Bit 7 TF2 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EXF2 RCLK TCLK EXEN2 TR2 0 0 0 0 0

CT2 CPRL2 0 0

TF2:Timer 2 interrupt (overflow) flag. Must be cleared by software. The flag will not be set when either RCLK or TCLK is set. All Timer 2 related bits generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Interrupt flag Function Active level / edge Flag resets Vector Natural priority TF2 Interrnal, Timer2 Software 0x2B 6
Table12.6 Timer 2 interrupt

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Please note that SMOD0 bit is ignored by UART when clocked by Timer2. The RLCK/TCLK frequency is equal to:

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Figure12.9

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Timer 2 block diagram as UART0 baud rate generator

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Interrupt is also generated at falling edge of T2EX pin, while EXEN2 bit is set. This interrupt doesn’t set TF2 flag, but EXF2 only and also uses 0x2B vector. Please see picture below. Timer2 internal logic configured as baud ‐rate generator is shwon below.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
13. UART 0,1
UART0 is full duplex, meaning it can transmit and receive concurrently. It is receive double‐buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. The serial port can operate in 4 modes: one synchronous and three asynchronous modes. Mode 2 and 3 has a special feature for multiprocessor communications. This feature is enabled by setting SM02 bit in SCON0 register. The master processor first sends out an address byte, which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM02 = 1, no slave will be interrupted by a data byte. An address byte will interrupt all slaves. The addressed slave will clear its SM02 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM02 set and ignoring the incoming data.

13.1 UART0 PINS DESCRIPTION

SBUF0 register

(0x99)

Reset SB0[7:0]:UART0 buffer SCON0 register

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Address/Name R/W 99h R/W SBUF0

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The UART0 has the same functionality as a standard 8051 UART. The UART0 related registers are: SBUF0(0x99), SCON0(0x98), PCON(0x87), IE(0xA8) and IP(0xB8). The UART0 data buffer (SBUF0) consists of two separate registers: transmit and receive registers. A data writes into the SBUF0 sets this data in UART0 output register and starts a transmission. A data reads from SBUF0, reads data from the UART0 receive register.

Bit 7

Bit 6

N
Bit 5 0 0 0 Bit 5

13.2 FUNCTIONALITY

FI D
Bit 4 Bit 3 0 Bit 4 Bit 3 TB08 0 0 0

PIN Rxd_0(P3.0) Txd_0(P3.1)

ACTIVE TYPE DESCRIPTION Input / Output Serial receiver I_0 / O_0 Output Serial transmitter line 0 Table13.1 UART0 pins description

EN
Bit 2 Bit 1 0 0 Bit 2 RB08 0 0

The UART0 pins functionality is described in the following table. All pins are one directional. There are no three‐state output pins and internal signals.

0

IC

M

Address/Name 98h SCON0 Reset

C

(0x98)

R/W R/W

Bit 7

Bit 6

SM00 SM01 SM02 REN0 0 0

A

SM02:Enable a multiprocessor communication feature SM0[1:0]:Sets baud rate SM00 SM01 Mode Description Baud Rate 0 0 0 Shift register FCLK/12, FCLK/4 0 1 1 8-bit UART Variable(16bit) 1 0 2 9-bit UART FCLK/32 or FCLK/64 1 1 3 9-bit UART Variable(16bit) Timer 2 cannot be used as baud rate generator when Compare Capture unit is present in the system. The UART0 baud rates are presented in the table below.

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Bit 0 0 Bit 1 TI0 Bit 0 RI0 0

L

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Baud Rate FCLK/12 Timer 1 overflow rate – T1ov SMOD0 = 0 T1ov/32 SMOD0 = 1 T1ov/16 Timer 2 overflow rate – T2ov SMOD0 = x T2ov/16 Mode 2 SMOD0 = 0 FCLK/64 SMOD0 = 1 FCLK/32 The SMOD0 bit is located in PCON register. Mode Mode 0 Mode 1, 3

PCON register

0

0

FI D
0 0 0 ET2 0 ES0 0 ET1 0 0 Bit 4 PS0 0 Bit 3 PT1 0 PT2 0

(0x87) Address/Name 87h PCON Reset

R/W R/W

Bit 7

Bit 6

Bit 5 -

Bit 4

EN
Bit 3 Bit 2 0 EX1 ET0 0 Bit 2 PX1 0 0 Bit 2 RB08 0 0

SMOD0 SMOD1

PWE

SMOD0:UART0 double baud rate bit when clocked by Timer 1 only.

IE register

(0xA8) Address/Name A8h IE Reset

R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EA 0 0 EX0 0

ES0:RI0 & TI0 interrupt enable flag IP register (0xB8) Address/Name B8h IP Reset

C

O

M

IC

R/W R/W

C O

? INTERRUPTS UART0 interrupt related bits are shown below. An interrupt can be turned on / off by IE register, and set into high / low priority group by IP register.

Bit 7 0

Bit 6 0

N

Bit 5

PS0:RI0 & TI0 interrupt priority flag

A

(0x98) Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 98h R/W SM00 SM01 SM02 REN0 TB08 SCON0 Reset 0 0 0 0 0 TI0:Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. RI0:Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.

SCON0 register

M

All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software.
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Bit 1 Bit 0 SWB STOP PMM 0 0 Bit 1 PT0 Bit 0 PX0 0 Bit 1 TI0 Bit 0 RI0 0

REN0:If set, enable serial reception. Cleared by software to disable reception. TB08:The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.) th RB08:In Modes 2 and 3 it is the 9 data bit received. In Mode 1, if SM02 is 0, RB08 is the stop bit. In Mode 0 this bit is not used.

L

A9108
Sub1GHz FSK/GFSK Transceiver SOC
Interrupt flag TI0 & RI0 Function Internal, UART0 Active level / edge Flag resets Software Vector 0x23 Natural priority 5

Table13.3

UART0 interrupt

13.3 OPERATING MODES
Pin RXD0I serves as input and RXD0O as output. TXD0 output is a shift clock. The baud rate is fixed at 1/12 of the CLK clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON0 as follows: RI0=0 and REN0=1.

13.3.2 UART0 MODE 1, 8-BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE
Pin RXD0I serves as input, and TXD0 serves as serial output. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading SBUF0, and stop bit sets the flag RB08 in the SFR SCON0. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. SMOD0 bit is ignored when UART is clocked by Timer2.

O

A

M

IC

This mode is similar to Mode 1 with two differences. The baud rate is fixed at 1/32 or 1/64 of CLK clock frequency, and 11 th th bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9 bit, and a stop bit (1). The 9 bit can be th used to control the parity of the UART0 interface: at transmission, bit TB08 in SCON0 is output as the 9 bit, and at receive, the th 9 bit affects RB08 in SCON0.

C

13.3.3 UART0 MODE 2, 9‐BIT UART, FIXED BAUD RATE

13.3.4 UART0 MODE 3, 9‐BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE
The only difference between Mode 2 and Mode 3 is that the baud rate is a variable in Mode 3. When REN0=1 data receiving is enabled. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. SMOD0 bit is ignored when UART is clocked by Timer2.

M

Figure13.4

Figure13.5

C O

UART0 transmission mode 1 timing diagram

UART0 transmission mode 2 timing diagram

N
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Figure13.3

UART0 transmission mode 0 timing diagram

AMICCOM Electronics Corporation

EN

TI A

L

13.3.1 UART0 MODE 0, SYNCHRONOUS

A9108
Sub1GHz FSK/GFSK Transceiver SOC

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IC

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(1) FXTAL: Crystal frequency. (2) FXREF: Crystal Ref. Clock = FXTAL * (DBL+1). (3) FCGR: Clock Generation Reference = 2MHz = FXREF / (GRC+1), where FCGR is used to generate 32M PLL. (4) FMCLK: Master Clock is either FXREF: or 32M PLL, where FMCLK is used to generate FSYCK. (5) FSYCK: System Clock = 16MHz=FMCLK / CSC= 32 * FIF, where FIF is recommended to set 500KHz. (6) FDR: Data Rate Clock = FIF / (SDR+1). (7) FFPD: VCO Compared Clock = = FXREF / (RRC+1).

TI A

L

A9108 supports different crystal frequency by programmable “Clock Register” (0Dh). Based on this, three important internal clocks FCGR , FDR and FSYCK are generated.

Figure13.6

UART0 transmission mode 3 timing diagram

A9108
Sub1GHz FSK/GFSK Transceiver SOC
14. IIC interface
A9108’s I C peripheral provides two-wire interface between the device and I C -compatible device by the two-wire I C serial bus. The I2C peripheral supports the following functions. ? Conforms to v2.1 of the I2C specification (published by Philips Semiconductor) ? Master transmitter / receiver ? Slave transmitter / receiver ? Flexible transmission speed modes: Standard (up to 100 Kb/s) and Fast (up to 400Kb/s) ? Multi-master systems supported ? Supports 7-bit addressing modes on the I2C bus ? Interrupt generation ? Allows operation from a wide range of input clock frequencies (build-in 8-bit timer) PIN 23 and PIN 24 are I2C Interface in A9108. The alternate function is Port 0.5 and Port 0.6. User can set BBSEL (BBH) to set up the PIN function. Please refer the Chapter 11 for more detail information. PIN SCL(P0.5) SDA(P0.6) TYPE INPUT /OUTPUT INPUT/ OUTPUT
Table14.1
2 2 2

DESCRIPTION I2C clock input /output 2 I C data input /output

I2C interface pins description

14.1 Master mode I C

The I2C master mode provides an interface between a microprocessor and an I 2C bus. It can be programmed to operate with arbitration and clock synchronization to allow it to operate in multi‐master systems. Master mode I2C supports transmission speeds up to 400Kb/s.

There are six registers used to interface to the host: the Control, Status, Slave Address, Transmitted Data, Received Data and Timer Period Register. Register Slave address – I2CMSA Control – I2CMCR Transmitted data I2CBUF Timer period - I2CMTP
Table14.3
2

C O

14.1.1 I2C REGISTERS

N O
Address 0xF4 0xF5 0xF6 0xF7 Address 0xF4 0xF5 0xF6 0xF7

M

I C Registers for writing

IC

Register Slave address – I2CMSA Status – I2CMSR Received data - I2CBUF Timer period - I2CMTP
Table14.4
2

C

A

I2C Master mode Timer Period Register To generate wide range of SCL frequencies the core have built‐in 8‐bit timer. Programming sequence must be done at least once after system reset. After reset, register have 0x01 value by default. ? SCL_PERIOD = 2 x (1+TIMER_PRD) x (SCL_LP + 1) x CLK_PRD For example: - CLK_PRD = 33,33ns (CLK_FRQ = 30MHz); - TIMER_PRD = 3; - SCL_LP = 6; SCL_PERIOD = 2 x (1 + 3) x (6 + 1 ) x 33,33ns = 3200ns = 2,666us SCL_FREQUENCY = 1 / 2,666us = 375 KHz SCL_PRD - SCL line period (I2C clock line) TIMER PRD -Timer period register value (range 1 to 255)
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I C Registers for reading

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AMICCOM Electronics Corporation

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
SCL_LP CLK_PRD I2CMTP (0xE7) Address/Name R/W E7h R/W I2CMTP Reset ? Bit 7 0 0 Bit 6 P.6 0 Bit 5 P.5 0 Bit 4 P.4 0 Bit 3 P.3 0 Bit 2 P.2 0 Bit 1 P.1 0 Bit 0 P.0 - SCL_LOW_PERIOD constant value (range 2 to 15) - System clock period (1/fclk)

I2CMCR

(0xF5) Address/Name F5h I2CMCR Reset R/W R/W

C O

I2C CONTROL AND STATUS REGISTERS The Control Register consists of eight bits: the RUN, START, STOP, ACK, HS, ADDR, SLRST and RSTB bit. The RSTB bit performs reset of whole I 2C controller and behaves identically as external reset provided by RST pin. Using this bit software application can reinitialize I 2C mater module when some problem is encountered on I 2C bus. In case when I2C Slave device blocks I2C bus, then SLRST bit should be set along with RUN bit (just after issuing the RSTB). SLRST bit causes that I2C master module generates 9 SCK clocks (no START is generated) to recover Slave device to known state and issues at the end STOP. This bit is automatically cleared by I2C MASTER MODULE, thus, it is always read as ‘0’. The BUSY bit should be checked to know when this transmission is ended. The START bit will cause the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle will stop at the end of the data cycle, or continue on to a burst. To generate a single send cycle, the Slave Address register is written with the desired address, the R/S bit is set to ‘0’, and Control Register is written with HS=0, ACK=x, STOP=1, START=1, RUN=1 (binary xxx0x111 x‐mean 0 or 1) to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt is generated. The data may be read from Received Data Register. When I2C MASTER MODULE core operates in Master receiver mode the ACK bit must be set normally to logic 1. This cause the I2C MASTER MODULE bus controller to send acknowledge automatically after each byte. This bit must be reset when the I2C MASTER MODULE bus controller requires no further data to be sent from slave transmitter. The ADDR bit along with RUN bit cause the generation of the START condition and transmission of Slave Address. Next STOP can end transmission, or REPEATED START generates the START and ADDRRESS sequence once again. In both cases STOP can ends transmission. See I2C MASTER MODULE ACK Polling chapter for details.

Bit 7

Bit 6

N
Bit 5 0 RUN 1 1

FI D
Bit 4 HS 0 Bit 3 ACK 0 1 1 1 1 1 1 1

EN
Bit 2 0 0

M

RSTB SLRST ADDR 0 0 START 1 1

STOP START RUN 0

0

0

0

C

RSTB 0

SLRST 0

ADDR 0

O

HS 0 0

R/S 0 0

ACK -

STOP 0 1

0

0

IC

OPERATION START condition followed by SEND (Master remains in Transmitter mode) START condition followed by SEND and STOP condition START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) START condition followed by RECEIVE and STOP condition START condition followed by RECEIVE (Master remains in Receiver mode) forbidden sequence Master Code sending and switching to High‐speed mode I2CM module software reset Reset slaves connected to I2C bus by generating 9 SCK clocks followed by STOP START condition followed by Slave Address

0

0

1

0

0

1

A

0 0 0 0 1 0 0

M

0 0 0 0 0 1 0

0 0 0 0 0 0 1

0 0 0 1 0 0

1 1 1 0 0 0

0 1 1 0 0 0

1 0 1 0 0 0

1 1 1 0 0 0

Table14.5

Control bits combinations permitted in IDLE state *

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Bit 1 Bit 0

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1

A9108
Sub1GHz FSK/GFSK Transceiver SOC
RSTB 0 0 0 0 0 0 SLRST 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 HS 0 0 0 0 0 0 R/S 0 0 1 ACK 0 STOP 0 1 1 0 1 0 START 0 0 0 1 1 1 RUN 1 0 1 1 1 1 OPERATION SEND operation (Master remains in Transmitter mode) STOP condition SEND followed by STOP condition Repeated START condition followed by SEND (Master remains in Transmitter mode) Repeated START condition followed by SEND and STOP condition Repeated START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) Repeated START condition followed by SEND and STOP condition Repeated START condition followed by RECEIVE (Master remains in Receiver mode) forbidden sequence I2CM module software reset Repeated START condition followed by Slave Address

0 0 0 1 0

0 0 0 0 0

0 0 0 0 1

0 0 0 0

1 1 1 0

0 1 1 -

1 0 1 0

1 1 1 1

1 1 1 1

Table14.6

Control bits combinations permitted in Master Transmitter mode

RSTB 0 0 0 0 0 0

SLRST 0 0 0 0 0 0

ADDR 0 0 0 0 0 0

HS 0 0 0 0 0 0

R/S 1

ACK 0 0 1 1 0

STOP 0 1 1 0 1 0

START 0 0 0 0 0 1

C O

0 0 0 0 1

0 0 0 0 0

0 0 0 0 0

0 0 0 0 -

1 1 0 0 -

M

0 1 -

1 0 0 1 -

O

C

IC

A

The status Register is consisted of six bits:the BUSY bit, the ERROR bit, the ADDR_ACK bit, the DATA_ACK bit, the ARB_LOST bit, and the IDLE bit. I2CMSR (0xF5)

M

Table14.7

Control bits combinations permitted in Master Receiver mode

Address/Name R/W F5h R/W I2CMSR Reset 0x20

Bit 7 0

Bit 6 BUS_ BUSY 0

Bit 5 IDLE 1

N
0 1 1 1 1 1 1 1 1 1 1 1 1 Bit 4 ARB_ LOST 0

FI D
RUN 1 Bit 3 DATA_ ACK 0

OPERATION RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) STOP condition** RECEIVE followed by STOP condition RECEIVE operation (Master remains in Receiver mode) forbidden sequence Repeated START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) Repeated START condition followed by RECEIVE and STOP condition Repeated START condition followed by RECEIVE (Master remains in Receiver mode) Repeated START condition followed by SEND (Master remains in Transmitter mode) Repeated START condition followed by SEND and STOP condition I2CM module software reset

EN
Bit 2 ADDR_ ACK 0

TI A
Bit 1 ERROR 0

IDLE:This bit indicates that I2C BUS controller is in the IDLE state。

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Bit 0 BUSY 0

A9108
Sub1GHz FSK/GFSK Transceiver SOC
BUSY:This bit indicates that I2C BUS controller receiving, or transmitting data on the bus, and other bits of Status register are no valid; BUS_BUSY:This bit indicates that the Bus is Busy, and access is not possible. This bit is set / reset by START and STOP conditions; ERROR:This bit indicates that due the last operation an error occurred: slave address wasn’t acknowledged, transmitted data wasn’t acknowledged, or I2C Bus controller lost the arbitration; ADDR_ACK:This bit indicates that due the last operation slave address wasn’t acknowledged; ARB_LOST:This bit indicates that due the last operation I2C Bus controller lost the arbitration; SLAVE ADDRESS REGISTER The Slave address Register consists of eight bits:Seven address bits (A6-A0), and Receive/ not send bit R/S. The R/S bit determines if the next operation will be a Receive (high), or Send (low). I2CMSA (0xF4) Address/Name R/W F4h R/W I2CMCA Reset ? Bit 7 A.6 0 Bit 6 A.5 0 Bit 5 A.4 0 Bit 4 A.3 0 Bit 3 A.2 0 ?

EN
Bit 2 A.1 0 Bit 1 A.0 0 Bit 3 D.3 0 Bit 2 D.2 0 Bit 1 D.1 0 Bit 3 D.3 0 Bit 2 D.2 0 Bit 1 D.1 0

I2C Buffer – RECEIVER AND TRANSMITTER REGISTERS I2C module has two separated 1 byte buffer in receiver and transmitter and these are located in the same address (0xF6). The Transmitted Data Register consists of eight data bits which will be sent on the bus due the next Send, or Burst Send operation. The first send bit is D.7 (MSB). (0xF6) Address/Name R/W F6h R/W I2CBUF Reset Bit 7 D.7 0

I2CBUF

C O

Bit 6 D.6 0

N
Bit 5 D.5 0 Bit 4 D.4 0 Bit 0 D.P 0 Address/Name R/W F6h R/W I2CBUF Reset

O

The Receiver Data Register consists of eight data bits which have been received on the bus due the last receive, or Burst Receive operation. I2CBUF (0xF6)

M

Bit 7 D.7 0

Bit 6 D.6 0

Bit 5 D.5 0

FI D
Bit 4 D.4 0

C

Default transmission parameter/constant values are shown in sections below. SCL clock frequency can be changed by modification of timer period values as show in the table below.

A

?

I2C MASTER MODULE STANDARD MODE Typical configuration values for Standard speed mode: The following table gives an example parameters for standard I2C speed mode. System clock TIMER_PERIOD Transmission speed 4 MHz 1 (01h) 100kb/s 6 MHz 2 (02h) 100kb/s 10 MHz 4 (04h) 100kb/s 16 MHz 7 (07h) 100kb/s 20 MHz 9 (09h) 100kb/s
Table14.8 I2C MASTER MODULE Timer period values for standard speed mode

M

14.2.4 I2C MASTER MODULE AVAILABLE SPEED MODES

IC

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Bit 0 R/S 0 Bit 0 D.P 0

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
? I2C MASTER MODULE FAST MODE Typical configuration values for Fast speed mode: The following table gives example parameters for Fast I2C speed mode. System clock TIMER_PERIOD Transmission speed 10 MHz 1 (01h) 250 Kb/s 16 MHz 1 (01h) 400 Kb/s 20 MHz 2 (02h) 333 Kb/s Table14.8 I2C MASTER MODULE Timer period values for Fast speed mode

14.2.5 I2C MASTER MODULE AVAILABLE COMMAND SEQUENCES
? I2C MASTER MODULE SINGLE SEND
IDLE Write Slave Address to I2CSA register Write Data to I2CBUF register

NO

Bus Busy=“0” YES

C

IC

O

M

YES

M

Write ,,---0-111”to I2CCR register

Read I2CCR register

NO

Bus Busy=“0” YES Error =“0” NO

A

IDLE

Figure14.4

?

I2C MASTER MODULE SINGLE RECEIVE

C O

Error service

I2C MASTER MODULE Single SEND flowchart

N
IDLE

Read I2CCR register

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This sequence may be omitted in single-Master systems

AMICCOM Electronics Corporation

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A9108
Sub1GHz FSK/GFSK Transceiver SOC

IDLE Write Slave Address to I2CSA register This sequence may be omitted in single-Master systems

Read I2CCR register NO

Bus Busy=“0” YES

Write ,,---00111”to I2CCR register

Read I2CCR register

NO

Bus Busy=“0” YES

YES

Error =“0”

Read Data from I2CBUF register IDLE

M

O

?

I2C MASTER MODULE BURST SEND

A

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Figure14.5

N
NO Error service IDLE
Single RECEIVE flowchart

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
IDLE Write Slave Address to I2CSA register Write Data to I2CBUF register This sequence may be omitted in single-Master systems

Bus Busy=“0” YES

Read I2CCR register

Bus Busy=“0” YES Error =“0” YES

NO

N
YES NO

NO

C O

Write Data to I2CBUF register

FI D
Arb_Lost =‘1’ YES NO Write ,,---0-100”to I2CCR register Error service Error service IDLE IDLE Error service IDLE

NO

Index = n

YES

Write ,,---0-001”to I2CCR register

M

Write ,,---0-101”to I2CCR register Read I2CCR register

C

O

NO

Bus Busy=“0”

IC

YES IDLE

A

M

Error =“0”

Figure14.6

I2C MASTER MODULE Sending n bytes flowchart

?

I2C MASTER MODULE BURST RECEIVE

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EN

Write ,,---0-011”to I2CCR register

TI A

NO

L

Read I2CCR register

A9108
Sub1GHz FSK/GFSK Transceiver SOC
IDLE Write Slave Address to I2CSA register This sequence may be omitted in single-Master systems

Read I2CCR register

Bus Busy=“0” YES

Write ,,---01011”to I2CCR register

Read I2CCR register

YES Error =“0” YES

NO

N
YES

C O

Read Data from I2CBUF register NO

FI D
Arb_Lost =‘1’ YES NO Write ,,---0-100”to I2CCR register Error service Error service IDLE IDLE NO Error service IDLE

Bus Busy=“0”

NO

YES

Index = m-1

Write ,,---01001”to I2CCR register

M

Write ,,---00101”to I2CCR register Read I2CCR register

C

O

NO

Bus Busy=“0”

IC

YES Read Data from I2CBUF register IDLE
Figure14.7

A

M

Error =“0”

I2C MASTER MODULE Receiving m bytes flowchart

?

I2C MASTER MODULE BURST RECEIVE AFTER BURST SEND

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EN

TI A

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NO

A9108
Sub1GHz FSK/GFSK Transceiver SOC

Figure14.8

I2C MASTER MODULE Sending n bytes then Repeated Start and Receiving m bytes flowchart

?

I2C MASTER MODULE BURST SEND AFTER BURST RECEIVE

A

M

IC

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O

M

C O

N
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Sub1GHz FSK/GFSK Transceiver SOC

Figure14.9

I2C MASTER MODULE Receiving m bytes then Repeated Start and Sending n bytes flowchart

I2C MASTER MODULE ACK POLLING

A

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?

C

Figure14.10 I2C MASTER MODULE Single RECEIVE with 10-bit addressing flowchart

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Sub1GHz FSK/GFSK Transceiver SOC
IDLE Write Slave Address to I2CSA register Read I2CCR register

NO

BUS BUSY= ‘0’ YES Write ,,00100001" to I2CCR register Read I2CCR register

NO

C O

YES

YES

ADDR_ACK=‘0’

O

Burst Send or Stop

M

C

IC

M

A

N
NO Write ,,00100011" to I2CCR register Read I2CCR register NO BUSY= ‘0’ YES YES ADDR_ACK=‘0’ NO

BUSY= ‘0’

Burst Send or Stop
Figure14.11 I2C MASTER MODULE ACK Polling flowchart

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Sub1GHz FSK/GFSK Transceiver SOC
14.3 I2C MASTER MODULE INTERRUPT GENERATION
I2C MASTER MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or transfer error has occurred. I2CMIF flag has to be cleared by software. Interrupt flag I2CMIF Function Internal, I2C MASTER MODULE
Table14.11

Active level/edge -

Flag resets Software

Vector 0x6B

Natural priority 14

I2C MASTER MODULE interrupt summary

EIE

(0xE8)

Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E8h EI2CS R/W EI2CM EWDI EINT6 EINT5 EINT4 EINT3 EINT2 EIE ESPI Reset 0 0 0 0 0 0 0 0 EI2CM:Enable I2C MASTER MODULE interrupts EIP (0xF8) Address/Name R/W F8h R/W EIP Reset

PI2CM:I2C MASTER MODULE priority level control (at 1-high-level)

14.5 Slave mode I2C

M

A

The I C module provides an interface between a microprocessor and I C bus. It can works as a slave receiver or transmitter depending on working mode determined by microprocessor/microcontroller. The core incorporates all features required by I 2C 2 specification. The I C module supports all the transmission modes: Standard and Fast.

2

IC

I2CMIF:I2C MASTER MODULE interrupt flag Must be cleared by software writing logic ‘1’. Writing ‘0’ does not change its content.

C

Address/Name R/W 91h R/W EIF Reset

O

M

EIF

(0x91)

C O

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI2CS PI2CM PWDI PINT6 PINT5 PINT4 PINT3 PINT2 PSPI 0 0 0 0 0 0 0 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CSF I2CMF INT6F INT5F INT4F INT3F INT2F SPIF 0 0 0 0 0 0 0 0

N
80

14.5.1 I2C MODULE INTERNAL REGISTERS
There are five registers used to interface to the target device:The Own Address, Control, Status, Transmitted Data and Received Data registers. Register Own address – I2CSOA Control – I2CSCR Transmitted data – I2CSBUF
Table14.12

I2C MODULE Registers for writing

Dec. 2014, Version 0.5(Preliminary)

FI D
2

Address 0xF1 0xF2 0xF3

AMICCOM Electronics Corporation

EN

TI A

I2C MASTER MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1) bit called EA.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
Register Own address – I2CSOA Control – I2CSSR Received data – I2CSBUF
Table14.13

Address 0xF1 0xF2 0xF3

I2C MODULE Registers for reading

?

0

A.6 0

A.5 0

A.4 0

A.3 0

A.2 0

I2CSCR

(0xF2)

A

The Status Register consists of five bits: the DA, BUSACTIVE, RECFIN, SENDFIN bit, RREQ bit, TREQ bit. The receive finished RECFIN bit indicates that Master I2C controller has finished transmitting of data during single or burst receive operations. It also causes generation of interrupt on IRQ pin. The send finished SENDFIN bit indicates that Master I2C controller has finished receiving of data during single or burst send operations. It also causes generation of interrupt on IRQ pin. 2 2 The Receive Request RREQ bit indicates that I C module device has received data byte from I2C master. I C module host device (usually CPU) should read one data byte from the Received Data register I2CSBUF. The Transmit Request TREQ bit 2 indicates that I2C MODULE device is addressed as Slave Transmitter and I C module host device (usually CPU) should write one data byte into the Transmitted Data register I2CSBUF. The BUSACTIVE ‘1’ signalizes that any transmission (send, receive 2 or own address detection) is in progress. BUSACTIVE is cleared (‘0’) automatically by I C module in case when there is no any transmission. This is read only bit. The DA bit should be polled (read) when CPU wrote DA=0. The DA bit is not immediately cleared when any I2C transmission (send, receive or own address detection) is in progress. When current transmission has completed then this bit is 2 cleared to ‘0’ and I C module become inactive. I2CSSR

DA:Device Active – enable (‘1’) or disable (‘0’) the I2C MODULE device operation; BUSACTIVE:Bus ACTIVE – ‘1’ signalizes that any transmission: send, receive or own address detection RREQ:Indicates that I2C module device has received data byte from I 2C master; It is automatically cleared by read of I2CSBUF. 81

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(0xF2) Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2h R/W DA - BUSACTIVE RECFIN SENDFIN TREQ RREQ I2CSSR Reset 0 0 0 0 0 0 0 0

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DA:Device Active – enable or disable the I2C module device operation; RSTB:Reset of whole I2C controller by writing ‘1’ to this bit. It behaves identically as RST pin RECFINCLR:Writing ‘1’ to this bit clears RECFIN bit from the I2C MODULE status register. SENDFINCLR:Writing ‘1’ to this bit clears SENDFIN bit from the I2C MODULE status register.

C O

Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2h R/W RSTB DA - RECFINCLR SENDFINCLR I2CSCR Reset 0 0 0 0 0 0 0 0

N

FI D

EN

?

I2CSCR – CONTROL AND STATUS REGISTERS The Control Register consists of the bits:The RSTB and DA bit. The RSTB bit performs reset of whole I 2C controller and 2 behaves identically as external reset provided by RST pin. Using this bit software application can reinitialize I C module when some problem is encountered on I2C bus. The DA bit enables (‘1’) and disable (‘0’) the I2C module device operation. DA is set immediately to ‘1’ when CPU write DA=1. This register can be only written at address 0xF2. Reading this address puts status register on data bus – see below.

Dec. 2014, Version 0.5(Preliminary)

AMICCOM Electronics Corporation

TI A
A.1 0 A0 0

Address/Name R/W F1h R/W I2CSOA Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

L

I2CSOA – OWN ADDRESS REGISTER The Own Address Register consists of seven address bits which identify I2C module core on I2C Bus. This register can be read and written at the address 0xF1. I2CSOA (0xF1)

is in progress;

A9108
Sub1GHz FSK/GFSK Transceiver SOC
TREQ:Indicates that I2C module device is addressed as transmitter and requires data byte from host device; It is automatically cleared by write data I2CSBUF. RECFIN:Indicates that Master I2C controller has ended transmit operation. It means that no more RREQ will be set during this single or burst I2C module receive operation. It is cleared by writing ‘1’ to the RECFINCLR bit in the I2C module control register. SENDFIN:Indicates that Master I2C controller has ended receive operation. It means that no more TREQ will be set during this single or burst I2C module send operation. It is cleared by writing ‘1’ to the SENDFINCLR bit in the I2C control register. NOTE:All bits are active at HIGH level (‘1’). I2CSBUF – RECEIVER AND TRANSMITTER REGISTERS The Transmitter Data Register consists of eight Data bits which will be sent on the bus due the next Send operation. The first send bit is the D.7(MSB). I2CSBUF (0xF3) ? Address/Name F3h I2CSBUF Reset R/W R/W Bit 7 D.7 0 Bit 6 D.6 0 Bit 5 D.5 0 Bit 4 D.4 0 Bit 3 D.3 0 Bit 2 D.2 0

EN
0 Bit 3 D.3 0 Bit 2 D.2 0 0

0

0

N

Address/Name F3h I2CSBUF Reset

R/W R/W

Bit 7 D.7

Bit 6 D.6

Bit 5 D.5 0

FI D
Bit 4 D.4 0

The Receiver Data Register consists of eight data bits which have been received on the bus due the last Receive operation. I2CSBUF (0xF3) Bit 1 D.1 Bit 0 D.0 0

14.7 AVAILABLE I2C MODULE TRANSMISSION MODES
14.7.1 I2C module SINGLE RECEIVE

The figure below shows a set of sequences during Single data Send by I2C MODULE. Single send sequences : ? Start condition 2 ? I C module is addressed by I2C Master as transmitter 2 ? Address is acknowledged by I C module 2 ? Data is transmitted by I C module ? Data is not acknowledged by I2C Master ? Stop condition

A

14.7.3 I2C module BURST RECEIVE

The figure below shows a set of sequences during Burst data Receive by I2C module. Burst receive sequences: ? Start condition ? I2C module is addressed by I2C Master as receiver 2 ? Address is acknowledged by I C module ? (1)Data is received by I2C module ? (2)Data is acknowledged by I2C module 82

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14.7.2 I2C module SINGLE SEND

IC

The figure below shows a set of sequences during Single data Receive by I2C MODULE. Single receive sequences: ? Start condition ? I2C module is addressed by I2C Master as receiver ? Address is acknowledged by I2C module 2 ? Data is received by I C module ? Data is acknowledged by I2C module ? Stop condition

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This chapter describes all available transmission modes of the I2C module core. Default I2C own address for all presented waveforms is 0x39 (“0111001”).

C O

Dec. 2014, Version 0.5(Preliminary)

AMICCOM Electronics Corporation

TI A
Bit 1 D.1 Bit 0 D.0 0

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
? STOP condition Sequences (1) and (2) are repeated until Stop condition occurs.

14.7.4 I2C module BURST SEND

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Dec. 2014, Version 0.5(Preliminary)

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The figure below shows a set of sequences during Burst Data Send by I2C module. Burst send sequences: ? Start condition ? I2C module is addressed by I2C Master as transmitter ? Address is acknowledged by I2C module ? (1)Data is transmitted by I2C module ? (2)Data is acknowledged by I2C Master ? (3)Last data is not acknowledged by I2C Master ? Stop condition Sequences (1) and (2) are repeated until last transmitted data is not acknowledged (3) by I2C Master.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
14.7.5 AVAILABLE I2C module COMMAND SEQUENCES FLOWCHART
IDLE software reset Write own Address to I2CSOA register Write ,,1-------“ to I2CSCR register Write ,,01------“ to I2CSCR register Read I2CSCR register

RREQ = ‘1’ NO

YES

TREQ = ‘1’ NO

(Burst) Send is done

M

C O

YES

SENDFIN = ‘1’ NO

N O
Clear SENDFIN bit RECFIN = ‘1’ NO

IC

C

M

A

Figure14.20 Available I2C MODULE command sequences flowchart

14.8 I2C MODULE INTERRUPT GENERATION
I2C MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or transfer error has occurred. I2CSIF flag has to be cleared by software. Interrupt flag I2CSIF Function Internal, DI2CS
Table14.16

Active level/edge -

FI D
YES YES

Read data from I2CSBUF register

write data to I2CSBUF register

Flag resets Software

I2C MODULE interrupt summary

I2C MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1) bit called EA. 84

Dec. 2014, Version 0.5(Preliminary)

AMICCOM Electronics Corporation

EN
(Burst) Receive is done Clear RECFIN bit

Vector 0x73

TI A
Natural priority 15

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
EIE (0xE8) Address/Name E8h EIE Reset R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EI2CS EI2CM EWDI EINT6 EINT5 EINT4 EINT3 EINT2 ESPI 0 0 0 0 0 0 0 0

EI2CS:Enable I2C MODULE interrupts

Address/Name F8h EIP Reset

R/W R/W

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI2CS PI2CM PWDI PINT6 PINT5 PINT4 PINT3 PINT2 PSPI

PI2CS:I2C MODULE priority level control (at 1-high-level) EIF (0x91) Address/Name 91h EIF Reset R/W R/W

Bit 7 Bit 6 Bit 5 I2CSF I2CMF SPIF 0 0 0

FI D
Bit 4 Bit 3 0 0

EN
Bit 2 Bit 1 0 0

0

0

0

0

0

INT6F INT5F INT4F INT3F INT2F 0

C O

I2CSIF:I2C MODULE interrupt flag Software should determine the source of interrupt by check both modules’ interrupt related bits. Must software writing 0x80. It cannot be set by software. -:Unimplemented bit. Read as 0 or 1.

N

TI A
0 0 0 Bit 0 be cleared by

EIP

(0xF8)

A

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C

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Sub1GHz FSK/GFSK Transceiver SOC
15. SPI interface
The SPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. The SPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of inter-processor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. The SPI is a technology independent design that can be implemented in a variety of process technologies. The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as System clock divided by four (CLK/4). Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. The SPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support inter-processor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple ‐master mode‐fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to be become bus master.

15.1 KEY FEATURES
?

?

SPI Master ? Full duplex synchronous serial data transfer ? Master operation ? Multi-master system supported ? Up to 8 SPI slaves can be addressed ? System error detection ? Interrupt generation ? Supports speeds up to 1/4 up to system clock ? Bit rates generated 1/4, 1/8, 1/32, 1/64, 1/128, 1/512 of system clock ? Four transfer formats supported ? Simple interface allows easy connection to microcontrollers SPI Slave ? Full duplex synchronous serial data transfer ? Slave operation ? System error detection ? Interrupt generation ? Supports speeds up to 1/4 of system clock ? Simple interface allows easy connection to microcontrollers

A

M

IC

All features listed below are included in the current version of SPI core.

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C O

N
Dec. 2014, Version 0.5(Preliminary)

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AMICCOM Electronics Corporation

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
? ? Four transfer formats supported Fully synthesizable, static synchronous design with no internal tri-states

15.2 SPI PINS DESCRIPTION
PIN Scki_Scko(P0.0) Miso(P0.1) simo(P0.2) ss(P0.3) ss7o – ss0o(P0.4) TYPE INPUT / OUTPUT INPUT / OUTPUT INPUT / OUTPUT INPUT OUTPUT ACTIVE low low DESCRIPTION SPI clock input / output Master serial data input / Slave serial data output Slave serial data input / Master serial data output Slave select Slave select output

Table15.1

SPI pins description

15.3.1 BLOCK DIAGRAM

A

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The eight pins are associated with the SPI: the SS, clock pins SCKI, SCKO and SCKEN, master pins MI and MO and slave pins SOEN, SI and SO. The SS input pin in a master mode is used to detect mode‐fault errors. A low on this pin indicates that some other device in a multi‐master system has become a master and trying to select the SPI MODULE as a slave. The SS input pin in a slave mode is used to enable transfer.

M

C O

Figure 15.2 SPI Block Diagram

N
87

When an SPI transfer occurs, an 8‐bit character is shifted out on data pin while a different 8‐bit character is simultaneously shifted in a second data pin. Another way to view this transfer is that an 8 ‐bit shift register in the master and another 8‐bit shift register in the slave are connected as a circular 16‐bit shift register. When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged. The central element in the SPI system is the block containing the shift register and the read data buffer. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means new data for transmission cannot be written to the shifter until the previous transaction is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition will occur.

Dec. 2014, Version 0.5(Preliminary)

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AMICCOM Electronics Corporation

EN

15.3 SPI HARDWARE DESCRIPTION

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
The SCKI pin is used when the SPI is configured as a slave. The input clock from a master synchronizes data transfer between a master and the slave devices. The slave device ignore the SCKI signal unless the SS (slave select) pin is active low. The SCKO and SCKEN pins are used as the SPI clock signal reference in a master mode. When the master initiates a transfer eight clock cycles is automatically generated on the SCKO pin. When the SPI is configured as a slave the SI pin is the slave input data line, and the SO is the slave output data line. When the SPI is configured as a master, the MI pin is the master input data line, and the MO is the master output data line.

15.3.2 INTERNAL REGISTERS
?

R/W

SPIE 0

SPE 0

SPR2 MSTR CPOL CPHA SPR1 SPR0 0 0 0 1 0 0

Reset

?

A

M

Slave Select Control Register The control register may be read or written at any time. It is used to configure which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O ‐SS0O pins when SPI master transmission starts. SSCR (0xEF) Address/Name EFh SSCR Reset R/W R/W Bit 7 SS7 Bit 6 SS6 1 Bit 5 SS5 1 Bit 4 SS4 1 Bit 3 SS3 1 Bit 2 SS2 1 Bit 1 SS1 1 Bit 0 SS0 1

1 SS7 – SS0 = 0, Pin SSxO assigned while Master Transfer = 1, Pin SSxO is forced to logic 1 ? SPI Status Register SPSR (0xED) Address/Name R/W Bit 7

IC

C

SPIE:SPI interrupt enable = 0, interrupts are disabled, polling mode is used = 1, interrupts are enabled SPE:SPI system enable = 0, system is off = 1, system is on MSTR:Master/Slave mode select = 0, slave = 1, master CPOL:Clock polarity select = 0, high level; SCK idle low = 1, low level; SCK idle high CPHA:Clock phase.. Select one of two different transfer formats SPR[2:0]:SPI clock rate select bits. See the table below SPR2 SPR1 SPR0 System clock divided by 0 0 0 4 0 0 1 8 0 1 0 16 0 1 1 32 1 0 0 64 1 0 1 128 1 1 0 256 1 1 1 512

O

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C O

Bit 6

N
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 88

Dec. 2014, Version 0.5(Preliminary)

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AMICCOM Electronics Corporation

EN

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Address/Name ECh EIE

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

L
Bit 0

SPI Control Register The control register may be read or written at any time, is used to configure the SPI System. SPCR (0xEC)

A9108
Sub1GHz FSK/GFSK Transceiver SOC
EDh EIE Reset R/W SPIF WCOL 0 0 0 MODF 0 0 1 0 SSCEN 0

Reset

C O

EEh SPDR

R/W

D.7 0

D.6 0

N

Address/Name

R/W

Bit 7

Bit 6

Bit 5 D.5 0

FI D
Bit 4 D.4 0 Bit 3 D.3 0 Bit 4 D.4 0 Bit 3 D.3 0 D.5 0

SPI status register (SPSR) contains flags indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence. SPIF and WCOL are automatically cleared by reading SPSR followed by an access of the SPDR. MODF flag is cleared by reading SPSR with MODF set followed by a write to SPCR. The SSCSEN bit is a enable bit of automatic Slave Select Outputs assertion. When SSCEN is set (‘1’) then during master transmission the SSXO lines are automatically loaded with contents of SSCR register before each byte transfer, and deasserted when byte is transferred. When SSCEN bit is cleared the SSXO lines always shows contents of the SSCR register, regardless of the transmission is in progress or SPI MODULE is in IDLE state. ? Receiver and Transmitter Registers The Transmitted Data Register consists of eight data bits, which will be sending on the bus due the next Send operation. The first send bit is the D.7 (MSB). SPDR (0xEE)

EN
Bit 2 D.2 1 0 Bit 2 D.2 1 0

The Received Data Register consists of eight data bits, which were received on the bus due the last Receive operation. SPDR (0xEE) Address/Name EEh SPDR Reset

M

R/W R/W

Bit 7 D.7 0

Bit 6 D.6 0

Bit 5

O

15.4 MASTER OPERATIONS
When the SPI MODULE core is configured as a SPI master, the transfer is initiated by write to the SPDR register. When the new byte is written to the SPDR register, SPI MODULE begins transfer on the nearest BAUD timer overflow. The serial clock SCK is generated by the SPI MODULE. In master mode the SPI MODULE activates the SCKEN to enable the SCK output driver. The SPI MODULE in master mode can select one of the eight SPI slave devices, through the SSxO lines. The SSxO lines – Slave Select output lines are loaded with contents of the SSCR register (0x03). The SSCEN bit from the SPSR register select between automatic SSxO lines control and software control. When set the automatic Slave Select outputs assertion is enabled. With SSCEN bit set in master mode the SSXO lines are automatically loaded with contents of SSCR register before each byte transfer, and deasserted when byte is transferred. When SSCEN bit is cleared the SSXO lines are controlled by the software, and always shows contents of the SSCR register, regardless of the transmission is in progress or the SPI MODULE is in IDLE state.

A

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AMICCOM Electronics Corporation

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Bit 1 D.1 Bit 0 D.0 0 Bit 1 D.1 Bit 0 D.0 0

SPIF:SPI interrupt request. The flag is automatically set to one at the end of an SPI transfer. WCOL:Write collision error status flag. The flag is automatically set if the SPDR is written while a transfer MODF:SPI mode-fault error status flag This flag is set if SS pin goes to active low while the SPI is configured as a master (MSTR = 1) SSCEN: = 1, auto SS assertions enabled = 0, auto SS assertions disabled – SSO always shows contents of SSCR

is in process.

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A9108
Sub1GHz FSK/GFSK Transceiver SOC

Figure15.3

Automatic slave select lines assertion

Figure15.4

Software controlled SSxO lines

15.4.1 MASTER MODE ERRORS

In master mode two system errors can be detected by the SPI MODULE. The first type of error arises in multiple‐master system when more than one SPI device simultaneously tries to be a master. This error is called a Mode Fault. The second error type, a Write Collision, indicates that CPU tried to write the SPDR register while transfer was in progress. ? MODE FAULT ERROR Mode fault error occur when the SPI MODULE is configured as a master and some other SPI master device will select this device as if it were a slave. If a Mode Fault Error occur : ? The MSTR bit is forced to zero to reconfigure the SPI MODULE as a slave. ? The SPE bit is forced to zero to disable the SPI MODULE system ? The MODF status flag is set and an interrupt request is generated

A

M

IC

The MODF flag is cleared by reading SPSR with MODF set followed by a write to SPCR

C

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?

WRITE-COLLISION ERROR 90

C O

Figure15.5

N

Mode Fault Error generation

Dec. 2014, Version 0.5(Preliminary)

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AMICCOM Electronics Corporation

EN

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A9108
Sub1GHz FSK/GFSK Transceiver SOC
A write collision occurs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. The Write Collision is indicated by the WCOL flag in SPSR (3) register. The WCOL flag is set automatically by hardware, when the WCOL error condition occurs. To clear the WCOL bit, user should execute the following sequence: ? Read contents of the SPSR register ? Perform access to the SPDR register ( read or write )

Figure15.6

Write Collision Error in SPI Master mode

15.5 SLAVE OPERATIONS

15.5.1 SLAVE MODE ERRORS

A

M

IC

C

?

WRITE-COLLISION ERROR A write collision occurs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. The Write Collision is indicated by the WCOL flag in SPSR (3) register. The WCOL flag is set automatically by hardware, when the WCOL error condition occurs. To clear the WCLO bit, user should execute the following sequence: ? Read contents of the SPSR register ? Perform access to the SPDR register ( read or write )

Figure15.7

O

In slave mode, only the Write Collision Error can be detected by the SPI MODULE. The Write Collision Error occurs when the SPDR register write is performed while the SPI MODULE transfer is in progress. In SLAVE mode when the CPHA is cleared, the write collision error may occur as long as the SS Slave Select line is driven low, even if all bits are already transferred. This is because there is not clearly specified the transfer beginning, and SS driven low after full byte transfer may indicate beginning of the next byte transfer.

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Write Collision Error – SPI Slave mode – SPDR write during transfer

C O

When configured as SPI Slave the SPI MODULE transfer is initiated by external SPI master module by assertion of the SPI MODULE Slave Select input, and gen

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