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PVD Process introduction-TJ050419


PVD Process Introduction

Outline 1. IC Typical Schematic
2. PVD Technology 3. AlCu PVD 4. Salicide PVD 5. Barrier PVD 6. WCVD

Logic- Typical Schematic

15KA

Passivation

M4

17KA

IMD-3 M3

17KA

IMD-2 M2

PETEOS SACVD

17KA

IMD-1 M1 ILD FOX P+ N-well FOX P+ N+
P-

PETEOS AlCu SACVD

W
FOX
NNPP-

N+

PP-well

P- P-

Memory- Typical Schematic
PI Ti 50A/TiN 700A
PASS-2

TiN 500A AlCu 6500A

PI

PI

AlCu 4000A Ti 200A/TiN 500A
PASS-2 PASS-1 PASS-1

Ti 200A/TiN 500A PASS-2
PASS-1 PASS-2 PASS-1

M3

WCVD 4K MOTiN 2x35A IMP TI 200A PCII 250A

IMD2

IMD2

IMD1

IMD1

WCVD 2.4K MOTiN 2x35A IMP TI 200A PCII 250A

WCVD 1K

ILD

TiCl4 TiN 200A TiCL4 Ti 100A PCII 75A
P2 P2 STI P2 P2 P2 P2 STI STI FOX FOX STI N-Well PERIPHERAL CROSS SECTION P-Well STI

Cell CELL ARRAY CROSS SECTION

WSix 1K

1. IC Typical Schematic

2. PVD Technology
3. AlCu PVD 4. Salicide PVD 5. Barrier PVD 6. WCVD

Sputtering

Sputtering

Target Erosion

AMAT ENDURA 5500
Transfer Chamber

PVD Chamber

Robot

Preclean Chamber

Cooldown Chamber

Buffer Chamber

Wafer Orienter/Degas Chamber

PVD Chamber Configuration
COOLING WATER
MOTOR

MAGNET

DC POWER
TARGET

GATE VALVE

SHIELD WAFER CLAMP RING LIFTER PEDESTAL GAS VALVE

CRYO PUMP

ROUGHING VALVE ROUGHING VALVE

MFC
GAS VALVE BAKE OUT LAMP

GAS DC Voltage

MFC

GAS

CDA
To ROUGHING PUMP

EV

1. IC Typical Schematic 2. PVD Technology

3. AlCu PVD
4. Salicide PVD 5. Barrier PVD 6. WCVD

Film Stacks
Si O
Bottom TTN Layer 1) Ti:a)Buffer; Ti =>TiO+Si (Rs low);

O

ARC

2) TiN: 隔开AL : AL+Ti=>TiAL3 (Rs ) Top TTN-Dep : AL+Ti+TiN Rs high& AL+Ti=>TiAL3 (AL Rough); 2) Ti: a. if no Ti layer:AL+N+=> ALN3 b. if has Ti layer: AL+Ti+ N+ =>ALTi3+TiN ALTi3(Rs) <ALN3(Rs)> c. Ti can prevent EM.

AL
TIN
Ti

ARC
TI

AL
TIN
Ti

TTN process

Al-Cu Phase Diagram Al-

270C

Cu 0.5%

1. IC Typical Schematic 2. PVD Technology 3. AlCu PVD

4. Salicide PVD
5. Barrier PVD 6. WCVD

Salicide Process
HF Dip (100: 1) 120s (to remove native oxide) PC II (~50?) (to remove remaining oxide) Ti, Co Deposition Capping Layer Dep. ( TiN, 80-150?)

1st RTA (~500C, ~30s) Selective Etch (Piranha etch)

2nd RTA (~800C, ~45s)

Titanium Salicide Process
Salicide = Self Aligned Silicide

Sputtered Ti layer Gate
Ox Spacer Ox Spacer Spacer

Oxide P+ Source

Poly Gate Ox

Oxide P+

N+

Drain

1. A thin Ti layer is sputter over the entire wafer surface.

Titanium Salicide Process (con’t)
Gate
Ox Spacer

TiSi Oxide P+ Source

TiSi Poly Gate Ox N+

TiSi Oxide P+ Drain

2. The wafer is then annealed at low temperature (about 600C). At low temperature the Ti layer only reacts with the silicon contacts to form a high resistivity TiSi phase (C49). 3. The un-reacted titanium is then etched off the wafer surface (An etch solution that does not remove silicide or oxide is used) 4. A second anneal is then performed at high temperature (>800C) to convert the high resistivity phase (C49 or TiSi) to the desired low resistivity phase (C54 or TiSi2).

Ox Spacer

Comparison of Different Silicide Schemes
Silicide Resistivity (??-cm) RTA1 Temperature (oC) RTA2 Temperature (oC) Film Stress (dyn/cm 2) Silicon Consumption (element/silicon/silicide) (A) Line width Dependence Moving species Stability (oC) TiSi2 (C54) 13-16 600-800 (C49) 700-900 (C54) 1.5 E10 1 / 2.22 / 2.50 CoSi2 14-18 400-600 (CoSi) 650-850 (CoSi2) 1.2 E10 1 / 3.61 / 3.49

High resistivity at low line width Si 900

No apparent dependence Co ~1000 (with Ti cap)

1. IC Typical Schematic 2. PVD Technology 3. AlCu PVD 4. Salicide PVD

5. Barrier PVD
6. WCVD

PVD Step Coverage Technology
Techniques are : Mechanical collimator : the sputtered atoms pass through a grid in the chamber Long Throw technology : the distance between the target and the wafer is increased (190, 245, 430 mm) and the neutral atoms arrive plus or minus perpendicularly on the wafer Ionized plasma : the neutral atoms sputtered from the target are ionized inside the chamber, and the metallic ions are collimated to the wafer which is biased

Step Coverage

Via or Trench filling with Sputtering
- High aspect ratio features have limited line of sight to target. - Conventional, non-directional sputtering results in “cusping” of sputtered material at the via opening creating a void.

Void

Long Throw PVD

IMP Sputter Process
-IMP: Ionized Metal Plasma -ve bias on the wafer attracts ionized metal into the wafer “vertically” improving bottom coverage

IMP PVD (Ion Metal Plasma)
TARGET RF COIL DC POWER

RF POWER

PEDESTAL

WAFER

CHAMBER RF BIAS (option)

Applied MOCVD-TiN (TDMAT)

MOCVDMOCVD-TiN TxZ process sequence

MOCVD TiN

plasma treatment TDMAT(TiCxNyHz) N2 H2

TiN

MOCVD TiN
Plasma Treatment Enhance Key Film Properties

N2

+

H2

+

CxHy+HNR2

(By-products pumped out)

TiCxNyHz
(50~60% of as deposited thickness)

Barrier Process Overview

1. IC Typical Schematic 2. PVD Technology 3. AlCu PVD 4. Salicide PVD 5. Barrier PVD

6. WCVD

AMAT CENTURA 5200

WCVD Basic Reaction A. 1. Reaction during WCVD Nucleation: WF6 + SiH4 W(s) + SiF4 +HF WF6 + H2 2. Bulk deposition: WF6 + H2 3. Substrate attack: WF6 + Ti W(s) + HF W(s) + HF TiFx + W W(s) + SiFx

Si + WF6 B. Reaction during clean NF3

N2+xF2+YF WFx

W + xF2 +yF

ILD
Si/TiSix/CoSix/WSix ILD patterning ILD Si/TiSix/CoSix/WSix

ILD Si/TiSix/CoSix/WSix

Blank W Depositi on

ILD 1.Ti/Anneal/TiN 2.Ti/TiN Si/TiSix/CoSix/WSix

Metal 2
ILD Si/TiSix/CoSix/WSix

W removed by plasma etching or CMP

ILD Si/TiSix/CoSix/WSix


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