Synchronous buck MOSFET loss calculations with Excel model
Jon Klein Power Management Applications
buck circuit is in widespread use to provide “point of use” high current, low voltage power for CPU’s, chipsets, peripherals etc. Typically used to convert from a 12V or 5V “bulk” supply, they provide outputs as low as 0.7V for low voltage CPUs made in sub-micron technologies. The majority of the power lost in the conversion process is due to losses in the power MOSFET switches. The profiles of loss for the High-Side and Low-Side MOSFET are quite different. These low output voltage converters have low duty cycles, concentrating the majority of the conduction loss in the low-side MOSFET.
PWM CONTROLLER H igh-Side Q1 SW N O D E D1 Low -S ide Q2
The power loss in any MOSFET is the combination of the switching losses and the MOSFET’s conduction losses.
PMOSFET = PSW + PCOND
Q1 (Figure 1) bears the brunt of the switching losses, since it swings the full input voltage with full current through it. In low duty cycle converters (for example: 12VIN to 1.8VOUT) switching losses tend to dominate.
High-Side Conduction Losses:
Calculating high-side conduction loss is straightforward as the conduction losses are just the I2R losses in the MOSFET times the MOSFET’s duty cycle:
PCOND = IOUT 2 RDS(ON) VOUT VIN
VO UT –
where RDS(ON) is @ the maximum operating MOSFET junction temperature (TJ(MAX) ). The maximum operating junction temperature is equation can be calculated by using an iterative technique. Since
RDS(ON) rises with TJ and TJ rises with PD (dissipated power) and PD is largely being determined by I2 x RDS(ON) .
Figure 1. Synchronous Buck output stage
For the examples in the following discussion, we will be analyzing losses for the following synchronous buck converter:
System Parameters VIN VOUT IOUT FSW 12 1.5 15 300 V V A kHz
The spreadsheet calculator iterates the die temperature and accounts for the MOSFET's positive RDS(ON) temperature coefficient. Iteration continues in the "DieTemp" custom function until the die temperature has stabilized to within 0.01°C.
High-Side Switching Losses:
The switching time is broken up into 5 periods (t1-t5) as illustrated in Figure 3. The top drawing in Figure 3 shows the voltage across the MOSFET and the current through it. The bottom timing graph represents VGS as a function of time. The shape of this graph is identical to the shape of the QG curve contained in MOSFET datasheets, which assumes the gate is being driven with a constant current. The QG
Table 1. Example Synchronous Buck
A spreadsheet to aid in the estimation of synchronous buck losses is available on Fairchild’s web site on (click here to download): http://www.fairchildsemi.com/collateral/AN6005.zip. Operation of the spreadsheet is described in the Appendix at the end of this document.
Synchronous Buck Loss Calculation
notations indicate which QG is being charged during the corresponding time period.
VIN VDRIVE (VDD) CRSS RDRIVER HDRV G RGATE CGS SW S COSS D
During this time the current is constant (at IOUT) and the voltage is falling fairly linearly from VIN to 0, therefore:
V I E t3 = t3 IN OUT 2
Figure 2. Drive Equivalent Circuit
During t4 and t5, the MOSFET is just fully enhancing the channel to obtain its rated RDS(ON) at a rated VGS. The losses during this time are very small compared to t2 and t3, when the MOSFET is simultaneously sustaining voltage and conducting current, so we can safely ignore them in the analysis. The switching loss for any given edge is just the power that occurs in each switching interval, multipied by the duty cycle of the switching interval:
S w itching losses are in S haded section
V I PSW = IN OUT (t2 + t3) (FSW ) 2
Now, all we need to determine are t2 and t3. Each period is determined by how long it takes the gate driver to deliver all of the charge required to move through that time period:
V SP V TH Q G (SW ) t1 t2 t3 t4 t5
Q G(x) I DRIVER
CISS = CGS + CRSS Figure 3. High-Side Switching losses and QG
Most of the switching interval is spent in t3, which occurs at a voltage we refer to as “VSP”, or the “switching point” voltage. While this is not specifically specified in most MOSFET datasheets, it can be read from the Gate Charge graph, or approximated using the following equation:
I VSP ≈ VTH + OUT GM
The switching interval begins when the high-side MOSFET driver turns on and begins to supply current to Q1’s gate to charge its input capacitance. There are no switching losses until VGS reaches the MOSFET’s VTH. therefore Pt1 = 0. When VGS reaches VTH, the input capacitance (CISS) is being charged and ID (the MOSFET’s drain current) is rising linearly until it reaches the current in L1 (IL) which is presumed to be IOUT. During this period (t2) the MOSFET is sustaining the entire input voltage across it, therefore, the energy in the MOSFET during t2 is:
where GM is the MOSFET’s transconductance, and VTH is its typical gate threshold voltage. With VSP known, the gate current can be determined by Ohm’s law on the circuit in Figure 2:
IDRIVER(L H) = VDD - VSP RDRIVER(PULL -UP) + RGATE
IDRIVER(HL ) =
VSP (8B) RDRIVER(PULL-DOWN) + RGATE
V I E t2 = t2 IN OUT 2
The rising time (L-H) and falling times (H-L) are treated separately, since IDRIVER can be different for each edge. The VGS excursion during t2 is from VTH to VSP. Approximating this as VSP simplifies the calculation considerably and introduces no significant error. This approximation also allows us to use the QG(SW) term to represent the gate charge for a MOSFET to move through the switching interval. A few
Now, we enter t3. At this point, IOUT is flowing through Q1, and the VDS begins to fall. Now, all of the gate current will be going to recharge CGD. CGD is similar to the “Miller” capacitance of bipolar transistors, so t3 could be thought of as “Miller time”.
Synchronous Buck Loss Calculation
MOSFET manufacturers specify QG(SW) on their data sheets. For those that don't, it can be approximated by:
QG(SW ) ≈ QGD + QGS 2
Driver dissipation calculates to :
PDR(H-L) = PDR(L-H) = 500 * 5 = 147mW 2(8.5) 500 * 2 = 91mW 2(5.5)
so the switching times therefore are:
t S(L H) = tS(HL ) = QG(SW) IDRIVER(L -H) QG(SW) IDRIVER(H-L)
PDRIVER = PDR(H-L) + PDR(L -H) = 238mW (11G)
The power to charge the MOSFET’s output capacitance:
PCOSS ≈ C oss VIN2 FSW 2 (11H)
The switching loss discussion above can be summarized as:
V XI PSW = IN OUT (FSW ) t S(L -H) + t S(H L ) (10C) 2
where COSS is the MOSFETs output capacitance, (CDS +CDG). 3. If an external schottky is used across Q2, the Schottky’s capacitance needs to be charged during the high-side MOSFET’s turn-on:
PC(SCHOTTKY) = CSCHOTTKY VIN2 FSW 2 (12A)
There are several additional losses that are typically much smaller than the aforementioned losses. Although their proportional impact on efficiency is low, they can be significant because of where the dissipation occurs (for example, driver dissipation). They are listed in order of importance: 1. The power to charge the gate:
PGATE = QG X VDD X FSW (11A)
If a Schottky diode is not used: 4. Reverse recover power for Q2’s body diode:
PQRR = QRR VIN FSW (12B)
Note that PGATE is the power from the VDD supply required to drive a MOSFET gate. It is independent of the driver's output resistance and includes both the rising and falling edges. PGATE is distributed between RDRIVER, RGATE, and RDAMPING propoprtional to their resistances. Dissipation in the driver for the rising edge is:
PDR(L -H) =
where RTOTAL = RDRIVER + RGATE + RDAMPING (11C)
where QRR is the body diode’s reverse recovery charge. If the MOSFET contains an integrated body diode (like SyncFET), the QRR figure in the datasheet is actually QOSS, or the charge required by the MOSFET’s COSS . If a SyncFET is used, then set QRR to 0 in the companion spreadsheet.
Low-side losses (PLS) are also comprised of conduction losses and switching losses.
PLS = PSW + PCOND (13)
PGATE RDRIVER(PULL -UP) 2(RTOTAL )
Similarly, dissipation in the driver for the falling edge is:
PDR(H-L) = PGATE RDRIVER(PULL -DOWN) 2(RTOTAL )
Switching losses are negligible, since Q2 switches on and off with only a diode drop across it, however for completeness we will include the analysis. Conduction losses for Q2 are given by:
PCOND = ( 1 D ) X IOUT 2 X R DS(ON)
For an output stage (Driver + MOSFET) with the following parameters: PGATE RDRIVER (PULL-UP) RDRIVER (PULL-DOWN) RDAMPING RGATE 500 5 2 2 1.5 mW
where RDS(ON) is the RDS(ON) of the MOSFET at the anticipated operating junction temperature and D=
is the duty cycle for the converter.
The junction temperature (TJ) of the MOSFET can be calculated if the junction to ambient thermal resistance (θJA) and maximum ambient temperature are known.
Synchronous Buck Loss Calculation
TJ = TA + (PLS θ JA )
PCOND dominates PLS. Since RDS(ON) determines PCOND , and is a function of TJ, either an iterative calculation can be used, or TJ can be assumed to be some maximum number determined by the design goals. The calculations in the accompanying spreadsheet use TA and θJA iteratively to determine the low-side operating TJ at full current, assuming a MOSFET RDS(ON) temperature coefficient of 0.4%/°C, which is typical for the MOSFETs used in this application.
the RDS(ON) is typically 110% of the specified RDS(ON) . The rising edge transition times for the low-side (t2 and t3 in Figure 4) can now be calculated from the RC equations.
t2R = K 2R (R DRIVER + R GATE ) CISS where (17A)
VDRIVE VDRIVE K 2R = ln ln (17B) VDRIVE VTH VDRIVE VSP
t3R = K 3R (R DRIVER + R GATE ) CISS where (17C)
Low-side Switching Losses
C 0 – IO U T x R D S (O N )
VDRIVE VDRIVE K 3R = ln ln VDRIVE 0.9VSPEC VDRIVE VSP
– IO U T t1 V D R IV ER V SP 0.9 x V S P EC t2 t3
and where CISS is the MOSFET’s input capacitance (CGS + CGD) when VDS is near 0V. If the MOSFET datasheet has no graph of capacitance vs. VDS, use 1.25 times the typical CISS value, which is usually given with of the rated VDS across the MOSFET. The turn-off losses are the same, but in reverse, so the switching waveforms are:
– I x R D S (O N )
Figure 4. Low-Side turn-on switching loss waveforms
–I t3 t2 t1 V D R IV ER 0.9 x V S P EC V SP
Low-side switching losses for each edge can be calculated in a similar fashion to high-side switching losses:
VF + IOUT 1.1 RDS(ON) t2 VF + t3 IOUT Fsw 2
(16) PSW(LS) ≈
but instead of VIN as in eq. 3, we use VF , the schottky diode drop (approximated as 0.6V) in the equation. Also, there is almost no Miller effect for the low-side MOSFET, since VDS is increasing (becoming less negative) as we turn the device on, the gate driver is not having to supply charge to CGD. The voltage collapse for Q2 is caused by the RDS(ON) going from
0 .6 IOUT
Figure 5. Low-Side turn-off switching loss waveforms
The falling edge transition times for the low-side (t3 and t2 in Figure 5) can now be calculated from the RC equations:
t3F = K 3F (R DRIVER + R GATE ) CISS where (18A)
@ VGS = VSP, to 90% of VSPEC, the gate voltage
for the highest specified RDS(ON) . At 90% of VSPEC
Synchronous Buck Loss Calculation
0.9VSPEC K3F = ln VSP t2F = K 2F (R DRIVER + R GATE ) C ISS where V K2F = ln SP VTH
t TH ≈
Q GS 2 ILDRV
This approximation holds, since prior to reaching threshold, the gate voltage is low enough that ILDRV can be approximated with a constant current of
V VDRIVER TH 2 ≈ R GATE + R DRIVER
Q GS . 2
Dead-Time (Diode Conduction) Losses The dead-time is the amount of time that both MOSFETs are off. During this time the diode (body diode or parallel schottky diode) is in forward conduction. It's power loss is:
PDIODE = tDEADTIME FSW VF IOUT
and typically Q G( TH) ≈
The diode's total on-time on the falling edge is then:
t DEADTIME(F) ≈ t DELAY(F) +
where tDEADTIME = tDEADTIME(R) + tDEADTIME(F), which are the deadtimes associated before the SW Node (Figure 1) rises, after Q2 turns off, and after SW Node falls, before Q2 turns on, respectively. To determine tDEADTIME, we need to consider how the driver controls the MOSFET gate drives. Most drivers use "adaptive dead-time circuits, which wait for the voltage of the opposite MOSFET to reach an "off" voltage before beginning to charge its own MOSFET. Most drivers add a fixed delay to prevent shoot-through, especially on the low to high transition.
HDRV H.S. MOSFET
40nS 1V LDRV RDamping RDRIVER G CGD RGATE CGS
Q GS (R GATE + RDRIVER ) VTH VDRIVER 2
On the rising edge, tDELAY(R) is usually much longer to allow the low-side MOSFET’s gate to discharge completely. This is necessary since charge is coupled into the low-side gate during the rising edge of the SW node. The peak of the resultant voltage “spike” at the low-side gate is the sum of the amplitude of the injected spike and the voltage the gate has discharged to when the SW node begins to rise. Sufficient delay is necessary to avoid having the resultant peak rise significantly above the low-side’s VTH , turning on both MOSFETs, and inducing “shoot-through” losses.
SW NODE VOLTAGE
14 12 10 8
LS MOSFET GATE
4 VGS 3 2
6 4 2
Figure 6. Typical Adaptive Gate drive (low-high transition)
0 20 40
0 -2 60 80
For the tDEADTIME(F) the diode will be conducting the full load current from the time the switch node falls, until the Low-side MOSFET reaches threshold. This "deadtime" consists of 2 portions: 1. tDELAY(F) : The driver’s built in delay time from detection of 1VGS at the high-side MOSFET gate until beginning of low-side MOSFET turnon, plus tTH : the time for the driver to charge the lowside MOSFET's gate to reach threshold (VTH).
Figure 7. Coupled voltage spike on Low-side MOSFET gate from SW node rising edge
The other component of deadtime on the rising edge is the time it takes for the high-side MOSFET’s gate to charge to VSP. This is typically less than 10% of tDELAY(R) so we will ignore it and set:
tDEADTIME(R) ≈ tDELAY(R) (23)
tTH can be approximated by:
Synchronous Buck Loss Calculation
Summary of results
A spreadsheet which contains MOSFET parameters is used to compute the losses for our example circuit (Table 1) using a 5V gate drive with 6 pull-up and 2 pull-down strength.
MOSFET Switching Loss Conduction Loss Other Losses Total Losses Output Power Efficiency High-Side Low-Side FDD6644 FDB6676 Total 1.09 0.31 1.40 W 0.21 1.15 1.36 W 0.26 W 1.30 1.46 3.02 W 22.5 W 88%
Table 2. Results for 15A example (Table 1)
It’s instructive to review the results in order to observe a few key points: Switching losses for the low-side MOSFET are only 15% of low-side MOSFET’s total losses. Unless the switching frequency is very high (above 1 Mhz.), the loss contribution due to diode conduction (deadtime loss) is minimal. High-side losses are dominated by switching losses since the duty cycle is low.
Synchronous Buck Loss Calculation
Appendix: Using the efficiency and loss calculation spreadsheet tool
The spreadsheet is contained in the following file: http://www.fairchildsemi.com/collateral/AN-6005.zip The spreadsheet implements the loss calculations described in this app note. To see the sheet in action press the "Run" button on the "EfficiencySummary" sheet. The controller/driver database models several Fairchild products driver products. A listing of these is found in the ControllerDriver tab. These detailed instructions can also be found in the " General Instructions" tab of the spreadsheet:
Notes: Be sure to turn off Macro Protection in Excel to allow the custom functions and macros in this sheet to run. For Excel 2000, this is done through "Tools|Macro|Security". Set the level to "low". In Excel 97, you can do this through "Tools|Options. In the "General" tab, the "Macro Virus Protection" box should not be checked. RDS(ON) is a function of die temperature, and the die temperature is a function of Power Dissipation which is in turn dependent on RDS(ON). To solve for dissipation or die temperature, the conduction loss calculations in this spreadsheet use an iterative calculation method to arrive at the die temperature and dissipation.
Tabs Definitions EfficiencyChart LossChart ControllerDriver MOSFETDatabase EfficiencySummary Output
Function / Description Provides guidance on what MOSFET parametric data to enter in the "MOSFETDatabase" tab. This sheet is a hotlink destination from some of the column headings in the MOSFETDatabase table. Plots efficiency data from the table in EfficiencySummary tab. Plots power loss data from the table in EfficiencySummary tab. Database for the IC Controllers. Fairchild's portable PWM controllers are featured in this database. Any controller can be added by using the "Add" button and filling in the appropriate fields. Database for the MOSFETs. Many popular Fairchild MOSFETs are featured in this database. Any MOSFET can be added by using the "Add" button and filling in the appropriate fields. The main sheet where the system requirements and MOSFET choices can be entered, and the data is stored for graphing. To run the graphing routine, push the "RUN" button at the top of the sheet. The calculations contained in the "Synchronous buck MOSFET loss calculations" app note are programmed into this sheet. The EfficiencySummary macro uses this sheet as its calculator. If a particular operating point needs to be examined in more detail, then use this sheet, and enter the parameters by hand. Be sure to save a copy of this workbook before overwriting formulas in "Output" tab.
Cells are color coded as follows: Indicates user input parameters Indicates calculated values that can be overwritten with selected values if desired. These fields default to the calculated value directly above them. These fields are written into, or contain formulae that were input on the "EfficiencySummary" sheet.
Macro Security Note: "AN-6005 Switching Loss Calculation.xls" uses macros extensively. For the spreadsheet to operate properly, check the “Always trust macros from this source” box if a security warning appears, then click the “Enable Macros” button.. This is only required the first time you run a Fairchild spreadsheet tool with macros.