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ADS工程移植到IAR工程的方法


ARMDeveloperSuite
to

ARMIAREmbeddedWorkbench
MigrationGuide

Partno:EWMRVARM1b

Introduction
This guide examines the differences between using t

he ARM Developer Suite (ADS) development tools IDE and the IAR Systems ARM development tools IDE. The issues related to assembler conversion range from basic topics such as command line options, system segment/area names, listing/output options, code generation options, register naming differences, assembler operators, assembler directives, pseudo-instructions, and other assembler differences, to advanced topics such as predefined symbols, conditional assembly, macros, and modules. Linker related topics such as command line options and image memory mapping are also documented. The features, options, descriptions, and examples specified in the document are based on tools associated with ARM Developer Suite Version 1.2 and ARM IAR Embedded Workbench Version 4.20A. Information about the ARM development tools was obtained from the ARM Developer Suite Version 1.2 Assembler Guide (ARM DUI 0068B) the ARM Developer Suite Version 1.2 Linker and Utilities Guide (ARM DUI 0151A) and the ARM Developer Suite Version 1.2 Developer Guide (ARM DUI 0056D). Information about the IAR Systems development tools is based on the ARM IAR Assembler Reference Guide (AARM-6), the ARM IAR C/C++ Compiler Reference Guide (CARM-10) and the IAR Linker and Library Tools Reference Guide (XLINK-459I).

IAREmbeddedWorkbenchIDEoverview
The IAR Embedded Workbench IDE consists of tools such as a compiler, assembler, linker, library builder, librarian, editor, project manager, command line interface, debugger, and simulator. ARM Developer Suite includes command-line development tools (which includes a compiler, ARM assembler, linker and various support libraries), GUI development tools (which includes a debugger, editor and project manager), a librarian and a simulator. Equivalent tools from both development environments are listed in table 1 together with the command line commands for invoking them:
Tools ARMDeveloperSuite IAREmbeddedWorkbenchIDE

Compiler Assembler Linker Librarybuilder Librarian Debugger Simulator
1.

ADSC/C++compiler,armccorarmcpp ADSARMassembler,armasm ADSARMlinker,armlink ADSARMlibrarian,armar ADSARMeXtendedDebugger(AXD) ADSARMulator

IARC/C++Compiler,iccarm IARARMAssembler,aarm IARXLINKLinker,xlink IARXARLibraryBuilder,xar IARXLIBLibrarian,xlib IARCSPYDebugger IARCSPYSimulator

ARM Developer Suite and IAR Embedded Workbench IDE equivalents

The ARM IAR C/C++ Compiler features efficient code generation with debug information, C/C++ language support facilities and type checking. The ARM IAR Assembler features a built-in C preprocessor and supports conditional assembly. The IAR XLINK Linker links object files produced by the compiler or assembler to produce machine code for the ARM core, while the IAR XAR Library Builder and IAR XLIB Librarian allow manipulation of library object files. The IAR C-SPY Debugger is a high-level language debugger that is integrated into the IDE, so corrections are made directly in the same source code window used to control the debugging.

TOOLSCOMPARISON
An immediate difference between the tool sets is the level of integration of the development environment. In IAR Embedded Workbench, the C-SPY Debugger is completely integrated with the IDE, whereas in ARM Developer Suite, the Codewarrior IDE by Metrowerks and the ARM eXtended Debugger (AXD) are separate tools that form a complete GUI-based development environment. However, essential project management options and tools, and make/build/debug menus are similar. Metrowerks Codewarrior IDE is a project management tool for managing source files and building software development projects, while the AXD debugger provides an environment for debugging C, C++ and assembly language source code. By default, the AXD debugger is called to debug and run images built from the Codewarrior IDE. The AXD debugger is available for Microsoft Windows and UNIX, but the Codewarrior IDE is only available for Windows. General debugger features like source and disassembly level debugging, source stepping, setting breakpoints, variable, register and expression monitoring/watching, call stack information and facilities for third-party extensions (RTOS awareness, simulation modules, emulator drivers, etc.) are available in both tool sets. Both source code editors provide typical utilities such as colored keywords and search and replace. ARM also provides an IDE called the RealView Developer Suite. Project files created with the Codewarrior IDE have the filename extension .mcp, compared to RealView Developer Suite project files that have the extension .prj. Note that if you migrate from the Codewarrior IDE to the RealView Developer Suite tools or vice versa, the project file will need to be re-created and relevant source files re-added. No automatic conversion tools exist.

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Gettingstarted
This section discusses how to get started with converting C and assembler projects from ARM Developer Suite to IAR Embedded Workbench.

Filenameextensions
In ARM Developer Suite, projects list all associated source files required by the target application. These project files have a .mcp filename extension. In IAR Embedded Workbench, workspaces are used for organizing multiple projects. This is useful when you are simultaneously managing several related projects. Workspace files have the filename extension .eww, and project files have the extension .ewp in IAR Embedded Workbench. The filename extensions of C source and header files are .c and .h, respectively, in both ARM Developer Suite and IAR Embedded Workbench, which includes standard library files and user-specific files. The filename extension of assembler source files in ARM Developer Suite is .s. IAR Embedded Workbench uses .s79 by default, but in addition accepts the .s extension. The object files produced by the compiler or assembler have the filename extension .o (in ARM Developer Suite) or .r79 (in IAR Embedded Workbench).

ConvertinganADSprojecttoanIARproject
The guidelines below describe how to convert an existing ARM Developer Suite project, extract the options used for building and convert the project into an IAR project. As an example, the Codewarrior IDE project file test.mcp in the following figure contains main.c and counter.c source files in C, a counter.h header file in C and a load.s assembly file. This simple main function calls a counter function that delays up to the value of index and assigns the temp variable the value of the external variable value from load.s.

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2.

The Metrowerks Codewarrior IDE window

The project settings window is located under Edit -> "Debug/DebugRel/Release" Settings (Alt + F7) and is shown in the following figure.

3.

The project settings window of the Codewarrior IDE

Settings for either the ARM Developer Suite compiler, assembler, linker or debugger can be selected from the 'Target Settings Panel' at the left of the window. The command line outputs for each of these tools can be found under their respective 'Equivalent Command Line' fields in their project settings window.

When the project settings have been selected, build/make/compile the project. Any errors or warnings will be displayed in the window below.

4.

The make window of the Codewarrior IDE

Once this process is successful, to run the AXD debugger, go to Project -> Debug (F5).

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5.

The ARM eXtended Debugger (AXD) window

In order to begin conversion of the ARM Developer Suite project to an IAR Embedded Workbench project, follow the guidelines below. Comparison screen captures have been provided to aid in the conversion process.

CREATEANEWIARPROJECT/WORKSPACE
Start the IAR Embedded Workbench program and create a new workspace (if required) for adding the new project or open an existing workspace, create the new project and add it to the existing workspace. To create a new workspace, go to File -> New -> Workspace and to create a new project, go to Project -> Create New Project...

ADDSOURCEFILES
Next, add the C source and assembler files (i.e. main.c, counter.c and load.s) from the ARM Developer Suite project into the new IAR Embedded Workbench project. To add project files, go to Project -> Add Files... Note that the assembler file, load.s needed to be converted according to the guidelines described in the remainder of this guide. In this example, the AREA and DCB directives for creating a new code/data section and for allocating a byte of memory respectively, needed to be converted to their equivalent IAR directives, which are RSEG and DC8.

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6.

The IAR Embedded Workbench IDE window

SETCCOMPILERCORETYPE
Project options for the IAR Embedded Workbench project are located in Project -> Options (Alt + F7). A window as shown at the right of the following figure should appear. In the example project, the ARM7TDMI processor core has been selected. A comparison screen capture for selecting a processor core in ARM Developer Suite is shown at the left of the figure. This option can be viewed by selecting 'ARM C Compiler' from the 'Target Settings Panel' at the left of the project settings window (which can be opened from Edit -> "Debug/DebugRel/Release" Settings (Alt + F7) as mentioned previously). For IAR Embedded Workbench, the target core can be selected from the 'Processor variant' panel under 'General Options' in the 'Category:' panel when the project options window is opened.
ADS IAR

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7.

Selecting a processor core for the compiler in ARM Developer Suite and IAR Embedded Workbench

SETCCOMPILERARM/THUMBMODE
To define ARM or Thumb mode for the C Compiler in ARM Developer Suite, go to the 'File Mappings' option in 'Target Settings Panels' and select the appropriate compiler with the 'Compiler:' multiple selection box for the associated file extensions. In the example project, the ARM C Compiler will be used for the .c and .h source files. For IAR Embedded Workbench, the option to choose ARM or Thumb mode can be found in the 'Processor Mode' panel under 'General Options' in the 'Category:' panel. 1)
ADS IAR

8.

Setting ARM./Thumb mode for the C compiler in ARM Developer Suite and IAR Embedded Workbench

The following screen captures demonstrate how to tell the C compiler to generate ARM or Thumb interwork code in ARM Developer Suite. Choose either the 'ARM C Compiler' or 'Thumb C Compiler' options from 'Target Settings Panels', select the 'ATPCS' tab, then select the 'ARM/Thumb interworking' checkbox in the 'ARM/Thumb Procedure Call Standard Options' panel. To perform ARM/Thumb interworking in IAR Embedded Workbench, select the 'Generate interwork code' checkbox from 'General Options' in the 'Category:' panel as shown in the previous figure.

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Setting ARM./Thumb interworking mode for the C compiler in ARM Developer Suite

SETCCOMPILERINCLUDEDIRECTORIES
Include directories for ARM Developer Suite projects can be found by selecting 'Source Trees' from 'Target Settings Panels' in the project settings window. For the example project, the ADSINC variable contains the directory path to the include files. In IAR Embedded Workbench, include paths can be defined by selecting 'C/C++ Compiler' from the 'Category:' panel at the left of the project options window, selecting the 'Preprocessor' tab and adding the paths to the 'Include paths (one per line)' panel.

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IAR

10. Setting include directories for the C compiler in ARM Developer Suite and IAR Embedded Workbench

SETCCOMPILERPREDEFINEDSYMBOLS
The figure below shows the location of predefined compiler symbols and variables for ARM Developer Suite and IAR Embedded Workbench. In ARM Developer Suite, the predefined symbols are located under the 'Preprocessor' tab in the 'ARM C Compiler' option in 'Target Settings Panels', while in IAR Embedded Workbench, the variables are located in the 'Defined symbols (one per line)' panel under the 'Preprocessor' tab in the 'C/C++ Compiler' option in the 'Category:' panel.

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IAR

11. Setting C compiler predefines in ARM Developer Suite and IAR Embedded Workbench

SETASSEMBLERCORETYPE
As mentioned previously, the example project uses the ARM7TDMI processor core. To change a processor core type for the ADS Developer Suite assembler, go to 'ARM Assembler' from 'Target Settings Panels' and select the desired core type from the 'Architecture or Processor' multiple options box. For IAR Embedded Workbench, the target core for the assembler is set in the same location as the compiler. This is located in the 'Processor variant' panel under 'General Options' in the 'Category:' panel as shown in the comparison figures below. It is not possible to select a different core type for the C compiler and assembler in IAR Embedded Workbench.

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ADS

IAR

12. Selecting a processor core for the assembler in ARM Developer Suite and IAR Embedded Workbench

SETASSEMBLERARM/THUMBMODE
In order to define either ARM or Thumb mode for the assembler, refer to the figure below. In ARM Developer Suite, this is defined in the 'Initial State' panel in the 'Target' tab of the 'ARM Assembler' option in 'Target Settings Panels'. For IAR Embedded Workbench, this option is defined in the 'Processor mode' panel of the 'Target' tab in 'General Options' in the 'Category:' panel. This is similar to setting ARM/Thumb mode for the IAR Embedded Workbench C compiler.

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IAR

13. Setting ARM/Thumb mode for the assembler in ARM Developer Suite and IAR Embedded Workbench

SETASSEMBLERINCLUDEDIRECTORIES
This step sets the include directories for the assembler. In ARM Developer Suite, the include directories are set in the same location in the project settings window as the compiler, i.e. under the 'Source Trees' option in 'Target Settings Panels'. For IAR Embedded Workbench, include paths can be defined in the 'Include paths (one per line)' panel in the 'Include' tab from the 'Assembler' option in the 'Category:' panel. The figure below shows the comparison screen captures.

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14. Setting include directories for the assembler in ARM Developer Suite and IAR Embedded Workbench

SETASSEMBLERPREDEFINEDSYMBOLS
The list of assembler predefined symbols or variables for both ARM Developer Suite and IAR Embedded Workbench are shown in the figure below. In ARM Developer Suite, the symbols are located in the 'Predefines' tab under 'ARM Assembler' in 'Target Settings Panels' and for IAR Embedded Workbench, they can be found in the '#undef' tab under the 'Assembler' option in the 'Category:' panel. Note that the ARM Developer Suite allows predefined variables to be edited.

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IAR

15. Selecting a processor core for the assembler in ARM Developer Suite and IAR Embedded Workbench

SETLINKERCODEANDDATABASEADDRESSES
The example project has a memory map with read-only and read-write base addresses of 0x0000 and 0xA000 respectively. In the ARM Developer Suite, this information can be input to the linker by selecting the 'Output' tab from the 'ARM Linker' option in 'Target Settings Panels' and filling in the 'RO Base' and 'RW Base' fields as shown. Although the IAR Embedded Workbench does not have an equivalent fields to input this information, the 'Cmd Opt' tab (selected from the 'Linker' option in the 'Category:' panel) can be used. Select the 'Use command line options' checkbox and add in the commands as shown in the figure below. A discussion of specifying a memory map of an image to the linker can be found further in the guide. Note that in ARM Developer Suite, the fromELF utility of the linker may be used to translate executable image files generated by the linker into other output formats such as plain binary.

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16. Selecting a processor core for the assembler in ARM Developer Suite and IAR Embedded Workbench

STARTIARCSPYDEBUGGER
After setting the relevant project options, compile/make/build the project and go to Project -> Debug (Ctrl + D) to start the IAR CSPY Debugger as shown in the figure below. Once in the IAR C-SPY Debugger, to return to the editor go to Debug -> Stop Debugging.

17. The IAR C-SPY Debugger window

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Convertingassemblersourcefiles
The guidelines in the following sections describe how to accurately and systematically convert assembler source files from ARM Developer Suite to IAR Embedded Workbench.

BASICASSEMBLERCONVERSION
For basic assembler conversion, use the following steps, shown with a simple example: 1) Redefine system segments and areas.
Beforestep1:

index

value

AREA test,CODE . RN 9 LDR r0, [index,#4] . LDR r1,=&FF00 . AREA hash,DATA . DCFD 12.3 . EQU 8 LDR r5,=value || 0xF9 . END

Afterstep1:

index

value

RSEG test:CODE:NOROOT(2) . RN 9 LDR r0, [index,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DCFD 12.3 . EQU 8 LDR r5,=value || 0xF9 . END

2)

Remove use of the ARM Developer Suite RN directive. Rename registers (if required).
Beforestep2:

index

value

RSEG test:CODE:NOROOT(2) . RN 9 LDR r0, [index,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DCFD 12.3 . EQU 8 LDR r5,=value || 0xF9 . END

Afterstep2:

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2)

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Afterstep2:

value

. DCFD 12.3 . EQU 8 LDR r5,=value || 0xF9 . END

3)

Modify unary and binary assembler operators, while noting operator precedence. The example shows the modification of the bitwise OR operator from || (in ARM Developer Suite) to | (in IAR Embedded Workbench).
Beforestep3:

value

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DCFD 12.3 . EQU 8 LDR r5,=value || 0xF9 . END

Afterstep3:

value

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DCFD 12.3 . EQU 8 LDR r5,=value | 0xF9 . END

4)

Modify assembler directives
Beforestep4:

value

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DCFD 12.3 . EQU 8 LDR r5,=value :OR: 0xF9 . END

Afterstep4:

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) .

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Afterstep4:

value

DF64 12.3 . EQU 8 LDR r5,=value :OR: 0xF9 . END

5)

Modify assembler symbols, numeric literals and numeric expressions (if required). Note that assembler pseudo-instructions and labels do not need to be modified. The example below shows the modification of a numeric literal.
Beforestep5:

value

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=&FF00 . RSEG hash:DATA:NOROOT(2) . DF64 12.3 . EQU 8 LDR r5,=value :OR: 0xF9 . END

Afterstep5:

value

RSEG test:CODE:NOROOT(2) . LDR r0, [r9,#4] . LDR r1,=0xFF00 . RSEG hash:DATA:NOROOT(2) . DF64 12.3 . EQU 8 LDR r5,=value :OR: 0xF9 . END

COMPLEXASSEMBLERCONVERSION
For more complex assembler conversions, follow the steps outlined below. (Detailed descriptions and associated examples have been provided in the section Advanced conversion 24.) 1) 2) 3) 4) Modify predefined symbols. Modify conditional assembly directives. Convert macros. Create modules (if required).

Makefiles
ARM Developer Suite tools may also be used with makefiles. If makefiles are required, the following steps describe the method of converting makefiles from ARM Developer Suite to IAR Embedded Workbench. A simple example of a makefile conversion is provided. 1) Change the assembler to use from armasm (ARM Developer Suite) to aarm (IAR Embedded Workbench)
Beforestep1:

#Assembler to use AS=armasm
#Options to pass to the assembler AFLAGS=-g -bigend -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s

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Beforestep1:

clean: rm -rf *.o
Afterstep1:

#Assembler to use AS=aarm
#Options to pass to the assembler AFLAGS=-g -bigend -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o

2)

Modify command line options. The example shows how to change the -g option used for generating debug information in ARM Developer Suite to the equivalent option in IAR Embedded Workbench, -r.
Beforestep2:

#Assembler to use AS=aarm
#Options to pass to the assembler AFLAGS=-g -bigend -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o
Afterstep2:

#Assembler to use AS=aarm
#Options to pass to the assembler AFLAGS=-r -bigend -list=test

hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o

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3)

Modify code generation options. The example shows how to change the ARM Developer Suite option for generating big-endian ordered code and data to the equivalent option in IAR Embedded Workbench.
Beforestep3:

#Assembler to use AS=aarm #Options to pass to the assembler AFLAGS=-r -bigend -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o
Afterstep3:

#Assemblertouse AS=aarm #Options to pass to the assembler AFLAGS=-r --endian big -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o

4)

Modify listing/output options. The example shows how to change the ARM Developer Suite option for producing a listing output file to the equivalent option in IAR Embedded Workbench.
Beforestep4:

#Assemblertouse AS=aarm #Options to pass to the assembler AFLAGS=-r --endian big -list=test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o
Afterstep4:

#Assemblertouse AS=aarm #Options to pass to the assembler AFLAGS=-r --endian big -l test hello.o: hello.s $(AS) $(AFLAGS) hello.s clean: rm -rf *.o

LinkerFiles
Converting linker files from ARM Developer Suite to IAR Embedded Workbench is similar to the conversion of makefiles. Refer to the section Linker and other tools 28 for a detailed description of linker options and the memory mapping mechanism. Follow these steps: 1) 2) 6) Modify linker command line options. Change the memory mapping method from using scatter loading (ARM Developer Suite) to segment control (IAR Embedded Workbench).

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Migrationreference
This section lists the differences in assembler, compiler, and linker options between ARM Developer Suite and ARM IAR Embedded Workbench.

Assemblerconversion
In ARM Developer Suite, the assembler is called armasm, while in ARM IAR Embedded Workbench, the assembler is called aarm.

COMMONASSEMBLERCOMMANDLINEOPTIONS
The following table lists the commonly used command line options.
ADS IAR Description

-apcs [none| [/qualifier[/qualif ier[...]]] -bigendor-bi -bigendor-bi, -littleendor-li -cpu name -i dir [,dir]... -g -list [filename] -m -o filename -via file -xref or -x

Noequivalent

SpecifieswhichProcedureCallStandardfortheARMArchitecture(AAPCS)thatisbeing used

-e Generatescodeinbigendianbyteorder --endian{little|l|big| Specifiesthebyteorderofthegeneratedcodeanddata b} --cpu name SpecifiesthetargetCPUorcore -Iprefix Addsdirectoriestotheincludefilesearchpath -r[en] Instructstheassemblertogeneratedebuginformation;-reincludesthefullsourcefile intotheobjectfileand-rngeneratesanobjectfilewithoutsourceinformation -l filename Instructstheassemblertogeneratealisting Noequivalent Instructstheassemblertowritesourcefiledependencyliststostdout -o filename Setstheoutputobjectfilename -f extend.xcl Instructstheassemblertoopenandreadcommandlineargumentsfromafile -x{DI2} Instructstheassemblertolistcrossreferenceinformation;InARMIAREmbedded Workbench,-xDincludes#definereferences,-xIincludesinternalsymbolsand -x2includesduallinespacing

18. Common command line options in ARM Developer Suite and ARM IAR Embedded Workbench

DEFININGSYSTEMSEGMENTS/AREAS
System segments and areas are defined with the AREA directive in ARM Developer Suite. In ARM IAR Embedded Workbench, the equivalent directive is called RSEG. In ARM IAR Embedded Workbench, ORG is used to set the program location counter of the current segment to the value of an expression. There is no support for ORG in ARM Developer Suite. Instead, ARM Developer Suite uses either the armlink option -first or scatter loading. The example below compares the methods of defining system segments/areas in ARM Developer Suite and ARM IAR Embedded Workbench.
ADS IAR Description

AREA test,CODE . MOV R0,#10 LDR R3,=0x1234 . . END

RSEG test:CODE:NOROOT(2) . MOV R0, #10 LDR R3,=0x1234 . . END

;Assembles a new code section called test ;Set up a parameter ;Load 0x1234 into register R3

;End of source file

19. Defining system segments/areas in ARM Developer Suite and ARM IAR Embedded Workbench

LISTING/OUTPUTOPTIONS
In both ARM Developer Suite and ARM IAR Embedded Workbench, the -o command line option sets the filename to be used for the output object file. If no filename argument (or extension) is defined, the assembler creates an object filename of the form inputfilename.o (in ARM Developer Suite) or inputfilename.r79 (in ARM IAR Embedded Workbench). In order to instruct the assembler to generate a detailed list file of the assembler code it produced, the -list option in ARM Developer Suite or the -l option in ARM IAR Embedded Workbench can be used. By default, the assembler does not generate a list file. The behavior of -list (in ARM Developer Suite) and -l (in IAR) can be controlled with the cross-reference option. In ARM Developer Suite, the -xref (or -x) command line option instructs the assembler to list cross-reference information about where symbols were defined and where they were used, both inside and outside macros. In comparison, the -x option in IAR Embedded Workbench makes the assembler include a cross-reference table at the end of the list file. Additionally, IAR Embedded Workbench

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provides the following parameters: -xD for inclusion of #define symbols, -xI for inclusion of internal symbols and -x2 for inclusion of dual line spacing.

CODEGENERATIONOPTIONS
In ARM Developer Suite, the -apcs command line option can be used to specify the attributes of code sections. There is no equivalent command line option in IAR Embedded Workbench. Valid qualifiers for -apcs are provided in the table below.
[qualifier] Description

/none /interwork or /inter /nointerwork or /nointer /ropi or /pic /noropi or /nopic /rwpi or /pid /norwpi or /nopid /swstackcheck or /swst /noswstackcheck or /noswst /swstna

InputfiledoesnotuseAAPCS CodeintheinputfileissuitableforARM/Thumbinterworking CodeintheinputfileisnotsuitableforARM/Thumbinterworking Contentoftheinputfileisreadonlypositionindependent Contentoftheinputfileisnotreadonlypositionindependent(default) Contentoftheinputfileisreadwritepositionindependent Contentoftheinputfileisnotreadwritepositionindependent(default) Codeintheinputfileperformssoftwarestacklimitchecking Codeintheinputfiledoesnotperformsoftwarestacklimitchecking(default) Codeintheinputfileiscompatiblewithcodethatperformsanddoesnotperformsoftwarestacklimitchecking

20. Qualifiers for the -apcs command line option in ARM Developer Suite

The -bigend (or -bi) and -littleend (or -li) options in ARM Developer Suite specify the byte order of the generated code or data, while the equivalent option in IAR Embedded Workbench is --endian{little|l|big|b}. Furthermore, the -e option in IAR Embedded Workbench can also be used to generate code in big-endian byte order. The default byte order in both ARM Developer Suite and ARM IAR Embedded Workbench is little-endian. The -cpu command line option in ARM Developer Suite and the --cpu option in IAR Embedded Workbench are used to specify the target core and obtain the correct instruction set. The default CPU name is ARM7TDMI in both ARM Developer Suite and IAR Embedded Workbench.

REGISTERNAMINGDIFFERENCES
The following table lists the register naming differences between ARM Developer Suite and IAR Embedded Workbench. Note that the assembler option -j (for allowing alternative register names, mnemonics, and operands) is needed to allow the use of the register names A1–A4, V1–V8, SB, SL, FP, and IP in IAR Embedded Workbench.
ADS IAR Description

r0,R0,anda1 r1,R1,anda2 r2,R2,anda3 r3,R3,anda4 r4,R4,andv1 r5,R5,andv2 r6,R6,andv3 r7,R7,andv4 r8,R8,andv5 r9,R9,andv6 r10,R10,andv7 r11,R11,andv8 r12andR12 sbandSB slandSL fpandFP ipandIP spandSP lrandLR pcandPC cpsrandCPSR spsrandSPSR

R0andA1 R1andA2 R2andA3 R3andA4 R4andV1 R5andV2 R6andV3 R7andV4 R8andV5 R9andV6 R10andV7 R11 R12 SB SL FP IP R13(SP) R14(LR) R15(PC) CPSR SPSR

Argument,resultorscratchregister Argument,resultorscratchregister Argument,resultorscratchregister Argument,resultorscratchregister Variableregister Variableregister Variableregister Variableregister Variableregister Variableregister Variableregister Variableregister Generalpurposeregister Staticbase,r9 Stacklimit,r10 Framepointer,r11 Intraprocedurecallscratchregister,r12 Stackpointer,r13 Linkregister,r14 Programcounter,r15 Currentprogramstatusregister Savedprogressstatusregister

21. Register naming differences in ARM Developer Suite and IAR Embedded Workbench

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ASSEMBLEROPERATORS
ARM Developer Suite and IAR Embedded Workbench possess many operators in common, and shift and mask operators can be used to implement many of the missing operators.

Operatorprecedence
The assemblers in ARM Developer Suite and IAR Embedded Workbench use extensive sets of operators. Operators with the highest precedence are evaluated first, followed by the operators with the second highest precedence and so forth until the lowest precedence operators are evaluated. If an expression contains operators of equal precedence, the operators are evaluated from left to right. In ARM Developer Suite and IAR Embedded Workbench both, the parentheses ( and ) can be used for grouping operators and operands and to denote precedence. The table below shows the order of precedence (from top to bottom) of operators in both development environments.
ADS IAR

Unaryoperators Multiplicativearithmeticoperators Stringmanipulationoperators Shiftoperators Addition,subtractionandlogicaloperators Relationaloperators Booleanoperators
22. Operator precedence in ARM Developer Suite and IAR Embedded Workbench

Unaryoperators Multiplicativearithmeticoperators Additionandsubtractionoperators Shiftoperators LogicalANDoperators LogicalORoperators Relationaloperators

Unaryoperators
The following table shows the equivalent assembler unary operators in ARM Developer Suite and IAR Embedded Workbench. Note that IAR Embedded Workbench does not have any unary operators that return strings, only numeric or logical values.
ADS Returnsstrings IAR Description

:CHR: :STR:
Returnsnumericorlogicalvalues

Noequivalent Noequivalent

ASCIIcharacterreturn Numericexpression:Returns8digithexstring Logicalexpression:Returns"T"or"F" Unaryplus Unaryminus Logicalcomplement Bitwisecomplement Lowbyte Highbyte Firstbyte Secondbyte Thirdbyte Fourthbyte Lowword Highword Currenttime/date Segmentbegin Segmentend Segmentsize Numberofbytesofexecutablecodegeneratedbylinedefiningasymbol,for example?A Numberofregistercomponent Ifdefined,TRUE,elseFALSE Offsetfrombaseregister Lengthofstring Bits[19:12] Leastsignificant12bytes

+ :LNOT: :NOT:
Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent

+ !or:LNOT: ~or:NOT: LOW HIGH BYTE1 BYTE2 BYTE3 BYTE4 LWRD HWRD DATE SFB SFE SIZEOF
Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent

? :BASE: :DEF: :INDEX: :LEN: :SB_OFFSET_19_12: :SB_OFFSET_11_0:

(:SHR:) :AND: 0xFF :AND: 0xFFF

23. Unary operators in ARM Developer Suite and IAR Embedded Workbench

19

Binaryoperators
The following table shows the equivalent assembler binary operators in ARM Developer Suite and IAR Embedded Workbench.
ADS MultiplicativeArithmeticOperators IAR Description

* / :MOD:
StringManipulationOperators

* / % or :MOD:
Noequivalent Noequivalent Noequivalent Noequivalent

Multiplication Division Modulo Concatenate Leftmostcharacters Rightmostcharacters Logicalrotationleft.InIAREmbeddedWorkbench,thereisnodirectequivalent,but canbeachievedwiththefollowing(x :SHL: 1) :OR: (x :SHR

:CC: :LEFT: :RIGHT:
ShiftOperators

:ROL:

(32-1)) :ROR: :SHL: :SHR: + :LAND: :AND: :LOR: :OR: :LEOR: :EOR:
RelationalorComparisonOperators

Noequivalent

Logicalrotationright.InIAREmbeddedWorkbench,thereisnodirectequivalent, butcanbeachievedwiththefollowing(x :SHR: 1) :OR: (x :SHL

(32-1)) << or :SHL: >> or :SHR: + && or :LAND: & or :AND: || or :LOR: | or :OR: XOR or :LEOR: ^ or :EOR: =or== <>or!= > < >= <= UGT ULT
Logicalshiftleft Logicalshiftright Addition Subtraction LogicalAND BitwiseAND LogicalOR BitwiseOR LogicalexclusiveOR BitwiseexclusiveOR Equal Notequal Greaterthan Lessthan Greaterthanorequal Lessthanorequal Unsignedgreaterthan Unsignedlessthan

Addition,Subtraction,LogicalandBooleanOperators

= /=or<> > < >= <=
Noequivalent Noequivalent

24. Binary operators in ARM Developer Suite and IAR Embedded Workbench

ASSEMBLERDIRECTIVES
The following table shows the equivalent common assembler directives in ARM Developer Suite and IAR Embedded Workbench.
ADS IAR Description

ALIGN AREA CODE16 CODE32 DATA DCB or = DCD or & DCFD DCW END ENTRY EQU or *

ALIGNROM RSEG CODE16 CODE32 DATA DCB or DC8 DCD or DC32 DF64 DCW or DC16 END END expression EQU or =

Alignsthecurrentlocationtoaspecifiedboundarybypaddingwithzeroes.Note thatinIAREmbeddedWorkbench,thereisalsoadirectivecalledALIGNRAM thatalignsthelocationcounterbyincrementingit. Instructsassemblertoassembleanewcodeordatasection Instructsassemblertointerpretsubsequentinstructionsas16bitThumb instructions Instructsassemblertointerpretsubsequentinstructionsas32bitARMinstructions Definesanareaofdatawithinacodesegment.NotethatinARMDeveloperSuite, thisdirectiveisnolongerneededandisignoredbytheassembler. Allocatesoneormorebytesofmemoryanddefinesinitialruntimecontentsofthe memory Allocatesoneormorewordsofmemory,alignedon4byteboundariesanddefines initialruntimecontentsofthememory Allocatesmemoryforwordaligneddoubleprecisionfloatingpointnumbersand definesinitialruntimecontentsoftheregister Allocatesoneormorehalfwordsofmemory,alignedon2byteboundariesand definestheinitialruntimecontentsofthememory Informstheassemblerthattheendofasourcefilehasbeenreached Declaresanentrypointtoaprogram.InIAREmbeddedWorkbench, expressionprovidestheentrypointaddress.Anentrypointtoaprogram canalsobedefinedwiththelinkercommandlineoption-sinIAREmbedded Workbench Givesasymbolicnametoanumericconstant,aregisterrelativevalueora

20

ADS

IAR

Description

EXPORTorGLOBAL INCLUDEorGET INCBIN IMPORT LTORG RN

EXPORT or PUBLIC INCLUDE or $
Noequivalent

IMPORT or EXTERN LTORG
Noequivalent

SPACE or %

Noequivalent

programrelativevalue Declaresasymbolthatcanbeusedbythelinkertoresolvesymbolreferencesin separateobjectandlibraryfiles.NotethatinIAREmbeddedWorkbench, #includemayalsobeused. Includesafilewithinthefilebeingassembled Includesabinaryfileasitis(withoutbeingassembled)withinthefilebeing assembled.ThereisnodirectequivalentinIAREmbeddedWorkbench,butcanbe definedwiththelinkercommandlineoption--image_input Providestheassemblerwithanamethatisnotdefinedinthecurrentassembly Instructstheassemblertoassemblethecurrentliteralpoolimmediatelyfollowing thedirective Definesaregisternameforaspecifiedregister Reservesazeroedblockofmemory.ThereisnodirectequivalentinIAR EmbeddedWorkbench,butaworkaroundtothiswouldbetousetheREPT directivetozeroablockofmemory.Alternatively,theDS8,DS16,DS24,or DS32directivesmaybeused,butthememoryisnotfilledwithzeroes.Ifthese directivesareused,thedefaultROM/Flashcontentwillbepreserved.

25. Assembler directives in ARM Developer Suite and IAR Embedded Workbench

The example below compares the use of directives in ARM Developer Suite and IAR Embedded Workbench.
ADS IAR Description/Comments

data

INCLUDE "header.inc" INCBIN "data.dat" . AREA fred,CODE ENTRY CODE32 BX func . . CODE16 BX thumb . . AREA john,DATA . ALIGN 16

table

DCB "test" DCD 1,5,10 DCFD 1.2E-8 DCW -255

table

test tab

EQU 5 . RN 4 ADR tab,table ADRL tab,table LDR r0,=table LTORG SPACE 50 EXPORT table . END

test

INCLUDE "header.inc" ;Include a header file . ;Include a binary file. . RSEG fred:CODE:NOROOT(2) ;Assembles a new code section called fred . ;Entry point to the program. CODE32 ;Following instructions are 32bit ARM instructions BX func ;Branch and change to Thumb state . . CODE16 ;Following instructions are 16bit Thumb instructions BX thumb ;Branch and change back to ARM state . . RSEG john:DATA:NOROOT(2) ;Assembles a new data section called john . ALIGNROM 4 ;Aligns current location to 16byte boundaries DC8 'test' ;Defines a string DC32 1,5,10 ;Defines 3 words containing decimal values 1, 5 and 10 DF64 1.2E-8 ;Defines a floating point number 1.2 x 10-8 DC16 -225 ;Defines a halfword with a value of -255 EQU 5 ;Assign test a value of 5 . . ;Defines tab for register 4 ADR r4,table ;Load address of table into register 4 ADRL r4,table ;Load address of table into register 4 LDR r0,=table ;Load address of table into register 0 LTORG ;Assemble current literal pool DC8 0x32 ;Reserves 50 bytes of memory EXPORT table ;Export the label table . END ;End of source file

21

26. Use of directives in ARM Developer Suite and IAR Embedded Workbench

CONVERTINGPSEUDOINSTRUCTIONS
The following table compares the available pseudo-instructions on ARM Developer Suite and equivalent instructions on IAR Embedded Workbench.
ADS IAR Mode Description

ADR ADRL LDR NOP MOV
Noequivalent

ADR ADRL LDR NOP MOV BLF

ARM,Thumb ARM ARM,Thumb ARM,Thumb Thumb ARM,Thumb

Loadaprogramrelativeorregisterrelativeaddressintoaregister(shortrange) Loadaprogramrelativeorregisterrelativeaddressintoaregister(widerange) Loadaregisterwitha32bitconstantvalueoranaddress GeneratethepreferredARMnooperationcode Movethevalueofalowregistertoanotherlowregister(R0–R7).Thistranslatestothe instruction:ADDRn,Rn,0 CallsfunctionsthatmaybefarawayorinARM/Thumbmode

27. Pseudo-instructions in ARM Developer Suite and IAR Embedded Workbench

ASSEMBLERDIFFERENCES
This section highlights other differences between and the ADS ARM Assembler, armasm and the ARM IAR Embedded Workbench Assembler, aarm.

Labeldifferences
In both ARM Developer Suite and IAR Embedded Workbench, symbols representing addresses or memory locations of instructions or data are referred to as labels. Labels can be program-relative, register-relative, or absolute. There are no label differences between ARM Developer Suite and IAR Embedded Workbench.

Symbolnamingrules
In ARM Developer Suite and IAR Embedded Workbench, user-defined symbols can use a to z (lowercase letters), A to Z (uppercase letters), 0 to 9 (numeric characters) or _ (underscore). Numeric characters cannot be used for the first character of symbol names, although in IAR Embedded Workbench the ? (question mark) may be used to begin a symbol name and the $ (dollar) may also be included in a symbol name. User-defined symbols in IAR Embedded Workbench can be up to 255 characters long. Symbol names are case-sensitive, all character names in the symbol are significant and the symbol name must be unique. For built-in symbols such as instructions, registers, operators, and directives, case is insignificant. Symbols are allowed to contain any printable characters if they are delimited with the | (single bar) in ARM Developer Suite or the ` (backquote) in IAR Embedded Workbench. Note that the single bars or backquotes do not form part of the symbol. The examples below define the symbol #funny-label@:
ADS: IAR:

|#funny-label@| `#funny-label@`

Numericliterals
Numeric literals in ARM Developer Suite and IAR Embedded Workbench can be of the binary, octal, decimal, hexadecimal, character or floating-point type. The table below shows the examples of the forms taken by numeric literals in ARM Developer Suite and IAR Embedded Workbench.
Type ADSExamples IARExamples

Binary Octal Decimal Hexadecimal ASCIIcharacter Floatingpoint

Noequivalent Noequivalent 1234,1234 0xFFFF,&FFFF 'ABCD' 12.3,1.23E24,1.23e24,1.0E3

0101b,b'0101' 1234q,q'1234' 1234,1234,d'1234' 0xFFFF,0FFFFh,h'FFFF' 'ABCD' 12.3,1.23E24,1.23e24,1.0E3

28. Numeric literals in ARM Developer Suite and IAR Embedded Workbench

Numericexpressions
In both ARM Developer Suite and IAR Embedded Workbench, numeric expressions consist of combinations of numeric constants, numeric variables, ordinary numeric literals, binary operators, and parentheses. Numeric expressions evaluate to 32-bit integers, which have an unsigned range from 0 to 232 - 1 and a signed range from -231 to 231 -1.

SPECIFICDIRECTIVESREFERENCE
This section describes some of the more complex assembler directives available in ARM Developer Suite and how to change them to work with IAR Embedded Workbench .

22

AREAdirective
In ARM Developer Suite, the AREA directive instructs the assembler to assemble a new code or data section. Sections are independent, named, indivisible chunks of code or data that are manipulated by the linker. In IAR Embedded Workbench, the equivalent directive is the RSEG directive. The RSEG directive is used to begin a program. Syntax ARM Developer Suite:
AREA sectionname{,attr}{,attr}...

Where

sectionname = the name to be given to the section attr = one or more comma-delimited section attributes. Valid attributes include ALIGN=expression, ASSOC=section, CODE, COMDEF, COMMON, DATA, NOALLOC, NOINIT, READONLY, READWRITE

IAR Embedded Workbench:
RSEG segmentname [:type][flag][(align)]

where

segmentname = the name assigned to the segment type = the memory type, typically CODE or DATA (and types supported by the IAR XLINK Linker) flag = may either be NOROOT, REORDER, or SORT. NOROOT indicates that the segment part may be discarded by the

linker even if no symbols in this segment are referred to. All segment parts except startup code and interrupt vectors should set this flag. The default mode is ROOT, which indicates that the segment part must not be discarded. REORDER allows the linker to reorder segment parts. The default mode is NOREORDER, which indicates that the segment parts must remain in order. SORT allows the linker to sort the segment parts in decreasing alignment order. The default mode is NOSORT which indicates that the segment parts will not be sorted.
align = exponent of the value to which the address should be aligned, in the range of 0 to 30. For example, if align is 1,

this results in word alignment 2 Example ARM Developer Suite: The following example defines a read-only code section named Test.
AREA Test,CODE,READONLY

IAR Embedded Workbench: The following example defines a 32-bit code segment named Test.
RSEG Test:CODE:NOROOT(2)

MAPdirective
In ARM Developer Suite, the MAP directive sets the origin of a storage map to a specified address. This directive is used in conjunction with the FIELD directive to describe a storage map. In IAR Embedded Workbench, there is no equivalent directive. Syntax ARM Developer Suite:
MAP expr{,base-register}

Where

expr = numeric or program-relative expression base-register = specifies a register. If specified, the address where the storage map starts is the sum of expr and the value of base-register at runtime

IAR Embedded Workbench: In IAR Embedded Workbench, there is no equivalent directive. See the FIELD directive 24 below for how to convert this construct.

23

Example ARM Developer Suite: The following example shows that the storage maps starts at the address stored in register r9.
MAP 0,r9

IAR Embedded Workbench: In IAR Embedded Workbench, there is no equivalent example.

FIELDdirective
In ARM Developer Suite, the FIELD directive describes space within a storage map that has been defined using the MAP directive. In IAR Embedded Workbench, there is no equivalent directive, although the EQU directive may be used to achieve the same purpose. Syntax ARM Developer Suite:
{label} FIELD expr

Where

label = optional label. If specified, label is assigned the value of storage location counter expr = expression that evaluates to the number of bytes to increment the storage counter

IAR Embedded Workbench:
Label EQU expr

where

label = symbol to be defined expr = value assigned to symbol

Example ARM Developer Suite: The following example shows how the MAP and FIELD directives are used to define register-relative labels:
MAP FIELD FIELD FIELD 0,r9 8 4 4 ;Set storage location counter to address stored in r9 ;Increment storage location counter by 8 bytes ;Set Code to the address [r9 + 8] and increment storage ;location counter by 4 bytes ;Set Size to the address [r9 + 12] and increment storage ;location counter by 4 bytes

Code Size . .

MOV LDR

r9,... r0,Code ;Equivalent to LDR r0,[r9,#8]

IAR Embedded Workbench: The following example shows the equivalent instructions in IAR to define register-relative labels:
Code Size . . EQU EQU 8 12 ;Set Code to the address [r9 + 8] ;Set Size to the address [r9 + 12]

MOV LDR

r9,... r0,[r9,#Code]

Advancedconversion
PREDEFINEDSYMBOLS
The following table compares the predefined symbols available in ARM Developer Suite and IAR Embedded Workbench.

24

ADS

IAR

Description

{ARCHITECTURE} {ARMASM_VERSION} or | ads$version|

Noequivalent

__VER__

NameofselectedARMarchitecture Integerthatincreaseswitheachversionnumber Hasthevalue32ifassemblerisassemblingARMcode,or16ifassemblingThumb code NameofselectedCPU InARMDeveloperSuite,thevalue'big'or'little'isreturneddepending ontheassemblermode.InIAREmbeddedWorkbench,thesymbolexpandstothe number1whenthecodeiscompiled,therebyidentifyingthebyteorderinuse Nameofselectedfpu HasthevalueTrueif/interisset.ThedefaultisFalse HasthevalueTrueif/swstisset.ThedefaultisFalse Holdsthevalueofthecurrentlysetlistingoption Addressofcurrentinstruction OffsetbetweentheaddressoftheSTR pc, [...]orSTM Rb,{...,pc}instructionandthevalueofpc stored out HasthevalueTrueif/ropiisset.ThedefaultisFalse HasthevalueTrueif/rwpiisset.ThedefaultisFalse HasthevalueTrueif/swstisset.ThedefaultisFalse Currentvalueofstoragearealocationcounter Stringindd/mm/yyyyformatindicatingthecurrentdate Stringindicatingthenameofthecurrentsourcefile HoldtheIAREmbeddedWorkbenchassembleridentifier Integerindicatinglinenumberincurrentsourcefile Targetidentityconsistingof2bytes.Highbyteistargetidentity,0x49forAARM), lowbyteisunused Stringinhh:mm:ssformatindicatingcurrenttime

{CODESIZE} or {CONFIG} Noequivalent {CPU} {ENDIAN} {FPU} {INTER} {NOSWST} {OPT} {PC} or . {PCSTOREOFFSET} {ROPI} {RWPI} {SWST} {VAR} or @
Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent

__BIG_ENDIAN__ or __LITTLE_ENDIAN__
Noequivalent Noequivalent Noequivalent Noequivalent . Noequivalent Noequivalent Noequivalent Noequivalent Noequivalent

__DATE__ __FILE__ __IAR_SYSTEMS_ASM__ __LINE__ __TID__ __TIME__

29. Predefined symbols in ARM Developer Suite and IAR Embedded Workbench

CONDITIONALASSEMBLY
The following table shows the equivalent conditional assembly directives in ARM Developer Suite and IAR Embedded Workbench.
ADS IAR Description

IFor[ ELSEor| ENDIFor] ELSE IFor|[ WHILE WEND INCLUDE,GETor#include SETA
Noequivalent Noequivalent

IF ELSE ENDIF ELSEIF REPT ENDR INCLUDE,$or#include SETA,ASSIGN,VARor #define #error #message #ifdef #ifndef #undef

Assembleasequenceofinstructionsifconditionistrue Assembleasequenceofinstructionsifconditionisfalse Markstheendofasequenceofinstructionsthatwereconditionallyassembled CreatesastructureequivalenttoELSE IF,withoutthenestingorrepeatingthe condition Beginsasequenceofinstructionsthatareassembledrepeatedly. Terminatesasequenceofinstructionsthatareassembledrepeatedly Includesafilewithinthefilebeingassembled.InARMDeveloperSuite, #includemaybeusedifthefileispreprocessedwiththeCpreprocessor,before usingarmasmtoassembleit. Setsthevalueofalocalorglobalarithmeticvariable Generatesanerror Generatemessageonstandardoutput Assembleasequenceofinstructionsifsymbolisdefined Assembleasequenceofinstructionsifsymbolisundefined Undefinealabel

[ :DEF: symbol [ :NOT: :DEF: symbol
Noequivalent

30. Conditional assembly directives in ARM Developer Suite and IAR Embedded Workbench

25

The example below compares the use of conditional assembly directives in ARM Developer Suite and IAR Embedded Workbench. It defines two different options for a FFT routine (1,2) plus an option with no routine.
ADS IAR Description/Comments

FFT_VARIANT SETA 1 [ DUMMY = 1
fft

#define FFT_VARIANT 1 IF DUMMY == 1 fft

;Define a variable called FFT_VARIANT that has a value of 1 ;Assemble sequence of instructions as condition is true ;Set up R0

MOV R0,#10 . . MOV PC,LR |[ FFT_VARIANT = 2
fft

MOV R0,#10 . . MOV PC,LR ELSEIF FFT_VARIANT == 2 fft

;Return ;Assemble sequence of instructions if condition is false ;FFT type 1

. . |
fft

. . ELSE fft

MOV R0, #-1 MOV PC,LR ]

MOV R0, #-1 MOV PC,LR ENDIF

;Assemble sequence of instructions if the next condition is true ;FFT type 2 ;Set up R0 (no fft available) ;Return ;End of conditionally assembled instructions

31. Use of conditional assembly directives in ARM Developer Suite and IAR Embedded Workbench

MACROS
Macros are user-defined symbols that represent a block of one or more assembler source lines. The symbol can then be used instead of repeating the whole block of code several times. The following table shows the equivalent macro processing directives in ARM Developer Suite and IAR Embedded Workbench.
ADS IAR Description

MACRO MEND MEXIT

MACRO ENDM EXITM

LCLA, LCLL or LCLS LOCAL

Definethestartofamacro Definetheendofamacro Generateprematureexitfromamacro Createsymbolslocaltoamacro.InARMDeveloperSuite,LCLAdeclaresanarithmeticvalue (initializedto0),LCLLdeclaresalogicalvariable(initializedto{FALSE})andLCLSdeclaresa stringvariable(initializedtoanullstring," ")

32. Macro processing directives in ARM Developer Suite and IAR Embedded Workbench

The example below compares the use of macro processing directives in ARM Developer Suite and IAR Embedded Workbench for decrementing a variable .
ADS IAR Descriptions

RSEG count:CODE:NOROOT(2) ENTRY . . . MACRO countdown MACRO start $label countdown $start . LCLA value LOCAL value value SETA $start value SETA start WHILE value > 0 REPT value DCD value DC32 value value SETA value - 1 value SETA value - 1 WEND ENDR DCD value DC32 value MEND ENDM . . tab5 countdown 5 tab5 countdown 5 . . END END
33. Use of macro processing directives in ARM Developer Suite and IAR Embedded Workbench

AREA count,CODE

;Assemble the source file count

;Start of macro called countdown ;Parameter accepted by the macro ;Create a local symbol ;Assign value the value of start ;Start of repeated statements ;Define a word called value ;Decrement value by 1 ;End of repeated statements ;Define a word called value ;End of a macro ;Begin countdown from 5 ;End of source file

The following list files show the value of value counting down from 5 to 1. ARMDeveloperSuitelisting
ARM Macro Assembler 1 00000000 2 00000000 3 00000000 Page 1 AREA ENTRY test,CODE

26

4 5 6 7 8 9 10 11 12 13 14 15 16 17 6 7 8 9 10 11 12 13 10 11 12 13 10 11 12 13 10 11 12 13 10 11 12 13 10 14 18 19

00000000 00000000 $label 00000000 00000000 00000000 value 00000000 00000000 00000000 00000000 value 00000000 00000000 00000000 00000000 00000000 tab50 00000000 00000000 00000000 00000005 value 00000000 00000000 00000000 00000005 00000004 00000004 value 00000004 00000004 00000004 00000004 00000008 00000003 value 00000008 00000008 00000008 00000003 0000000C 00000002 value 0000000C 0000000C 0000000C 00000002 00000010 00000001 value 00000010 00000010 00000010 00000001 00000014 00000000 value 00000014 00000014 00000014 00000000 00000018 00000018

MACRO countdown LCLA SETA WHILE DCD SETA WEND DCD MEND countdown LCLA

$start value $start value > 0 value value - 1 value

5 value

SETA WHILE DCD SETA WEND WHILE DCD SETA WEND WHILE DCD SETA WEND WHILE DCD SETA WEND WHILE DCD SETA WEND WHILE DCD END

5 value > 0 value value - 1 value > 0 value value - 1 value > 0 value value - 1 value > 0 value value - 1 value > 0 value value - 1 value > 0 value

Command Line: -list=test count.s

IAREmbeddedWorkbenchlisting
############################################################################### # # # IAR Systems ARM Assembler V4.20A/W32 dd/Mmm/yyyy hh:mm:ss # # Copyright 1999-2005 IAR Systems. All rights reserved. # # # # Source file = count.s # # List file = test.lst # # Object file = count.r79 # # Command line = -l test count.s # # # ############################################################################### 1 2 2.1 3 17 00000000 00000000 00000000 00000000 00000000 RSEG count:CODE:NOROOT(2) ALIGNROM 2

27

18 00000000 18.1 00000000 18.2 00000000 18.3 00000000 18.4 00000005 18.5 00000000 18.6 00000000 18.7 00000000 18.8 00000000 18.9 00000000 18 00000000 05000000 18.1 00000004 18.2 00000004 18 00000004 04000000 18.1 00000003 18.2 00000008 18 00000008 03000000 18.1 00000002 18.2 0000000C 18 0000000C 02000000 18.1 00000001 18.2 00000010 18 00000010 01000000 18.1 00000000 18.2 00000014 18 00000014 00000000 18.1 00000018 0000A0E1 18.2 0000001C 19 0000001C 20 0000001C ############################## # CRC:4E7E # # Errors: 0 # # Warnings: 0 # # Bytes: 28 # ##############################

tab5

countdown LOCAL value

5

value

value

SETA REPT DC32 SETA ENDR DC32 SETA DC32 SETA DC32 SETA DC32 SETA DC32 SETA

5 value value value - 1

value

value value - 1 value value - 1 value value - 1 value value - 1 value value - 1 5

value

value

value

value tab5

countdown NOP ENDM END

MODULES
In IAR Embedded Workbench, module directives are used to create libraries containing many small modules, where each module represents a single routine. The number of source and object files can be reduced using module directives. There is no direct equivalent in ARM Developer Suite, but a similar result can be achieved using the AREA directive.
ADS IAR Description

Noequivalent Noequivalent

MODULEorLIBRARY ENDMOD

Definesthebeginningofalibrarymodule. Definestheendofalibrarymodule

The Call Frame Information (CFI) directives are used to define backtrace information for the instructions in a program. The backtrace information is used to keep track of the contents of resources in the assembler code. In the case of library functions and assembler code, backtrace information has to be added in order to use the call frame stack in the debugger.

Linkerandothertools
In ARM Developer Suite, the linker is called armlink, while in the IAR Embedded Workbench IDE, the linker is called the IAR XLINK Linker.

LINKERCOMMANDLINEOPTIONS
The table below compares the basic linker command line options in ARM Developer Suite and IAR Embedded Workbench.
ADS IAR Description

-help or -h

Noequivalent

-vsn

Noequivalent

-ro-base or -ro address -Z type segment=start -rw-base or -rw address -Z type segment=start

Printssummaryofcommonlyusedcommandlineoptions.Thereisnodirect equivalentinIAREmbeddedWorkbench,butthetaskcanbeperformedby invokingxlinkwithoutarguments. Displaysarmlinkversioninformationandlicensedetails.Thereisnodirect equivalentinIAREmbeddedWorkbench,butthetaskcanbeperformedby invokingxlinkwithoutarguments. Setsloadandexecutionaddressesoftheregioncontainingthereadonly outputsection Setsexecutionaddressesoftheregioncontainingthereadwriteoutputsection

28

ADS

IAR

Description

-first section-id -last section-id -entry location -libpath pathlist -remove -map -symbols or -s -xref -list file -verbose or -v -via file -output or -o file

-Z segment=start-end or -Z segment=start:+size -Z segment=start-end or -Z segment=start:+size -s symbol -Ipathname
Noequivalent

Placestheselectedinputsectionfirstinitsexecutionregion Placestheselectedinputsectionlastinitsexecutionregion Specifiestheuniqueentrypointoftheimage SpecifiesalistofpathsusedtosearchforARMstandardC/C++libraries Removesunusedsectionsfromtheimage.ThisisperformedbydefaultinIAR EmbeddedWorkbench. Createsanimage/modulemap. Listsalllocalandglobalsymbolsusedinlinking,andtheirvalues Listsallcrossreferencesbetweeninputsections Redirectsthediagnosticsfromtheoutputofthecommandlineoptionstoafile Printsdetailedinformationaboutthelinkoperation,includingobjectsand libraries Readsalistofinputfilenamesandlinkeroptionsfromafile Specifiesthenameoftheoutputfile

-l -l -l -l

file -xm file -xe file -xm file

Noequivalent

-f file -o file

34. Linker command line options in ARM Developer Suite and IAR Embedded Workbench

LINKERSCATTERLOADINGANDSEGMENTCONTROL
In order to specify the memory map of an image to the linker, ARM Developer Suite utilizes the scatter loading mechanism. Although there is no direct IAR Embedded Workbench equivalent to this mechanism, a similar result can be achieved through segment control. With ARM Developer Suite, depending on the complexity of the memory maps of the image, images that have simple memory maps may also be created using command line options. Scatter loading is used for images that have a complex memory map where complete control is required over the grouping and placement of image components, for example, in situations where there are different types of memory or memory-mapped I/O. The command line option for scatter loading in ARM Developer Suite is:
-scatter filename

This option instructs the linker to construct the image memory map as described in the description file filename. The scatterloading description file is a text file that describes the memory map of the target to link. The file extension of the description file is not significant if the linker is used from the command line. However, if Codewarrior is used the default extension for a description file is .scf (this default extension that Codewarrior recognises may be changed if required). As mentioned previously, the linker in IAR Embedded Workbench does not have a single equivalent command line option. However, a similar result can be achieved with segment control using multiple -Z options to allocate or place segments in memory. Segment placement is performed one placement command at a time, taking in to account previous placement commands. As each command is processed, any parts of the ranges given for that placement command that are already in use (for example, by segments placed with earlier segment placement commands) are removed from the considered ranges. Furthermore, the -Q option in IAR Embedded Workbench can be used to do automatic setup for copy initialization of segments. The command line option has the format below:
-Qsegment=initializer_segment

This option will make the linker place all data contents of the segment segment into a segment initializer_segment. Debugging information, etc, is still associated with the segment segment. At runtime, the application must copy the contents of initializer_segment (in ROM) to segment (in RAM) using any suitable method of copy (the standard memcpy routine is perhaps the easiest way). This is useful for code that needs to be in RAM. The table below shows an example of a simple ARM Developer Suite scatter loading description file for loading code and data sections into non-contiguous regions in memory. The description file loads code (RO) at address 0x0000 in memory, data (RW) at address 0xA000 in memory, and dynamically creates a zero-initialized (ZI) section at runtime.
DescriptionFileListing Description/Comments

LR_1 0x0000 { ER_RO +0 { * } ER_RW { * } ER_ZI { * (+ZI) (+RO) 0xA000 (+RW) +0

;Define load region LR_1 ;The execution region containing code, ER_RO has no offset and begins at address 0x0000 ;All RO sections are placed consecutively into this region ;The execution region containing data, ER_RW is offset to address 0xA000 ;All RW sections are placed consecutively into this region ;The execution region containing the ZI section, ER_ZI has no offset and is placed at address 0xA000 + size of the ER_RW region ;All ZI sections are placed consecutively into this region

29

DescriptionFileListing

Description/Comments

} }
35. Example of scatter loading in ARM Developer Suite

Note that the equivalent linker command line option in ARM Developer Suite is:
armlink -ro-base 0x0000 -rw-base 0xA000

The equivalent segment placement commands in IAR Embedded Workbench for placing a code segment at address 0x0000 in memory and a data segment at address 0xA000 in memory are the following:
-Z (CODE) SEG_RO = 0x0000 -Z (DATA) SEG_RW,SEG_ZI = 0xA000

CCOMPILEREXTENDEDKEYWORDS
In ARM Developer Suite, function type attributes can be specified either before or after the return type:
__irq void InterruptHandler (void); void __irq InterruptHandler (void);

In IAR Embedded Workbench, function type attributes can only be specified before the return type:
__irq void InterruptHandler (void);

USINGTHEFROMELFUTILITY
The ARM Developer Suite linker generates executable image files that have a format called ELF (Executable Linkable Format). To convert ELF images to other formats, the fromELF utility can be used. This utility translates ELF images into other formats, e.g. plain binary format, that are suited to ROM tools and to loading directly into memory. The fromELF command syntax is shown below:
fromelf -options

In comparison, the final output of the IAR Embedded Workbench XLINK linker is an absolute, executable object file that can be put into ROM, downloaded to a hardware emulator or executed with the IAR C-SPY Debugger/Simulator.

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