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pcm1702


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49% FPO

PCM1702P PCM1702U

BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
FEATURES
q ULTRA LOW –96dB max THD+N (No External Adju

stment Required) q q q q q NEAR-IDEAL LOW LEVEL OPERATION GLITCH-FREE OUTPUT 120dB SNR TYP (A-Weight Method) INDUSTRY STD SERIAL INPUT FORMAT FAST (200ns) CURRENT OUTPUT (±1.2mA)

DESCRIPTION
The PCM1702 is a precision 20-bit digital-to-analog converter with ultra-low distortion (–96dB typ with a full scale output). Incorporated into the PCM1702 is an advanced sign magnitude architecture that eliminates unwanted glitches and other nonlinearities around bipolar zero. The PCM1702 also features a very low noise (120dB typ SNR: A-weighted method) and fast settling current output (200ns typ, 1.2mA step) which is capable of 16X oversampling rates. Applications include very low distortion frequency synthesis and high-end consumer and professional digital audio applications.

q CAPABLE OF 16X OVERSAMPLING q COMPLETE WITH REFERENCE q LOW POWER (150mW typ)

Clock Data LE DCOM ACOM +VCC –VCC

Input Shift Register and Control Logic

Balanced Current Segment DAC A

Balanced Current Segment DAC B Reference and Servo Bipolar Offset

IOUT

RF DC

SERV DC

BPO DC

International Airport Industrial Park ? Mailing Address: PO Box 11400 Tel: (520) 746-1111 ? Twx: 910-952-1111 ? Cable: BBRCORP ? ? 1993 Burr-Brown Corporation

? Tucson, AZ 85734 ? Street Address: 6730 S. Tucson Blvd. ? Tucson, AZ 85706 Telex: 066-6491 ? FAX: (520) 889-1510 ? Immediate Product Info: (800) 548-6132 PDS-1175B Printed in U.S.A. June, 1995
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PCM1702

SBAS026

SPECIFICATIONS
All specifications at 25°C, ±VCC and +VDD = ±5V unless otherwise noted. PCM1702P/U, -J, -K PARAMETER RESOLUTION DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight DIGITAL INPUT Logic Family Logic Level: VIH VIL IIH IIL Data Format Input Clock Frequency TOTAL HARMONIC DISTORTION + N P/U VO = 0dB VO = –20dB VO = –60dB P/U, -J VO = 0dB VO = –20dB VO = –60dB P/U, -K VO = 0dB VO = –20dB VO = –60dB ACCURACY Level Linearity Gain Error Bipolar Zero Error(5) Gain Drift Bipolar Zero Drift Warm-up Time IDLE CHANNEL SNR(6) ANALOG OUTPUT Output Range Output Impedance Settling Time Glitch Energy POWER SUPPLY REQUIREMENTS Supply Voltage Range: +VCC = +VDD –VCC = –VDD Combined Supply Current: +ICC Combined Supply Current: –ICC Power Dissipation TEMPERATURE RANGE Operating Storage
(2)

CONDITIONS

MIN 20

TYP

MAX

UNITS Bits

110 TTL/CMOS Compatible +2.4 0 +VDD 0.8 ±10 ±10 Serial, MSB First, BTC(1) 12.5 20.0

dB

VIH = +VDD VIL = 0V

V V ?A ?A MHz dB dB dB dB dB dB dB dB dB dB % % ppm of FSR/°C ppm of FSR/°C minute dB mA k? ns

fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) fS = 352.8kHz(3), f = 1002Hz(4) At –90dB Signal Level

–92 –82 –46 –96 –83 –48 –100 –84 –50 ±0.5 ±0.5 ±0.25 ±25 ±5 1 110 120 ±1.2 1.0 200 No Glitch Around Zero +4.75 –4.75 +5.00 –5.00 +5.00 –25.00 150

–88 –74 –40 –92 –76 –42 –96 –80 –44

±3

0°C to 70°C 0°C to 70°C Bipolar Zero, A-weighted Filter

(±0.003% of FSR, 1.2mA Step)

+VCC = +VDD = +5V –VCC = –VDD = –5V ±VCC = ±VDD = ±5V –25 –55

+5.25 –5.25 +9.0 –41.0 250 +85 +125

V V mA mA mW °C °C

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling). (4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5k? feedback and an A-weighted filter.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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PCM1702

2

ABSOLUTE MAXIMUM RATINGS (DIP Package)
Power Supply Voltage .................................................................. ±6.5VDC Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V Operating Temperature ..................................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Power Dissipation .......................................................................... 500mW Lead Temperature (soldering, 10s) .................................................. 260°C

ABSOLUTE MAXIMUM RATINGS (SOP Package)
Power Supply Voltage .................................................................. ±6.5VDC Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V Operating Temperature ..................................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Power Dissipation .......................................................................... 300mW Lead Temperature (soldering, 5s) .................................................... 260°C

PIN ASSIGNMENTS (DIP Package)
PIN 1 2 3 4 5 6 7 8 MNEMONIC DATA CLOCK +VDD DCOM –VDD LE NC NC PIN 9 10 11 12 13 14 15 16 MNEMONIC +VCC BPO DC IOUT ACOM ACOM SERV DC REF DC –VCC

PIN ASSIGNMENTS (SOP Package)
PIN 1 2 3 4 5 6 7 8 9 10 MNEMONIC DATA CLOCK NC +VDD DCOM –VDD LE NC NC NC PIN 11 12 13 14 15 16 17 18 19 20 MNEMONIC +VCC BPO DC NC IOUT ACOM ACOM SERV DC NC RFE DC –VCC

PACKAGE INFORMATION(1)
MODEL PCM1702P PCM1702U PACKAGE 16-Pin Plastic DIP 20-Pin Plastic SOP PACKAGE DRAWING NUMBER 180 248

GRADE MARKING (SOP Package)
MODEL PCM1702U PCM1702U-J PCM1702U-K PACKAGE Marked PCM1702. Marked with white dot by pin 10. Marked with red dot by pin 10.

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

CONNECTION DIAGRAM
47?F +

CLOCK DATA LE +5V VDD 47?F 47?F –5V VDD + +

2 1 7 4 5 6

2 1 6 3 4 5

16 20 + 15 19 14 17 11 14 10 12 9 11 + +5V VCC 47?F 47?F + 22?F + 100?F

–5V VCC RNF

VOUT

13 16 12 15

= SOP = DIP

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PCM1702

TYPICAL PERFORMANCE CURVES
All specifications at 25°C, ±VA and ±VD = ±5.0V unless otherwise noted.

THD+N vs FREQUENCY –40

16-BIT LEVEL LINEARITY (Dithered Fade-to-Noise) 8
Deviation from Ideal Level (dB)

–60dB –60

6 4 2 0 –2 –4 –6 –8 –120

THD+N (dB)

–40dB –80 –20dB –100 0dB

–120 20 100 1k Output Frequency (Hz) 10k

–110

–100

–90

–80

–70

–60

Output Signal Level (dB)

16-BIT MONOTONICITY 1.5 1 0.5 0 –0.5 –1 –1.5 8.83ms/div

–90dB SIGNAL SPECTRUM (100Hz Bandwidth) –80

Power Spectrum (dB)

Output Voltage (mV)

–100

–120

–140

–160 0 4k 8k 12k 16k 20k Frequency (Hz)

–90dB SIGNAL (10Hz to 20kHz Bandwidth) 200

–110dB SIGNAL (10Hz to 20kHz Bandwidth) 40

Output Level (?V)

100

0

Output Level (?V)
0 400 800 1200 1600 2000

20

0

–100

–20

–200 Time (?s)

–40 0 400 800 1200 1600 2000 Time (?s)

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PCM1702

4

THEORY OF OPERATION
ADVANCED SIGN MAGNITUDE Digital audio systems have traditionally used laser-trimmed, current-source DACs in order to achieve sufficient accuracy. However, even the best of these suffer from potential lowlevel nonlinearity due to errors at the major carry bipolar zero transition. More recently, DACs employing a different architecture which utilizes noise shaping techniques and very high over-sampling frequencies, have been introduced (“Bitstream”, “MASH”, or 1-bit DAC). These DACs overcome the low level linearity problem, but only at the expense of signal-to-noise performance, and often to the detriment of channel separation and intermodulation distortion if the succeeding circuitry is not carefully designed. The PCM1702 is a new solution to the problem. It combines all the advantages of a conventional DAC (excellent full scale performance, high signal-to-noise ratio and ease of use) with superior low-level performance. Two DACs are combined in a complementary arrangement to produce an extremely linear output. The two DACs share a common reference, and a common R-2R ladder for bit current sources by dual balanced current segments to ensure perfect tracking under all conditions. By interleaving the individual bits of each DAC and employing precise laser trimming of resistors, the highly accurate match required between DACs is achieved. This new, complementary linear or advanced sign magnitude approach, which steps away from zero with small steps in both directions, avoids any glitching or “large” linearity errors and provides an absolute current output. The low level performance of the PCM1702 is such that real 20-bit resolution can be realized, especially around the critical bipolar zero point. Table 1 shows the conversion made by the internal logic of the PCM1702 from binary two’s complement (BTC). Also, the resulting internal codes to the upper and lower DACs (see front page block diagram) are listed. Notice that only the LSB portions of either internal DAC are changing around bipolar zero. This accounts for the superlative performance of the PCM1702 in this area of operation.

DISCUSSION OF SPECIFICATIONS
DYNAMIC SPECIFICATIONS Total Harmonic Distortion + Noise The key specifications for the PCM1702 is total harmonic distortion plus noise (THD+N). Digital data words are read into the PCM1702 at eight times the standard compact disk audio sampling frequency of 44.1kHz (352.8kHz) so that a sine wave output of 1002Hz is realized. For production testing, the output of the DAC goes to an I to V converter, then through a 40kHz low pass filter, and then to a programmable gain amplifier to provide gain at lower signal output test levels before being fed into an analog-type distortion analyzer. Figure 1 shows a block diagram of the production THD+N test setup. For the audio bandwidth, THD+N of the PCM1702 is essentially flat for all frequencies. The typical performance curve, “THD+N vs Frequency”, shows four different output signal levels: 0dB, –20dB, –40dB, and –60dB. The test signals are derived from a special compact test disk (the CBS CD-1). It is interesting to note that the –20dB signal falls only about 10dB below the full scale signal instead of the expected 20dB. This is primarily due to the superior low level signal performance of the advanced sign magnitude architecture of the PCM1702. In terms of signal measurement, THD+N is the ratio of DistortionRMS + NoiseRMS/ SignalRMS expressed in dB. For the PCM1702, THD+N is 100% tested at all three specified output levels using the test setup shown in Figure 1. It is significant to note that this test setup does not include any output deglitching circuitry. All specifications are achieved without the use of external deglitchers. Dynamic Range Dynamic range in audio converters is specified as the measure of THD+N at an effective output signal level of –60dB referred to 0dB. Resolution is commonly used as a theoretical measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. The advanced sign magnitude architecture of the PCM1702, with its ideal performance around bipolar zero, provides a more usable dynamic range, even using the strict audio definition, than any previously available D/A converter.
LOWER DAC CODE (19-bit Straight Binary) 111...111+1LSB(1) 111...111+1LSB(1) 111...111+1LSB(1) 111...111+1LSB(1) 111...111+1LSB(1) 111...111 111...110 000...001 000...000 UPPER DAC CODE (19-bit Straight Binary) 111...111 111...110 000...010 000...001 000...000 000...000 000...000 000...000 000...000

ANALOG OUTPUT +Full Scale +Full Scale –1LSB Bipolar Zero +2LSB Bipolar Zero +1LSB Bipolar Zero Bipolar Zero –1LSB Bipolar Zero –2LSB –Full Scale +LSB –Full Scale

INPUT CODE (20-bit Binary Two's Complement) 011...111 011...110 000...010 000...001 000...000 111...111 111...110 100...001 100...000

NOTE: (1) The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.

TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart.
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PCM1702

Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings

Distortion Analyzer (Shiba Soku Model 725 or Equivalent)

Programmable Gain Amp 0dB to 60dB

Low-Pass Filter 40kHz 3rd Order GIC Type

Binary Counter

Digital Code (EPROM)

DATA

Parallel-to-Serial Conversion

DUT (PCM1702)

I to V Converter OPA627

CLOCK LE (Latch Enable)

Timing Logic

Sampling Rate = 44.1kHz x 8(352.8kHz) Output Frequency = 1002Hz

FIGURE 1. Production THD+N Test Setup. Level Linearity Deviation from ideal versus actual signal level is sometimes called “level linearity” in digital audio converter testing. See the “–90dB Signal Spectrum” plot in the Typical Performance Curves section for the power spectrum of a PCM1702 at a –90dB output level. (The “–90dB Signal” plot shows the actual –90dB output of the DAC). The deviation from ideal for PCM1702 at this signal level is typically less than ±0.3dB. For the “–110dB Signal” plot in the Typical Performance Curves section, true 20-bit digital code is used to generate a –110dB output signal. This type of performance is possible only with the lownoise, near-theoretical performance around bipolar zero of the PCM1702 advanced sign magnitude. A commonly tested digital audio parameter is the amount of deviation from ideal of a 1kHz signal when its amplitude is decreased form –60dB to –120dB. A digitally dithered input signal is applied to reach effective output levels of –120dB using only the available 16-bit code from a special compact disk test input. See the “16-bit Level Linearity” plot in the Typical Performance Curves section for the results of a PCM1702 tested using this 16-bit dithered fade-to-noise signal. Note the very small deviation from ideal as the signal goes from –60dB to –100dB. DC SPECIFICATION Idle Channel SNR Another appropriate specification for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of noise on the DAC output at bipolar zero in relation to the full scale range of the DAC. To make this measurement, the digital input is continuously fed the code for bipolar zero, while the output of the DAC is bandlimited from 20Hz to 20kHz and an A-weighted filter is applied. The idle channel SNR for the PCM1702 is typically greater than 120dB, making it ideal for low-noise applications. Monotonicity Because of the unique advanced sign magnitude architecture of the PCM1702, increasing values of digital input will always result in increasing values of DAC output as the signal moves away from bipolar zero in one-LSB steps (in either direction). The “16-bit Monotonicity” plot in the Typical Performance Curves section was generated using 16-bit digital code from a test compact disk. The test starts with 10 periods of bipolar zero. Next are 10 periods of alternating 1LSBs above and below zero, and then 10 periods of alternating 2LSBs above and below zero, and so on until 10LSBs above and below zero are reached. The signal pattern then begins again at bipolar zero. With PCM1702, the low-noise steps are clearly defined and increase in near-perfect proportion. This performance is achieved without any external adjustments. By contrast, sigma-delta (“Bit-stream”, “MASH”, or 1-bit DAC) architectures are too noisy to even see the first 3 or 4 bits change (at 16 bits), other than by a change in the noise level. Absolute Linearity Even though absolute integral and differential linearity specs are not given for the PCM1702, the extremely low THD+N performance is typically indicative of 17-bit integral linearity in the DAC. The relationship between THD+N and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. Offset, Gain, and Temperature Drift Although the PCM1702 is primarily meant for use in dynamic applications, specifications are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain and offset drift. DIGITAL INPUT Timing Considerations The PCM1702 accepts TTL compatible logic input levels. The data format of the PCM1702 is binary two’s complement (BTC) with the most significant bit (MSB) being first

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PCM1702

6

in the serial input bit stream. Table II describes the exact relationship of input data to voltage output coding. Any number of bits can precede the 20 bits to be loaded, since only the last 20 will be transferred to the parallel DAC register after Latch Enable (Pin6 <PCM1702P>, Pin7 <PCM1702U>, LE) has gone low. All DAC serial input data (Pin1, DATA) bit transfers are triggered on positive clock (Pin2, CLOCK), edges. The serial-to-parallel data transfer to the DAC occurs on the falling edge of Latch Enable. The change in the output of the DAC occurs at a rising edge of the 4th clock of the CLOCK after the falling edge of Latch Enable. Refer to Figure 2 for graphical relationships of these signals. Maximum Clock Rate A typical clock rate of 16.9MHz for the PCM1702 is derived by multiplying the standard audio sample rate of 44.1kHz by sixteen times (16X over-sampling) the standard audio word bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note that this clock rate accommodates a 24-bit word length, even though only 20 bits are actually being used. The setup and hold timing relationships are shown in Figure 3. “Stopped Clock” Operation The PCM1702 is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 20 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until Latch Enable goes low. Latch Enable must remain low until after the first clock cycle of the next data word to insure proper DAC operation. In any case, the setup and hold times for Data and LE must be observed as shown in Figure 3.
DIGITAL INPUT 1,048,576LSBs 1LSB 7FFFFHEX 00000HEX 80000HEX ANALOG OUTPUT Full Scale Range NA +Full Scale Bipolar Zero –1LSB –Full Scale CURRENT OUTPUT 2.40000000mA 2.28882054nA –1.19999771mA 0.00000000mA +1.20000000mA

INSTALLATION
POWER SUPPLIES Refer to CONNECTION DIAGRAM for proper connection of the PCM1702. The PCM1702 only requires a ±5V supply. Both positive supplies should be tied together at a single point. Similarly, both negative supplies should be connected together. No real advantage is gained by using separate analog and digital supplies. It is more important that both these supplies be as “clean” as possible to reduce coupling of supply noise to the output. Power supply decoupling capacitors should be used at each supply pin to maximize power supply rejection, as shown in CONNECTION DIAGRAM regardless of how good the supplies are. Both commons should be connected to an analog ground plane as close to the PCM1702 as possible. FILTER CAPACITOR REQUIREMENTS As shown in CONNECTION DIAGRAM, various size decoupling capacitors can be used, with no special tolerances being required. The size of the offset decoupling capacitor is not critical either, with larger values (up to 100?F) giving slightly better SNR readings. All capacitors should be as close to the appropriate pins of the PCM1702 as possible to reduce noise pickup from surrounding circuitry.

> 40ns Data Input LSB > 15ns > 15ns Clock Input MSB

> 20ns

> 20ns > 15ns

Latch Enable

> 15ns > One Clock Cycle > One Clock Cycle

TABLE II. Digital Input/Output Relationships.

FIGURE 3. Setup and Hold Timing Diagram.

Clock
DATA "N"

Data

1
MSB

2

3

4

12 13 14 15 16 17 18 19 20
LSB

1

Latch Enable IOUT
N-1 N

NOTES : (1) If clock is stopped between input of 20-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 20-bit data word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable (LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative. (5) IOUT changes on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).

FIGURE 2. Timing Diagram.

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7

PCM1702

+5V 4.7?F +5V 1 DATA –5V + C49 100?F + RF2 2.5k? IC1-4: OPA2604 C51 100?F –5V VCC BCK +5V PCM1702P 4 GND 11 R12 IC1 6.04k? +5V VCC + C47 3.3?F R15 4.02k? IC2 IC1 R14 4.02k? 2k? C61 1000pF + C54 100?F 9 10 R20 C55 220p 15 14 13 12 2 3 3 + C41 3.3?F 8X Interpolation Digital Filter 17 22 16 +5V VCC + 4.7?F 7 0.1?F + 4.7?F C45 3.3?F +

4.7?F

?

+

17.1k?

+5V

1

Digital Interface Format Receiver

FIGURE 4. Typical Application for Stereo Audio 8X Oversampling system.
φA 8
DOR 23 BCO 26 5 6 LE +5V –5V BPO DC WCK 25 DOL 24 Burr-Brown DF1700P 14 100pF 14 4 8 10 16 21 IOUT 2 28 1 6 + C49 3.3?F IC2 VO L/R 15 DA 17 Low-pass 3-pole Butterworth f–3dB = 40kHz C57 1000pF C46 3.3?F + 1 DATA –5V + C50 100?F + C52 100?F BCK +5V PCM1702P 4 GND 11 10 + C54 100?F 9 + C48 3.3?F R18 4.02k? IC4 IC3 +5V VCC IC3 6.04k? R17 4.02k? 2k? C62 1000pF + C44 3.3?F 5 6 LE +5V –5V VCC –5V BPO DC IOUT 15 14 13 12 2 3 + C42 3.3?F 16 –5V VCC RF2 2.5k? C56 220p R16 5.36k? C58 1000pF R13 R21 IC4 VO Low-pass 3-pole Butterworth f–3dB = 40kHz C59 1000pF R19 5.36k? See Application Bulletin AB-026 for information on GIC filters. C60 1000pF

PCM1702

Interleaved Digital Input

28

6

BCO 12

5

16.9344MHz (192F S)

1M?

Yamaha YM3623

10pF

10pF

3

4

150?

4700pF

8

PACKAGE OPTION ADDENDUM
www.ti.com

14-Oct-2008

PACKAGING INFORMATION
Orderable Device PCM1702P PCM1702P-J PCM1702P-JG4 PCM1702P-K PCM1702P-KG4 PCM1702PG4 PCM1702U PCM1702U-2/2K PCM1702U-2/2KE6 PCM1702U-J PCM1702U-JE6 PCM1702U-K PCM1702U-KE6 PCM1702U/2K PCM1702U/2KE6 PCM1702UE6
(1)

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Package Type PDIP PDIP PDIP PDIP PDIP PDIP SO SO SO SO SO SO SO SO SO SO

Package Drawing N N N N N N NS NS NS NS NS NS NS NS NS NS

Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 20 20 20 20 20 20 20 20 20 20 38 38 38 38 2000 2000 38 25 25 25 25 25 25 38 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) TBD TBD Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU SNBI Call TI Call TI CU SNBI CU SNBI CU SNBI CU SNBI CU SNBI CU SNBI CU SNBI

MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-2-260C-1 YEAR Call TI Call TI Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

14-Oct-2008

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Aug-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SO NS 20

SPQ

Reel Reel Diameter Width (mm) W1 (mm) 330.0 25.4

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm) 12.0

W Pin1 (mm) Quadrant 24.0 Q1

PCM1702U/2K

2000

8.8

13.1

2.8

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Aug-2008

*All dimensions are nominal

Device PCM1702U/2K

Package Type SO

Package Drawing NS

Pins 20

SPQ 2000

Length (mm) 346.0

Width (mm) 346.0

Height (mm) 41.0

Pack Materials-Page 2

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