lanxicy.com

第一范文网 文档专家

第一范文网 文档专家

Modeling and Design of Feedback Loops for a Voltage-Mode Single-Inductor Dual-Output Buck Converter

Kun-Yu Lin, Chun-Shih Huang, Dan Chen and Kwang H. Liu*

National Taiwan University, Electrical Engineering Department, Taipei, Taiwan * Green Mark Inc., 5F., No.205-1, Sec. 3, Beisin Rd., Sindian City, Taipei, Taiwan

Abstract—In recent years, single-inductor dual-output (SIDO) converters have found applications in hand-held electronic devices. The focus of the paper is about the modeling and the design of the feedback control loop for a voltage-mode SIDO buck converter working in continuous conduction mode. A small-signal model was developed and verified by simulations and experimental results. This model is practically useful in designing the feedback compensation and predicting the closed-loop performances including circuit stability, line regulation, and output impedances. Single-Inductor Dual-Output (SIDO), Buck Keywords Converter, Voltage-Mode, Modeling.

? ? ? ?

the gate-drive timing diagram and the inductor current waveform in CCM mode. Depending on the input-voltage, output-voltage and load conditions, the circuit CCM operation can be classified into three categories according to the relative magnitude of the two duty cycles of the two respective MOSFET switches Q1 and Q2. When D1 is greater than D2, the operation is called Class-A. When D1 is equal to D2, the operation is called Class-B, When D1 is less than D2, it is called Class-C. Fig. 2 shows the waveforms for the three classes of operation.

DB

L

rL

Vo2

I. INTRODUCTION In recent years, single-inductor dual-output (SIDO) non-isolated DC-DC converters have been reported [1, 710]. Because of circuit simplicity and low cost, this class of converters has found low-power applications requiring multiple-output voltages such as hand-held electronic devices. The operation of SIDO converters can be classified into two modes: discontinuous conduction mode (DCM) and continuous conduction mode (CCM), depending upon the inductor current waveform [15-18]. SIDO converters with DCM operation work just like two independent converters with the inductor multiplexing current to different outputs and can be modeled and designed similar to conventional buck converters. SIDO converters with CCM operation, however, present problems with cross-coupling between the two outputs in the feedback [16-18] which makes it hard for the design of feedback control circuit [2-6]. The focus of the present paper is to model the feedback control loop for a SIDO buck converter working in CCM mode. In this paper, the operation of the CCM SIDO buck converter will be reviewed first. The DC analysis of the SIDO converter is presented. A small-signal model will be developed and verified by simulations and hardware. This model is practically useful in designing the feedback compensation and predicting the closed-loop performances including circuit stability, line regulation, and output impedances. II. OPERATION OF SIDO BUCK CONVERTERS

Q1

Q2

rC 1

Vo1

rC 2

C2

R2

Vin

DA

R1

C1

ZB

? d2 F m1

ZA

EA1

Vref 1

V p1

ZD

? d1

ZC

Fm 2

EA 2

Vref 2

V p2

Figure 1. Circuit diagram of the SIDO buck converter

B. Description of operation Class-A: D1>D2 In Class-A operation, Q1 and Q2 are both turned on during the period t1a, and the inductor current iL ramps up

A. Circuit Diagram Fig. 1 shows a circuit diagram of a SIDO buck converter with two voltage feedback loops. Fig. 2 shows

978-1-4244-1668-4/08/$25.00 ?2008 IEEE

3389

with the slope of (Vin-Vo1)/L and the diode DB is reversebiased because Vo2 is greater than Vo1. During the period t2a when Q1 is still on but Q2 is off, the inductor current iL ramps up with the slope of (Vin-Vo2)/L and flows to Vo2 through diode DB. During t3a when both Q1 and Q2 are off, the inductor current is flowing through both diodes DA and the DB to discharge to Vo2, and iL ramps down with the slope of Vo2/L. In this class of operation, the inductor is charged through two periods and is discharged to output voltage Vo2 in the last period. Class-B: D1=D2 In Class-B operation, Q1 and Q2 are both turned on during t1b, the inductor current iL ramps up with the slope of (Vin-Vo1)/L and the diode DB is reverse-biased because Vo2 is greater than Vo1. In the t2b duration when both Q1 and Q2 are off, the inductor current is flowing through both diodes DA and DB to discharge to Vo2, and iL ramps down with the slope of Vo2/L. In this class of operation, the inductor is charged through one period and is discharged to output voltage Vo2 in the last period. Class-C: D1<D2 In Class-C operation, Q1 and Q2 are both turned on during t1c, the inductor current iL ramps up with the slope of (Vin-Vo1)/L and the diode DB is reverse-biased because Vo2 is greater than Vo1. During t2c period, Q2 is still on but Q1 is off, and the inductor current iL ramps down with the slope of Vo1/L and flows to Vo1 through the diode DA. In the t3c period when both Q1 and Q2 are off, the inductor current is flowing through both diodes DA and DB to discharge to Vo2, and iL ramps down with the slope of Vo2/L. In summary, when Q1 is on, the energy is stored in the inductor; when Q1 is off, the power is distributed to one of the two outputs, depending on the state of Q2.

iL (t )

(Vin ? Vo1 ) L

(?Vo 2 ) L

t 1b

Ts

t 2b

Time

Clock Time

Vgs1

Q 1 ON

DA ON

Time

Vgs 2

Q 2 ON DB ON

(b) Class-B: D1=D2

Time

iL (t )

(Vin ? Vo1 ) L

(?Vo1 ) L

(?Vo2 ) L

t 1c

Ts

Clock

t 2c

t 3c

Time

i L ( t ) (Vin ? Vo1 )

L

(Vin ? Vo 2 )

L

( ?Vo 2 ) L

Time

Vgs1

Q 1 ON

DA ON

Time

DB ON

Vgs 2

Q 2 ON

Time

t 1a

t 2a TS

t 3a

(c) Class-C: D1<D2

Time

Figure 2. Timing diagram of the SIDO buck converter

Clock

Time

Vgs1

Q1 ON

C. DC voltage gain and determination of operating class Using the “pulse width modulation (PWM) switch model” [19], the expressions for DC voltage gains can be derived. The two DC voltage gain expressions are shown by (1) and (2), where R1 and R2 are load resistances. It’s noted that these expressions were obtained under the assumption that both the transistors and the diodes are ideal switches.

DA ON

Time

Vgs 2

Q 2 ON

DB

ON

Time

(a) Class-A: D1>D2

3390

Vo1 D1 ? D2 ? R1 = Vin D2 2 ? R1 + (1 ? D2 )2 ? R2 + rL Vo 2 D1 ? (1 ? D2 ) ? R2 = Vin D2 2 ? R1 + (1 ? D2 )2 ? R2 + rL

(1)

(2)

where 0 < D1 < 1 and 0 < D2 < 1 By solving simultaneous equations (1) and (2), D1 and D2 can be represented by (3) and (4). It can be seen that the duty cycles depend on both the voltages and the load conditions even for a CCM operation of this type of converter. Depending on the relative magnitude of the two duty cycles, the three classes of waveforms shown in Fig.2 can be determined.

D2 = I o1 I o1 + I o 2

Vo1 ? D2 2 ? R1 + (1 ? D2 ) ? R2 + rL

2

can be simplified as shown in (5) and (6). The transfer functions inside the brackets of the two equations can be expressed by converter parameters as shown by (7) and (8). Notice that in the expression G1(s), there are one pole and one equivalent-series-resistance (ESR) zero. Therefore, the compensation gain A1 should provide one canceling zero, one canceling pole and a low-frequency pole to make the loop gain T1 stable by crossing 0dB at minus20 dB/decade slope. In the expression G2(s), there are two poles and one ESR zero. This can be obtained by substituting in Req2(s) in (8) by using the expression of Req2(s) at the bottom of Table I. The two poles can be obtained by solving the resultant second-order algebraic equation of the denominator. The compensation gain T2 uses the same way to let loop gain T2 stable.

T1 ( s ) ? Gd 21 ( s ) ? Gd 11 ( s ) ? Gd 22 ( s ) Gd 12 ( s ) Gd 11 ( s ) ? Gd 22 ( s ) Gd 21 ( s ) ? Fm1 ? A1 ( s )

(3)

(5)

G1 ( s ) ? Fm1 ? A1 ( s )

D1 =

Vin ? D2 ? R1

(4)

T2 ( s ) ? Gd 12 ( s ) ?

? Fm 2 ? A 2 ( s )

(6)

G2 ( s ) ? Fm 2 ? A2 ( s )

III.

SMALL-SIGNAL MODEL

G1 ( s ) Gd 21 ( s ) ? =

Because there are two independently-controlled active switches involved, the control model of conventional buck converters doesn’t apply anymore. A new model was derived in this paper using the “pulse width modulation (PWM) switch model” concept [19] and also confirmed by “state-space averaging method” [20]. This model applies to Class-A, Class-B and Class-C operations. Fig. 3 shows the control block diagram and Table I summarizes the symbol definitions, the expressions of the transfer function and the analytical results describing the dependencies of the various converter closed-loop performances on loop gains, including closed-loop line-to-output, closed-loop selfoutput impedances and closed-loop cross-output impedances for both outputs. There are two loop gains T1 and T2 measured at the designated location in Fig. 3. Symbols Fm1, and A1 represent, respectively, the modulator gain of the PWM block and the compensator gain of Loop_1. Same rule applies to Fm2 and A2. The parameters in the Table II can be classified into three groups: power-stage parameters, feedback parameters, and line-load dc conditions. D1 and D2 values can be found from (3) and (4). IV. COMPENSATION DESIGN

Gd 11 ( s ) ? Gd 22 ( s ) Gd 12 ( s )

1 + s ? C1 ? ( R1 + rC 1 ) Gd 11 ( s ) ? Gd 22 ( s ) (8) G2 ( s ) Gd 12 ( s ) ? Gd 21 ( s ) Vin ? I L ? Req 2 ( s ) = I L ? (1 ? D2 ) ? Req 2 ( s ) + s ? L + rL + D2 ? (Vo 2 ? Vo1 )

(1 ? D2 ) ?

I L ? R1 ? (1 + s ? C1 ? rC1 )

(7)

? vin

Gv1

Z o11

Z o 21

? vo1

Gd 21

? d2

i?o1 i?o2

Fm1

A1

Gd11

Gv 2

Gd22

? vo2

Z o12

Z o 22

Gd 12

d?1

The goal of the compensator design is to find proper compensator gains A1 and A2 such that the loop gains T1 and T2 meet the bandwidth requirements with specified phase margins. Because of the intertwining of the two loops, the compensator design is no longer as straightforward as that in a single-output converter [11-14]. However, the complexity can be reduced if TX and TY are both much larger than unity, then the loop gains T1 and T2

Fm 2

A2

TX TP

Gd 21 ? Fm1 ? A1 Gd 22 ? Fm1 ? A1

TY TQ

Gd 12 ? Fm 2 ? A2 Gd 11 ? Fm 2 ? A2

Figure 3. Control block diagram of SIDO buck converter

3391

TABLE I. TRANSFER FUNCTIONS OF THE BLOCK Transfer Functions Open-loop line-to-output

TABLE II. ANALYTICAL RESULTS

Analytical Results

Gv1 ( s )

? vo1 ( s ) D1 ? D2 ? Req1 ( s ) = ? vin ( s ) Δ( s )

(9) (10)

Loop gain Loop gain 1:

T1 ( s ) = Tx ( s ) ?

Loop gain 2:

TP ( s ) ? TQ ( s )

1 + TY ( s )

(19)

Gv 2 ( s )

? vo 2 ( s ) D1 ? (1 ? D2 ) ? Req 2 ( s ) = ? vin ( s ) Δ( s )

Open-loop control-to-output

T2 ( s ) = TY ( s ) ?

TP ( s ) ? TQ ( s )

1 + TX ( s )

(20)

Gd 11 ( s )

Gd 12 ( s ) Gd 21 ( s ) =

? vo1 ( s ) Vin ? D2 ? Req1 ( s ) = ? Δ( s ) d ( s)

? vo 2 ( s ) Vin ? (1 ? D2 ) ? Req 2 ( s ) = ? Δ( s ) d ( s)

1

(11) (12) (13)

Closed-loop line-to-output

1

? vo1 ( s ) (Closed ? loop) ? v in ( s )

Gv1 ( s ) ? Gv 2 ( s )

TQ ( s )

(21)

? vo1 ( s ) ? d ( s)

2

1 + TY ( s ) 1 + T1 ( s )

I L ? Req1 ( s ) ? (1 ? D2 ) ? Req 2 ( s ) + s ? L + rL + D2 ? Req1 ( s ) ? (Vo 2 ? Vo1 ) Δ( s ) ? vo 2 ( s ) ? d ( s)

2

? vo 2 ( s ) (Closed ? loop) ? vin ( s )

(22)

Gd 22 ( s )

(14)

=

? I L ? Req 2 ( s ) ? ( D2 ? Req1 ( s ) + s ? L + rL ) + (1 ? D2 ) ? Req 2 ( s ) ? (Vo1 ? Vo 2 ) Δ( s )

T ( s) Gv 2 ( s ) ? Gv1 ( s ) P 1 + TX ( s ) 1 + T2 ( s )

Closed-loop self-output impedance

Open-loop self-output impedance

? vo1 ( s ) (Closed ? loop ) ? i ( s)

o1

? v ( s) Zo11( s) o1 ? i ( s)

o1

(23)

TQ ( s )

=

Z o 22 ( s ) =

(1? D2 )

? vo 2 ( s ) ? i ( s)

o2

(15)

2

Z o11 ( s ) ? Z o12 ( s )

? Req1( s) ? Req2 (s) + Req1(s) ? rL + s ? L ? Req1(s) Δ(s)

(16)

Δ( s )

1 + TY ( s ) 1 + T1 ( s )

? vo 2 ( s ) (Closed ? loop) ? i ( s)

o2

(24)

D2 ? Req1 ( s ) ? Req 2 ( s ) + Req 2 ( s ) ? rL + s ? L ? Req 2 ( s )

2

T ( s) Z o 22 ( s ) ? Z o 21 ( s ) P 1 + TX ( s ) 1 + T2 ( s )

Closed-loop cross-output impedance

Open-loop cross-output impedance

Z o12 ( s )

? vo 2 ( s ) ? D2 ? (1 ? D2 ) ? Req1 ( s ) ? Req 2 ( s ) = ? Δ( s ) i ( s)

(17)

? vo1 ( s ) (Closed ? loop ) ? ( s) i

o2

(25)

TQ ( s )

Z o 21 ( s )

Parameters

? vo1 ( s ) ? D2 ? (1 ? D2 ) ? Req1 ( s ) ? Req 2 ( s ) = ? Δ( s ) i ( s)

o2

o1

(18)

Z o 21 ( s ) ? Z o 22 ( s ) 1 + T1 ( s )

1 + TY ( s )

D1 : duty cycle of Q1 ; 0 < D1 < 1 D2 : duty cycle of Q2 ; 0 < D2 < 1 I o1 = IL = Vo1 R1 ; Io2 = Vo 2 R2

? vo 2 ( s ) (Closed ? loop ) ? i ( s)

o1

(26)

Z o12 ( s ) ? Z o11 ( s )

Parameters

Vo1 Vo 2 + = I o1 + I o 2 R1 R2

TP ( s ) 1 + TX ( s ) 1 + T2 ( s )

1 Vp2

Req1 ( s ) Req 2 ( s )

R1 // R2 //

2

R1 ? (1 + s ? C1 ? rC 1 ) 1 + rC 1 = s ? C1 1 + s ? C1 ? ( R1 + rC 1 ) R2 ? (1 + s ? C 2 ? rC 2 ) 1 + rC 2 = s ? C2 1 + s ? C 2 ? ( R2 + rC 2 )

2

Fm1

1 ; Fm 2 V p1

TX ( s ) Gd 21 ( s ) ? Fm1 ? A 1( s ) TY ( s ) Gd 12 ( s ) ? Fm 2 ? A2 ( s ) TP ( s ) Gd 22 ( s ) ? Fm1 ? A1( s ) TQ ( s ) Gd 11 ( s ) ? Fm 2 ? A2 ( s )

Δ( s ) = D2 ? Req1 ( s ) + (1 ? D2 ) ? Req 2 ( s ) + s ? L + rL

3392

V.

EXPERIMENTAL VERIFICATIONS

A SIDO buck converter was built for verifying the proposed model. The circuit parameters and the working conditions are as follow: Vin=5V, Vo1=1.8V, Vo2=3.3V, L=10.3 H, Co1=33 F, Co2=47 F and switching frequency fs=100kHz. R1 and R2 values vary according to the load current level Io1 and Io2. Fig. 4-(a) shows the measured waveforms as Io1=0.5A and Io2=1A, Fig. 4-(b) shows the measured waveforms as Io1=0.76A and Io2=0.5A, Fig. 4-(c) shows the measured waveforms as Io1=1A and Io2=0.33A. Fig. 5 show the Bode plots for various transfer functions for the load current of Io1=1A and Io2=0.33A. For each figure, the plots were based on the proposed model were compared against the model calculation results, the SIMPLIS simulations and the measured results. The crossover frequencies are 7.5kHz for T1 and 8.2kHz for T2. It can be seen that the model predicts the results fairly well up to half switching frequency. VI. CONCLUSIONS

Fig. 4-(c) Io1=1A, Io2=0.33A, (D1<D2) Figure 4. Experimental waveforms (a) Class-A (b) Class-B (c) Class-C Vin=5V, Vo1=1.8V, Vo2=3.3V

A small-signal model was proposed and verified experimentally for SIDO buck converter. This model is practically useful in designing the feedback compensation and predicting the closed-loop performances. A DC analysis was also given to find out the dependency of the two duty cycles on the power circuit parameters and working conditions. Without the model, it’s difficult to design the feedback for such a converter.

Fig. 5-(a) Loop gain T1 (Eq.19)

Fig. 4-(a) Io1=0.5A, Io2=1A, (D1>D2)

Fig. 4-(b) Io1=0.76A, Io2=0.5A, (D1=D2)

Fig. 5-(b) Loop gain T2 (Eg.20)

3393

Fig. 5-(c) Closed-loop line-to-output_1 (Eq.21)

Fig. 5-(f) Closed-loop self-output_2 impedance (Eq.24)

Fig. 5-(d) Closed-loop line-to-output_2 (Eq.22)

Fig. 5-(g) Closed-loop cross-output_1 impedance (Eq.25)

Fig. 5-(e) Closed-loop self-output_1 impedance (Eq.23)

Fig. 5-(h) Closed-loop cross-output_2 impedance (Eq.26) Figure 5. Bode plots of calculation, simulation and measurement under Vin=5V, Vo1=1.8V, Vo2=3.3V, Io1=1A, Io2=0.33A

3394

ACKNOWLEDGMENT The work was supported by Taiwan National Science Council Research gain NSC-96-2221-E-002-292-MYZT to National Taiwan University. The authors also wish to thank Catena Software Ltd. for supplying SIMetrix/ SIMPLIS software. REFERENCES

[1] [2] U.S. Patent 7,224,085, Jun Chen et al., “Single inductor dual output buck converter”, May 29 2007. P. Patra, A. Patra and D. Kastha, “On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology”, VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference, pp. 935–940, Jan. 2007 C. Sreekumar and V. Agarwal, “On the hybrid automaton models and control synthesis of a single inductor, double output boost converter”, Power Electronics and Motion Control Conference, 2006. IPEMC '06. CES/IEEE 5th International Vol. 1 pp. 1– 5, Aug. 2006. E. Bayer and G. Thiele, “A single-inductor multiple-output converter with peak current state-machine control”, Applied Power Electronics Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE19-23 March 2006. A. Sharma and Y.S. Pavan, “A single inductor multiple output converter with adaptive delta current mode control”, Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006. P. Patra, S. Samanta, A. Patra and S. Chattopadhyay, “A novel control technique for single-snductor multiple-output DC-DC Buck Converters”, Industrial Technology, 2006. ICIT 2006. IEEE International Conference, pp. 807–811, Dec. 2006. U.S. Patent 6,900,620, Eiji Nishimori et al., “Switching regulator having two or more outputs”, May 31 2005. U.S. Patent 6,222,352, Ronald J Lenk et al., “Multiple voltage output buck converter with a single inductor”, Apr. 24 2001. U.S. Patent 6,075,295, Thomas Li et al., “Single inductor multiple output boost regulator”, June 13 2000. U.S. Patent 6,552,110, Vadim V. Ivanov et al., “Multiple output switching regulator”, Feb. 18 2003. D. Trevisan, , P. Mattavelli and P. Tenti, “Digital control of single-inductor dual-output DC-DC converters in continuousconduction mode”, Power Electronics Specialists Conference, PESC '05. IEEE 36th 2005, pp. 2616–2622, 2005 V. Moreno and L. Benadero, “Investigating stability of a single inductor current mode controlled dual switching DC-DC converter”, Power Electronics and Applications, 2005 European Conference, 2005 S.-C Koon, Y.-H. Lam and W.-H Ki, “Integrated charge-control single-inductor dual-output step-up/step-down converter”, Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium, Vol. 4 pp. 3071-3074, May 2005. D. Trevisan, W. Stefanutti, P. Mattavelli and P. Tenti, “FPGA control of SIMO DC-DC converters using load current estimation”, Industrial Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE, Nov. 2005. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok, “Single-inductor multiple-output switching converters with timemultiplexing control in discontinuous conduction mode”, SolidState Circuits, IEEE Journal of vol. 38, Issue 1 pp.89-100, Jan. 2003. D. Ma, W.-H. Ki and C. Y. Tsui "A pseudo-CCM/DCM SIMO switching converter with freewheel switching", Solid-State Circuits, IEEE Journal of Vol. 38, Issue 6 pp.1007-1014, June 2003. W.-H. Ki and D. Ma “Single-inductor multiple-output switching converters”, Power Electronics Specialists Conference, PESC, IEEE 32nd Annual Vol.1 pp. 226 - 231, June 2001. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok, “A 1.8 V single-inductor dual-output switching converter for

power reduction techniques”, Symposium on VLSI Circuit Digest of Technical Papers, pp.137-140, June 2001. [19] R. W. Erickson, Dragan Maksimovic, “Fundamental of Power Electronics” second edition, Kluwer Academic Publisher, 1999. [20] Mohan, Undeland, Robbins, “Power Electronics” third edition, John Wiely & Soncs, Inc., 2003.

[3]

[4]

[5]

[6]

[7] [8] [9] [10] [11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

3395

相关文章:

- 电气专业毕业论文外文翻译
*review**of**loop*compensation techniques applied to ...(with zero*inductor*current), thus effectively ...“*A*More Accurate Current-*Mode*Control*Model*”,...

- 电气、自动化控制电路设计
*review**of**loop*compensation techniques applied to ...(with zero*inductor*current), thus effectively ...“*A*More Accurate Current-*Mode*Control*Model*”,...

- ic设计网站大全
*Inductor**Design*/LNA*Design*/PLL*Design*/Transceiver ...*Loops**and*Clock Recovery Circuits 5.Fundamentals ...论坛 上没有) 3.*Feedback*Linearization*of*RF ...

- 设计、分析和实时测试控制器的多总线微电网系统_图文
- 2, the
*single*-phase equivalent*model**of*the ...*and*is the current through filter*inductor*.( ...*voltage**feedback**loop*, whose open-*loop*transfer ...

- Output LC filter Design of single-phase UPS Inverter(逆变LC...
- Output LC filter
*Design**of**single*-phase UPS ...The larger*inductor*value corresponds to little ...*design**of*LC is tangled with the*feedback*...

- The analysis and layout of a switching Power Supply
- Analysis
*and**Design**of**a*... 12页 8财富值 ...By minimizing the*voltage**feedback**loop*length, ...1. Place the*inductor*(Transformer) first. 2. ...

更多相关标签:

- 电源反馈设计速成篇之五设计篇 (Voltage mode, CCM)
- Choosing the Inductor for a Buck Converter
- Inductor Design In Smps(1)
- Loop Compensation of Voltage-Mode Buck Converters
- Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators
- On the design of single-inductor double-output DC-DC buck, boost and buck-boost converters
- an-1162_Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier
- A Current-Mode DC-DC Buck Converter with High Stability Independent of Load and Supply Voltage
- Design of the dual mode DC-DC buck converter using low power control method
- Design of a current-mode, MOS, DC-DC buck converter with a quadratic slope compensation scheme
- (重点)Emulated Current Mode Control for Buck Regulators Using Sample and Hold Technique
- Loop Compensation of Voltage-Mode Buck Converters
- Loop Design of Buck Converters with Voltage-Mode Control
- Analysis of the control loop for a DC-DC Converter
- Fast mode-switching technique in hrbrid-mode operation