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A Current-Mode DC-DC Buck Converter with Efficiency-Optimized Frequency Control and Reconfigurable Compensation

Jia-Ming Liu, Student Member, IEEE, Pai-Yi Wang, Student Member, IEEE, and Tai-Haur Kuo, Member, IEEE

Abstract—Large input voltage range and wide output current range are usually needed for DC-DC converters. For these input and output conditions, the converter’s efficiency can be maximized by a proposed method, Efficiency-Optimized switching-Frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the above three proposed methods, a monolithic currentmode DC-DC buck converter is implemented in a 0.35mm 3.3V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16mW and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40mV and 12ms, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm2. Index Terms—compensation, current control, DC-DC power conversion

I. INTRODUCTION

W

the rapidly growing market of portable electronic devices, high-efficiency DC-DC converter ICs, which are required to extend the standby and operation time of battery-powered portable devices, are in widespread demand. In general, a wide load current range and a large input voltage range are required for the DC-DC converters. However, the efficiencies of a fixed switching-frequency DC-DC converter can be degraded under various operating conditions. Pulse frequency modulation [1], adaptive on-time [2], dithering skip modulation [3], and pulse skipping modulation [4], can vary the switching frequencies for efficiency improvements in light load; however, the heavy-load efficiencies, which are also important

ITH

Manuscript received July 30, 2010; revised October 9, 2010, December 30, 2010 and May 19, 2011. This work was supported by the National Science Council of Taiwan under Grant NSC 98-2218-E-006-242. The authors are all with Department of Electrical Engineering, National Cheng Kung University, Tainan City 70101, Taiwan. (phone: +886-6-2081999; fax: +886-6-2345482; e-mail: jmliu@msic.ee.ncku.edu.tw, pywang@msic.ee. ncku.edu.tw, thkuo@msic.ee. ncku.edu.tw).

for battery-life, are not optimized. Though adaptive frequency control (AFC) in [5] can further improve heavy-load efficiencies, the additional control circuits, including analog-to-digital converters (ADCs) and minimum input power tracking circuits, are required and thus result in increased power loss. In this paper, an Efficiency-Optimized switchingFrequency (EOF) control method is proposed. The optimal switching frequencies, which are generated by a low-complexity and low-power EOF generator, can maximize the converter’s efficiencies in different load currents and input voltages. Additionally, the proposed EOF control can also reduce the electro-magnetic interference (EMI). Integrating different control modes into a DC-DC converter has been applied for efficiency improvement. In [1]-[3], different controllers are used for different load conditions. As such, extra control and detection circuits are required, leading to increased hardware complexity and power consumption. In this paper, a controller with reconfigurable compensation is proposed. The controller can be reconfigured for continuous-conduction mode (CCM) and discontinuousconduction mode (DCM) with only three transmission gates. The control signals of the transmission gates are generated by the zero-current detector (ZCD), which widely exists in switching DC-DC converters to prevent reverse inductor current in DCM; thus, no extra control circuit is required. Furthermore, the output voltage variation can be reduced and the transient recovery time can be improved. A current sensor is required in current-mode control for obtaining the inductor current’s information. In contrast to the conventional design with a fixed current scaling ratio [6], a piecewise-linear current sensor (PLCS) is proposed. By using two scaling ratios in light and heavy loads, the sensor power loss can be reduced without sacrificing the sensing accuracy. In this paper, a monolithic current-mode DC-DC converter, with the proposed EOF generator, reconfigurable compensator, and PLCS, is implemented and measured. The organization of this paper is described as follows. Section II presents the proposed EOF control. In section III, the reconfigurable compensator design will be addressed. The monolithic DC-DC converter implementation is discussed in section IV, while the measurement results are shown in section V. Finally, conclusions will be drawn in Section VI.

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Fig. 1. Block diagram of a typical DC-DC buck converter.

II. EFFICIENCY-OPTIMIZATION FREQUENCY (EOF) CONTROL In this section, the EOF control method will be presented. Not only focusing on light-load efficiency improvement [1]-[4], the low-complexity and low-power EOF control can also improve the converter’s efficiencies over the entire load range without using complex control circuits, as in [5]. The EOF control is to maximize the efficiency of a DC-DC converter by using optimal switching frequencies for different operating conditions. To obtain the optimal switching frequencies, detailed power-loss models must be analyzed. The building blocks of a typical DC-DC converter, as shown in Fig. 1, can be divided into the pulse-width modulation (PWM) controller, the

TABLE I POWER-LOSS MODELS IN A DC-DC CONVERTER

gate driver, and the power stage. The power stage is composed of the power MOSFETs, MP and MN, and the output LC filter. The power-loss models [7] of the converter in Fig. 1 can be classified into four categories, as given in Table I, with the definitions of the parameters summarized in Table II. The switching loss PSW and the dead-time loss Pdead increase as the PWM switching frequency fSW increases, while the current-ripple conduction loss Prip decreases as fSW increases. Further, the average conduction loss Pavg and the controller loss Pstatic are independent of the fSW. In general, a DC-DC converter needs to provide a stable VOUT despite a large VIN range and a wide Iload range. If a fixed fSW is adopted, the total power loss won’t be minimized for these various operating conditions. The total power loss Ploss of a DC-DC converter can be obtained by summing the power-loss equations in Table I, and then the efficiencies can be evaluated by Pout/(Pout+Ploss), where Pout is the output power of the converter. Therefore, the efficiencies versus different load currents and switching frequencies can be plotted in Fig. 2 with the given parameter values in Table II. These parameter values will be used throughout this paper unless otherwise specified. The EOF control method is to select the optimal switching frequencies in different load currents according to Fig. 2 and plotted as the solid line in Fig. 3(a), where the dashed line is for fixed switching-frequency control. The fixed switching frequency is selected to have the same maximum voltage ripple as that of the EOF control. With the EOF control, as revealed in Figs. 3(b)

CATEGORIES

SYMBOL PSW,DCM PSW,CCM

EQUATION

2 ( C gp + C gn ) × V IN × fSW + 2 é V 2 + VO + (V IN - VO )2 ù C L × ê IN ú × f SW 2 ê ú ? ?

Switching

2 ( C L + C gp + C gn ) × VIN × fSW

Dead-time

Pdead,DCM Pdead,CCM Pavg

td × I peak , DCM × VD × fSW

2 × td × I avg × VD × fSW

2 2 I load × rL + d1 × I load × RDS , P + 2 d2 × I load × RDS , N

2 2 I rip × ( rL + rC ) + d1 × I rip × RDS ,P + 2 d2 × I rip × RDS ,N

Conduction Prip Controller Pstatic

I static × VIN

Fig. 2. Efficiencies versus switching frequencies and load currents. TABLE II DEFINITIONS OF THE PARAMETERS IN TABLE I

DESIGN PARAMETERS Input voltage Output voltage Duty cycle of MP on and MN offa Duty cycle of MP off and MN ona Inductor current Average of IL Ripple of IL Dead-time Peak inductor current in DCM Switching frequency

a

SYMBOL VIN VOUT d1 d2 IL Iload Irip td Ipeak,DCM fSW

VALUE 3.3V 1.8V 0.545 0.454 ---20ns ---

POWER STAGE PARAMETERS Filter inductor ESR of inductor L Filter capacitor ESR of capacitor C On resistance of MP On resistance of MN Gate capacitance of MN Gate capacitance of MP Total capacitance of converter output Turn-on voltage of MN’s body-diode

SYMBOL L rL C rC RDS,P RDS,N Cgn Cgp CL VD

VALUE 2μH 0.05Ω 22μF 0.2Ω 0.2Ω 0.2Ω 200pF 400pF 1nF 0.7V

d1+d2=1 for CCM, while d1+d2<1 for DCM.

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Fig. 4. Optimal switching frequency versus load current with different input voltages.

Fig. 3. (a) Switching frequency versus load current with fixed-frequency and EOF control, (b) the expected power-loss reduction, and (c) the efficiency improvement with the EOF control.

and 3(c), the expected power-loss reductions are 16mW and 19mW, corresponding to efficiency improvements of 17.9% and 1%, in light and heavy loads, respectively. Fig. 4 plots the relationship of the optimal switching frequencies versus the load currents Iload with different input voltages VIN. To realize the relationship, an EOF generator is thus proposed.

Fig. 5 shows the schematic of the EOF generator, which can be partitioned into four main blocks, i.e., the CCM control-voltage generator, the DCM control-voltage generator, the multiplexer, and the voltage-controlled ramp generator. The CCM and DCM control-voltage generators receive the load information Vsen from the load current sensor and generate the corresponding control voltage, i.e., VCCM and VDCM. The VCCM and VDCM are then selected to be the voltage-controlled ramp generator input Vctrl by the multiplexer, which is controlled by the CCM/DCM flag VZ. Accompanied by the swing-limited voltage VH and VL in the voltage-controlled ramp generator, the Vctrl determines the charging current of the capacitor Cramp and generates the ramp signal Vramp. The generated Vramp and the clock signal clk are used to compensate the current loop of the current-mode control and synchronize the switching DC-DC converter, respectively. In DCM operation, the load information signal Vsen is converted to a current IS by the voltage-controlled current source consisting of OP1, MDCM and RDCM. The current IS is mirrored by the Mchg and thus determines the charging current of the capacitor Cramp. The generated frequency of the compensation ramp Vramp and the synchronous signal clk can be expressed as

Fig. 5. Schematic of the EOF generator.

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fSW =

( W / L ) Mchg V sen × , R DCM C ramp ( V H - V L ) ( W / L ) Mp1

(1)

where (W/L)Mchg and (W/L)Mp1 are the aspect ratios of Mchg and MP1, respectively. The trickle current induced by the Mtrickle is used to maintain a low switching frequency when the converter’s load is removed, i.e., Vsen is zero. As for CCM operation, the VCCM control voltage is determined by a weighted summer consisting of OP2 and the resistors R1~R4. The Vctrl in CCM, which can be written as

V ctrl = R1 + R 2 R1 ? R3 ? R2 R4 (2) ×? ? R + R × V sen + R + R × Vb 2 ÷ - R × Vb1 , ÷ 4 3 4 1 è 3 ?

will increase as the load current increases so that the generated switching frequency decreases as the load current increases. Vb1 and Vb2 are selected to generate Vctrl so that the fSW v.s. ILoad curve for CCM in Fig. 4 can be well-fitted. Vb1 is generated by a resistor string composed of Rb11 and Rb12 so that Vb1 is proportional to VIN. By using the internal node vbp of Fig. 13 and a simple unity gain buffer, Vb2 is generated. Since vbp is generated by the constant-gm bias circuit, Vb2 is proportional to VIN. Therefore, Vb1 and Vb2 introduce the input voltage information to generate the supply-dependent switching frequencies for our requirement. Hence, the solid line in Fig. 3(a) can be generated by the circuit shown in Fig. 5. If the generated frequency deviates within 20% from the curve in Fig. 4 due to

Fig. 6. The load current pattern for EMI verification.

process variation, the efficiency improvement in DCM and CCM may be degraded by up to 3% and 0.2%, respectively. The PWM frequency of a DC-DC converter is the frequency of the major EMI noise source. In general, this frequency is in the conducted EMI regulation’s frequency range, i.e., 450kHz to 30MHz. For conventional fixed-frequency PWM, significant tones will occur on the spectrum at the switching frequency and its harmonics. An effective EMI reduction technique for the applications without EMI filters is to modulate the switching frequency [8][9]. In practical applications, the load current of a DC-DC converter is time-varied. Since the EOF control varies the switching frequency with load current changes, the change of the switching frequency will spread-out the harmonic power so that no significant EMI frequency exists. As an example, Fig. 6 shows a time-domain load current pattern, while Figs. 7(a) and 7(b) illustrate the resultant spectrum with the conventional fixed-frequency PWM and EOF control, respectively. Compared with the fixed-frequency PWM, the resultant power density of the switching frequency’s tone of around 1.13MHz can be reduced by 6dB with the EOF control. In conventional current-mode control, a compensation ramp is added with the sensed current signal to prevent the converter from sub-harmonic oscillation [6]. The stability of a DC-DC converter is related to a slope-compensation parameter mc=1+(SE/SN) [10], where the SE and SN are the slope of the compensation ramp’s and sensed inductor current’s signal, respectively. Since the EOF generator varies the switching frequencies according to the load currents and input voltages, the compensation ramp’s slopes, i.e., the slopes of Vramp, are also varied. Therefore, the loop stability with the EOF control should be reconsidered by expressing the compensation ramp’s slope SE with VIN and rewriting the slope-compensation parameter as K × V IN × fSW K × L × f SW (3) ? mc = 1 + , = 1+ V IN - VOUT 1 - d1 L where K is between 0 and 1. By replacing mc with mc’ in (3), the loop transfer function of the current-mode DC-DC converter with the EOF control can be obtained. The pole-zero locations of the compensator can thus be designed accordingly to optimize the loop’s bandwidth and phase margin. III. THE RECONFIGURABLE COMPENSATION For a current-mode DC-DC converter, general proportionalintegration (PI) compensation is employed and can be realized by a conventional Type-II compensator [11], as in Fig. 8. In this section, a reconfigurable compensation is proposed. Compared to the conventional fixed Type-II compensator, the reconfigurable compensator can reduce the output voltage variation over the load range and shorten the transient time from CCM to DCM. The reconfigurable compensator is shown in Fig. 9(a) while its control for the transmission gates TG1, TG2 and TG3 is given in Fig. 9(b). The compensator can be reconfigured to either a typical Type-II compensator for CCM or an inverting amplifier

Fig. 7. Output spectrum for (a) fixed-frequency and (b) EOF control.

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Fig. 8. Typical Type-II compensator.

Fig. 9. (a) The reconfigurable compensator and (b) its switch control.

for DCM. The DC gains of Verr/VFB in CCM and DCM, denoted as ACCM and ADCM, respectively, are equal to the OPAMP’s open-loop gain and the resistor ratio R2/R11, respectively. To illustrate the advantage of this design, Fig. 10 plots the load regulation curve with the conventional compensation and the proposed reconfigurable compensation. For a conventional compensation with a specific DC gain, the output voltage variation is denoted as ΔVfix. The compensation with higher DC gain results in smaller ΔVfix, as plotted with the dashed line, than that with lower DC gain, as plotted with the dash-dot line. The idea of the proposed reconfigurable compensation is to reduce the ΔVfix by lowering the DC gain of VFB/Verr in DCM. As the solid line in Fig. 9 shows, the output voltage variation with reconfigurable compensation ΔVrec is less than ΔVfix. The voltage variation at the DCM/CCM boundary ΔV can be expressed as ACCM - A DCM (4) × V ref , DV @ ACCM × A DCM × b 2 where β is the feedback factor from the converter’s output VOUT to the compensator’s input VFB. Since ΔVrec is the maximum of

Fig. 11. Transient waveforms for transient from CCM to DCM with conventional Type-II compensators and reconfigurable compensation.

Fig. 10. The load regulation with different DC gain for the error amplifier.

the voltage variations at DCM, CCM and DCM/CCM boundary, the ADCM, ACCM, and the difference between ACCM and ADCM, should be appropriately selected to further reduce ΔVrec. Besides load regulation, the reconfigurable compensation can also improve the transient response for the converter’s operation from CCM to DCM. The transient response from CCM to DCM can be dominated by the discharging time of the output capacitor, as will be described in the next paragraph. For DCM to CCM transient, the compensator will be changed to a Type-II configuration once the CCM/DCM flag VZ is changed. The loop transfer function will become the conventional current-mode control with Type-II compensation. The transient response of the converter can thus perform adequate dynamic response [6]. Therefore, this design focuses on improving the transient from CCM to DCM. Fig. 11 illustrates and compares the typical waveforms for the conventional and the reconfigurable compensation. The transient progress of the conventional design can be divided into four regions. Region I indicates that the converter is in CCM. Region II starts from varying the load current and ends when the error amplifier output voltage is decreased such that the PWM duty is fully turned-off. Within this region, the response of the error amplifier output voltage is determined by the loop transfer function. Though the inductor current is gradually decreased, it still charges the output capacitor until it is less than the load current. In region III, the PWM duty is fully turned-off such that the energy stored in the output capacitor can be discharged by the load current. Subsequently, the transient will gradually terminate in region IV, which is in DCM. As for reconfigurable compensation, the transient progress is also divided into four regions. Within region II’, once the

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> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < inductor current degrades to zero, which makes VZ to be pulled to “0”, as shown in Fig. 11, the compensator configuration will be changed from a Type-II compensator to an inverting amplifier. The degraded DC gain lowers the error amplifier’s output voltage level suddenly and then the inverting amplifier configuration enlarges the effective loop bandwidth. Based on these two reasons, the error amplifier output voltage can achieve its final value faster than that with a conventional compensator. Since the transient progress enters region III’ with faster speed, the inductor current’s excess charging time for the output capacitor in region II’ can be shortened. The transient time from CCM to DCM is thus shortened. The design of the resistors and the capacitors for a Type-II compensator is explained as follows. The control-to-output transfer function of the current-mode DC-DC converter can be rewritten as [10]

VO ( s ) R = × VC ( s ) R i × 1 1+ RT SW L s 2p f ZC × (m c D' - 0 .5 ) 1 + s 2p f PC 1+ ? ÷ ÷ ? ,

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Fig. 12. The pole-zero locations of the Type-II compensator, the control-to-output transfer function, and the resultant loop transfer function, respectively.

(5)

? s ?1 + ? 2p f PC 2 è

1 ? ? s ÷ × ?1 + ÷ ? 2p f PC 3 ? è

where R, TSW, mc, and D’ are the load resistance, the switching period, the compensation slope, and the turned-off duty-cycle, respectively. fPC and fZC are T 1 é 1 ù (6) × + SW (mc D' -0.5)ú , fPC = 2p ê CR LC ? ? and 1 (7) fZC = , 2p × C × rC respectively. As revealed in Fig. 12, the pole fPC and the zero fZC of the current-mode control-to-output transfer function are cancelled by the zero fZ1 and the pole fP2 of the Type-II compensator, respectively. The loop gain transfer function has a pole fP1 contributed by the Type-II compensator while the double poles fPC2 and fPC3 are far away from fP1. Considering the finite gain and limited bandwidth effects of the OPAMP, the compensator’s transfer function can be expressed as - A 0 × (1 + s / s Z 1 ) V err (s ) (8) = = V FB (s ) ? s ?? s ?? s ? ÷ ÷? 1 + ?1 + ÷? 1 + ? s P 1 ÷? s P 2 ÷? sP 3 ÷ è ?è ?è ? A0 × (1 + sC1 R 2 ) , ?? ? ?? s s s ? ? ÷ ?1 + ÷ ? 1 A R (C + C ) ÷?1 + 1 R (C // C ) ÷?1 + A w ÷ ÷? 0 1 1 2 ?è 2 1 2 ?è 0 p ? è where A0 and ωp are the DC gain and the dominant pole of the OPAMP, respectively. The RC value of the Type-II compensator can thus be designed. The schematics of the OPAMP used in Fig. 9(a) and its bias circuit are shown in Figs. 13(a) and 13(b), respectively. The folded-cascode architecture, instead of two-stage, is used for low controller power loss. It should be mentioned that the

Fig. 13. The schematic of (a) the compensator OPAMP and (b) its bias circuit.

voltage vbp in Fig. 13(b) is connected to Vb2 in Fig. 5. When the pole-zero locations of the compensator are determined, the products of resistances and capacitances are fixed. With a set of pole-zero locations, each resistance and capacitance can be expressed with a variable X and a coefficient. By setting one of the passive components, say the resistor R2, to be X(MW), the resistance R1, and the capacitances C1 and C2 can be expressed as PX(MW), Q/X(pF), and M/X(pF), respectively. The total area A(X) of the passive components can then be expressed as a function of X Q+M (9) A( X ) = (1 + P ) × X × AR + × AC , X

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> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < where AR and AC is the unit area of the resistor and the capacitor, respectively. The minimum A(X) can be obtained when dA(X)/dX=0. Since the passive components are on-chip, 30% of process variation is taken to guarantee the loop stability. IV. CIRCUIT IMPLEMENTATION OF THE CURRENT-MODE DC-DC CONVERTER The block diagram of the monolithic current-mode DC-DC converter implemented in this paper is shown in Fig. 14. The converter is fabricated in a 0.35μm 3.3V CMOS process. The power MOSFETs, MP and MN, are driven by the gate-driver with internal dead-time control. The zero current detector (ZCD) is used to detect if the inductor current is flowing back into the converter in DCM. The CCM/DCM flag VZ generated by ZCD is required by the EOF generator and the PLCS. When the converter is operating in CCM, the flag VZ is high, while VZ is low in DCM operation. The inductor current is sensed by the proposed piecewise-linear current sensor (PLCS). The sensed information Vsen is added with the compensation ramp Vramp generated by the EOF generator. The EOF generator receives the load current information to generate the synchronous clock clk with the optimal frequencies. To minimize the external components, the compensator’s passive components are all implemented on the chip. The building blocks of the current-mode DC-DC converter in Fig. 14 are all integrated into the monolithic IC. In the following, the detailed circuit design will be divided into two subsections and will be elaborated respectively. A. Piecewise-Linear Current Sensor (PLCS) A conventional current sensor is shown in Fig. 15. The size of the sensing MOSFET MPS is 1/N of that of the power MOSFET MP, thus resulting in the current scaling ratio of N. The sensed current can be transformed into the voltage signal Vsen by the resistor Rsen. In a conventional design, the current scaling ratio N is fixed in all load ranges [12][13]. The sensed current will be increased as the inductor current is increased, and thus the controller power loss will also be larger. As shown in Fig. 16(a), the PLCS uses two sensing ratios in light and heavy loads. A large scaling ratio N’ is used for heavy loads while N in the conventional design is used for light loads.

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Fig. 15. Conventional current senor.

Fig. 16. The relationship between (a) the inductor current (IL) vs. the sensed current (Isen), and (b) the Isen -to- Vsen conversion with respect to IL..

Fig. 14. The block diagram for the current-mode DC-DC converter.

Hence, the sensed current Isen won’t be too small under light load condition so that the coupling noises are negligible. As for heavy load condition, the sensed current is reduced due to the large scaling ratio N’ and the reduced power loss can be expressed as I N?- N (10) DP = V DD × load × , N N? where N’=10000 and N=1000 in this design. Thus, the saved power losses ΔP is 3mW for ILoad=1A. As shown in Fig. 16(b), with the conventional and the proposed PLCS, the Vsen/Isen ratios are Rsen1 and Rsen1+Rsen2 for DCM and CCM, respectively. Vsen/IL is thus the same for the PLCS in both DCM and CCM operation, so that the resultant current-loop gain is not changed. A detailed schematic of the proposed current sensor is shown in Fig. 17. The MPS1 and MPS2 are parallel-combined and used to generate the sensed current IP to implement the different scaling ratios in CCM and DCM. The MPS2 controlled by the switch SW1 will be activated when the converter is operated in CCM.

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Fig. 17. Detailed schematic for the PLCS.

The control signals for SW1, SW2 and SW3 are provided by the CCM/DCM flag VZ generated by the ZCD circuit. When the MN is turned on, the current through MNS will pass through MP1. By the closed loop consisting of OPSN, MN2 and MP2, the current through MP1 can be mirrored to MNS1 and MNS2. Similar to MPS2, MNS2 is activated when the converter works in CCM. The resistors Rsen1 and Rsen2 are used to convert the summed currents of IP and IN to a voltage VSUM. The discontinuity of IL/Isen at the CCM and DCM boundary can be eliminated by designing the Rsen1/Rsen2 ratio to be N/(N’-N). Therefore, the ratio of Vsen/IL for the PLCS can be kept the same in CCM and DCM. The OPAMP OPSP is used for equating the drain-source voltages of MP and MPS1. In addition, the other OPAMP OPSN is used for equating the drain-source voltages of MN and MNS. The RF and CF are used to filter out the glitch which occurs when the power MOSFETs MP and MN are switched. The sensed inductor current in voltage form when MP is turned-on, Vsen,p, is synchronously generated from Vsen by SW4, which is controlled by Vgp. B. Other Building Blocks The other necessary building blocks presented in this subsection are the zero-current detector (ZCD) and the gate-driver with built-in dead-time generation, as shown in Fig. 18 and Fig. 19, respectively. The zero-current detector (ZCD) is used to turn-off the power NMOSFET MN when the inductor current is

Fig. 19. Gate-driver with built-in dead-time generation and power MOSFET.

flowing back into the converter in DCM. This mechanism can avoid unnecessary power loss. However, the ringing phenomenon, which is caused by current injecting into the resonant tank formed by the inductor L and parasitic capacitance at node VX, could lead to a misjudgment of the comparator. To avoid this problem, an error-masking circuit composed of the delay-line and AND-gate is inserted. The generated zero-current signal VZ, which is synchronized by a D flip-flop with the clock signal clk in Fig. 5, can be used as the CCM/DCM flag since the zero-current will only occur in DCM. The on-resistances of the power MOSFETs are about 0.2W. The gate driver is designed with built-in dead-time determined by delay-line A and delay-line B. An appropriate stage ratio for driving the power MOSFETs is also designed.

V. MEASUREMENT RESULTS A photograph of the implemented chip, fabricated in 0.35μm 3.3V CMOS process, is shown in Fig. 20. The chip area is 0.97mm2. The measurement conditions for the implemented converter in this section are given in Table II unless otherwise specified. The steady-state waveforms shown in Figs. 21(a) and 21(b) illustrate that the converter can normally operate in both light

Fig. 18. Zero-current detector (ZCD) with error-masking.

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Fig. 20. Chip photograph.

Fig. 23. (a) The measured efficiencies and (b) the reduced power losses versus load currents.

Fig. 21. The measured steady-state waveform under (a) light and (b) heavy load conditions.

and heavy loads with a load range of 0~1.05A. The switching frequencies for light and heavy loads are different since the EOF control is enabled. Fig. 22 reveals that the measured switching frequencies well fit the line for VIN=3.3V in Fig. 4. The measured efficiencies versus load currents are shown in Fig. 23(a). Compared with fixed-frequency control, the proposed EOF control improves efficiencies by 16% and 1% for light and heavy loads, respectively. As can be seen in Fig. 23(b), the reduced power loss achieves 16mW and 15mW in both the light and heavy loads, respectively. Fig. 24 illustrates the comparison between the load regulation curves for reconfigurable compensation and fixed Type-II compensation. The bent load regulation curve of reconfigurable

Fig. 22. Comparison between the measured and expected switching frequencies versus load currents.

Fig. 24. Measured load regulation for the reconfigurable and Type-II compensators.

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Fig. 25. Measured transient waveforms with (a) fixed Type-II and (b) reconfigurable compensators. The load current change is from 280mA to 140mA.

Fig. 26. (a) DCM-to-CCM, and (b) CCM-to-DCM transient response with 1A load current step (from 1050mA to 50mA).

compensation reduces the output voltage variation. In this work, a moderate OPAMP gain is designed for proof of the concept. The output voltage variation can further be reduced with a larger OPAMP gain. The measured transient responses of fixed Type-II and reconfigurable compensators are shown in Figs.

25(a) and 25(b), respectively. In Fig. 25, the fixed-frequency control is used to correctly identify the effectiveness of the reconfigurable compensation. As revealed in Fig. 25, the transient response is about 12μs faster and the output voltage variation is reduced by 40mV. Figs. 26(a) and (b) illustrate the transient response with the load current step of 1A. The DCM-to-CCM and CCM-to-DCM transient times are 85μs and 140μs, respectively. Fig. 27 shows the measured transient waveforms when the load current changes between 100mA and 150mA. Under this condition, the converter is operated around the peak switching frequency. The start and the end of the transient are marked with tST and tEND, respectively. During the transient, the change of the switching frequency can be observed when the CCM/DCM flag is changed at tZCD. The measured performance of the DC-DC converter is summarized in Table III, and comparisons with other published state-of-the-art converters in 0.35μm CMOS process is shown in Table IV. The converter efficiencies in both light and heavy loads are improved with the optimal switching frequencies in a range of 200kHz ~ 2MHz, while other works are with fixed-frequency in heavy load. Furthermore, the converter achieves the highest efficiency with the smallest area. VI. CONCLUSION The monolithic current-mode DC-DC buck converter implemented in this paper has achieved a high efficiency of 96.3% with only a 0.97mm2 chip area. These results demonstrate that the three proposed methods are suitable for cost-effective design and low-power applications, especially in

Fig. 27. Measured transient waveforms with the current changes from (a) 100mA to 150mA and (b) 150mA to 100mA.

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TABLE IV COMPARISONS WITH STATE-OF-THE-ART CONVERTERS IN 0.35UM CMOS PROCESS References Process (μm) Chip Area (mm2) Efficiency Improvement @ Light Load Efficiency Improvement @ Heavy Load Maximum Efficiency (%) Load Range(mA) Inductor (μH) Capacitor (μF) Switching Frequency (Hz) Published Issue [3] 0.35 3.2 (active) Yes Yes 95@0.3A 500 4.7 4.7 1M IEEE JSSC, 11/2007 [14] 0.35 1.4 Yes No 90@0.2A 500 2.2 2.2 250k/500k/ 1M/2M IEEE ISSCC, 02/2008 [15] 0.35 1.815 No No 96@0.26A 800 4.7 9.4 1M IEEE JSSC, 11/2007 [4] [5] [16] 0.35 2.89 No No 93@0.15A 500 4.7 4.7 800k IEEE PE, 04/2010 [17] 0.35 1.32 Yes No 91@0.1A 180 1 6.8 ~500k IEEE CAS-II, 03/2010 [18] 0.35 1.674 Yes No 94.5@N/A 800 4.7 10 850k IEEE JSSC, 04/2008 This work 0.35 0.97 Yes Yes 96.3@0.13A 1050 4.7 10 200k~2M

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portable devices. The proposed EOF control can be applied to different converter types, such as boost or buck-boost, for efficiency optimization and EMI reduction, while the PLCS can be employed in other applications with current sensors.

TABLE III MEASUREMENT SUMMARY OF THE DC-DC CONVERTER Parameters Input voltage range Output voltage range Line regulation Load regulation Load current range Switching frequency Output ripple Maximum Efficiency Transient time L=4.7μH, C=10μF (50mA←→1050mA) CCM-to-DCM DCM-to-CCM VIN = 2.4V VIN = 3.6V VIN =2.4V ~ 3.6V ILoad = 200mA VIN = 3.3V Conditions Value 2.4V ~ 3.6V 0.7V ~ 2.0V 0.9V ~ 3.3V ±1.7 %/V ±4.0 %/A 0~1050mA 200kHz ~ 2MHz 16mV 96.3% 140μs 85μs

[6] [7] [8]

[9]

[10] [11] [12] [13] [14] [15]

ACKNOWLEDGMENT The authors would like to acknowledge fabrication support provided by National Chip Implementation Center (CIC), Taiwan. REFERENCES

[1] [2] X. Zhou, M. Donati, L. Amoroso, and F. C. Lee, "Improved light-load efficiency for synchronous rectifier voltage regulator module", IEEE Trans. Power Electron., vol. 15, no. 5, pp.826-834, Sep., 2000. B. Sahu, G. A. Rincón-Mora, “An accurate, low-voltage, CMOS switching power supply with adaptive on-time pulse-frequency modulation (PFM) Control”, IEEE Tran. Circuits and Systems-I., vol. 54, no.2, pp.312-321, Feb., 2007. H. W. Huang, K. H. Chen, and S. Y. Kuo, “Dithering skip modulation, width and dead time controllers in highly efficient DC-DC converters for system-On-chip applications”, IEEE J. Solid-State Circuits, vol. 42, no. 11, pp.2451- 2465, Nov., 2007.

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P. Sandri, M. R. Borghi, and L. Rigazio, “DC-to-DC converter functioning in a pulse-skipping mode with low power consumption and PWM inhibit,” U.S. Patent 5,745,352, Apr., 28, 1998. Wisam Al-Hoor, Jaber A. Abu-Qahouq, L. Huang, and I. Batarseh, “Adaptive variable switching frequency digital controller algorithm to optimize efficiency”, in Proc. IEEE Int. Symp. Circuits and Systems, pp.781-784, May 2007. C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan., 2004. X. Zhou, Thomas G. Wang and Fred C. Lee, “Optimizing design for low voltage DC-DC converters”, in Proc. IEEE Applied Power Electron. Conf., 1997, pp. 612-616. F. Mihaliˇc, and D. Kos, “Reduced conductive EMI in switched-mode DC–DC power converters without EMI Filters: PWM versus randomized PWM”, IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1783-1794, Nov., 2006. K. K. Tse, S. H. Chung, S.Y. Hui, and H. C. So, “Analysis and spectral characteristics of a spread-spectrum technique for conducted EMI suppression,” IEEE Trans. Power Electron., vol. 15 no.2, pp.399-410, Mar., 2000. R. B. Ridley, ”A new, continuous-time model for current-mode control”, IEEE Trans. Power Electron., vol. 6, no. 2, pp.271-280, Apr., 1991. A. I. Pressman, K. H. Billings, and T. Morey, Switching Power Supply Design, New York: McGraw-Hill, 2009, ch. 12. H. P. Forghani-Zadeh and G. A. Rincon-Mora, "Current-sensing techniques for DC-DC converters," in Proc. IEEE Midwest Symp. Circuits and Syst., pp. II-577 – II-580, 2002. W. H. Ki, "Current sensing technique using MOS transistors scaling with matched bipolar current sources", US Patent 5,757,174, May 26, 1998. T. Y. Man, Philip K. T. Mok, and M. Chan “An auto-selectable-frequency pulse width modulator for buck converters with improved light-load efficiency”, in IEEE ISSCC Dig Tech. Papers, pp.440-441, Feb., 2008. Patrick Y. Wu and Philip K. T. Mok, “A monolithic buck converter with near-optimum reference tracking response using adaptive-outputfeedback”, IEEE J. Solid-State Circuits, vol 42, no. 11, pp. 2441-2450, Nov., 2007. Y. H. Lee, S. J. Wang, and K. H. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitor”, IEEE Trans. Power Electron., vol. 25, no. 4, pp. 829-838, Apr., 2010. H. Lee and S. R. Ryu, “An efficiency-enhanced DCM buck regulator with improved switching timing of power transistors”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 238-242, Mar., 2010. F. Su, W. H. Ki, and C. Y. Tsu, “Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications”, IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 815-822, Apr., 2008

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Jia-Ming Liu (S’10) was born in Taichung, Taiwan, in 1980. He received the B.S. degree in electrical engineering from National Cheng-Kung University, Tainan, Taiwan, in 2002. He is currently working toward the Ph.D. degree at the same university. From 2003 to 2005, he was initially a Design Engineer and then a Project Leader with Advanic Technologies, Tainan, participating in the design and development of digital class-D audio amplifiers. Due to a company merger, he was with Elite Semiconductor Memory Technology in 2006, working on the design of analog class-D audio amplifiers. His main research interests include power management ICs, class-D audio amplifiers, and delta-sigma modulators.

12

Pai-Yi Wang (S’10) was born in Taichung, Taiwan, in 1985. In 2007 and 2009, he received the B.S. and M.S. degree in electronic engineering from Fu-Jen Catholic University, Xinzhuang, Taiwan, and National Cheng Kung University, Tainan, Taiwan, respectively. He is currently working toward the Ph.D. degree in National Cheng Kung University. His current research interests include power management circuits, mixed-signal circuit designs, and analog integrated circuit designs.

Tai-Haur Kuo (S’87–M’10) was born in Tainan, Taiwan, in 1960. He received the B.S. degree in electrical engineering from National Cheng Kung University (NCKU), Tainan, Taiwan, in 1982, and the M.S. and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, in 1988 and 1990, respectively. From 1984 to 1986, he was an Analog IC Designer at the Industrial Technology and Research Institute, Hsinchu, Taiwan, where he received an Annual Personal Special Contribution Award in 1986. In 1989, he worked with the Aerospace Technology Center of Allied-Signal, Columbia, MD, performing research work on the design of monolithic ultrahigh-speed RTD-HEMT ICs. From 1990 to 1992, he was initially a Design Engineer with Integrated Device Technology, Santa Clara, CA, and then a Project Manager with the Industrial Technology and Research Institute. Since 1992, he has been with the Department of Electrical Engineering, NCKU, where he is currently Professor. In 2004, he took three years’ leave from NCKU, during which time he joined Advanic Technologies, Tainan, Taiwan, as its President. In 2005, due to a company merger, he became a Vice-President of Elite Semiconductor Memory Technology. He then returned to NCKU in 2007. His current research interests include data converters, class-D audio amplifiers, solar/wind energy related circuits, and power management ICs. He holds 14 U.S. patents.

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