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Freescale Automotive EB659


Freescale Semiconductor Engineering Bulletin

EB659 Rev. 1, 11/2006
Because of an order from the United States International Trade Commission, BGA-packaged product lines and pa

rt numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5500 Family Overview
by: Randy Dees 32-bit Automotive Applications Ray Marshall TSPG Powertrain Systems

1

Introduction

Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MPC5500 Roadmap. . . . . . . . . . . . . . . . . . . . . . 2 MPC5533 Block Diagram . . . . . . . . . . . . . . . . . 3 MPC5534 Block Diagram . . . . . . . . . . . . . . . . . 4 MPC5553 Block Diagram . . . . . . . . . . . . . . . . . 5 MPC5554 Block Diagram . . . . . . . . . . . . . . . . . 6 MPC5551 Block Diagram . . . . . . . . . . . . . . . . . 7 MPC5565 Block Diagram . . . . . . . . . . . . . . . . . 8 MPC5566 Block Diagram . . . . . . . . . . . . . . . . . 9 MPC5567 Block Diagram . . . . . . . . . . . . . . . . 10 MPC5500 Family Comparison . . . . . . . . . . . . . . 11 MPC5500 Family Memory Map . . . . . . . . . . . . . 12 Package Options. . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 416 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 17 4.2 324 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 20 4.3 208 MAP BGA Ball Map . . . . . . . . . . . . . . . 21 Appendix A: Revision History

The MPC5554 microcontroller (MCU) was the first member of the MPC5500 family of next generation microcontrollers based on Power Architecture technology initially designed for next generation automotive powertrain applications. More devices in the family have been introduced, including the MPC5533, MPC5534, MPC5553, MPC5561, MPC5565, MPC5566, and MPC5567 (all included in this document). The host processor core of the MPC5500 family devices is compatible with the Power Architecture technology. It is 100 percent user-mode compatible (with floating point library) with the PowerPC ISA. This core has instructions beyond the classic PowerPC ISA, including digital signal processing (DSP) instructions. The MPC553x and MPC556x devices include the variable length encoding (VLE) option for improved code density.

2 3 4

Freescale Semiconductor, Inc., 2006. All rights reserved.

Introduction

2 Performance/Integration 1999

MPC500 Family

MPC555 MPC565 MPC561 MPC563

2005 MPC5534 MPC5553 Availability

MPC5554

Figure 1. MPC5500 Roadmap

MPC5500 Family Overview, Rev. 1 MPC5533 2006 MPC5510 Family

MPC5500 Family

MPC5565 MPC5561

MPC5566

MPC5567

MPC557x

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Introduction

e200z3 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Load/Store Unit

Interrupt Controller

FMPLL

Nexus

Memory Management Unit Calibration Bus

eDMA 32 Channels

Master

Master

External Master Interface Master

External Bus Interface

Master Crossbar Switch (XBAR) Slave Slave

Slave Boot Assist Module

Flash 768-Kb

System/Bus Integration

Slave

Slave

SRAM 48-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

DSPI

DSPI

eTPU (32 Ch)

eSCI

2.5-Kb Data RAM 12-Kb Code RAM

eQADC ADCi ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z3 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 2. MPC5533 Block Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 3

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5533

Introduction

1.5V Regulator Control

Signal Processing Engine Integer Execution Unit Multiply Unit JTAG

64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit

Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Load/Store Unit

MPC5534

Interrupt Controller

FMPLL

Nexus Interface

Nexus

Memory Management Unit Calibration Bus

eDMA 32 Channels

Master

Master

External Master Interface Master

External Bus Interface

Master Crossbar Switch (XBAR) Slave Slave

Slave Boot Assist Module

Flash 1-Mb

System/Bus Integration

Slave

Slave

SRAM 64-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

eTPU (32 Ch)

12-Kb Code RAM

eMIOS (24 Ch)

eSCI

eSCI

2.5-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z3 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 3. MPC5534 Block Diagram

MPC5500 Family Overview, Rev. 1 4 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

e200z3 Core

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Load/Store Unit Memory Management Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Unified 8-Kb Cache

Interrupt Controller

FMPLL

Nexus

eDMA 32 Channels

Fast Ethernet Controller Master

Master

External Master Interface Master

External Bus Interface

Master

Crossbar Switch (XBAR) Slave Slave Slave Boot Assist Module

Flash 1.5-Mb

System/Bus Integration

Slave

Slave

SRAM 64-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

eSCI

eTPU (32 Ch)

12-Kb Code RAM

eMIOS (24 Ch)

eSCI

2.5-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 4. MPC5553 Block Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 5

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5553

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Unified 32-Kb Cache Load/Store Unit

Interrupt Controller

FMPLL

Nexus

Memory Management Unit

eDMA 64 Channels

Master

External Master Interface Master

External Bus Interface

Master Crossbar Switch (XBAR) Slave Slave

Slave Boot Assist Module

Flash 2-Mb

System/Bus Integration

Slave

Slave

SRAM 64-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

DSPI

eTPU (32 Ch)

16-Kb Code RAM

eTPU (32 Ch)

eMIOS (24 Ch)

eSCI

eSCI

3-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 5. MPC5554 Block Diagram

MPC5500 Family Overview, Rev. 1 6 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5554

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Load/Store Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Unified 32-Kb Cache Memory Management Unit

Interrupt Controller

FMPLL

Nexus

Calibration Bus eDMA 32 Channels External Master Interface Master External Bus Interface

Master

FlexRay

Master

Master Crossbar Switch (XBAR)

Slave

Slave

Slave Boot Assist Module

Flash 1-Mb

System/Bus Integration

Slave

Slave

Slave

SRAM 192-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

eQADC ADCi ADC ADC AMUX

eMIOS (24 Ch)

PDI

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 6. MPC5561 Block Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 7

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5561

DSPI

DSPI

eSCI

eSCI

eSCI

eSCI

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Load/Store Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Unified 8-Kb Cache Memory Management Unit

Interrupt Controller

FMPLL

Nexus

Calibration Bus eDMA 32 Channels External Master Interface Master Crossbar Switch (XBAR) Slave Slave Slave Boot Assist Module External Bus Interface

Master

Master

Flash 2-Mb

System/Bus Integration

Slave

Slave

SRAM 64-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

eTPU (32 Ch)

12-Kb Code RAM

eMIOS (24 Ch)

eSCI

eSCI

2.5-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 7. MPC5565 Block Diagram

MPC5500 Family Overview, Rev. 1 8 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5565

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Load/Store Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Unified 32-Kb Cache Memory Management Unit

Interrupt Controller

FMPLL

Nexus

Calibration Bus eDMA 64 Channels Fast Ethernet Controller Master Crossbar Switch (XBAR) Slave Slave Slave Boot Assist Module External Master Interface Master External Bus Interface

Master

Master

Flash 3-Mb

System/Bus Integration

Slave

Slave

SRAM 128-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

DSPI

eTPU (32 Ch)

20-Kb Code RAM

eTPU (32 Ch)

eMIOS (24 Ch)

eSCI

eSCI

4-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 8. MPC5566 Block Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 9

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5566

Introduction

e200z6 Core
1.5V Regulator Control Signal Processing Engine Integer Execution Unit Multiply Unit JTAG Nexus Interface 64-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Load/Store Unit Core Timers Unit (FIT, TB, DEC) Exception Handler Variable Length Encoded Instruction Unified 8-Kb Cache Memory Management Unit

Interrupt Controller

FMPLL

Nexus

Calibration Bus eDMA 32 Channels Fast Ethernet Controller Master External Master Interface Master External Bus Interface

Master

FlexRay

Master

Master

Crossbar Switch (XBAR) Slave Slave Slave Boot Assist Module

Flash 2-Mb

System/Bus Integration

Slave

Slave

SRAM 64-Kb

Peripheral Bridge A (PBRIDGE_A)

Peripheral Bridge B (PBRIDGE_B)

FlexCAN

FlexCAN

FlexCAN

FlexCAN

FlexCAN

DSPI

DSPI

DSPI

eTPU (32 Ch)

12-Kb Code RAM

eMIOS (24 Ch)

eSCI

eSCI

2.5-Kb Data RAM

eQADC ADCi ADC ADC AMUX

LEGEND MPC5500 Device Module Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM e200z6 Core Component Acronyms DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer

Figure 9. MPC5567 Block Diagram

MPC5500 Family Overview, Rev. 1 10 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5567

MPC5500 Family Comparison

2

MPC5500 Family Comparison
Table 1. MPC5500 Family Members
MPC5500 Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 e200z3 Yes None 16 entry 4x5 Class 3+ (NZ3C3) 48 Kbyte Main Array Shadow Block 768 Kbyte5 1 Kbyte 16-bit 24 Yes 32 channel None 1 eSCI_A eSCI_B eSCI_C eSCI_D Yes No No No 2 64 buf No 64 buf No No 2 DSPI_A DSPI_B DSPI_C DSPI_D No No Yes Yes 0 channel
7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Power Core Variable Length Instruction Support Cache Memory Management Unit (MMU) Crossbar Core Nexus SRAM Flash

e200z3 Yes None 16 entry 4x5 Class 3+ (NZ3C3) 64 Kbyte 1 Mbyte5

e200z6 No 8 Kbyte Unified1 32 entry 4x5 Class 3+ (NZ6C3) 64 Kbyte 1.5 Mbyte6 1 Kbyte 32 bit7

e200z6 No 32 Kbyte Unified2 32 entry 3x5 Class 3+ (NZ6C3) 2 Mbyte6 1 Kbyte 32 bit7

e200z6 Yes 32 Kbyte Unified3 32 entry 4x6 Class 3+ (NZ6C3) 1 Mbyte6 1 Kbyte 32-bit7 268 Yes 32 channel Class 3 4 Yes Yes Yes Yes 3
9

e200z6 Yes 8 Kbyte Unified1 32 entry 3 x5 Class 3+ (NZ6C3) 2 Mbyte6 1 Kbyte 32-bit7 268 Yes 32 channel Class 3 2 Yes Yes No No 39 64 buf 64 buf 64 buf No No 3 No Yes Yes Yes 24 channel
4

e200z6 Yes 32 Kbyte Unified3 32 entry 4x5 Class 3+ (NZ6C3) 3 Mbyte6 1 Kbyte 32-bit7 268 Yes 64 channel Class 3 2 Yes Yes No No 49 64 buf 64 buf 64 buf 64 buf No 4 Yes Yes Yes Yes 24 channel

e200z6 Yes 8 Kbyte Unified1 32 entry 5x5 Class 3+ (NZ6C3) 2 Mbyte6 1 Kbyte 32-bit7 268 Yes 32 channel Class 3 2 Yes Yes No No 59 64 buf 64 buf 64 buf 64 buf 64 buf 3 No Yes Yes Yes 24 channel

64 Kbyte 192 Kbyte 64 Kbyte 128 Kbyte 80 Kbyte

1 Kbyte 16 bit7

External Bus (EBI)

Data Bus Address Bus

24 Yes 32 channel None 2 Yes Yes No No 2 64 buf No 64 buf No No 3 No Yes Yes Yes 24 channel

24 Partial 32 channel Class 3 2 Yes Yes No No 2 64 buf No 64 buf No No 3 No Yes Yes Yes 24 channel

24 No 64 channel Class 3 2 Yes Yes No No 3 64 buf 64 buf 64 buf No No 4 Yes Yes Yes Yes 24 channel

Calibration Bus Direct Memory Access (DMA) DMA Nexus Serial

Controller Area Network (CAN) CAN_A CAN_B CAN_C CAN_D CAN_E SPI

64 buf No 64 buf No No 3 No Yes Yes No 24 channel

eMIOS

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 11

MPC5500 Family Memory Map

Table 1. MPC5500 Family Members (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5500 Device eTPU eTPU_A eTPU_B Code Memory Parameter RAM Nexus Interrupt Controller Analog to Digital Converter (eQADC) ADC_0 ADC_1 Fast Ethernet Controller (FEC) FlexRay FlexRay Nexus Phase Lock Loop (PLL) Maximum System Frequency Crystal Range Voltage Regulator Controller (VRC)
12

MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 32 channel Yes No 12 Kbyte Class 3 178 channel 40 channel Yes No No No No FM 80 MHz Yes 32 channel Yes No 12 Kbyte Class 3 210 channel 40 channel Yes Yes No No No FM 80 MHz Yes 32 channel Yes No 12 Kbyte Class 3 210 channel 40 channel Yes Yes Yes
10

64 channel Yes Yes 16 Kbyte 3 Kbyte Class 3 300 channel 40 channel Yes Yes No No No FM 132 MHz Yes

0 channel No No 0 Kbyte 0 Kbyte No 231 channel 40 channel Yes Yes No Yes Class 3 FM 132 MHz Yes

32 channel Yes No 12 Kbyte 2.5 Kbyte Class 3 231 channel 40 channel Yes Yes No No No FM 132 MHz Yes

64 channel Yes Yes 20 Kbyte 4 Kbyte Class 3 329 channel 40 channel Yes Yes Yes10 No No FM 132 MHz Yes

32 channel Yes No 12 Kbyte 2.5 Kbyte Class 3 281 channel 40 channel Yes Yes Yes11 Yes Class 3 FM 132 MHz Yes

2.5 Kbyte 2.5 Kbyte 2.5 Kbyte

No No FM 132 MHz Yes

8–20 MHz 8–20 MHz 8–20 MHz 8–20 MHz 8–40 MHz 8–20 MHz 8–20 MHz 8–40 MHz

NOTES: 1 2-way associative 2 8-way associative 3 4-way or 8-way associative 4 The actual crossbar is implemented as a 5x5 crossbar with two unused ports 5 16-byte flash page size for programming 6 32-byte flash page size for programming 7 May not be externally available in some package configurations 8 Either ADDR[8:31] or ADDR[6:29] can be selected. 9 Updated FlexCAN module with optional individual receive filters 10 The FEC signals are shared with data bus pins DATA[16:31] 11 The FEC signals are shared with the calibration bus 12 Initial automotive temperature range qualification

3

MPC5500 Family Memory Map

This section describes the memory map for the MPC5500 devices discussed in this document. All addresses in the device, including those that are reserved, are identified in the tables. The addresses represent the physical addresses assigned to each IP module. Logical addresses are translated by the memory management unit (MMU) into physical addresses. Under software control of the MMU, the logical addresses allocated to IP blocks may be changed on a minimum of a 4-Kbyte boundary. Peripheral blocks may be redundantly mapped. The customer must use the MMU to prevent corruption.

MPC5500 Family Overview, Rev. 1 12 Freescale Semiconductor

MPC5500 Family Memory Map

Table 2 shows a detailed memory map.
Table 2. Detailed MPC5500 Family Memory Map
Address Range1 0x0000_0000–0x000B_FFFF 0x000C_0000–0x000F_FFFF 0x0010_0000–0x0017_FFFF 0x0018_0000–0x001F_FFFF 0x0020_0000–0x002F_FFFF 0x0030_0000–0x00FF_FBFF 0x00FF_FC00–0x00FF_FFFF 0x0100_0000–0x1FFF_FFFF 0x2000_0000–0x3FFF_FFFF 0x4000_0000–0x4000_7FFF 0x4000_8000–0x4000_BFFF 0x4000_C000–0x4000_FFFF 0x4001_0000–0x4001_3FFF 0x4001_4000–0x4001_FFFF 0x4002_0000–0x4002_FFFF 0x4003_0000–0x9FFF_FFFF 0xA000_0000–0xBFFF_FFFF Allocated Size Used Size Use Flash Array Flash Array Flash Array Flash Array Flash Array Reserved Flash Shadow Block Emulation Mapping of Flash Array External Memory SRAM Array, Standby Powered SRAM Array SRAM Array SRAM Array SRAM Array SRAM Array Reserved Parallel Digital Interface √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5532

MPC5533

MPC5534

MPC5553

MPC5554

MPC5561

MPC5565 √ √ √ √

MPC5566 √ √ √ √ √ √ √ √ √ √ √ √

768 Kbyte 768 Kbyte 256 Kbyte 256 Kbyte 512 Kbyte 512 Kbyte 512 Kbyte 512 Kbyte 1 Mbyte ~13 Mbyte 1024 bytes 496 Mbyte 512 Mbyte 32 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 48 Kbyte 64 Kbyte (<15 Gb) 512 Mbyte 1 Mbyte N/A 1024 bytes 2 Mbyte N/A 32 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 48 Kbyte 64 Kbyte N/A 256 Mbyte N/A 16 kbyte N/A 20 kbyte 48 Kbyte 28 Kbyte N/A 2.5 Kb N/A 1056 1056 N/A 3 Kbyte N/A

√ √



√ √

√ √ √

√ √ √ √

√ √

Bridge A Peripherals 0xC000_0000–0xC3EF_FFFF 0xC3F0_0000–0xC3F0_3FFF 0xC3F0_4000–0xC3F7_FFFF 0xC3F8_0000–0xC3F8_3FFF 0xC3F8_4000–0xC3F8_7FFF 0xC3F8_8000–0xC3F8_BFFF 0xC3F8_C000–0xC3F8_FFFF 0xC3F9_0000–0xC3F9_3FFF 0xC3F9_4000–0xC3F9_FFFF 0xC3FA_0000–0xC3FA_3FFF 0xC3FA_4000–0xC3FA_7FFF 0xC3FA_8000–0xC3FB_FFFF 0xC3FC_0000–0xC3FC_3FFF 0xC3FC_4000–0xC3FC_7FFF 63 Mbyte 16 kbyte 496 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 48 Kbyte 16 Kbyte 16 Kbyte 96 Kbyte 16 Kbyte 16 Kbyte Reserved Bridge A Registers Reserved FMPLL External Bus Interface (EBI) Configuration Flash Configuration Reserved System Integration Unit (SIU) Reserved Modular Timer System (eMIOS) Modular Timer System (eMIOS_B) Reserved Enhanced Time Processing Unit (eTPU) Registers Reserved √ √ √ √ √ √ √
3

√ √ √ √ √ √

√ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 13

MPC5567 √ √ √ √ √ √ √ √ √ √

MPC5500 Family Memory Map

Table 2. Detailed MPC5500 Family Memory Map (continued)
MPC5532 MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 Address Range1 0xC3FC_8000–0xC3FC_09FF 0xC3FC_8A00–0xC3FC_8BFF 0xC3FC_8C00–0xC3FC_8FFF 0xC3FC_9000–0xC3FC_BFFF 0xC3FC_C000–0xC3FC_FFFF 0xC3FD_0000–0xC3FD_2FFF 0xC3FD_3000–0xC3FD_3FFF 0xC3FD_4000–0xC3FD_4FFF 0xC3FD_5000–0xC3FF_7FFF 0xC3FF_8000–0xC3FF_BFFF 0xC3FF_C000–0xC3FF_FFFF 156 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 20 Kbyte 3 Kbyte 12 Kbyte 4 Kbyte 4 Kbyte N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 164 164 N/A 200 200 200 200 Reserved Reserved Reserved Reserved Bridge B Peripherals 0xE000_0000–0xFBFF_FFFF (448 Mbyte) 0xFC00_0000–0xFFEF_FFFF 0xFFF0_0000–0xFFF0_3FFF 0xFFF0_4000–0xFFF0_7FFF 0xFFF0_8000–0xFFF0_FFFF 0xFFF1_0000–0xFFF3_FFFF 0xFFF4_0000–0xFFF4_3FFF 0xFFF4_4000–0xFFF4_7FFF 0xFFF4_8000–0xFFF4_BFFF 0xFFF4_C000–0xFFF4_C3FF 0xFFF4_C400–0xFFF4_FFFF 0xFFF5_0000–0xFFF7_FFFF 0xFFF8_0000–0xFFF8_3FFF 0xFFF8_4000–0xFFF8_7FFF 0xFFF8_8000–0xFFF8_FFFF 0xFFF9_0000–0xFFF9_3FFF 0xFFF9_4000–0xFFF9_7FFF 0xFFF9_8000–0xFFF9_BFFF 0xFFF9_C000–0xFFF9_FFFF 63 Mbyte 16 Kbyte 16 Kbyte 32 Kbyte 192 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 1 Kbyte 15 Kbyte 192 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte Reserved Reserved Bridge B Registers Crossbar (XBAR) Reserved Reserved ECSM DMA Controller 2 (eDMA) Interrupt Controller (INTC) Fast Ethernet Controller (FEC) Reserved Reserved Enhanced Queued Analog-to-Digital Converter (eQADC) Enhanced Queued Analog-to-Digital Converter (eQADC_B)3 Reserved Deserial Serial Peripheral Interface (DSPI_A) Deserial Serial Peripheral Interface (DSPI_B) Deserial Serial Peripheral Interface (DSPI_C) Deserial Serial Peripheral Interface (DSPI_D) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
2

Use eTPU Shared Data Memory (Parameter RAM)

16 Kbyte

2.5 Kbyte 0.5 Kbyte 1 Kbyte









√ √



√ √ √



eTPU Parameter RAM Reserved eTPU Shared Data Memory (Parameter RAM) mirror eTPU Shared Code RAM (12K,16K, or 20K) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

0xC400_0000–0xDFFF_FFFF (448 Mbyte)

√ √

√ √

√ √

√ √

√ √

√ √

√ √

√ √

√ √

√ √ √

√ √ √

√ √ √

√ √ √ √

√ √ √

√ √ √

√ √ √

√ √ √ √

√ √ √ √

MPC5500 Family Overview, Rev. 1 14 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Allocated Size

Used Size

MPC5567

MPC5500 Family Memory Map

Table 2. Detailed MPC5500 Family Memory Map (continued)
MPC5532 MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 Address Range1 0xFFFA_0000–0xFFFA_3FFF 0xFFFA_4000–0xFFFA_7FFF 0xFFFA_8000–0xFFFA_FFFF 0xFFFB_0000–0xFFFB_3FFF 0xFFFB_4000–0xFFFB_7FFF 0xFFFB_8000–0xFFFB_BFFF 0xFFFB_C000–0xFFFC_FFFF 0xFFFC_0000–0xFFFC_3FFF 0xFFFC_4000–0xFFFC_7FFF 0xFFFC_8000–0xFFFC_BFFF 0xFFFC_C000–0xFFFC_FFFF 0xFFFD_0000–0xFFFD_3FFF 0xFFFD_4000–0xFFFD_FFFF 0xFFFE_0000–0xFFFE_3FFF 0xFFFE4000–0xFFFE_7FFF 0xFFFE_8000–0xFFFE_BFFF 0xFFFF_C000–0xFFFF_FFFF4 Use Deserial Serial Peripheral Interface (DSPI_E)3 Deserial Serial Peripheral Interface (DSPI_F)3 Reserved Serial Communications Interface (SCI_A) Serial Communications Interface (SCI_B) Serial Communications Interface (SCI_C) Serial Communications Interface (SCI_D) Controller Area Network (FlexCAN_A) Controller Area Network (FlexCAN_B) Controller Area Network (FlexCAN_C) Controller Area Network (FlexCAN_D) Controller Area Network (FlexCAN_E) Reserved FlexRay Reserved Parallel Digital Interface 16 Kbyte Boot Assist Module (BAM) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Allocated Size 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 48 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte

Used Size 200 200 N/A 44 44 44 44 1152 1152 1152 1152 1152 N/A 2 kbyte

NOTES: 1 If allocated size is greater than used size, the base address for the module is the lowest address of the listed address range, unless noted otherwise. 2 The fast Ethernet controller (FEC) uses different pins on the MPC5553/MPC5566 and the MPC5567. 3 Reserved for future compatibility. No device is currently defined that uses these regions. 4 BAM address range is configured so that 4 kbytes BAM occupies 0xFFFF_F000-0xFFFF_FFFF.

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 15

MPC5567

Package Options

4

Package Options
Table 3. Device Package Options
Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 208 MAPBGA1 Yes3,4 Yes
3,4
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

The members of the MPC5500 family are all pin-compatible, but the different devices are available in a range of packages. Not all features are available in the smaller packages or on all devices.

324 PBGA No7 Yes
3

416 PBGA No No Yes5 Yes3 No No4,7 Yes3 Yes3,5 4 or 12-bit MDO

496 CSP2 Yes Yes Yes Yes No Yes Yes Yes 4 or 12-bit MDO

Calibration Bus Yes Yes Partial6 No No Yes Yes Yes

Yes4 No No No7 No No7

Yes3 No Yes Yes3,4 No Yes4

Nexus port availability 4-bit MDO Only 4 or 12-bit MDO Bus availability None (OE and CS0 available for GPIO) None 16-bit data / 20-bit address 4 chip selects8 None

32-bit data / 32-bit data / 24/26-bit address 24/26-bit address 4 chip selects 4 chip selects None 16-bit data / 21/19-bit address 1/3 chip selects 40 —

Calibration bus availability Analog channels Ethernet available
9

34 No

40 No

40 Yes

NOTES: 1 The 208 MAPBGA package is not available through distribution. If demand warrants, consult factory on availability. 2 The VertiCal CSP package is a 496 ball device mounted on a sub-assembly to fit into the 208, 324, or 416 ball footprint. It is not available as a standalone packaged device. 3 Predominate package. Though all packages may be available, the predominate package is the package in which most of the volume deliveries are expected. 4 Not available to distribution customers. 5 Predominate package for Ethernet use. 6 The MPC5553 lose use of 16 data bus signals in the 416 ball sub-assembly for the calibration data bus. The address bus is shared between the calibration bus and the normal system bus. Note: the fast Ethernet controller (FEC) requires these same 16 data bus signals on this devices. On the MPC5567, the FEC is shared with the calibration bus. 7 Depending on demand, consult factory for availability, 8 Up to 24 bits of address with zero chip selects can optionally be selected. 9 On devices that include Ethernet only.

MPC5500 Family Overview, Rev. 1 16 Freescale Semiconductor

Package Options

4.1
4.1.1

416 PBGA Ball Maps
MPC5554/MPC5566
NOTE: On the MPC5554, Ball J23 is VDDEH6. On the MPC5566, ball J23 is VDDEH10.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Figure 10 is a pinout for the MPC5554/MPC5566 416 PBGA package, Revision A.

1 A B VSS VDD

2 VSTBY VSS VDD

3 AN37 AN36 VSS VDD

4 AN11 AN39 AN8 VSS VDD

5 VDDA1 AN19 AN17 AN38

6 AN16 AN20 VSSA1 AN9

7 AN1 AN0 AN21 AN10

8 AN5 AN4 AN3 AN18

9 VRH REF BYPC AN7 AN2

10 AN23 AN22 VRL AN6

11 AN27 AN26 AN25 AN24

12 AN28 AN31 AN30 AN29

13 AN35 AN32 AN33

14 VSSA0 VSSA0 VDDA0

15 AN15 AN14 AN13

16

17

18

19

20

21 GPIO 205

22

23

24 VDD MDO0 VSS VDDE7 TMS

25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204

26 VSS A

ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27

MDO11 MDO8 MDO4 MDO1 VSS VDDE7

ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO6 MDO3

VDDE7 B VDD TDI TEST C D E

C VDD33

ETPUA ETPUA D 30 31 E

AN34 VDDEH AN12 9

MDO2 VDDEH 8

ETPUA ETPUA VDDEH 28 29 1

ETPUA ETPUA ETPUA VDDEH F 24 27 26 1 G H ETPUA ETPUA ETPUA ETPUA 23 22 25 21 ETPUA ETPUA ETPUA ETPUA 20 19 18 17

MSEO0 JCOMP MSEO1 MCKO

EVTO F ETPUB G 15

Version 1.3p – 29 May 2004

RDY

GPIO 203

ETPUB ETPUB H 14 13

ETPUA ETPUA ETPUA ETPUA J 13 16 15 14 K L ETPUA ETPUA ETPUA ETPUA 12 11 10 9 ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS

VDDEH ETPUB ETPUB ETPUB J 6/10* 12 11 9 ETPUB ETPUB ETPUB ETPUB K 10 8 7 5 ETPUB ETPUB ETPUB ETPUB L 6 4 3 2 TCRCLK ETPUB ETPUB B 1 0 SINB M

ETPUA ETPUA ETPUA ETPUA M 4 3 2 1 N P R BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS

SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T

T VDDE2 TSIZ0 RD_WR VDDE2 U V ADDR 16 ADDR 18 TSIZ1 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10

VDDE2 VDDE2 VDDE2 VDDE2

PCSA1 PCSA0 PCSA2

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2

PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V

ADDR W 20 Y ADDR 22

RXDB CNRXC TXDB RESET W

ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 29 DATA 0 GPIO 206 8

Note:

NC

No connect. AC22 & AD23 reserved

WKP CFG

BOOT CFG1

VRC VSS

VSS SYN

Y

ADDR AA 24 AB VDDE2 AC ADDR 26

VDDEH PLL 6 CFG1 VDD DATA 30 VDD33 DATA 2 DATA 1 9 DATA 31 GPIO 207 DATA 4 DATA 3 10 DATA 8 DATA 9 DATA 6 VDDE2 11 DATA 10 DATA 11 OE DATA 5 12 VDDE2 DATA 13 BR DATA 7 13 DATA 12 DATA 15 BG BB 14 DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC VSS NC VRC CTL VDD VSS

BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC

ADDR AD 28 AE AF ADDR 29 VSS 1

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 3 10 15 17 22

VDD33 AD VDD VSS 26 AE AF

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 15 16 17 18 19 20 21 22 23 24 ENG CLK 25

Figure 10. MPC5554/MPC5566 416 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 17

Package Options

4.1.2

MPC5553
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Figure 11 is a pinout for the MPC5553 416 PBGA package. The MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible; however, the MPC5553 ball map is shown here to highlight the balls not connected to any signal on the MCP5553 (the eTPUB[0:31] and TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the MPC5553. NOTE Some pins have names that include functions unavailable on all family members. For example, ball R25 of the 416 BGA package is named ‘SINA’, but the MPC5553 does not have a DSPI_A module. In this case, the SINA pin can only be used for its alternate functions of GPIO94 or PCSC2. See the specific device reference manual for functions available on each device in the family. If the MPC5534 were available in the 416 PBGA package, then it would also be missing the following signals: WE2, WE3, ADDR[8:11], and TEA.
1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 14 VSSA0 VSSA0 VDDA0 15 AN15 AN14 AN13 16 ETRIG 1 ETRIG 0 NC_9 17 NC_1 NC_5 18 NC_2 NC_6 19 NC_3 NC_7 20 NC_4 21 GPIO 205 22 23 24 VDD MDO0 VSS VDDE7 TMS 25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204 26 VSS A

MDO11 MDO8 MDO4 MDO1 VSS VDDE7

NC_8 MDO10 MDO7 MDO6 MDO3

VDDE7 B VDD TDI TEST C D E

C VDD33

NC_10 NC_11 NC_12 MDO9

ETPUA ETPUA D 30 31 E F G

AN34 VDDEH AN12 9

NC_13 NC_14 NC_15 NC_16 MDO5

MDO2 VDDEH 8

ETPUA ETPUA VDDEH 28 29 1

ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ETPUA ETPUA ETPUA ETPUA 23 22 25 21

MSEO0 JCOMP MSEO1 MCKO

EVTO F NC_17 G

ETPUA ETPUA ETPUA ETPUA H 20 19 18 17 J ETPUA ETPUA ETPUA ETPUA 16 15 14 13 VSS VSS

Version 2.1 – 13 July 2004

RDY

GPIO 203

NC_18 NC_19 H

VDDEH NC_20 NC_21 NC_22 J 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS NC_23 NC_24 NC_25 NC_26 K NC_27 NC_28 NC_29 NC_30 L NC_31 NC_32 NC_33 SINB M

ETPUA ETPUA ETPUA ETPUA K 12 11 10 9 L M N P R ETPUA ETPUA ETPUA ETPUA 8 7 6 5 ETPUA ETPUA ETPUA ETPUA 4 3 2 1 BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS

SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T

T VDDE2 NC_34 RD_WR VDDE2 U V ADDR NC_35 16 ADDR 18 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10

VDDE2 VDDE2 VDDE2 VDDE2

PCSA1 PCSA0 PCSA2

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2

PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V

ADDR W 20 Y AA ADDR 22 ADDR 24

Note:

NC_X NC_36

No connects (x = 1 to 38)
NC_37

RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 VRC VSS VSS SYN Y

ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 29 DATA 0 GPIO 206 8 DATA 30 VDD33 DATA 2 DATA 1 9 DATA 31 GPIO 207 DATA 4 DATA 3 10 DATA 8 DATA 9 DATA 6 VDDE2 11 DATA 10 DATA 11 OE DATA 5 12 VDDE2 DATA 13 BR DATA 7 13 DATA 12 DATA 15 BG DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4

No connect. AC22 & AD23 reserved

VDDEH PLL 6 CFG1 VDD VSS VRC CTL VDD VSS

BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC

AB VDDE2 ADDR AC 26 AD AE AF ADDR 28 ADDR 29 VSS 1

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 3 6 10 15 17 22

VDD33 AD VDD VSS 26 AE AF

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 ENG CLK 25

NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 14 15 16 17 18 19 20 21 22 23 24

Figure 11. MPC5553 416 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1 18 Freescale Semiconductor

Package Options

4.1.3

MPC5567
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Figure 11 is a pinout for the MPC5567 416 PBGA package. The MPC5567 and the MPC5553/MPC5554 are pin-compatible; however, the MPC5567 ball map is shown here to highlight the balls not connected to any signals and the balls used for Ethernet.
1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 14 VSSA0 VSSA0 VDDA0 15 AN15 AN14 AN13 16 ETRIG 1 ETRIG 0 NC NC 17 NC NC NC FEC_ COL 18 19 20 21 GPIO 205 22 23 24 VDD MDO0 VSS VDDE7 TMS 25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204 26 VSS A

VDDE FEC_ FEC_ 13 TX_CLK TX_ER FEC_ TXD2 FEC_ TX_EN FEC_ CRS FEC_ TXD1 FEC_ TXD3 VDDE 13

MDO11 MDO8 MDO4 MDO1 VSS VDDE7

FEC_ MDO10 MDO7 TXD0 MDO9 MDO5 MDO6 MDO3

VDDE7 B VDD TDI TEST C D E

C VDD33

ETPUA ETPUA D 30 31 E

AN34 VDDEH AN12 9

MDO2 VDDEH 8

ETPUA ETPUA VDDEH 28 29 1

ETPUA ETPUA ETPUA VDDEH F 24 27 26 1 G H ETPUA ETPUA ETPUA ETPUA 23 22 25 21 ETPUA ETPUA ETPUA ETPUA 20 19 18 17

MSEO0 JCOMP MSEO1 MCKO

EVTO F FEC_ RX_ER G

Version 1.2 – 11 July 2005

RDY

GPIO 203

FEC_ VDDE H RX_DV 12 FEC_ FEC_ RXD3 RX_CLK J FEC_ RXD1 NC NC FEC_ RXD0 NC SINB K L M

ETPUA ETPUA ETPUA ETPUA J 16 15 14 13 ETPUA ETPUA ETPUA ETPUA K 12 11 10 9 L ETPUA ETPUA ETPUA ETPUA 6 5 8 7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS

VDDEH FEC_ 10 MDC VDDE 12 FEC_ MDIO NC FEC_ RXD2 NC NC

ETPUA ETPUA ETPUA ETPUA M 4 3 2 1 N P R BDIP CS3 WE3 TEA CS2 WE2 NC NC ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS

SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T

T VDDE2 U V ADDR 16 ADDR 18

RD_WR VDDE2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10

VDDE2 VDDE2 VDDE2 VDDE2

PCSA1 PCSA0 PCSA2

VDDE2 VDDE2 VDDE2 VDDE2 VDDE2

PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V

ADDR W 20 Y ADDR 22

Note:

NC NC_1

No connect
NC_2

RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 PLL CFG2 VSS SYN Y

ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 29 DATA 0 GPIO 206 8 DATA 30 VDD33 DATA 2 DATA 1 9 DATA 31 GPIO 207 DATA 4 DATA 3 10 DATA 8 DATA 9 DATA 6 VDDE2 11 DATA 10 DATA 11 OE DATA 5 12 VDDE2 DATA 13 BR DATA 7 13 DATA 12 DATA 15 BG NC 14 DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC_1

ADDR AA 24 AB VDDE2 AC ADDR 26

No connect. AC22 & AD23 reserved

VDDEH PLL 6 CFG1 VDD VSS NC_2 VRC CTL VDD VSS

BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC

ADDR AD 28 AE AF ADDR 29 VSS 1

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 3 6 10 15 17 22

VDD33 AD VDD VSS 26 AE AF

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 15 16 17 18 19 20 21 22 23 24 ENG CLK 25

Figure 12. MPC5567 416 PBGA Ball Map Diagram

NOTE Ball Y25 changes from VRCVSS on all other MPC5500 devices (currently defined) to PLLCFG2 on the MPC5567. PLLCFG2 is required to support a 40-MHz clock option for the FlexRay.

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 19

Package Options

4.2
4.2.1

324 PBGA Ball Maps
MPC5533/MPC5534/MPC5553/MPC5561/MPC5565
1 A VSS 2 VDD VSS 3 VSTBY VDD VSS 4 AN37 AN36 VDD VSS 5 AN11 AN39 AN8 VDD 6 7 8 AN1 AN0 AN21 AN10 9 AN5 AN4 AN3 AN18 10 VRH REF BYPC AN7 AN2 11 VRL AN23 AN22 AN6 12 AN27 AN26 AN25 AN24 13 AN28 AN31 AN30 AN29 14 AN35 AN32 AN33 15 VSSA0 VSSA0 VDDA0 16 AN12 AN13 AN14 17 18 19 20 VDD MDO0 VSS VDDE7 TMS 21 VDD33 VSS VDDE7 TCK TDO EVTI 22 VSS A

Figure 13 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5561/MPC5565 324 PBGA package.
VDDA1 VSSA1 AN19 AN17 AN38 AN16 AN20 AN9 MDO11 MDO10 MDO8 MDO9 MDO5 MDO6 MDO7 MDO2 MDO3 MDO4 MDO1 VSS VDDE7

B VDD33 C

VDDE7 B VDD TDI TEST C D E

ETPUA ETPUA 30 31

ETPUA ETPUA ETPUA D 26 28 29 E

AN34 VDDEH AN15 9

ETPUA ETPUA ETPUA ETPUA 21 24 27 25

ETPUA ETPUA ETPUA ETPUA F 18 23 22 17 G H ETPUA ETPUA ETPUA ETPUA 20 19 14 13 ETPUA ETPUA ETPUA VDDEH 16 15 10 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VSS VSS VSS VSS VSS

VDDE7 JCOMP

EVTO F

Version 2.2p – 13 July 2004

RDY

MCKO MSEO0 MSEO1 G GPIO 204 SINB H

VDDEH GPIO 10 203

ETPUA ETPUA ETPUA ETPUA J 12 11 9 6 K L M N P ETPUA ETPUA ETPUA ETPUA 8 7 2 5 ETPUA ETPUA ETPUA ETPUA 4 3 0 1 TCRCLK BDIP A CS3 ADDR 16 CS2 CS1 WE1 CS0 WE0

SOUTB PCSB3 PCSB0 PCSB1 J PCSA3 PCSB4 SCKB PCSB2 K PCSB5 SOUTA SINA SCKA L VPP M

VDDE2 VDDE2 VSS VSS VSS VSS

PCSA1 PCSA0 PCSA2

PCSA4 TXDA PCSA5 VFLASH N CNTXC RXDA RSTOUT RST CFG WKP CFG RXDB P

ADDR RD_WR VDD33 17 ADDR VDDE2 19 ADDR 21 ADDR 23 ADDR 25 ADDR 12 ADDR 13 ADDR 15 TA TS ADDR 14 ADDR 31 VSS VDD VDDE2 DATA 0 4 VDD VDDE2 DATA 1 DATA 2 5 VDDE2 VDD33 VDDE2 DATA 8 VDDE2 DATA 3 6 DATA 9 GPIO 206 DATA 4 7 DATA 10 DATA 5 DATA 6 8

ADDR R 18 T U V ADDR 20 ADDR 22 ADDR 24

CNRXC TXDB RESET R BOOT CFG1 VRC VSS VSS SYN T

Note:

NC

No connect. Reserved (W18 & Y19 are shorted to each other)

VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS

BOOT EXTAL U CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN V W

ADDR ADDR W VDDE2 26 30 Y AA AB ADDR 28 ADDR 29 VSS 1 ADDR 27 VSS VDD 2 VSS VDD VDDE2 3

DATA 11 GPIO 207 DATA 7 OE 9

DATA 12 DATA 13

DATA 14 DATA 15

EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 2 4 12 8 21

NC

VSS NC

EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 10 15 17 22

VDD33 Y VDD VSS 22 AA AB

VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 3 5 9 13 16 19 23 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 1 4 7 11 14 18 20 10 11 12 13 14 15 16 17 18 19 20 ENG CLK 21

Figure 13. MPC5533/MPC5534/MPC5553/MPC5565 324 PBGA Ball Map Diagram

On the MPC5561 and MPC5567 ball T21 is PLLCFG2 instead of VRCVSS. PLLCFG2 is required to support a 40 MHz clock option for the FlexRay.

MPC5500 Family Overview, Rev. 1 20 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Package Options

4.3
4.3.1

208 MAP BGA Ball Map
MPC5533/MPC5534/MPC5553/MPC5565/MPC5566/MPC5567
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Figure 14 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5565/MPC5567 208 MAP PBGA package. NOTE VDDEH10 and VDDEH6 are connected internally on the 208-ball package and are listed as VDDEH6.
1 A B VSS VDD 2 AN9 VSS VDD AN39 3 AN11 AN38 VSS VDD AN37 4 5 6 AN1 AN4 AN16 AN2 7 AN5 REF BYPC AN3 AN6 8 VRH AN22 AN7 AN24 9 VRL AN25 AN23 AN30 10 AN27 AN28 AN32 AN31 11 VSSA0 VDDA0 AN33 12 AN12 AN13 AN14 13 MDO2 MDO3 AN15 VSS VDDE7 14 15 16 VSS VDD TCK TEST A B C D VDDA1 VSSA1 AN21 AN17 VSS VDD AN36 VSS VSS VSS VSS AN0 AN34 AN18 MDO0 VDD33 MDO1 VSS TMS TDI TDO VSS MSEO0 EVTO EVTI

C VSTBY D VDD33 E F

AN35 VDDEH 9

ETPUA ETPUA 30 31

MSEO1 E

ETPUA ETPUA ETPUA 28 29 26

8 June 2005p
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDEH 6

MCKO JCOMP F SINB PCSB0 G

ETPUA ETPUA ETPUA ETPUA G 24 27 25 21 H J ETPUA ETPUA ETPUA ETPUA 18 23 22 17 ETPUA ETPUA ETPUA ETPUA 20 19 13 14

SOUTB PCSB3

PCSA3 PCSB4 PCSB2 PCSB1 H PCSB5 TXDA PCSA2 SCKB J CNTXC RXDA RSTOUT VPP TXDB CNRXC WKP CFG BOOT CFG1 PLL CFG1 VRC33 VSS VDD 15 K

ETPUA ETPUA ETPUA VDDEH K 1 16 15 7 L M ETPUA ETPUA ETPUA TCRCLK 12 11 6 A ETPUA ETPUA ETPUA ETPUA 10 9 1 5 VSS VDD GPIO 206

RESET L VSS SYN M

Note:

CS0

No connect. R1 reserved for CS0
RXDB VSS VDD

PLL CFG0 VRC CTL VSS VDD ENG CLK 14

ETPUA ETPUA ETPUA N 8 4 0 P R T ETPUA ETPUA 3 2 CS0 VSS 1 VSS VDD 2 VSS VDD OE 3

VDD GPIO 207

VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33 2 10 21 4 12 VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA 6 8 22 16 17

EXTAL N XTAL VDD SYN VSS 16 P R T

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB 4 3 9 11 14 19 23

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5 0 1 5 7 13 15 18 20 4 5 6 7 8 9 10 11 12 13

Figure 14. MPC5534/MPC5553/MPC5565/MPC5567 208 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 21

Package Options

Appendix A: Revision History
Table 4 is a revision history for this document.
Table 4. Revision History
Revision Number 0 A.1 Initial release. Added Section 11, “MPC5554 Evaluation Board Availability.” (now removed) Changed TCRCLKB(IRQ6) to TCRCLKA(IRQ) in Table 16.(now removed) Changed NC to eTPUB24 and NC to TCRCLKB in Table 17.(now removed) First Confidential release for customers. Added MPC5566. Corrected memory map for MPC5565 and MPC5567 showing flash size and eTPU shared RAM size. Corrected MPC5565 and MPC5567 block diagrams - only 1 eTPU each. Re-ordered the block diagrams and tables to put into devices into numeric order, instead of introduction order. Added place holder for MPC557x future devices in the device roadmap. Added MPC5533 block diagram. L2 SRAM renamed just SRAM. Corrected SINA ball number in Section 4.1.2. Modified ordering of device introduction schedules in Figure 1 MPC5500 roadmap figure. Added cache associativity to Table 1 Renamed all pinout diagrams to ball map diagrams for consistency. Removed eMIOS on MPC5533. Corrected eDMA channels on MPC5533, MPC5534, MPC5565, MPC5567. Corrected number of interrupt channels in Table 1. Corrected FlexCAN memory map for MPC5533, MPC5534, and MPC5553 in Table 2. MPC5567 ball map updated for VDDE13. Cache associativity added to feature table. Review comment - MPC5566 has 64 eTPU channels. Updated introduction paragraph to reference all parts covered in this document. Changed MPC5567 SRAM size to 80K from 64K for revision A of the MPC5567. Substantive Changes
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

A.4 A.5

MPC5500 Family Overview, Rev. 1 22 Freescale Semiconductor

Package Options

Table 4. Revision History (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages

Revision Number A.6

Substantive Changes Changed MPC5565 416 BPGA package to consult factory—tooling based on forecasted demand. Notes added to 208 MAPBGA and some other configurations that they will not be available through the distribution channel. Reviewed by BB, LW, and VG. Editorial and formatting edits by AE. Figures redrawn. First Public Release Removed second ADC from MPC5533 block diagram (Figure 2). Updated package availability for family. On package options that were previously as Yes (available) with the footnotes 4 (Not available to distribution customers) or 7 (Depending on demand, consult factory) changed to “No - consult factory for availability”. Corrected Ball J23 (VDDEH10) on 416 MPC5553, MPC5566, and MPC5567 Ball Map. Corrected VDDEH10 on 324 (H19) ball maps. Corrected eTPUA6 (ball L3) in the 208 MAPBGA (Figure 14). Added MPC5561 to family comparison (Table 1) and memory map (Table 2). Added MPC5561 block diagram. Added note on MPC5565 crossbar size in comparison table (Table 1) to indicate that there are 5 ports with 2 unused. Updated references from PowerPC to Power. Added reference for PLLCFG2 for the 324 Ball Map for the MPC5567 and MPC5561. Updated roadmap timing, including the MPC5561 part number, added MPC5510 Family. Deleted 324 package options for MPC5533. Small editorial and formatting edits by SF.

A.6.1 0 1

MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 23

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EB659 Rev. 1, 11/2006

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565, MPC5566 and MPC5567 products in 496 MAPBGA packages


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