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FPGA 设计外文原文及译文
一、外文原文
FPGA application and development in all fields
Through increased density, lower power consumption and cost, and other means to traditional ASIC FPGA has be routed area, in a variety of emerging application areas to accelerate penetration. But its future development "devoting to this" FPGA today not only applies the Horn continuously reaching wider areas, in areas such as communications, consumer and embedded FPGA DSP "functions", via embedded processor core application replace the MCU, FPGA development space of imagination. 1 Field of FPGA DSP accelerated penetration

According to a study, in multiple DSP FPGA will play an increasingly important role in high-end applications, such as high-end communications infrastructure requires significant application of parallel computing and high performance requirements, independent DSP FPGA performance benefits to more than. ALTERA Corporation recently announced the sale of the industry's first 65-nanometer low-cost FPGA-Cyclone III series. Currently over more than 250 customers have Cyclone III FPGA design are used in a large number of applications, application areas covered in the consumer, automotive, military, industrial and wireless communications. Cyclone III provide a wealth of logic, memory, and DSP functions, it contains 5K nm logic units, 288 digital signal processing (DSP) multipliers, storage 4Mbits. Previous generation compared to the 90 nm process devices, 65 nanometer Cyclone III has 1.7 times times the logic; 3.5 times times the memory; twice times the multiplier, multiplier performance achieved the 260MHz each logical unit (LE) cost reduction 20%; 50%, low power consumption, in terms of low power, low cost and high performance are increased dramatically. In addition to interpretation, as always, to high performance and low cost FPGA upgrade significance outside ALTERA Cyclone III have also been special emphasis in wireless micro base stations, software radio, video monitors and portable medical devices and other emerging case replace the MCU and DSP in the application. In wireless applications, Cyclone III FPGA DSP for low-power, high density and sufficient functionality allows designers to achieve wireless micro base station for digital baseband
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and IF functions. In software-defined radio (SDR), Cyclone III integrated SDR signal processing in a single device, static power consumption is lower than 0.5W. In the video coding, through the use of Cyclone III, customers at costs below US $ 20 full H.264 encoder, or less than US $ 5 cost of high-definition (HD) zoom function. In addition, the application displays, Cyclone III device optimized for display applications, is the first to meet the needs of all of the 1080p HDTV performance low cost FPGA. Where you can see a significant change is that the low-cost FPGA application in these areas "behalf" part of the DSP functions. ALTERA broadcasting, automotive electronics and consumer electronics business Vice President Tim Colleran said, compared to DSP,FPGA the biggest advantage of parallel processing, handling a wide variety of tasks at the same time, and involves complex calculations to unload some of the tasks into FPGA DSP processing. From FPGA another giant wave of sailingsi move can also see that the substitution of FPGA for DSP. Introduced in sailingsi his FPGA DSP module-XtremeDSP technology, available for aerospace and military products, digital communications, multimedia, video processing and other industries of high performance custom DSP solution. Sailingsi also claimed its Spartan-3 series is cost minimum of high performance DSP solution programme, it can processing as: each seconds can completed 1.8 billion take and cumulative operation (MAC), up to 104 a 18x18 embedded multiplication device, for implementation close of DSP structure, as MAC engine and the since adaptation, and full parallel FIR filter; complex of DSP algorithm (as forward error correction (FEC) series decoding device, and filter), for digital communication and imaging application. Despite being seen in some applications in FPGA can directly replace the DSP, but is not FPGA overnight complete subversion of the existing pattern. Tim Colleran said, the future relationship between FPGA and DSP is more processing, FPGA and DSP has broad applications of space, because the DSP and FPGA programming, you can reuse and have common algorithm upgrade, you can use the DSP or FPGA for lower power consumption and high performance. Not only that, Tim Colleran said, ALTERA Nios II soft core 32-bit embedded FPGA can replace the application of MCU, particularly more high-end MCU for more complex applications. 2 Battle for the soft core upgrade

In system design complexity and constantly improve and market cycles for new products under the pressures of shrinking, embedded on the same core FPGA and microprocessor chip, build a programmable chip SOPC become the choice of the system.
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XILINX and ALTERA SOPC launched their own soft core. XILINX Micro Blaze soft core is a 32-bit Harvard RISC architecture, support for Spartan FPGA products and Virtex series. ALTERA Nios II soft core is users are free to configure and build a 16-bit/32-bit bus instruction set microprocessor soft core embedded system and data channel, it uses the Avalon bus communications interface, with enhanced memory, debugging, and software capabilities, all its implantable ALTERA FPGA product series. Strong ARM processor kernel now also in the field of FPGA take force attack. Actel and ARM company recently released the first dedicated high-performance 32-bit processor optimized for FPGA application Cortex-M1. Cortex-M1 processor extends the ARM architecture in the field of FPGA application, can be used in portable consumer electronics, automotive electronics, industrial, communications, military/aerospace and other fields. ARM Tan Jun, President of China said that it is specifically optimized for FPGA, because the traditional solid-core efficiency is not high, will waste a lot of resources. Powered by Cortex-M1 processor core FPGA will benefit designers, it is able to shorten the development time for system on chip design, and reduce costs, especially for lower-volume products. Field Programmable Gate Arrays (FPGAs) are programmable semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. As opposed to Application Specific Integrated Circuits (ASICs) where the device is custom built for the particular design, FPGAs can be programmed to the desired application or functionality requirements. Although one-time programmable (OTP) FPGAs are available, the dominant type are SRAM based which can be reprogrammed as the design evolves. 3 Characteristics and development trends of FPGA

Programmable logic devices (Programmable Logical Device) design a flexible, powerful, especially in high density programmable logic devices (Field Programmable Gate Array) its performance is fully comparable to ASIC design, and since the gradual popularization of FPGA, its price-performance ratio is enough to contend with ASIC. Therefore, the FPGA has occupied an increasingly important position. FPGA for basic structure consists of the following components: ? CLB programmable logic function module (Configurable Logic Blocks) ? IOB programmable input/output modules (Input/Output Blocks) ? programmable interconnect resources within PI (Programmable Interconnection)
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As technology advances and application of the system requirements, usually in the FPGA optional resources also contain the following: ? memory resources (Block Select RAM and RAM) ? digital clock management unit (divider/multiplier, digital delay) ? I/O multilevel standards-compliant (Select I/O) ? count arithmetic unit (multiplier, Adder) ? special function modules (such as MAC hard IP core) ? microprocessor (PPC405 hard processor) PLD products based on the FPGA is the fastest growing product in the integrated circuit in recent years. With the rapid development of FPGA performance and design staff's own ability to improve, will further expand programmable FPGA chip for territory, complex ASIC squeezed to the high-end and ultra-complex applications. Current trends of FPGA is mainly reflected in the following areas: ? to higher density, more capacity do door system-level direction ? to low-cost, low-voltage, low power, micro-encapsulated and green development ? IP resource reuse concept design will be recognized and become the main way ? MCU, DSP, MPU and embedded processor IP will become the core of FPGA application As processors embedded in FPGA as IP, between ASIC and FPGA are increasingly blurred, some circuit board on the future may have only two circuit: the simulation (including power) and a FPGA chips, up to some large capacity storage. Most next-generation FPGA:Spartan II/E, companies such as Xilinx Virtex II Pro and related IP Core of launch, we have reason to believe, programmable SOC (System on Programmable Chip) era has not so far away from us. (1) IOB Details Today? FPGAs provide support for dozens of I/O standards thus providing the ideal s interface bridge in your system. I/O in FPGAs is grouped in banks (see figure below) with each bank independently able to support different I/O standards. Today? leading FPGAs s provide over a dozen I/O banks, thus allowing flexibility in I/O support. (2) CLB Details The Configurable Logic Block is the basic logic unit in an FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc.), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift
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registers or RAM. A high level CLB overview is shown here. More architectural details can be found in the applicable device? data sheet. s (3) DCM Details Digital clock management is provided by most FPGAs in the industry (all Xilinx FPGAs have this feature), and has nearly eliminated the skew and other issues that designers had to face with in designing global signals into FPGAs in the past. (4) Common FPGA Features Today’s FPGAs have evolved far beyond the basic capabilities present in their predecessors, and incorporate hard (ASIC type) blocks of commonly used functionality such as RAM, clock management, and DSP. Following are the basic components in an FPGA. (5) Configurable Logic Block (CLBs) The CLB is the basic logic unit in an FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM. More architectural details can be found in the applicable device’s data sheet. (6) Interconnect While the CLB provides the logic capability, flexible interconnect routing routes the signals between CLBs and to and from I/Os. Routing comes in several flavors, from that designed to interconnect between CLBs to fast horizontal and vertical long lines spanning the device to global low-skew routing for Clocking and other global signals. The design software makes the interconnect routing task hidden to the user unless specified otherwise, thus significantly reducing design complexity. (7) SelectIO (IOBs) Today’s FPGAs provide support for dozens of I/O standards thus providing the ideal interface bridge in your system. I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards. Today’s leading FPGAs provide over a dozen I/O banks, thus allowing flexibility in I/O support. (8) Memory Embedded Block RAM memory is available in most FPGAs, which allows for on-chip memory in your design. These allow for on-chip memory for your design. Xilinx FPGAs provide up to 10 Mbits of on-chip memory in 36 kbit blocks that can support true dual-port operation.
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(9) Complete Clock Management Digital clock management is provided by most FPGAs in the industry (all Xilinx FPGAs have this feature). The most advanced FPGAs from Xilinx offer both digital clock management and phase-looped locking that provide precision clock synthesis combined with jitter reduction and filtering. 4 IP resource reuse ideas

(1) due to the complexity of the chip design and product time to market is critical to ensure that the terminal success rate in the market, designers constantly looking for way to shorten the design cycle, as well as the design of more effective ways. As we entered the era of system on chip, using IP cores and programmable logic design reuse is increasingly important. IP reuse resources (IP Reuse) refers to the integrated circuit design process, through inheritance, sharing, or purchase the required intellectual property rights of the kernel, and then using EDA tools for design, integration and verification, thus speeding up the flow design process and reduce development risk. IP Reuse has gradually become important means of modern IC design, in the face of changing application requirements, VLSI design is entering an era of integration of IP in the era. IP Reuse not only apply to ASIC design on FPGA-based embedded system design, but also has a vital role. FPGA IP cores in the front of the market, the reason for this is the following: ? FPGA has the characteristics of very high flexibility and shorter time to market, allowing multiple design iterations can be completed within a few hours instead of weeks ? due to FPGA density of up to a million doors, and even millions of doors, more and more designers tend to use IP cores to maintain and improve product yield ? programmable logic is inexpensive and can serve as practical tools, and best prototype design, and will not have to be expensive EDA design tools, dramatically reducing design thresholds (2) the IP Core design method: coding style and project templates IP Core is the core vehicle for IP Reuse and content, based on application requirements, specification of different protocols and industry standards, IP Core content is different. However, in order to make IP Core is easy to access and easy to integrate, its design must comply with certain specifications and guidelines. In the IP Core of development, many open groups enormous effort to promote IP Core
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development and promotion of IP Reuse ideas, the more famous is the Open Cores of development organizations (http://www.OpenCores.org). They are not only developed a number of open source IP Core, including processor IP, processor IP peripheral controller IP, arithmetic units, DSP algorithms such as IP, and prepared detailed IP Core coding style and project templates, and advocated a standard Wishbone bus, for the specification of various IP Core interface standard. Open groups of domestic IP Core development team (http://www. IPcore.com.cn) also in the development and promotion of IP Reuse ideas IP Core has made untiring efforts and universal. Coding style (Coding Style) is based on the guidance document prepared by the HDL IP Core source code, its readability is directly related to IP Core for ease of access and ease of integration. Coding style generally consists of several aspects of conventions: file header and the release notes, online comments, naming convention, can be integrated coding, and so on. Project template which provides the completion of an IP Core design contains the main content and the documents to be provided, content and document project templates directly related to the ease of integration of IP Core characteristics, an IP Core must be complete, fully validated, can be successfully integrated into the application in the project. Item template usually contains several content: project definition, interface design description, systems, structures, and modules, documentation, testing, validation reports, constraints, and bibliography of the implementation, evaluation, trial, and the release notes. Coding style and project templates more English version and Chinese version of the document can be obtained from the above two Web site. (3) IP Core verification: simulation, test and evaluation board IP Core design after the completion of the coding phase, on the functional tests verify that is a very important element, because it is directly related to IP Core resource availability. Just by functional simulation, timing simulation and validation of test vector of IP Core is incomplete, it must authenticate with the actual system. International companies often approach evaluation board is verified, that is, building a hardware environment consistent with the actual application system IP Core, by downloading FPGA configuration make it have the function of the appropriate logical and physical simulation. In addition, because of the high licensing costs of IP Core, users often want before purchasing IP Core, its capabilities are fully validated to determine whether appropriate for the target system, so as to reduce investment risk, and (of course, the kernel and source code is the intellectual property of and the measures of protection), Xilinx company Sing
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Once and Open Core for Altera Corporation provides the platform. Xilinx and Altera Corporation provides many of the company to assess IP Core FPGA evaluation board, such as USB, MAC, IEEE1394, and so on. Many third-party design centers, such as Insight, also developed for SOPC system integration of Virtex II Pro and Virtex II evaluation board MicroBlaze PPC405 evaluation board, and so on. Xilinx FPGA of domestic professional design company Changsha according to element technology (http://www.eestd.com) also development has for evaluation various basic IP Core and learning training uses of digital knife sword ? series (DigitalSword ? Series Kit) Assessment Board, as Figure 1 by as shown in, the series Assessment Board provides has VGA, and LCD, and audio, and keyboard mouse, and serial, and and mouth, and USB Slave, and I2C, level interface, and provides has standard extended bus and rich of child Board function module support.

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二、译文
FPGA 的发展和各个领域中的应用
通过提高密度、降低功耗和成本等手段,FPGA 已经披靡传统 ASIC 领域,在众多 新兴应用领域加速渗透。但它未来的发展“志不在此” ,如今 FPGA 不仅将应用触角不 断伸向更为广泛的领域,在通信、消费类、嵌入式等领域 FPGA 行使 DSP“职能” ,通 过嵌入处理器核取代 MCU 一些应用,FPGA 未来发展空间惹人想象。 1 FPGA 向 DSP 领域加速渗透 一项研究显示,在多个 DSP 高端应用中 FPGA 将扮演越来越重要的角色,例如高 端通信基础设施等需要大量并行运算且对性能要求很高的应用,FPGA 的性能优势要 超过独立 DSP。 近日 ALTERA 公司宣布开始发售业界首款 65 纳米低成本 FPGA—Cyclone III 系列。 目前 250 多家客户已在大量应用中采用 Cyclone III FPGA 进行设计,应用领域涵盖 在消费类、汽车、军事、工业和无线通信等。Cyclone III 提供丰富的逻辑、存储器 和 DSP 功能,它含有 5K 至 120K 逻辑单元,288 个数字信号处理(DSP)乘法器,存储 器达到 4Mbits。与上一代 90 纳米工艺器件相比,65 纳米 Cyclone III 具有 1.7 倍的 逻辑;3.5 倍的存储器;2 倍的乘法器,乘法器性能达到了 260MHz;每逻辑单元(LE) 成本降低 20%;功耗低 50%,在低功耗、低成本和高性能等方面均大幅提升。 除了一如既往地以高性能低成本来诠释 FPGA 升级意义之外,ALTERA 还特别强调 了 Cyclone III 在无线微基站、软件无线电、视频监控和便携医疗设备等新兴应用中 取代 MCU 和 DSP 的案例。在无线应用中,Cyclone III FPGA 的低功耗、高密度和充 足的 DSP 功能使设计人员可以实现无线微基站的数字 IF 和基带功能等。在软件无线 电(SDR)应用中, Cyclone III 在单个器件中集成了 SDR 信号处理, 静态功耗低于 0.5W。 在视频编码中,通过采用 Cyclone III,客户能以低于 20 美元的成本实现全 H.264 编码器,或者以低于 5 美元的成本实现高清晰(HD)缩放功能。此外,在显示应用中, Cyclone III 器件针对显示应用进行了优化,是第一款能够满足所有 1080p HDTV 性 能需求的低成本 FPGA。从中可看出一个显著的变化是,低成本 FPGA 在这些应用领域 开始“代行”部分 DSP 职能。ALTERA 广播、汽车电子及消费电子业务副总裁 Tim Colleran 表示,相比 DSP,FPGA 最大的优势是并行处理,在同一时间处理大量不同 的任务,因而在涉及到复杂计算时可把 DSP 的一些任务卸载到 FPGA 中处理。 从 FPGA 另一巨头赛灵思的举动亦可看出 FPGA 替代 DSP 的风潮。 赛灵思通过在其 FPGA 中引入 DSP 模块—XtremeDSP 技术,提供针对航天和军用产品、数字通信、多媒 体、视频处理等行业的高性能定制 DSP 解决方案。赛灵思还宣称其 Spartan-3 系列是
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成本最低的高性能 DSP 解决方案,它可以处理如:每秒可以完成 18 亿乘和累加操作 (MAC),高达 104 个 18×18 嵌入式乘法器,用于实现紧密的 DSP 结构,如 MAC 引擎及 自适应、全并行 FIR 滤波器;复杂的 DSP 算法(如向前纠错(FEC)编解码器、滤波器), 用于数字通信与成像应用等。 尽管已经看到在某些应用中 FPGA 可以直接取代 DSP,但 FPGA 不会在一夜之间彻 底颠覆现有格局。Tim Colleran 表示,未来 FPGA 和 DSP 更多是协处理关系,FPGA 和 DSP 都有广阔的应用空间,因为 DSP 和 FPGA 在可编程、可以重用和算法升级方面 有共通性, 可以使用 DSP 或 FPGA 实现更低功耗和更高性能。 不仅如此, Tim Colleran 还表示,ALTERA FPGA 中嵌入的 Nios II 32 位软核可以取代 MCU 的一些应用,特别 是面对更高端更复杂应用的 MCU。 2 软核之争升级 在系统设计复杂度不断的提高及新产品市场周期不断缩短的压力下,把 FPGA 及 微处理器的核心内嵌在同一芯片上, 构建可编程芯片系统 SOPC 成为不二之选。 XILINX 和 ALTERA 都针对 SOPC 推出的自己的软核。XILINX 的 Micro Blaze 软核是一个 32 位 哈佛 RISC 结构,支持的 FPGA 产品为 Spartan 和 Virtex 系列。ALTERA 的 Nios II 软 核是用户可随意配置和构建的 16 位/32 位总线指令集和数据通道的嵌入式系统微处 理器软核,它采用 Avalon 总线结构通信接口,带有增强的内存、调试和软件功能, 它可植入 ALTERA FPGA 产品的所有系列。 如今处理器核的劲旅 ARM 亦在 FPGA 领域借力出击。最近 Actel 和 ARM 公司发布 了第一款专门针对 FPGA 应用而优化的高性能 32 位处理器 Cortex-M1。Cortex-M1 处 理器扩展了 ARM 架构在 FPGA 领域的应用,可应用于便携式消费电子产品、汽车电子、 工业、通信、军事/航天等领域。ARM 中国区总裁谭军表示,它专门为 FPGA 而优化, 因为用传统的固核效率不高,会浪费许多门资源。采用 Cortex-M1 处理器核的 FPGA 将使设计人员受益,它能够缩短系统级芯片设计的开发时间,并降低成本,尤其是对 批量较低的产品。 现场可编程门阵列 (FPGA) 是由通过可编程互连连接的可配置逻辑块 (CLB) 矩 阵构成的可编程半导体器件。相对于专为特定设计定制构建的专用集成电路 (ASIC) 而言,FPGA 能通过编程来满足应用和功能要求。 虽然市面上也有一次性可编程 (OTP) FPGA,但绝大多数是基于 SRAM 的类型, 可随着设计的演化进行重编程。 3 FPGA 的特点及其发展趋势 可编程逻辑器件(Programmable Logical Device)设计灵活、功能强大,尤其

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是高密度现场可编程逻辑器件(Field Programmable Gate Array)其设计性能已完 全能够与 ASIC 媲美,而且由于 FPGA 的逐步普及,其性能价格比已足以与 ASIC 抗衡。 因此,FPGA 已占据着越来越重要的地位。 FPGA 的基本结构由以下几个部分构成: ? 可编程逻辑功能模块 CLB(Configurable Logic Blocks) ? 可编程输入输出模块 IOB(Input/Output Blocks) ? 可编程内部互连资源 PI(Programmable Interconnection) 随着工艺的进步和应用系统需求,一般在 FPGA 中还包含以下可选资源: ? 存储器资源(Block RAM 和 Select RAM) ? 数字时钟管理单元(分频/倍频、数字延迟) ? I/O 多电平标准兼容(Select I/O) ? 算数运算单元(乘法器、加法器) ? 特殊功能模块(MAC 等硬 IP 核) ? 微处理器(PPC405 等硬处理器) 以 FPGA 为核心的 PLD 产品是近几年集成电路中发展得最快的产品。随着 FPGA 性能的高速发展和设计人员自身能力的提高,FPGA 将进一步扩大可编程芯片的领地, 将复杂专用芯片挤向高端和超复杂应用。目前 FPGA 的发展趋势主要体现在以下几个 方面: ? 向更高密度、更大容量的千万门系统级方向迈进 ? 向低成本、低电压、微功耗、微封装和绿色化发展 ? IP 资源复用理念将得到普遍认同并成为主要设计方式 ? MCU、DSP、MPU 等嵌入式处理器 IP 将成为 FPGA 应用的核心 随着处理器以 IP 的形式嵌入到 FPGA 中, ASIC 和 FPGA 之间的界限将越来越模糊, 未来的某些电路版上可能只有这两部分电路:模拟部分(包括电源)和一块 FPGA 芯 片,最多还有一些大容量的存储器。Xilinx 等公司最新一代 FPGA:Spartan II/E、 Virtex II Pro 及其相关 IP Core 的推出, 使我们有理由相信, 可编程片上系统 (System on Programmable Chip)的时代已经离我们不远了。 (1)IOB 说明 目前的 FPGA 可支持许多种 I/O 标准, 因而为您的系统提供了理想的接口桥接。 FPGA 内的 I/O 按 bank 分组 (见下图) , 每个 bank 能独立支持不同的 I/O 标准。 目前最先进的 FPGA 提供了十多个 I/O bank,能够提供灵活的 I/O 支持。 (2)CLB 说明 可配置逻辑块是 FPGA 的基本逻辑单元。实际数量和特性会依器件的不同而改 变,但是每个 CLB 都包含一个由 4 或 6 个输入、一些选择电路(多路复用器等)
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和触发器组成的可配置开关矩阵。开关矩阵具有高度的灵活性,经配置可以处理组合 型逻辑、移位寄存器或 RAM。 这里给出了一个高层次的 CLB 简介。 (3)DCM 说明 业界大多数 FPGA 均提供数字时钟管理(Xilinx 所有 FPGA 均具有此特性) ,几 乎消除了过去设计者在将全局信号设计到 FPGA 中时不得不面对的歪斜及其它问题。 (4)FPGA 的常见特性 当今的 FPGA 已经远远超出了先前版本的基本性能,并且整合了如 RAM、时钟管 理和 DSP 这些常用功能的硬(ASIC 型)块。 (5)可配置逻辑块 (CLB) CLB 是 FPGA 的基本逻辑单元。实际数量和特性会依器件的不同而改变,但是每 个 CLB 都包含一个由 4 或 6 个输入、一些选择电路(多路复用器等)和触发器组 成的可配置开关矩阵。开关矩阵具有高度的灵活性,经配置可以处理组合型逻辑、移 位寄存器或 RAM。 有关更多架构细节。 (6)互连 CLB 提供了逻辑性能,灵活的互连布线则负责在 CLB 和 I/O 之间传递信号。布 线有几种类型,从设计用于专门实现 CLB 互连、到器件内的高速水平和垂直长线、 再到时钟与其它全局信号的全局低歪斜布线。除非另行说明,否则设计软件会将互连 布线任务隐藏起来,用户根本看不到,从而大幅降低了设计复杂性。 (7)SelectIO (IOB) 目前的 FPGA 可支持许多种 I/O 标准, 因而为您的系统提供了理想的接口桥接。 FPGA 内的 I/O 按 bank 分组 (见下图) , 每个 bank 能独立支持不同的 I/O 标准。 目前最先进的 FPGA 提供了十多个 I/O bank,能够提供灵活的 I/O 支持。 (8)存储器 大多数 FPGA 中都提供嵌入式块 RAM 存储器,这样可以在您的设计中实现片上 存储。这些能为您的设计实现片上存储。Xilinx FPGA 提供高达 10 Mbits 的片上存 储 (每个区块大小为 36 Kbits),能够支持真正的双端口运行。 (9)完整的时钟管理 业界大多数 FPGA 都提供数字时钟管理(所有 Xilinx FPGA 都具有此特性) Xilinx 推出的最高级 FPGA 提供了数字时钟管理和锁相环锁定功能,不仅提供了精 确时钟综合功能,而且能够降低抖动和实现过滤。 4 IP 资源复用理念 (1)由于芯片设计的复杂性和产品面市时间对于保证终端市场的成功率至关重 要,设计师不断寻求缩短设计周期的方法,以及更有效的设计方式。随着我们步入系
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统级芯片时代,利用 IP 内核和可编程逻辑进行设计复用显得日趋重要。 IP 资源复用(IP Reuse)是指在集成电路设计过程中,通过继承、共享或购买 所需的智力产权内核,然后再利用 EDA 工具进行设计、综合和验证,从而加速流片设 计过程,降低开发风险。IP Reuse 已逐渐成为现代集成电路设计的重要手段,在日 新月异的各种应用需求面前, 超大规模集成电路设计时代正步入一个 IP 整合的时代。 IP Reuse 不仅仅应用于专用集成电路设计,对基于 FPGA 的嵌入式系统设计领域 而言,更是具有举足轻重的地位。FPGA 在采用 IP 内核方面走在了市场的前面,其原 因有以下几个方面: ? FPGA 具有极高的灵活性和面市时间短的特点,这使得多项设计迭代可以在数 小时而不是数周内完成 ? 由于 FPGA 密度达到了百万门甚至是千万门,越来越多的设计师倾向于使用 IP 内核保持和提高产品的产量 ? 可编程逻辑价格低廉,可以作为切实可行的生产工具以及最佳原型设计,而且 不许要昂贵的 EDA 设计工具,大大降低了设计门槛 (2)IP Core 设计方法:编码风格与项目模板 IP Core 是 IP Reuse 的载体和核心内容,基于应用需求、规范协议和行业标准 的不同,IP Core 的内容也是千差万别的。但是,为了使 IP Core 易于访问和易于集 成,其设计必须遵循一定的规范和准则。 在 IP Core 的开发方面,许多开放性的团体都付出了巨大的努力来推动各种 IP Core 的开发和 IP Reuse 理念的推广,其中比较著名的是 Open Cores 开发组织 (http://www.opencores.org)。他们不仅开发了许多开放源代码的 IP Core,涵盖了 处理器 IP、处理器外设控制器 IP、算术运算单元 IP、DSP 算法 IP 等方面,而且编写 了详细的 IP Core 编码风格和项目模板,并倡导了一种总线标准 wishbone,用于规 范各种 IP Core 的接口标准。国内开放性团体 IP Core 开发小组也在 IP Core 开发和 IP Reuse 理念的推广和普及方面进行了不懈的努力。 编码风格(Coding Style)是基于 HDL 的 IP Core 源码编写的指导性文档,其可 读性直接关系到 IP Core 的易于访问和易于集成性。编码风格一般包含几个方面的约 定:文件头和版本说明、联机注释、命名规则、可综合编码等。 项目模板则规定了完成一个 IP Core 设计包含的主要内容及所需提供的文档,项 目模板内容及其文档直接关系到 IP Core 的易于集成特性,一个 IP Core 必须是完整 的、经过全面验证的,才能顺利地集成到应用项目中去。项目模板一般包含几个方面 的内容:项目定义、接口说明、系统结构和模块、设计文档说明、测试验证报告、约 束和实现、版本说明、试用评价以及参考文献等。 编码风格和项目模板详细文档的英文版和中文版可分别从上述两个网站获得。
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(3)IP Core 验证:仿真、测试与评估板 IP Core 设计在完成编码阶段以后, 对其功能的测试验证是一项非常重要的内容, 因为这直接关系到 IP Core 资源的可用性。仅仅通过功能仿真、时序仿真和测试向量 验证的 IP Core 是不完备的,它必须通过实际系统的验证。国际上各大公司通常采用 的办法是评估板验证,也即构建一个与实际系统 IP Core 应用一致的硬件环境,通过 下载 FPGA 配置使其具备相应的逻辑功能,并进行实物仿真。 另外,由于 IP Core 的许可成本较高,用户也通常希望在购买 IP Core 之前,对 其功能进行充分的验证以确定是否适合于目标系统,从而降低投资风险, (当然,内 核和源代码的知识产权是加了保护措施的) ,Xilinx 公司的 Sing Once 和 Altera 公 司的 Open Core 均提供了这样的平台。 Xilinx 公司和 Altera 公司均提供了许多用于评估 IP Core 的 FPGA 评估板,如 USB、MAC、IEEE1394 等等。许多第三方设计中心,如 Insight,还开发了用于 SOPC 系统集成的 Virtex II MicroBlaze 评估板和 Virtex II Pro PPC405 评估板等等。 Xilinx FPGA 的国内专业设计公司长沙依元素科技(http://www.eestd.com)还开发了 用于测评各类基本 IP Core 以及学习培训用途的数字刀剑?系列 (DigitalSword? Series Kit)评估板,如图 1 所示,该系列评估板提供了 VGA、LCD、音频、键盘鼠标、 串口、并口、USB Slave、I2C 等电平接口,并提供了标准扩展总线以及丰富的子板 功能模块支持。

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