当前位置:首页 >> 信息与通信 >>

Getting started with STM8L


AN3029 Application note
Getting started with STM8L
Introduction
This application note complements the information in the STM8L datasheets by describing the minimum hardware and

software environment required to build an application around an STM8L 8-bit microcontroller device. A brief description of the principal hardware components is given. The power supply, analog-to-digital converter (ADC), clock management, and reset control are described in some detail. In addition, some hardware recommendations are given. This application note also contains detailed reference design schematics with descriptions of the main components. The STM8L uses the same toolchain The STM8 development tools and software toolchain are common to STM8L, STM8S and STM8A and are presented in Section 8, and 9. Section 10 describes how to set up the STM8 development environment. Finally, Section 11 provides a list of relevant documentation and online support resources.

September 2009

Doc ID 16139 Rev 1

1/42
www.st.com

Contents

AN3029

Contents
1 2 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.1 4.3.2 4.3.3 4.3.4 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 15

5

Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 5.1.2 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2

Hardware reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6

Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 6.3 6.4 6.5 6.6 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/42

Doc ID 16139 Rev 1

AN3029

Contents

6.7 6.8

User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7

Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1.1 8.1.2 8.1.3 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2

STice emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2.1 8.2.2 8.2.3 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.3

RLink and STLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9

STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 9.2 9.3 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10

Setting up the STM8 development environment . . . . . . . . . . . . . . . . . 29
10.1 10.2 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2.1 10.2.2 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3

Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 34 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 16139 Rev 1

3/42

Contents

AN3029

11 12

Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42

Doc ID 16139 Rev 1

AN3029

List of tables

List of tables
Table 1. Table 2. Table 3. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc ID 16139 Rev 1

5/42

List of figures

AN3029

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Connecting the debug instrument to the STM8L101-EVAL evaluation board . . . . . . . . . . 35 Connecting the debug instrument to the STM8L15x-EVAL evaluation board . . . . . . . . . . 36 STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6/42

Doc ID 16139 Rev 1

AN3029

Hardware requirements summary

1

Hardware requirements summary
To build an application around an STM8L device, the application board should provide the following features:
● ● ● ●

Power supply (mandatory) Clock management (optional) Reset management (optional) Debugging tool support: Single wire interface module (SWIM) connector (optional)

2
2.1

Power supply
Power supply overview
The STM8L101 can be supplied through a 1.65 V to 3.6 V external source. The STM8L15x can be supplied through a 1.8 V to 3.6 V external source. However, after startup it can run on voltages down to 1.65 V. An on-chip power management system provides the constant digital supply to the core logic, both in normal and low power modes. This garantees that the logic consumes a constant current over the voltage range. It is also capable of detecting voltage drops and generate reset to avoid heratic behaviour. The STM8L device also provides:


One pair of pads, VDD/VSS (1.65 V or 1.8 V to 3.6 V) One pairs of pads dedicated for VDDIO/VSSIO, which are used to power only the I/O’s. VDDIO and VSSIO must be at the same potential respectively as VDD and VSS. One pair of pads, VDDA/VSSA, dedicated to analog functions. VDDA and VSSA must be at the same potential respectively as VDD and VSS. Refer to Section 3: Analog-to-digital converter (ADC) for more details.

The STM8L15x device also provides in the 48-pin package:
● ●

The STM8L152 device manages the supply voltage needed by the LCD in three different ways (see Figure 1): 1. 2. 3. If the LCD feature is not used, connect the VLCD pin to VDD. Apply to VLCD the voltage to be applied to the LCD. Leave the STM8L152 to provide the correct voltage, via its programmable LCD booster, by connecting the VLCD pin to a 1?F capacitor.

Doc ID 16139 Rev 1

7/42

Power supply Figure 1. Power supply
Only if internal booster is used to power LCD
To power LCD specii cally f 2.5V<VLCD<3.6V VDD For noisy environment 1uF OR OR

AN3029

If LCD is unused

For noisy environment

VDD

100uH

BEAD

VSS 100 O hm 1uF 100nF VSS VDD VSS 100nF VLCD VDDA VRef+ VDDIO VDD 1uF 100nF 100nF VSSIO OSC32_IN OSC_IN OSC_OUT NRST

3.6 V-1.8 V (1.65 V) (see note 1)

VSS/VSSA/VRef- OSC32_OUT Biggest package VSS

1. The device keeps operating as long as the battery voltage is above 1.65 V and no reset is generated.

Note:

The capacitors must be connected as close as possible to the device supplies. Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance ground must be connected as close as possible to VSS.

2.2

Main operating voltages
STM8L devices are processed in 0.13 ?m technology. The STM8L core and I/O peripherals need different power supplies. In fact, STM8L devices have an internal regulator with a nominal target output of 1.8 V.

8/42

Doc ID 16139 Rev 1

AN3029

Power supply

2.3

Power-on/power-down reset (POR/PDR)
The input supply to the main and low power regulators is monitored by a power-on/powerdown reset circuit. The monitoring voltage begins at 0.7 V. During power-on, the POR/PDR keeps the device under reset until the supply voltages (VDD and VDDIO) reach their specified working area. This internal reset is maintained during ~1ms in order to wait for supply stabilization. At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a reset release is defined in the electrical characteristics section of the product datasheets. A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall. The POR/PDR also generates a reset when the supply voltage drops below the VPOR/PDR threshold (isolated and repetitive events). For better power monitoring, the STM8L15x provides a programmable power voltage detection (PVD) and a brown out reset (BOR) for an earlier detection of voltage drop.

Recommendations
All pins need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have the lowest possible impedance. This is typically achieved with thick track widths and preferably dedicated power supply planes in multi-layer printed circuit boards (PCBs). In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C) at 100 nF with one chemical C (1..2 ?F) in parallel on the STM8L device. The ceramic capacitors should be placed as close as possible to the appropriate pins, or below the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 2 shows the typical layout of such a VDD/VSS pair. Figure 2. Typical layout of VDD/VSS pair
Via to VDD Cap. Via to VSS

VDD STM8

VSS

Doc ID 16139 Rev 1

9/42

Analog-to-digital converter (ADC)

AN3029

3

Analog-to-digital converter (ADC)
This section is unique for the STM8L15x.

3.1

Analog power
For 48-pin packages, the ADC unit has an independent, analog supply voltage, isolated on input pin VDDA, which allows the ADC to accept a very clean voltage source. This analog voltage, VDDA, should be identical to the digital voltage supply on pin VDD. To filter some noise, a ferrite bead can be added between VDD and VDDA. This ferrite bead should be choosen according to the frequencies to be filtered. The 48-pin package also provides a separate external analog reference voltage input for the ADC unit on the VREF+ pin. This gives better accuracy on low voltage input as follows:


VREF+ (input, analog reference positive): The higher/positive reference voltage for the ADC should be below or equal to VDDA. When VDDA is below 2.4 V, VREF+ must be equal to VDDA. This input is bonded to VDDA in devices that have no external VREF+ pin (packages with 32 pins or less). VREF- (input, analog reference negative): The lower/negative reference voltage is internally bonded to VSSA .



3.2

Analog input
STM8L15x devices have up to 28 analog input channels (including four fast channels), each multiplexed with an I/O, which are converted by the ADC one at a time. The analog input interface of the ADC is shown in Figure 3. The RADC, CADC, and IL real values are given in the chip datasheet. The external input impedance (RAIN) max value, in order to achieve an error below 1/4 of LSB can be calculated with the formula: Equation 1
Nsc R ain < ------------------------------------------------------------------------------------------------------- – R ADC 2 N+2 ( f CPU ? prescal ) × C TOTAL × In ( 2 )

Where: fCPU is the CPU frequency. Prescal is a programmable ADC clock prescaler with a value of 1 or 2. Usually fCPU/prescal is between 0.320 MHz and 16 MHz. Nsc is the programmable number of sampling cycles. Usually the minimum number of cycles is four and the maximum is 384. CTOTAL is the approximate sum of Cparasitic and CADC. N is the resolution which is programable between 6 and 12, but is usually 12. RADC is the sampling switch resistance which is usually around 1kΩ .. Please refer to Figure 3.

10/42

Doc ID 16139 Rev 1

AN3029 Figure 3. Analog input interface

Analog-to-digital converter (ADC)

STM8L15x

Please refer to the STM8L15x datasheet and reference manual for more details.

Doc ID 16139 Rev 1

11/42

Clock management

AN3029

4

Clock management
The STM8L101 has no external clock so no precautionary measures are needed. The following paragraph deals with STM8L15x chips only.

4.1

Clock management overview
STM8L15x devices offer a flexible way of selecting the core and peripheral clocks (ADC, memory, and digital peripherals). The devices have internal and external clock source inputs, both of which have a high speed and a low speed version. Any of those four clocks can be use for the CPU and most of the peripherals through a programable prescaler. An I/O can be programmed as output clock (CCO) to reflect one of the four clocks (with or without prescaling). The signal which leaves the I/O represents an output clock (CCO) divided by a division factor.

4.2

Internal clocks
STM8L devices have two kinds of internal clock: A high speed internal clock (HSI) running at 16 MHz and a low speed internal clock (LSI) running at 38 kHz. After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3

External clock
STM8L devices have two kinds of external clock: A high speed external clock (HSE) running at up to 16 MHz and a low speed external clock (LSE) running at 32.768 kHz.

4.3.1
Note:

HSE clock
STM8L15x devices can connect to an external crystal or an external oscillator. When no external clock is used, OSCIN and OSCOUT can be used as general purpose I/Os. Figure 4 describes the external clock connections.

External clock
● ●

Frequency: 0 kHz … 16 MHz Input hysteresis: 100 mV

Caution:

Without prescaler, a duty cycle of 45/55 % maximum must be respected at high speed

12/42

Doc ID 16139 Rev 1

AN3029