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msp430f2618头文件


/******************************************************************** * * Standard register and bit definitions for the Texas Instruments * MSP430 microcontroller. * * This file supports asse

mbler and C development for * MSP430x26x devices. * * Texas Instruments, Version 1.4 * * Rev. 1.0, Initial Version * Rev. 1.1, changed PAREN from sfrb to sfrw * Rev. 1.2 added TLV in INFO Memory * Rev. 1.3, added definitions for Interrupt Vectors xxIV * Rev. 1.4, changed 'void __data20 * volatile' definition * ********************************************************************/ #ifndef __msp430x26x #define __msp430x26x #ifdef __IAR_SYSTEMS_ICC__ #ifndef _SYSTEM_BUILD #pragma system_include #endif #endif #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */ #error msp430x26x.h file for use with ICC430/A430 only #endif

#ifdef __IAR_SYSTEMS_ICC__ #include <in430.h> #pragma language=extended #define DEFC(name, address) __no_init volatile unsigned char name @ address; #define DEFW(name, address) __no_init volatile unsigned short name @ address; #if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ #define DEFA(name, address) __no_init void __data20 * volatile name @ address; #else #define DEFA(name, address) __no_init volatile unsigned long name @ address;

#endif #define DEFXC volatile unsigned char #define DEFXW volatile unsigned short #if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ #define DEFXA void __data20 * volatile #else #define DEFXA volatile unsigned long #endif

#endif /* __IAR_SYSTEMS_ICC__

*/

#ifdef __IAR_SYSTEMS_ASM__ #define DEFC(name, address) sfrb name = address; #define DEFW(name, address) sfrw name = address; #define DEFA(name, address) sfrl name = address; #endif /* __IAR_SYSTEMS_ASM__*/ #ifdef __cplusplus #define READ_ONLY #else #define READ_ONLY const #endif /************************************************************ * STANDARD BITS ************************************************************/ #define BIT0 #define BIT1 #define BIT2 #define BIT3 #define BIT4 #define BIT5 #define BIT6 #define BIT7 #define BIT8 #define BIT9 #define BITA #define BITB #define BITC (0x0001) (0x0002) (0x0004) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080) (0x0100) (0x0200) (0x0400) (0x0800) (0x1000)

#define BITD #define BITE #define BITF

(0x2000) (0x4000) (0x8000)

/************************************************************ * STATUS REGISTER BITS ************************************************************/ #define C #define Z #define N #define V #define GIE #define CPUOFF #define OSCOFF #define SCG0 #define SCG1 (0x0001) (0x0002) (0x0004) (0x0100) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */ #ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */ #define LPM0 (CPUOFF) #define LPM1 (SCG0+CPUOFF) #define LPM2 (SCG1+CPUOFF) #define LPM3 (SCG1+SCG0+CPUOFF) #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) /* End #defines for assembler */ #else /* Begin #defines for C */ #define LPM0_bits #define LPM1_bits #define LPM2_bits #define LPM3_bits #define LPM4_bits #include <In430.h> #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */ #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */ #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */ #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */

(CPUOFF) (SCG0+CPUOFF) (SCG1+CPUOFF) (SCG1+SCG0+CPUOFF) (SCG1+SCG0+OSCOFF+CPUOFF)

#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */ #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */ #endif /* End #defines for C */ /************************************************************ * CPU ************************************************************/ #define __MSP430_HAS_MSP430X_CPU__ /* Definition to show that it has MSP430X CPU */ /************************************************************ * PERIPHERAL FILE MAP ************************************************************/ /************************************************************ * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS ************************************************************/ #define IE1_ DEFC( IE1 #define WDTIE #define OFIE #define NMIIE #define ACCVIE #define IFG1_ DEFC( IFG1 #define WDTIFG #define OFIFG #define PORIFG #define RSTIFG #define NMIIFG #define IE2_ DEFC( IE2 #define UC0IE #define UCA0RXIE #define UCA0TXIE #define UCB0RXIE #define UCB0TXIE #define IFG2_ DEFC( IFG2 (0x0000) /* Interrupt Enable 1 */ , IE1_) (0x01) /* Watchdog Interrupt Enable */ (0x02) /* Osc. Fault Interrupt Enable */ (0x10) /* NMI Interrupt Enable */ (0x20) /* Flash Access Violation Interrupt Enable */ (0x0002) /* Interrupt Flag 1 */ , IFG1_) (0x01) /* Watchdog Interrupt Flag */ (0x02) /* Osc. Fault Interrupt Flag */ (0x04) /* Power On Interrupt Flag */ (0x08) /* Reset Interrupt Flag */ (0x10) /* NMI Interrupt Flag */ (0x0001) /* Interrupt Enable 2 */ , IE2_) IE2 (0x01) (0x02) (0x04) (0x08) (0x0003) /* Interrupt Flag 2 */ , IFG2_)

#define UC0IFG #define UCA0RXIFG #define UCA0TXIFG #define UCB0RXIFG #define UCB0TXIFG #define UC1IE_ DEFC( UC1IE #define UCA1RXIE #define UCA1TXIE #define UCB1RXIE #define UCB1TXIE #define UC1IFG_ DEFC( UC1IFG #define UCA1RXIFG #define UCA1TXIFG #define UCB1RXIFG #define UCB1TXIFG

IFG2 (0x01) (0x02) (0x04) (0x08) (0x0006) /* USCI 1 Interrupt Enable */ , UC1IE_) (0x01) (0x02) (0x04) (0x08) (0x0007) /* ISCI 1 Interrupt Flags */ , UC1IFG_) (0x01) (0x02) (0x04) (0x08)

/************************************************************ * ADC12 ************************************************************/ #define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */ #define ADC12CTL0_ DEFW( ADC12CTL0 #define ADC12CTL1_ DEFW( ADC12CTL1 #define ADC12IFG_ DEFW( ADC12IFG #define ADC12IE_ DEFW( ADC12IE #define ADC12IV_ DEFW( ADC12IV #define ADC12MEM_ #ifndef __IAR_SYSTEMS_ICC #define ADC12MEM assembler) */ #else #define ADC12MEM */ #endif (0x01A0) /* ADC12 Control 0 */ , ADC12CTL0_) (0x01A2) /* ADC12 Control 1 */ , ADC12CTL1_) (0x01A4) /* ADC12 Interrupt Flag */ , ADC12IFG_) (0x01A6) /* ADC12 Interrupt Enable */ , ADC12IE_) (0x01A8) /* ADC12 Interrupt Vector Word */ , ADC12IV_) (0x0140) /* ADC12 Conversion Memory */ (ADC12MEM_) /* ADC12 Conversion Memory (for

((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C)

#define ADC12MEM0_ DEFW( ADC12MEM0 #define ADC12MEM1_ DEFW( ADC12MEM1 #define ADC12MEM2_ DEFW( ADC12MEM2 #define ADC12MEM3_ DEFW( ADC12MEM3 #define ADC12MEM4_ DEFW( ADC12MEM4 #define ADC12MEM5_ DEFW( ADC12MEM5 #define ADC12MEM6_ DEFW( ADC12MEM6 #define ADC12MEM7_ DEFW( ADC12MEM7 #define ADC12MEM8_ DEFW( ADC12MEM8 #define ADC12MEM9_ DEFW( ADC12MEM9 #define ADC12MEM10_ DEFW( ADC12MEM10 #define ADC12MEM11_ DEFW( ADC12MEM11 #define ADC12MEM12_ DEFW( ADC12MEM12 #define ADC12MEM13_ DEFW( ADC12MEM13 #define ADC12MEM14_ DEFW( ADC12MEM14 #define ADC12MEM15_ DEFW( ADC12MEM15 #define ADC12MCTL_ #ifndef __IAR_SYSTEMS_ICC #define ADC12MCTL */ #else #define ADC12MCTL */ #endif #define ADC12MCTL0_ DEFC( ADC12MCTL0 #define ADC12MCTL1_

(0x0140) /* ADC12 Conversion Memory 0 */ , ADC12MEM0_) (0x0142) /* ADC12 Conversion Memory 1 */ , ADC12MEM1_) (0x0144) /* ADC12 Conversion Memory 2 */ , ADC12MEM2_) (0x0146) /* ADC12 Conversion Memory 3 */ , ADC12MEM3_) (0x0148) /* ADC12 Conversion Memory 4 */ , ADC12MEM4_) (0x014A) /* ADC12 Conversion Memory 5 */ , ADC12MEM5_) (0x014C) /* ADC12 Conversion Memory 6 */ , ADC12MEM6_) (0x014E) /* ADC12 Conversion Memory 7 */ , ADC12MEM7_) (0x0150) /* ADC12 Conversion Memory 8 */ , ADC12MEM8_) (0x0152) /* ADC12 Conversion Memory 9 */ , ADC12MEM9_) (0x0154) /* ADC12 Conversion Memory 10 */ , ADC12MEM10_) (0x0156) /* ADC12 Conversion Memory 11 */ , ADC12MEM11_) (0x0158) /* ADC12 Conversion Memory 12 */ , ADC12MEM12_) (0x015A) /* ADC12 Conversion Memory 13 */ , ADC12MEM13_) (0x015C) /* ADC12 Conversion Memory 14 */ , ADC12MEM14_) (0x015E) /* ADC12 Conversion Memory 15 */ , ADC12MEM15_) (0x0080) /* ADC12 Memory Control */ (ADC12MCTL_) /* ADC12 Memory Control (for assembler)

((char*) ADC12MCTL_) /* ADC12 Memory Control (for C)

(0x0080) /* ADC12 Memory Control 0 */ , ADC12MCTL0_) (0x0081) /* ADC12 Memory Control 1 */

DEFC( ADC12MCTL1 #define ADC12MCTL2_ DEFC( ADC12MCTL2 #define ADC12MCTL3_ DEFC( ADC12MCTL3 #define ADC12MCTL4_ DEFC( ADC12MCTL4 #define ADC12MCTL5_ DEFC( ADC12MCTL5 #define ADC12MCTL6_ DEFC( ADC12MCTL6 #define ADC12MCTL7_ DEFC( ADC12MCTL7 #define ADC12MCTL8_ DEFC( ADC12MCTL8 #define ADC12MCTL9_ DEFC( ADC12MCTL9 #define ADC12MCTL10_ DEFC( ADC12MCTL10 #define ADC12MCTL11_ DEFC( ADC12MCTL11 #define ADC12MCTL12_ DEFC( ADC12MCTL12 #define ADC12MCTL13_ DEFC( ADC12MCTL13 #define ADC12MCTL14_ DEFC( ADC12MCTL14 #define ADC12MCTL15_ DEFC( ADC12MCTL15 /* ADC12CTL0 */ #define ADC12SC #define ENC #define ADC12TOVIE #define ADC12OVIE #define ADC12ON #define REFON #define REF2_5V #define MSC #define SHT00 #define SHT01 #define SHT02 #define SHT03 #define SHT10

, ADC12MCTL1_) (0x0082) /* ADC12 Memory Control 2 */ , ADC12MCTL2_) (0x0083) /* ADC12 Memory Control 3 */ , ADC12MCTL3_) (0x0084) /* ADC12 Memory Control 4 */ , ADC12MCTL4_) (0x0085) /* ADC12 Memory Control 5 */ , ADC12MCTL5_) (0x0086) /* ADC12 Memory Control 6 */ , ADC12MCTL6_) (0x0087) /* ADC12 Memory Control 7 */ , ADC12MCTL7_) (0x0088) /* ADC12 Memory Control 8 */ , ADC12MCTL8_) (0x0089) /* ADC12 Memory Control 9 */ , ADC12MCTL9_) (0x008A) /* ADC12 Memory Control 10 */ , ADC12MCTL10_) (0x008B) /* ADC12 Memory Control 11 */ , ADC12MCTL11_) (0x008C) /* ADC12 Memory Control 12 */ , ADC12MCTL12_) (0x008D) /* ADC12 Memory Control 13 */ , ADC12MCTL13_) (0x008E) /* ADC12 Memory Control 14 */ , ADC12MCTL14_) (0x008F) /* ADC12 Memory Control 15 */ , ADC12MCTL15_)

(0x001) (0x002) (0x004) (0x008) (0x010) (0x020) (0x040) (0x080) (0x0100) (0x0200) (0x0400) (0x0800) (0x1000)

/* ADC12 Start Conversion */ /* ADC12 Enable Conversion */ /* ADC12 Timer Overflow interrupt enable */ /* ADC12 Overflow interrupt enable */ /* ADC12 On/enable */ /* ADC12 Reference on */ /* ADC12 Ref 0:1.5V / 1:2.5V */ /* ADC12 Multiple SampleConversion */ /* ADC12 Sample Hold 0 Select 0 */ /* ADC12 Sample Hold 0 Select 1 */ /* ADC12 Sample Hold 0 Select 2 */ /* ADC12 Sample Hold 0 Select 3 */ /* ADC12 Sample Hold 0 Select 0 */

#define SHT11 #define SHT12 #define SHT13 #define MSH #define SHT0_0 #define SHT0_1 #define SHT0_2 #define SHT0_3 #define SHT0_4 #define SHT0_5 #define SHT0_6 #define SHT0_7 #define SHT0_8 #define SHT0_9 #define SHT0_10 #define SHT0_11 #define SHT0_12 #define SHT0_13 #define SHT0_14 #define SHT0_15 #define SHT1_0 #define SHT1_1 #define SHT1_2 #define SHT1_3 #define SHT1_4 #define SHT1_5 #define SHT1_6 #define SHT1_7 #define SHT1_8 #define SHT1_9 #define SHT1_10 #define SHT1_11 #define SHT1_12 #define SHT1_13 #define SHT1_14 #define SHT1_15 /* ADC12CTL1 */ #define ADC12BUSY #define CONSEQ0 #define CONSEQ1 #define ADC12SSEL0

(0x2000) /* ADC12 Sample Hold 1 Select 1 */ (0x4000) /* ADC12 Sample Hold 2 Select 2 */ (0x8000) /* ADC12 Sample Hold 3 Select 3 */ (0x080) (0*0x100u) (1*0x100u) (2*0x100u) (3*0x100u) (4*0x100u) (5*0x100u) (6*0x100u) (7*0x100u) (8*0x100u) (9*0x100u) (10*0x100u) (11*0x100u) (12*0x100u) (13*0x100u) (14*0x100u) (15*0x100u) (0*0x1000u) (1*0x1000u) (2*0x1000u) (3*0x1000u) (4*0x1000u) (5*0x1000u) (6*0x1000u) (7*0x1000u) (8*0x1000u) (9*0x1000u) (10*0x1000u) (11*0x1000u) (12*0x1000u) (13*0x1000u) (14*0x1000u) (15*0x1000u)

(0x0001) (0x0002) (0x0004) (0x0008)

/* ADC12 Busy */ /* ADC12 Conversion Sequence Select 0 */ /* ADC12 Conversion Sequence Select 1 */ /* ADC12 Clock Source Select 0 */

#define ADC12SSEL1 #define ADC12DIV0 #define ADC12DIV1 #define ADC12DIV2 #define ISSH #define SHP #define SHS0 #define SHS1 #define CSTARTADD0 #define CSTARTADD1 #define CSTARTADD2 #define CSTARTADD3 #define CONSEQ_0 #define CONSEQ_1 #define CONSEQ_2 #define CONSEQ_3 #define ADC12SSEL_0 #define ADC12SSEL_1 #define ADC12SSEL_2 #define ADC12SSEL_3 #define ADC12DIV_0 #define ADC12DIV_1 #define ADC12DIV_2 #define ADC12DIV_3 #define ADC12DIV_4 #define ADC12DIV_5 #define ADC12DIV_6 #define ADC12DIV_7 #define SHS_0 #define SHS_1 #define SHS_2 #define SHS_3 #define CSTARTADD_0 #define CSTARTADD_1 #define CSTARTADD_2 #define CSTARTADD_3 #define CSTARTADD_4 #define CSTARTADD_5 #define CSTARTADD_6 #define CSTARTADD_7 #define CSTARTADD_8 #define CSTARTADD_9 #define CSTARTADD_10

(0x0010) /* ADC12 Clock Source Select 1 */ (0x0020) /* ADC12 Clock Divider Select 0 */ (0x0040) /* ADC12 Clock Divider Select 1 */ (0x0080) /* ADC12 Clock Divider Select 2 */ (0x0100) /* ADC12 Invert Sample Hold Signal */ (0x0200) /* ADC12 Sample/Hold Pulse Mode */ (0x0400) /* ADC12 Sample/Hold Source 0 */ (0x0800) /* ADC12 Sample/Hold Source 1 */ (0x1000) /* ADC12 Conversion Start Address 0 */ (0x2000) /* ADC12 Conversion Start Address 1 */ (0x4000) /* ADC12 Conversion Start Address 2 */ (0x8000) /* ADC12 Conversion Start Address 3 */ (0*2u) (1*2u) (2*2u) (3*2u) (0*8u) (1*8u) (2*8u) (3*8u) (0*0x20u) (1*0x20u) (2*0x20u) (3*0x20u) (4*0x20u) (5*0x20u) (6*0x20u) (7*0x20u) (0*0x400u) (1*0x400u) (2*0x400u) (3*0x400u) (0*0x1000u) (1*0x1000u) (2*0x1000u) (3*0x1000u) (4*0x1000u) (5*0x1000u) (6*0x1000u) (7*0x1000u) (8*0x1000u) (9*0x1000u) (10*0x1000u)

#define CSTARTADD_11 #define CSTARTADD_12 #define CSTARTADD_13 #define CSTARTADD_14 #define CSTARTADD_15 /* ADC12MCTLx */ #define INCH0 #define INCH1 #define INCH2 #define INCH3 #define SREF0 #define SREF1 #define SREF2 #define EOS #define INCH_0 #define INCH_1 #define INCH_2 #define INCH_3 #define INCH_4 #define INCH_5 #define INCH_6 #define INCH_7 #define INCH_8 #define INCH_9 #define INCH_10 #define INCH_11 #define INCH_12 #define INCH_13 #define INCH_14 #define INCH_15 #define SREF_0 #define SREF_1 #define SREF_2 #define SREF_3 #define SREF_4 #define SREF_5 #define SREF_6 #define SREF_7 /* ADC12IV Definitions */ #define ADC12IV_NONE

(11*0x1000u) (12*0x1000u) (13*0x1000u) (14*0x1000u) (15*0x1000u)

(0x0001) (0x0002) (0x0004) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080) (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (0*0x10u) (1*0x10u) (2*0x10u) (3*0x10u) (4*0x10u) (5*0x10u) (6*0x10u) (7*0x10u)

/* ADC12 Input Channel Select Bit 0 */ /* ADC12 Input Channel Select Bit 1 */ /* ADC12 Input Channel Select Bit 2 */ /* ADC12 Input Channel Select Bit 3 */ /* ADC12 Select Reference Bit 0 */ /* ADC12 Select Reference Bit 1 */ /* ADC12 Select Reference Bit 2 */ /* ADC12 End of Sequence */

(0x0000)

/* No Interrupt pending */

#define ADC12IV_ADC12OVIFG (0x0002) #define ADC12IV_ADC12TOVIFG (0x0004) #define ADC12IV_ADC12IFG0 (0x0006) #define ADC12IV_ADC12IFG1 (0x0008) #define ADC12IV_ADC12IFG2 (0x000A) #define ADC12IV_ADC12IFG3 (0x000C) #define ADC12IV_ADC12IFG4 (0x000E) #define ADC12IV_ADC12IFG5 (0x0010) #define ADC12IV_ADC12IFG6 (0x0012) #define ADC12IV_ADC12IFG7 (0x0014) #define ADC12IV_ADC12IFG8 (0x0016) #define ADC12IV_ADC12IFG9 (0x0018) #define ADC12IV_ADC12IFG10 (0x001A) #define ADC12IV_ADC12IFG11 (0x001C) #define ADC12IV_ADC12IFG12 (0x001E) #define ADC12IV_ADC12IFG13 (0x0020) #define ADC12IV_ADC12IFG14 (0x0022) #define ADC12IV_ADC12IFG15 (0x0024)

/* ADC12OVIFG */ /* ADC12TOVIFG */ /* ADC12IFG0 */ /* ADC12IFG1 */ /* ADC12IFG2 */ /* ADC12IFG3 */ /* ADC12IFG4 */ /* ADC12IFG5 */ /* ADC12IFG6 */ /* ADC12IFG7 */ /* ADC12IFG8 */ /* ADC12IFG9 */ /* ADC12IFG10 */ /* ADC12IFG11 */ /* ADC12IFG12 */ /* ADC12IFG13 */ /* ADC12IFG14 */ /* ADC12IFG15 */

/************************************************************ * Basic Clock Module ************************************************************/ #define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ #define DCOCTL_ DEFC( DCOCTL #define BCSCTL1_ DEFC( BCSCTL1 #define BCSCTL2_ DEFC( BCSCTL2 #define BCSCTL3_ DEFC( BCSCTL3 #define MOD0 #define MOD1 #define MOD2 #define MOD3 #define MOD4 #define DCO0 #define DCO1 #define DCO2 #define RSEL0 #define RSEL1 (0x0056) /* DCO Clock Frequency Control */ , DCOCTL_) (0x0057) /* Basic Clock System Control 1 */ , BCSCTL1_) (0x0058) /* Basic Clock System Control 2 */ , BCSCTL2_) (0x0053) /* Basic Clock System Control 3 */ , BCSCTL3_) (0x01) (0x02) (0x04) (0x08) (0x10) (0x20) (0x40) (0x80) (0x01) (0x02) /* Modulation Bit 0 */ /* Modulation Bit 1 */ /* Modulation Bit 2 */ /* Modulation Bit 3 */ /* Modulation Bit 4 */ /* DCO Select Bit 0 */ /* DCO Select Bit 1 */ /* DCO Select Bit 2 */ /* Range Select Bit 0 */ /* Range Select Bit 1 */

#define RSEL2 #define RSEL3 #define DIVA0 #define DIVA1 #define XTS #define XT2OFF #define DIVA_0 #define DIVA_1 #define DIVA_2 #define DIVA_3 #define DCOR #define DIVS0 #define DIVS1 #define SELS 1:XT2CLK/LFXTCLK */ #define DIVM0 #define DIVM1 #define SELM0 #define SELM1 #define DIVS_0 #define DIVS_1 #define DIVS_2 #define DIVS_3 #define DIVM_0 #define DIVM_1 #define DIVM_2 #define DIVM_3 #define SELM_0 #define SELM_1 #define SELM_2 #define SELM_3 #define LFXT1OF #define XT2OF #define XCAP0 #define XCAP1 #define LFXT1S0 #define LFXT1S1 #define XT2S0

(0x04) (0x08) (0x10) (0x20) (0x40) (0x80) (0x00) (0x10) (0x20) (0x30) (0x01) (0x02) (0x04)

/* Range Select Bit 2 */ /* Range Select Bit 3 */ /* ACLK Divider 0 */ /* ACLK Divider 1 */ /* LFXTCLK 0:Low Freq. / 1: High Freq. */ /* Enable XT2CLK */ /* ACLK Divider 0: /1 */ /* ACLK Divider 1: /2 */ /* ACLK Divider 2: /4 */ /* ACLK Divider 3: /8 */ /* Enable External Resistor : 1 */ /* SMCLK Divider 0 */ /* SMCLK Divider 1 */ (0x08) /* SMCLK Source Select 0:DCOCLK / /* MCLK Divider 0 */ /* MCLK Divider 1 */ /* MCLK Source Select 0 */ /* MCLK Source Select 1 */ /* SMCLK Divider 0: /1 */ /* SMCLK Divider 1: /2 */ /* SMCLK Divider 2: /4 */ /* SMCLK Divider 3: /8 */ /* MCLK Divider 0: /1 */ /* MCLK Divider 1: /2 */ /* MCLK Divider 2: /4 */ /* MCLK Divider 3: /8 */ /* MCLK Source Select 0: DCOCLK */ /* MCLK Source Select 1: DCOCLK */ /* MCLK Source Select 2: XT2CLK/LFXTCLK */ /* MCLK Source Select 3: LFXTCLK */ /* Low/high Frequency Oscillator Fault Flag */ /* High frequency oscillator 2 fault flag */ /* XIN/XOUT Cap 0 */ /* XIN/XOUT Cap 1 */ /* Mode 0 for LFXT1 (XTS = 0) */ /* Mode 1 for LFXT1 (XTS = 0) */ /* Mode 0 for XT2 */

(0x10) (0x20) (0x40) (0x80) (0x00) (0x02) (0x04) (0x06) (0x00) (0x10) (0x20) (0x30) (0x00) (0x40) (0x80) (0xC0) (0x01) (0x02) (0x04) (0x08) (0x10) (0x20) (0x40)

#define XT2S1 #define XCAP_0 #define XCAP_1 #define XCAP_2 #define XCAP_3 #define LFXT1S_0 #define LFXT1S_1 #define LFXT1S_2 #define LFXT1S_3 #define XT2S_0 #define XT2S_1 #define XT2S_2 #define XT2S_3

(0x80) (0x00) (0x04) (0x08) (0x0C) (0x00) (0x10) (0x20) (0x30) (0x00) (0x40) (0x80) (0xC0)

/* Mode 1 for XT2 */ /* XIN/XOUT Cap : 0 pF */ /* XIN/XOUT Cap : 6 pF */ /* XIN/XOUT Cap : 10 pF */ /* XIN/XOUT Cap : 12.5 pF */ /* Mode 0 for LFXT1 : Normal operation */ /* Mode 1 for LFXT1 : Reserved */ /* Mode 2 for LFXT1 : VLO */ /* Mode 3 for LFXT1 : Digital input signal */ /* Mode 0 for XT2 : 0.4 - 1 MHz */ /* Mode 1 for XT2 : 1 - 4 MHz */ /* Mode 2 for XT2 : 2 - 16 MHz */ /* Mode 3 for XT2 : Digital input signal */

/************************************************************ * Comparator A ************************************************************/ #define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */ #define CACTL1_ DEFC( CACTL1 #define CACTL2_ DEFC( CACTL2 #define CAPD_ DEFC( CAPD #define CAIFG #define CAIE #define CAIES #define CAON #define CAREF0 #define CAREF1 #define CARSEL #define CAEX #define CAREF_0 #define CAREF_1 #define CAREF_2 #define CAREF_3 #define CAOUT (0x0059) /* Comparator A Control 1 */ , CACTL1_) (0x005A) /* Comparator A Control 2 */ , CACTL2_) (0x005B) /* Comparator A Port Disable */ , CAPD_) (0x01) (0x02) (0x04) (0x08) (0x10) (0x20) (0x40) (0x80) (0x00) (0x10) (0x20) (0x30) (0x01) /* Comp. A Interrupt Flag */ /* Comp. A Interrupt Enable */ /* Comp. A Int. Edge Select: 0:rising / 1:falling */ /* Comp. A enable */ /* Comp. A Internal Reference Select 0 */ /* Comp. A Internal Reference Select 1 */ /* Comp. A Internal Reference Enable */ /* Comp. A Exchange Inputs */ /* Comp. A Int. Ref. Select 0 : Off */ /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ /* Comp. A Int. Ref. Select 3 : Vt*/ /* Comp. A Output */

#define CAF #define P2CA0 #define P2CA1 #define P2CA2 #define P2CA3 #define P2CA4 #define CASHORT #define CAPD0 */ #define CAPD1 */ #define CAPD2 */ #define CAPD3 */ #define CAPD4 */ #define CAPD5 */ #define CAPD6 */ #define CAPD7 */

(0x02) (0x04) (0x08) (0x10) (0x20) (0x40) (0x80) (0x01) (0x02) (0x04) (0x08) (0x10) (0x20) (0x40) (0x80)

/* Comp. A Enable Output Filter */ /* Comp. A +Terminal Multiplexer */ /* Comp. A -Terminal Multiplexer */ /* Comp. A -Terminal Multiplexer */ /* Comp. A -Terminal Multiplexer */ /* Comp. A +Terminal Multiplexer */ /* Comp. A Short + and - Terminals */ /* Comp. A Disable Input Buffer of Port Register .0 /* Comp. A Disable Input Buffer of Port Register .1 /* Comp. A Disable Input Buffer of Port Register .2 /* Comp. A Disable Input Buffer of Port Register .3 /* Comp. A Disable Input Buffer of Port Register .4 /* Comp. A Disable Input Buffer of Port Register .5 /* Comp. A Disable Input Buffer of Port Register .6 /* Comp. A Disable Input Buffer of Port Register .7

/************************************************************ * DAC12 ************************************************************/ #define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ #define DAC12_0CTL_ DEFW( DAC12_0CTL #define DAC12_1CTL_ DEFW( DAC12_1CTL #define DAC12GRP #define DAC12ENC #define DAC12IFG #define DAC12IE #define DAC12DF #define DAC12AMP0 #define DAC12AMP1 #define DAC12AMP2 (0x01c0) /* DAC12_0 Control */ , DAC12_0CTL_) (0x01c2) /* DAC12_1 Control */ , DAC12_1CTL_) (0x0001) (0x0002) (0x0004) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080) /* DAC12 group */ /* DAC12 enable conversion */ /* DAC12 interrupt flag */ /* DAC12 interrupt enable */ /* DAC12 data format */ /* DAC12 amplifier bit 0 */ /* DAC12 amplifier bit 1 */ /* DAC12 amplifier bit 2 */

#define DAC12IR #define DAC12CALON #define DAC12LSEL0 #define DAC12LSEL1 #define DAC12RES #define DAC12SREF0 #define DAC12SREF1 #define DAC12OPS #define DAC12AMP_0 #define DAC12AMP_1 #define DAC12AMP_2 #define DAC12AMP_3 #define DAC12AMP_4 #define DAC12AMP_5 #define DAC12AMP_6 #define DAC12AMP_7 #define DAC12LSEL_0 #define DAC12LSEL_1 #define DAC12LSEL_2 Timer_A3.OUT1 */ #define DAC12LSEL_3 Timer_B7.OUT1 */ #define DAC12SREF_0 #define DAC12SREF_1 #define DAC12SREF_2 #define DAC12SREF_3

(0x0100) (0x0200) (0x0400) (0x0800) (0x1000) (0x2000) (0x4000) (0x8000)

/* DAC12 input reference and output range */ /* DAC12 calibration */ /* DAC12 load select bit 0 */ /* DAC12 load select bit 1 */ /* DAC12 resolution */ /* DAC12 reference bit 0 */ /* DAC12 reference bit 1 */ /* DAC12 Operation Amp. */ /* DAC12 amplifier 0: off, 3-state */ /* DAC12 amplifier 1: off, off */ /* DAC12 amplifier 2: low, low */ /* DAC12 amplifier 3: low, medium */ /* DAC12 amplifier 4: low, high */ /* DAC12 amplifier 5: medium, medium */ /* DAC12 amplifier 6: medium, high */ /* DAC12 amplifier 7: high, high */

(0*0x0020u) (1*0x0020u) (2*0x0020u) (3*0x0020u) (4*0x0020u) (5*0x0020u) (6*0x0020u) (7*0x0020u)

(0*0x0400u) /* DAC12 load select 0: direct */ (1*0x0400u) /* DAC12 load select 1: latched with DAT */ (2*0x0400u) /* DAC12 load select 2: latched with pos. (3*0x0400u) /* DAC12 load select 3: latched with pos.

(0*0x2000u) /* DAC12 reference 0: Vref+ */ (1*0x2000u) /* DAC12 reference 1: Vref+ */ (2*0x2000u) /* DAC12 reference 2: Veref+ */ (3*0x2000u) /* DAC12 reference 3: Veref+ */

#define DAC12_0DAT_ (0x01c8) /* DAC12_0 Data */ DEFW( DAC12_0DAT , DAC12_0DAT_) #define DAC12_1DAT_ (0x01ca) /* DAC12_1 Data */ DEFW( DAC12_1DAT , DAC12_1DAT_) /************************************************************ * DMA_X ************************************************************/ #define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ #define DMACTL0_ DEFW( DMACTL0 #define DMA0TSEL0 #define DMA0TSEL1 (0x0122) /* DMA Module Control 0 */ , DMACTL0_) (0x0001) /* DMA channel 0 transfer select bit 0 */ (0x0002) /* DMA channel 0 transfer select bit 1 */

#define DMA0TSEL2 #define DMA0TSEL3 #define DMA1TSEL0 #define DMA1TSEL1 #define DMA1TSEL2 #define DMA1TSEL3 #define DMA2TSEL0 #define DMA2TSEL1 #define DMA2TSEL2 #define DMA2TSEL3 #define DMA0TSEL_0 DMA_REQ (sw)*/ #define DMA0TSEL_1 (TACCR2.IFG) */ #define DMA0TSEL_2 (TBCCR2.IFG) */ #define DMA0TSEL_3 receive */ #define DMA0TSEL_4 transmit */ #define DMA0TSEL_5 DAC12_0CTL.DAC12IFG */ #define DMA0TSEL_6 (ADC12IFG) */ #define DMA0TSEL_7 (TACCR0.IFG) */ #define DMA0TSEL_8 (TBCCR0.IFG) */ #define DMA0TSEL_9 receive */ #define DMA0TSEL_10 transmit */ #define DMA0TSEL_11 ready */ #define DMA0TSEL_12 receive */ #define DMA0TSEL_13 transmit */ #define DMA0TSEL_14 DMA channel DMA2IFG */ #define DMA0TSEL_15 Trigger (DMAE0) */

(0x0004) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080) (0x0100) (0x0200) (0x0400) (0x0800)

/* DMA channel 0 transfer select bit 2 */ /* DMA channel 0 transfer select bit 3 */ /* DMA channel 1 transfer select bit 0 */ /* DMA channel 1 transfer select bit 1 */ /* DMA channel 1 transfer select bit 2 */ /* DMA channel 1 transfer select bit 3 */ /* DMA channel 2 transfer select bit 0 */ /* DMA channel 2 transfer select bit 1 */ /* DMA channel 2 transfer select bit 2 */ /* DMA channel 2 transfer select bit 3 */ /* DMA channel 0 transfer select 0:

(0*0x0001u)

(1*0x0001u) /* DMA channel 0 transfer select 1: Timer_A (2*0x0001u) /* DMA channel 0 transfer select 2: Timer_B (3*0x0001u) /* DMA channel 0 transfer select 3: USCIA0 (4*0x0001u) /* DMA channel 0 transfer select 4: USCIA0 (5*0x0001u) /* DMA channel 0 transfer select 5:

(6*0x0001u) /* DMA channel 0 transfer select 6: ADC12 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer_A (8*0x0001u) /* DMA channel 0 transfer select 8: Timer_B

(9*0x0001u) /* DMA channel 0 transfer select 9: USCIA1 (10*0x0001u) /* DMA channel 0 transfer select 10: USCIA1 (11*0x0001u) /* DMA channel 0 transfer select 11: Multiplier (12*0x0001u) /* DMA channel 0 transfer select 12: USCIB0 (13*0x0001u) /* DMA channel 0 transfer select 13: USCIB0 (14*0x0001u) /* DMA channel 0 transfer select 14: previous (15*0x0001u) /* DMA channel 0 transfer select 15: ext.

#define DMA1TSEL_0 DMA_REQ */ #define DMA1TSEL_1 CCRIFG.2 */ #define DMA1TSEL_2 CCRIFG.2 */ #define DMA1TSEL_3 receive */ #define DMA1TSEL_4 transmit */ #define DMA1TSEL_5 DAC12.0IFG */ #define DMA1TSEL_6 (ADC12IFG) */ #define DMA1TSEL_7 (TACCR0.IFG) */ #define DMA1TSEL_8 (TBCCR0.IFG) */ #define DMA1TSEL_9 receive */ #define DMA1TSEL_10 transmit */ #define DMA1TSEL_11 ready */ #define DMA1TSEL_12 receive */ #define DMA1TSEL_13 transmit */ #define DMA1TSEL_14 DMA channel DMA0IFG */ #define DMA1TSEL_15 Trigger (DMAE0) */ #define DMA2TSEL_0 DMA_REQ */ #define DMA2TSEL_1 CCRIFG.2 */ #define DMA2TSEL_2 CCRIFG.2 */ #define DMA2TSEL_3 receive */ #define DMA2TSEL_4 transmit */ #define DMA2TSEL_5

(0*0x0010u)

/* DMA channel 1 transfer select 0:

(1*0x0010u) /* DMA channel 1 transfer select 1: Timer_A (2*0x0010u) /* DMA channel 1 transfer select 2: Timer_B (3*0x0010u) /* DMA channel 1 transfer select 3: USCIA0 (4*0x0010u) /* DMA channel 1 transfer select 4: USCIA0 (5*0x0010u) /* DMA channel 1 transfer select 5:

(6*0x0010u) /* DMA channel 1 transfer select 6: ADC12 (7*0x0010u) /* DMA channel 1 transfer select 7: Timer_A (8*0x0010u) /* DMA channel 1 transfer select 8: Timer_B (9*0x0010u) /* DMA channel 1 transfer select 9: USCIA1 (10*0x0010u) /* DMA channel 1 transfer select 10: USCIA1 (11*0x0010u) /* DMA channel 1 transfer select 11: Multiplier (12*0x0010u) /* DMA channel 1 transfer select 12: USCIB0 (13*0x0010u) /* DMA channel 1 transfer select 13: USCIB0 (14*0x0010u) /* DMA channel 1 transfer select 14: previous (15*0x0010u) /* DMA channel 1 transfer select 15: ext.

(0*0x0100u)

/* DMA channel 2 transfer select 0:

(1*0x0100u) /* DMA channel 2 transfer select 1: Timer_A (2*0x0100u) /* DMA channel 2 transfer select 2: Timer_B (3*0x0100u) /* DMA channel 2 transfer select 3: USCIA0 (4*0x0100u) /* DMA channel 2 transfer select 4: USCIA0 (5*0x0100u) /* DMA channel 2 transfer select 5:

DAC12.0IFG */ #define DMA2TSEL_6 (ADC12IFG) */ #define DMA2TSEL_7 (TACCR0.IFG) */ #define DMA2TSEL_8 (TBCCR0.IFG) */ #define DMA2TSEL_9 receive */ #define DMA2TSEL_10 transmit */ #define DMA2TSEL_11 ready */ #define DMA2TSEL_12 receive */ #define DMA2TSEL_13 transmit */ #define DMA2TSEL_14 DMA channel DMA1IFG */ #define DMA2TSEL_15 Trigger (DMAE0) */ #define DMACTL1_ DEFW( DMACTL1 #define ENNMI #define ROUNDROBIN #define DMAONFETCH #define DMAIV_ DEFW( DMAIV #define DMA0CTL_ DEFW( DMA0CTL #define DMA1CTL_ DEFW( DMA1CTL #define DMA2CTL_ DEFW( DMA2CTL #define DMAREQ #define DMAABORT #define DMAIE #define DMAIFG #define DMAEN #define DMALEVEL #define DMASRCBYTE

(6*0x0100u) /* DMA channel 2 transfer select 6: ADC12 (7*0x0100u) /* DMA channel 2 transfer select 7: Timer_A (8*0x0100u) /* DMA channel 2 transfer select 8: Timer_B (9*0x0100u) /* DMA channel 2 transfer select 9: USCIA1 (10*0x0100u) /* DMA channel 2 transfer select 10: USCIA1 (11*0x0100u) /* DMA channel 2 transfer select 11: Multiplier (12*0x0100u) /* DMA channel 2 transfer select 12: USCIB0 (13*0x0100u) /* DMA channel 2 transfer select 13: USCIB0 (14*0x0100u) /* DMA channel 2 transfer select 14: previous (15*0x0100u) /* DMA channel 2 transfer select 15: ext.

(0x0124) /* DMA Module Control 1 */ , DMACTL1_) (0x0001) /* Enable NMI interruption of DMA */ (0x0002) /* Round-Robin DMA channel priorities */ (0x0004) /* DMA transfer on instruction fetch */ (0x0126) /* DMA Interrupt Vector Word */ , DMAIV_) (0x01d0) /* DMA Channel 0 Control */ , DMA0CTL_) (0x01dc) /* DMA Channel 1 Control */ , DMA1CTL_) (0x01e8) /* DMA Channel 2 Control */ , DMA2CTL_) (0x0001) /* Initiate DMA transfer with DMATSEL */ (0x0002) /* DMA transfer aborted by NMI */ (0x0004) /* DMA interrupt enable */ (0x0008) /* DMA interrupt flag */ (0x0010) /* DMA enable */ (0x0020) /* DMA level sensitive trigger select */ (0x0040) /* DMA source byte */

#define DMADSTBYTE #define DMASRCINCR0 #define DMASRCINCR1 #define DMADSTINCR0 #define DMADSTINCR1 #define DMADT0 #define DMADT1 #define DMADT2 #define DMASWDW word */ #define DMASBDW word */ #define DMASWDB byte */ #define DMASBDB byte */ #define DMASRCINCR_0 unchanged */ #define DMASRCINCR_1 unchanged */ #define DMASRCINCR_2 decremented */ #define DMASRCINCR_3 incremented */ #define DMADSTINCR_0 address unchanged */ #define DMADSTINCR_1 address unchanged */ #define DMADSTINCR_2 address decremented */ #define DMADSTINCR_3 address incremented */ #define DMADT_0 #define DMADT_1 #define DMADT_2 #define DMADT_3 #define DMADT_4 #define DMADT_5 #define DMADT_6 #define DMADT_7

(0x0080) (0x0100) (0x0200) (0x0400) (0x0800) (0x1000) (0x2000) (0x4000)

/* DMA destination byte */ /* DMA source increment bit 0 */ /* DMA source increment bit 1 */ /* DMA destination increment bit 0 */ /* DMA destination increment bit 1 */ /* DMA transfer mode bit 0 */ /* DMA transfer mode bit 1 */ /* DMA transfer mode bit 2 */

(0*0x0040u) /* DMA transfer: source word to destination (1*0x0040u) /* DMA transfer: source byte to destination (2*0x0040u) /* DMA transfer: source word to destination (3*0x0040u) /* DMA transfer: source byte to destination

(0*0x0100u) /* DMA source increment 0: source address (1*0x0100u) /* DMA source increment 1: source address (2*0x0100u) /* DMA source increment 2: source address (3*0x0100u) /* DMA source increment 3: source address

(0*0x0400u) /* DMA destination increment 0: destination (1*0x0400u) /* DMA destination increment 1: destination (2*0x0400u) /* DMA destination increment 2: destination (3*0x0400u) /* DMA destination increment 3: destination

(0*0x1000u) (1*0x1000u) (2*0x1000u) (3*0x1000u) (4*0x1000u) (5*0x1000u) (6*0x1000u) (7*0x1000u)

/* DMA transfer mode 0: single */ /* DMA transfer mode 1: block */ /* DMA transfer mode 2: interleaved */ /* DMA transfer mode 3: interleaved */ /* DMA transfer mode 4: single, repeat */ /* DMA transfer mode 5: block, repeat */ /* DMA transfer mode 6: interleaved, repeat */ /* DMA transfer mode 7: interleaved, repeat */

#define DMA0SA_ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA0SA #endif #define DMA0SAL_ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA0SAL #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DEFXA } @ 0x01D2; #endif #define DMA0DA_ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA0DA #endif #define DMA0DAL_ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA0DAL #endif

(0x01d2) , DMA0SA_) (0x01d2)

/* DMA Channel 0 Source Address */

/* DMA Channel 0 Source Address */

, DMA0SAL_)

DMA0SAL; DMA0SA;

(0x01d6)

/* DMA Channel 0 Destination Address */

, DMA0DA_) (0x01d6) /* DMA Channel 0 Destination Address */

, DMA0DAL_)

#ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DMA0DAL; DEFXA DMA0DA; } @ 0x01D6; #endif #define DMA0SZ_ (0x01da) /* DMA Channel 0 Transfer Size */ DEFW( DMA0SZ , DMA0SZ_) #define DMA1SA_ (0x01de) /* DMA Channel 1 Source Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA1SA , DMA1SA_) #endif #define DMA1SAL_ (0x01de) /* DMA Channel 1 Source Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA1SAL , DMA1SAL_) #endif

#ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DEFXA } @ 0x01DE; #endif #define DMA1DA_ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA1DA #endif #define DMA1DAL_ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA1DAL #endif

DMA1SAL; DMA1SA;

(0x01e2)

/* DMA Channel 1 Destination Address */

, DMA1DA_) (0x01e2) /* DMA Channel 1 Destination Address */

, DMA1DAL_)

#ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DMA1DAL; DEFXA DMA1DA; } @ 0x01E2; #endif #define DMA1SZ_ (0x01e6) /* DMA Channel 1 Transfer Size */ DEFW( DMA1SZ , DMA1SZ_) #define DMA2SA_ (0x01ea) /* DMA Channel 2 Source Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA2SA , DMA2SA_) #endif #define DMA2SAL_ (0x01ea) /* DMA Channel 2 Source Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA2SAL , DMA2SAL_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DMA2SAL; DEFXA DMA2SA; } @ 0x01EA; #endif #define DMA2DA_ (0x01ee) /* DMA Channel 2 Destination Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFA( DMA2DA , DMA2DA_)

#endif #define DMA2DAL_ (0x01ee) /* DMA Channel 2 Destination Address */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( DMA2DAL , DMA2DAL_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { DEFXW DMA2DAL; DEFXA DMA2DA; } @ 0x01EE; #endif #define DMA2SZ_ (0x01f2) /* DMA Channel 2 Transfer Size */ DEFW( DMA2SZ , DMA2SZ_) /* DMAIV Definitions */ #define DMAIV_NONE #define DMAIV_DMA0IFG #define DMAIV_DMA1IFG #define DMAIV_DMA2IFG

(0x0000) (0x0002) (0x0004) (0x0006)

/* No Interrupt pending */ /* DMA0IFG */ /* DMA1IFG */ /* DMA2IFG */

/************************************************************* * Flash Memory *************************************************************/ #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ #define FCTL1_ DEFW( FCTL1 #define FCTL2_ DEFW( FCTL2 #define FCTL3_ DEFW( FCTL3 #define FCTL4_ DEFW( FCTL4 #define FRKEY #define FWKEY #define FXKEY #define ERASE #define MERAS #define EEI #define EEIEX (0x0128) /* FLASH Control 1 */ , FCTL1_) (0x012A) /* FLASH Control 2 */ , FCTL2_) (0x012C) /* FLASH Control 3 */ , FCTL3_) (0x01BE) /* FLASH Control 4 */ , FCTL4_) (0x9600) /* Flash key returned by read */ (0xA500) /* Flash key for write */ (0x3300) /* for use with XOR instruction */ (0x0002) /* Enable bit for Flash segment erase */ (0x0004) /* Enable bit for Flash mass erase */ (0x0008) /* Enable Erase Interrupts */ (0x0010) /* Enable Emergency Interrupt Exit */

#define WRT #define BLKWRT #define SEGWRT write */ #define FN0 according to: */ #define FN1 + FN0 + 1 */ #ifndef FN2 #define FN2 #endif #ifndef FN3 #define FN3 #endif #ifndef FN4 #define FN4 #endif #define FN5 #define FSSEL0 from USART SSELx */ #define FSSEL1 #define FSSEL_0 #define FSSEL_1 #define FSSEL_2 #define FSSEL_3 #define BUSY #define KEYV #define ACCVIFG #define WAIT #define LOCK #define EMEX #define LOCKA locked (read only) */ #define FAIL #define MGR0 #define MGR1

(0x0040) /* Enable bit for Flash write */ (0x0080) /* Enable bit for Flash segment write */ (0x0080) /* old definition */ /* Enable bit for Flash segment

(0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1

(0x0004)

(0x0008)

(0x0010) (0x0020) (0x0040) /* Flash clock select 0 */ (0x0080) /* Flash clock select 1 */ (0x0000) (0x0040) (0x0080) (0x00C0) (0x0001) (0x0002) (0x0004) (0x0008) (0x0010) (0x0020) (0x0040) /* Flash clock select: 0 - ACLK */ /* Flash clock select: 1 - MCLK */ /* Flash clock select: 2 - SMCLK */ /* Flash clock select: 3 - SMCLK */ /* Flash busy: 1 */ /* Flash Key violation flag */ /* Flash Access violation flag */ /* Wait flag for segment write */ /* Lock bit: 1 - Flash is locked (read only) */ /* Flash Emergency Exit */ /* Segment A Lock bit: read = 1 - Segment is

/* to distinguish

(0x0080) /* Last Program or Erase failed */ (0x0010) /* Marginal read 0 mode. */ (0x0020) /* Marginal read 1 mode. */

/************************************************************ * HARDWARE MULTIPLIER ************************************************************/

#define __MSP430_HAS_MPY__

/* Definition to show that Module is available */

#define MPY_ (0x0130) /* Multiply Unsigned/Operand 1 */ DEFW( MPY , MPY_) #define MPYS_ (0x0132) /* Multiply Signed/Operand 1 */ DEFW( MPYS , MPYS_) #define MAC_ (0x0134) /* Multiply Unsigned and Accumulate/Operand 1 */ DEFW( MAC , MAC_) #define MACS_ (0x0136) /* Multiply Signed and Accumulate/Operand 1 */ DEFW( MACS , MACS_) #define OP2_ (0x0138) /* Operand 2 */ DEFW( OP2 , OP2_) #define RESLO_ (0x013A) /* Result Low Word */ DEFW( RESLO , RESLO_) #define RESHI_ (0x013C) /* Result High Word */ DEFW( RESHI , RESHI_) #define SUMEXT_ (0x013E) /* Sum Extend */ READ_ONLY DEFW( SUMEXT , SUMEXT_) /************************************************************ * DIGITAL I/O Port1/2 Pull up / Pull down Resistors ************************************************************/ #define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ #define P1IN_ READ_ONLY DEFC( P1IN #define P1OUT_ DEFC( P1OUT #define P1DIR_ DEFC( P1DIR #define P1IFG_ DEFC( P1IFG #define P1IES_ DEFC( P1IES #define P1IE_ DEFC( P1IE #define P1SEL_ DEFC( P1SEL #define P1REN_ DEFC( P1REN #define P2IN_ READ_ONLY DEFC( P2IN (0x0020) /* Port 1 Input */ , P1IN_) (0x0021) /* Port 1 Output */ , P1OUT_) (0x0022) /* Port 1 Direction */ , P1DIR_) (0x0023) /* Port 1 Interrupt Flag */ , P1IFG_) (0x0024) /* Port 1 Interrupt Edge Select */ , P1IES_) (0x0025) /* Port 1 Interrupt Enable */ , P1IE_) (0x0026) /* Port 1 Selection */ , P1SEL_) (0x0027) /* Port 1 Resistor Enable */ , P1REN_) (0x0028) /* Port 2 Input */ , P2IN_)

#define P2OUT_ DEFC( P2OUT #define P2DIR_ DEFC( P2DIR #define P2IFG_ DEFC( P2IFG #define P2IES_ DEFC( P2IES #define P2IE_ DEFC( P2IE #define P2SEL_ DEFC( P2SEL #define P2REN_ DEFC( P2REN

(0x0029) /* Port 2 Output */ , P2OUT_) (0x002A) /* Port 2 Direction */ , P2DIR_) (0x002B) /* Port 2 Interrupt Flag */ , P2IFG_) (0x002C) /* Port 2 Interrupt Edge Select */ , P2IES_) (0x002D) /* Port 2 Interrupt Enable */ , P2IE_) (0x002E) /* Port 2 Selection */ , P2SEL_) (0x002F) /* Port 2 Resistor Enable */ , P2REN_)

/************************************************************ * DIGITAL I/O Port3/4 Pull up / Pull down Resistors ************************************************************/ #define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ #define P3IN_ READ_ONLY DEFC( P3IN #define P3OUT_ DEFC( P3OUT #define P3DIR_ DEFC( P3DIR #define P3SEL_ DEFC( P3SEL #define P3REN_ DEFC( P3REN #define P4IN_ READ_ONLY DEFC( P4IN #define P4OUT_ DEFC( P4OUT #define P4DIR_ DEFC( P4DIR #define P4SEL_ DEFC( P4SEL #define P4REN_ DEFC( P4REN (0x0018) /* Port 3 Input */ , P3IN_) (0x0019) /* Port 3 Output */ , P3OUT_) (0x001A) /* Port 3 Direction */ , P3DIR_) (0x001B) /* Port 3 Selection */ , P3SEL_) (0x0010) /* Port 3 Resistor Enable */ , P3REN_) (0x001C) /* Port 4 Input */ , P4IN_) (0x001D) /* Port 4 Output */ , P4OUT_) (0x001E) /* Port 4 Direction */ , P4DIR_) (0x001F) /* Port 4 Selection */ , P4SEL_) (0x0011) /* Port 4 Resistor Enable */ , P4REN_)

/************************************************************ * DIGITAL I/O Port5/6 Pull up / Pull down Resistors ************************************************************/ #define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ #define P5IN_ READ_ONLY DEFC( P5IN #define P5OUT_ DEFC( P5OUT #define P5DIR_ DEFC( P5DIR #define P5SEL_ DEFC( P5SEL #define P5REN_ DEFC( P5REN #define P6IN_ READ_ONLY DEFC( P6IN #define P6OUT_ DEFC( P6OUT #define P6DIR_ DEFC( P6DIR #define P6SEL_ DEFC( P6SEL #define P6REN_ DEFC( P6REN (0x0030) /* Port 5 Input */ , P5IN_) (0x0031) /* Port 5 Output */ , P5OUT_) (0x0032) /* Port 5 Direction */ , P5DIR_) (0x0033) /* Port 5 Selection */ , P5SEL_) (0x0012) /* Port 5 Resistor Enable */ , P5REN_) (0x0034) /* Port 6 Input */ , P6IN_) (0x0035) /* Port 6 Output */ , P6OUT_) (0x0036) /* Port 6 Direction */ , P6DIR_) (0x0037) /* Port 6 Selection */ , P6SEL_) (0x0013) /* Port 6 Resistor Enable */ , P6REN_)

/************************************************************ * DIGITAL I/O Port7/8 Pull up / Pull down Resistors ************************************************************/ #define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ #define P7IN_ (0x0038) /* Port 7 Input */ #ifndef __IAR_SYSTEMS_ICC__ READ_ONLY DEFC( P7IN , P7IN_) #endif #define P7OUT_ (0x003A) /* Port 7 Output */ #ifndef __IAR_SYSTEMS_ICC__

DEFC( P7OUT , P7OUT_) #endif #define P7DIR_ (0x003C) /* Port 7 Direction */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P7DIR , P7DIR_) #endif #define P7SEL_ (0x003E) /* Port 7 Selection */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P7SEL , P7SEL_) #endif #define P7REN_ (0x0014) /* Port 7 Resistor Enable */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P7REN , P7REN_) #endif #define P8IN_ (0x0039) /* Port 8 Input */ #ifndef __IAR_SYSTEMS_ICC__ READ_ONLY DEFC( P8IN , P8IN_) #endif #define P8OUT_ (0x003B) /* Port 8 Output */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P8OUT , P8OUT_) #endif #define P8DIR_ (0x003D) /* Port 8 Direction */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P8DIR , P8DIR_) #endif #define P8SEL_ (0x003F) /* Port 8 Selection */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P8SEL , P8SEL_) #endif #define P8REN_ (0x0015) /* Port 8 Resistor Enable */ #ifndef __IAR_SYSTEMS_ICC__ DEFC( P8REN , P8REN_) #endif #define PAIN_ (0x0038) /* Port A Input */ #ifndef __IAR_SYSTEMS_ICC__ READ_ONLY DEFW( PAIN , PAIN_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union {

struct { READ_ONLY DEFXC P7IN; READ_ONLY DEFXC P8IN; }; READ_ONLY DEFXW PAIN; } @ 0x0038; #endif #define PAOUT_ (0x003A) /* Port A Output */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( PAOUT , PAOUT_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { struct { DEFXC P7OUT; DEFXC P8OUT; }; DEFXW PAOUT; } @ 0x003A; #endif #define PADIR_ (0x003C) /* Port A Direction */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( PADIR , PADIR_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { struct { DEFXC P7DIR; DEFXC P8DIR; }; DEFXW PADIR; } @ 0x003C; #endif #define PASEL_ (0x003E) /* Port A Selection */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( PASEL , PASEL_) #endif

#ifdef __IAR_SYSTEMS_ICC__ __no_init union { struct { DEFXC P7SEL; DEFXC P8SEL; }; DEFXW PASEL; } @ 0x003E; #endif #define PAREN_ (0x0014) /* Port A Resistor Enable */ #ifndef __IAR_SYSTEMS_ICC__ DEFW( PAREN , PAREN_) #endif #ifdef __IAR_SYSTEMS_ICC__ __no_init union { struct { DEFXC DEFXC }; DEFXW } @ 0x0014; #endif

P7REN; P8REN; PAREN;

/************************************************************ * Brown-Out, Supply Voltage Supervision (SVS) ************************************************************/ #define __MSP430_HAS_SVS__ /* Definition to show that Module is available */ #define SVSCTL_ DEFC( SVSCTL #define SVSFG #define SVSOP #define SVSON #define PORON #define VLD0 #define VLD1 #define VLD2 #define VLD3 (0x0055) /* SVS Control */ , SVSCTL_) (0x01) /* SVS Flag */ (0x02) /* SVS output (read only) */ (0x04) /* Switches the SVS on/off */ (0x08) /* Enable POR Generation if Low Voltage */ (0x10) (0x20) (0x40) (0x80)

#define VLDON #define VLDOFF #define VLD_1_8V

(0x10) (0x00) (0x10)

/************************************************************ * Timer A3 ************************************************************/ #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ #define TAIV_ READ_ONLY DEFW( TAIV #define TACTL_ DEFW( TACTL #define TACCTL0_ DEFW( TACCTL0 #define TACCTL1_ DEFW( TACCTL1 #define TACCTL2_ DEFW( TACCTL2 #define TAR_ DEFW( TAR #define TACCR0_ DEFW( TACCR0 #define TACCR1_ DEFW( TACCR1 #define TACCR2_ DEFW( TACCR2 /* Alternate register names */ #define CCTL0 #define CCTL1 #define CCTL2 #define CCR0 #define CCR1 #define CCR2 #define CCTL0_ #define CCTL1_ #define CCTL2_ #define CCR0_ #define CCR1_ #define CCR2_ #define TASSEL1 (0x012E) /* Timer A Interrupt Vector Word */ , TAIV_) (0x0160) /* Timer A Control */ , TACTL_) (0x0162) /* Timer A Capture/Compare Control 0 */ , TACCTL0_) (0x0164) /* Timer A Capture/Compare Control 1 */ , TACCTL1_) (0x0166) /* Timer A Capture/Compare Control 2 */ , TACCTL2_) (0x0170) /* Timer A */ , TAR_) (0x0172) /* Timer A Capture/Compare 0 */ , TACCR0_) (0x0174) /* Timer A Capture/Compare 1 */ , TACCR1_) (0x0176) /* Timer A Capture/Compare 2 */ , TACCR2_)

TACCTL0 TACCTL1 TACCTL2 TACCR0 TACCR1 TACCR2 TACCTL0_ TACCTL1_ TACCTL2_ TACCR0_ TACCR1_ TACCR2_

/* Timer A Capture/Compare Control 0 */ /* Timer A Capture/Compare Control 1 */ /* Timer A Capture/Compare Control 2 */ /* Timer A Capture/Compare 0 */ /* Timer A Capture/Compare 1 */ /* Timer A Capture/Compare 2 */ /* Timer A Capture/Compare Control 0 */ /* Timer A Capture/Compare Control 1 */ /* Timer A Capture/Compare Control 2 */ /* Timer A Capture/Compare 0 */ /* Timer A Capture/Compare 1 */ /* Timer A Capture/Compare 2 */

(0x0200) /* Timer A clock source select 0 */

#define TASSEL0 #define ID1 #define ID0 #define MC1 #define MC0 #define TACLR #define TAIE #define TAIFG #define MC_0 #define MC_1 #define MC_2 #define MC_3 #define ID_0 #define ID_1 #define ID_2 #define ID_3 #define TASSEL_0 #define TASSEL_1 #define TASSEL_2 #define TASSEL_3 #define CM1 #define CM0 #define CCIS1 #define CCIS0 #define SCS #define SCCI #define CAP #define OUTMOD2 #define OUTMOD1 #define OUTMOD0 #define CCIE #define CCI #define OUT #define COV #define CCIFG #define OUTMOD_0 #define OUTMOD_1 #define OUTMOD_2 #define OUTMOD_3 #define OUTMOD_4 #define OUTMOD_5

(0x0100) (0x0080) (0x0040) (0x0020) (0x0010) (0x0004) (0x0002) (0x0001)

/* Timer A clock source select 1 */ /* Timer A clock input divider 1 */ /* Timer A clock input divider 0 */ /* Timer A mode control 1 */ /* Timer A mode control 0 */ /* Timer A counter clear */ /* Timer A counter interrupt enable */ /* Timer A counter interrupt flag */

(0*0x10u) /* Timer A mode control: 0 - Stop */ (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ (2*0x10u) /* Timer A mode control: 2 - Continous up */ (3*0x10u) /* Timer A mode control: 3 - Up/Down */ (0*0x40u) /* Timer A input divider: 0 - /1 */ (1*0x40u) /* Timer A input divider: 1 - /2 */ (2*0x40u) /* Timer A input divider: 2 - /4 */ (3*0x40u) /* Timer A input divider: 3 - /8 */ (0*0x100u) /* Timer A clock source select: 0 - TACLK */ (1*0x100u) /* Timer A clock source select: 1 - ACLK */ (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ (3*0x100u) /* Timer A clock source select: 3 - INCLK */ (0x8000) /* Capture mode 1 */ (0x4000) /* Capture mode 0 */ (0x2000) /* Capture input select 1 */ (0x1000) /* Capture input select 0 */ (0x0800) /* Capture sychronize */ (0x0400) /* Latched capture signal (read) */ (0x0100) /* Capture mode: 1 /Compare mode : 0 */ (0x0080) /* Output mode 2 */ (0x0040) /* Output mode 1 */ (0x0020) /* Output mode 0 */ (0x0010) /* Capture/compare interrupt enable */ (0x0008) /* Capture input signal (read) */ (0x0004) /* PWM Output signal if output mode 0 */ (0x0002) /* Capture/compare overflow flag */ (0x0001) /* Capture/compare interrupt flag */ (0*0x20u) (1*0x20u) (2*0x20u) (3*0x20u) (4*0x20u) (5*0x20u) /* PWM output mode: 0 - output only */ /* PWM output mode: 1 - set */ /* PWM output mode: 2 - PWM toggle/reset */ /* PWM output mode: 3 - PWM set/reset */ /* PWM output mode: 4 - toggle */ /* PWM output mode: 5 - Reset */

#define OUTMOD_6 #define OUTMOD_7 #define CCIS_0 #define CCIS_1 #define CCIS_2 #define CCIS_3 #define CM_0 #define CM_1 #define CM_2 #define CM_3 /* TA3IV Definitions */ #define TAIV_NONE #define TAIV_TACCR1 #define TAIV_TACCR2 #define TAIV_6 #define TAIV_8 #define TAIV_TAIFG

(6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ (0*0x1000u) /* Capture input select: 0 - CCIxA */ (1*0x1000u) /* Capture input select: 1 - CCIxB */ (2*0x1000u) /* Capture input select: 2 - GND */ (3*0x1000u) /* Capture input select: 3 - Vcc */ (0*0x4000u) /* Capture mode: 0 - disabled */ (1*0x4000u) /* Capture mode: 1 - pos. edge */ (2*0x4000u) /* Capture mode: 1 - neg. edge */ (3*0x4000u) /* Capture mode: 1 - both edges */

(0x0000) (0x0002) (0x0004) (0x0006) (0x0008) (0x000A)

/* No Interrupt pending */ /* TACCR1_CCIFG */ /* TACCR2_CCIFG */ /* Reserved */ /* Reserved */ /* TAIFG */

/************************************************************ * Timer B7 ************************************************************/ #define __MSP430_HAS_TB7__ /* Definition to show that Module is available */ #define TBIV_ READ_ONLY DEFW( TBIV #define TBCTL_ DEFW( TBCTL #define TBCCTL0_ DEFW( TBCCTL0 #define TBCCTL1_ DEFW( TBCCTL1 #define TBCCTL2_ DEFW( TBCCTL2 #define TBCCTL3_ DEFW( TBCCTL3 #define TBCCTL4_ DEFW( TBCCTL4 #define TBCCTL5_ DEFW( TBCCTL5 #define TBCCTL6_ DEFW( TBCCTL6 #define TBR_ DEFW( TBR (0x011E) /* Timer B Interrupt Vector Word */ , TBIV_) (0x0180) /* Timer B Control */ , TBCTL_) (0x0182) /* Timer B Capture/Compare Control 0 */ , TBCCTL0_) (0x0184) /* Timer B Capture/Compare Control 1 */ , TBCCTL1_) (0x0186) /* Timer B Capture/Compare Control 2 */ , TBCCTL2_) (0x0188) /* Timer B Capture/Compare Control 3 */ , TBCCTL3_) (0x018A) /* Timer B Capture/Compare Control 4 */ , TBCCTL4_) (0x018C) /* Timer B Capture/Compare Control 5 */ , TBCCTL5_) (0x018E) /* Timer B Capture/Compare Control 6 */ , TBCCTL6_) (0x0190) /* Timer B */ , TBR_)

#define TBCCR0_ DEFW( TBCCR0 #define TBCCR1_ DEFW( TBCCR1 #define TBCCR2_ DEFW( TBCCR2 #define TBCCR3_ DEFW( TBCCR3 #define TBCCR4_ DEFW( TBCCR4 #define TBCCR5_ DEFW( TBCCR5 #define TBCCR6_ DEFW( TBCCR6 #define TBCLGRP1 #define TBCLGRP0 #define CNTL1 #define CNTL0 #define TBSSEL1 #define TBSSEL0 #define TBCLR #define TBIE #define TBIFG #define SHR1 #define SHR0 #define TBSSEL_0 #define TBSSEL_1 #define TBSSEL_2 #define TBSSEL_3 #define CNTL_0 #define CNTL_1 #define CNTL_2 #define CNTL_3 #define SHR_0 #define SHR_1 #define SHR_2 #define SHR_3 #define TBCLGRP_0 #define TBCLGRP_1 */ #define TBCLGRP_2

(0x0192) /* Timer B Capture/Compare 0 */ , TBCCR0_) (0x0194) /* Timer B Capture/Compare 1 */ , TBCCR1_) (0x0196) /* Timer B Capture/Compare 2 */ , TBCCR2_) (0x0198) /* Timer B Capture/Compare 3 */ , TBCCR3_) (0x019A) /* Timer B Capture/Compare 4 */ , TBCCR4_) (0x019C) /* Timer B Capture/Compare 5 */ , TBCCR5_) (0x019E) /* Timer B Capture/Compare 6 */ , TBCCR6_) (0x4000) /* Timer B Compare latch load group 1 */ (0x2000) /* Timer B Compare latch load group 0 */ (0x1000) /* Counter lenght 1 */ (0x0800) /* Counter lenght 0 */ (0x0200) /* Clock source 1 */ (0x0100) /* Clock source 0 */ (0x0004) /* Timer B counter clear */ (0x0002) /* Timer B interrupt enable */ (0x0001) /* Timer B interrupt flag */ (0x4000) /* Timer B Compare latch load group 1 */ (0x2000) /* Timer B Compare latch load group 0 */ (0*0x0100u) (1*0x0100u) (2*0x0100u) (3*0x0100u) (0*0x0800u) (1*0x0800u) (2*0x0800u) (3*0x0800u) (0*0x2000u) (1*0x2000u) (2*0x2000u) (3*0x2000u) (0*0x2000u) (1*0x2000u) /* Clock Source: TBCLK */ /* Clock Source: ACLK */ /* Clock Source: SMCLK */ /* Clock Source: INCLK */ /* Counter lenght: 16 bit */ /* Counter lenght: 12 bit */ /* Counter lenght: 10 bit */ /* Counter lenght: 8 bit */ /* Timer B Group: 0 - individually */ /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ /* Timer B Group: 3 - 1 group (all) */ /* Timer B Group: 0 - individually */ /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6)

(2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/

#define TBCLGRP_3

(3*0x2000u) /* Timer B Group: 3 - 1 group (all) */

/* Additional Timer B Control Register bits are defined in Timer A */ #define CLLD1 (0x0400) /* Compare latch load source 1 */ #define CLLD0 (0x0200) /* Compare latch load source 0 */ #define SLSHR1 #define SLSHR0 #define SLSHR_0 #define SLSHR_1 to 0 */ #define SLSHR_2 #define SLSHR_3 to TBCTL0 */ #define CLLD_0 #define CLLD_1 to 0 */ #define CLLD_2 #define CLLD_3 to TBCTL0 */ /* TB7IV Definitions */ #define TBIV_NONE #define TBIV_TBCCR1 #define TBIV_TBCCR2 #define TBIV_TBCCR3 #define TBIV_TBCCR4 #define TBIV_TBCCR5 #define TBIV_TBCCR6 #define TBIV_TBIFG (0x0400) /* Compare latch load source 1 */ (0x0200) /* Compare latch load source 0 */ (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts

(0*0x0200u) /* Compare latch load sourec : 0 - immediate */ (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts

(0x0000) (0x0002) (0x0004) (0x0006) (0x0008) (0x000A) (0x000C) (0x000E)

/* No Interrupt pending */ /* TBCCR1_CCIFG */ /* TBCCR2_CCIFG */ /* TBCCR3_CCIFG */ /* TBCCR4_CCIFG */ /* TBCCR3_CCIFG */ /* TBCCR4_CCIFG */ /* TBIFG */

/************************************************************ * USCI ************************************************************/ #define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ #define __MSP430_HAS_USCI_AB0__ /* Definition to show that Module is available */ #define __MSP430_HAS_USCI_AB1__ /* Definition to show that Module is available */ #define UCA0CTL0_ DEFC( UCA0CTL0 #define UCA0CTL1_ DEFC( UCA0CTL1 (0x0060) /* USCI A0 Control Register 0 */ , UCA0CTL0_) (0x0061) /* USCI A0 Control Register 1 */ , UCA0CTL1_)

#define UCA0BR0_ (0x0062) /* USCI A0 Baud Rate 0 */ DEFC( UCA0BR0 , UCA0BR0_) #define UCA0BR1_ (0x0063) /* USCI A0 Baud Rate 1 */ DEFC( UCA0BR1 , UCA0BR1_) #define UCA0MCTL_ (0x0064) /* USCI A0 Modulation Control */ DEFC( UCA0MCTL , UCA0MCTL_) #define UCA0STAT_ (0x0065) /* USCI A0 Status Register */ DEFC( UCA0STAT , UCA0STAT_) #define UCA0RXBUF_ (0x0066) /* USCI A0 Receive Buffer */ READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_) #define UCA0TXBUF_ (0x0067) /* USCI A0 Transmit Buffer */ DEFC( UCA0TXBUF , UCA0TXBUF_) #define UCA0ABCTL_ (0x005D) /* USCI A0 LIN Control */ DEFC( UCA0ABCTL , UCA0ABCTL_) #define UCA0IRTCTL_ (0x005E) /* USCI A0 IrDA Transmit Control */ DEFC( UCA0IRTCTL , UCA0IRTCTL_) #define UCA0IRRCTL_ (0x005F) /* USCI A0 IrDA Receive Control */ DEFC( UCA0IRRCTL , UCA0IRRCTL_)

#define UCB0CTL0_ (0x0068) /* USCI B0 Control Register 0 */ DEFC( UCB0CTL0 , UCB0CTL0_) #define UCB0CTL1_ (0x0069) /* USCI B0 Control Register 1 */ DEFC( UCB0CTL1 , UCB0CTL1_) #define UCB0BR0_ (0x006A) /* USCI B0 Baud Rate 0 */ DEFC( UCB0BR0 , UCB0BR0_) #define UCB0BR1_ (0x006B) /* USCI B0 Baud Rate 1 */ DEFC( UCB0BR1 , UCB0BR1_) #define UCB0I2CIE_ (0x006C) /* USCI B0 I2C Interrupt Enable Register */ DEFC( UCB0I2CIE , UCB0I2CIE_) #define UCB0STAT_ (0x006D) /* USCI B0 Status Register */ DEFC( UCB0STAT , UCB0STAT_) #define UCB0RXBUF_ (0x006E) /* USCI B0 Receive Buffer */ READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_) #define UCB0TXBUF_ (0x006F) /* USCI B0 Transmit Buffer */ DEFC( UCB0TXBUF , UCB0TXBUF_) #define UCB0I2COA_ (0x0118) /* USCI B0 I2C Own Address */ DEFW( UCB0I2COA , UCB0I2COA_) #define UCB0I2CSA_ (0x011A) /* USCI B0 I2C Slave Address */ DEFW( UCB0I2CSA , UCB0I2CSA_) #define UCA1CTL0_ DEFC( UCA1CTL0 (0x00D0) /* USCI A1 Control Register 0 */ , UCA1CTL0_)

#define UCA1CTL1_ (0x00D1) /* USCI A1 Control Register 1 */ DEFC( UCA1CTL1 , UCA1CTL1_) #define UCA1BR0_ (0x00D2) /* USCI A1 Baud Rate 0 */ DEFC( UCA1BR0 , UCA1BR0_) #define UCA1BR1_ (0x00D3) /* USCI A1 Baud Rate 1 */ DEFC( UCA1BR1 , UCA1BR1_) #define UCA1MCTL_ (0x00D4) /* USCI A1 Modulation Control */ DEFC( UCA1MCTL , UCA1MCTL_) #define UCA1STAT_ (0x00D5) /* USCI A1 Status Register */ DEFC( UCA1STAT , UCA1STAT_) #define UCA1RXBUF_ (0x00D6) /* USCI A1 Receive Buffer */ READ_ONLY DEFC( UCA1RXBUF , UCA1RXBUF_) #define UCA1TXBUF_ (0x00D7) /* USCI A1 Transmit Buffer */ DEFC( UCA1TXBUF , UCA1TXBUF_) #define UCA1ABCTL_ (0x00CD) /* USCI A1 LIN Control */ DEFC( UCA1ABCTL , UCA1ABCTL_) #define UCA1IRTCTL_ (0x00CE) /* USCI A1 IrDA Transmit Control */ DEFC( UCA1IRTCTL , UCA1IRTCTL_) #define UCA1IRRCTL_ (0x00CF) /* USCI A1 IrDA Receive Control */ DEFC( UCA1IRRCTL , UCA1IRRCTL_)

#define UCB1CTL0_ (0x00D8) /* USCI B1 Control Register 0 */ DEFC( UCB1CTL0 , UCB1CTL0_) #define UCB1CTL1_ (0x00D9) /* USCI B1 Control Register 1 */ DEFC( UCB1CTL1 , UCB1CTL1_) #define UCB1BR0_ (0x00DA) /* USCI B1 Baud Rate 0 */ DEFC( UCB1BR0 , UCB1BR0_) #define UCB1BR1_ (0x00DB) /* USCI B1 Baud Rate 1 */ DEFC( UCB1BR1 , UCB1BR1_) #define UCB1I2CIE_ (0x00DC) /* USCI B1 I2C Interrupt Enable Register */ DEFC( UCB1I2CIE , UCB1I2CIE_) #define UCB1STAT_ (0x00DD) /* USCI B1 Status Register */ DEFC( UCB1STAT , UCB1STAT_) #define UCB1RXBUF_ (0x00DE) /* USCI B1 Receive Buffer */ READ_ONLY DEFC( UCB1RXBUF , UCB1RXBUF_) #define UCB1TXBUF_ (0x00DF) /* USCI B1 Transmit Buffer */ DEFC( UCB1TXBUF , UCB1TXBUF_) #define UCB1I2COA_ (0x017C) /* USCI B1 I2C Own Address */ DEFW( UCB1I2COA , UCB1I2COA_) #define UCB1I2CSA_ (0x017E) /* USCI B1 I2C Slave Address */ DEFW( UCB1I2CSA , UCB1I2CSA_)

// UART-Mode Bits #define UCPEN #define UCPAR #define UCMSB #define UC7BIT #define UCSPB #define UCMODE1 #define UCMODE0 #define UCSYNC // SPI-Mode Bits #define UCCKPH #define UCCKPL #define UCMST // I2C-Mode Bits #define UCA10 #define UCSLA10 #define UCMM //#define res #define UCMODE_0 #define UCMODE_1 #define UCMODE_2 #define UCMODE_3 // UART-Mode Bits #define UCSSEL1 #define UCSSEL0 #define UCRXEIE #define UCBRKIE #define UCDORM #define UCTXADDR #define UCTXBRK #define UCSWRST // SPI-Mode Bits //#define res //#define res //#define res //#define res //#define res // I2C-Mode Bits //#define res

(0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01)

/* Async. Mode: Parity enable */ /* Async. Mode: Parity 0:odd / 1:even */ /* Async. Mode: MSB first 0:LSB / 1:MSB */ /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ /* Async. Mode: Stop Bits 0:one / 1: two */ /* Async. Mode: USCI Mode 1 */ /* Async. Mode: USCI Mode 0 */ /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */

(0x80) (0x40) (0x08)

/* Sync. Mode: Clock Phase */ /* Sync. Mode: Clock Polarity */ /* Sync. Mode: Master Select */

(0x80) /* 10-bit Address Mode */ (0x40) /* 10-bit Slave Address Mode */ (0x20) /* Multi-Master Environment */ (0x10) /* reserved */ (0x00) /* Sync. Mode: USCI Mode: 0 */ (0x02) /* Sync. Mode: USCI Mode: 1 */ (0x04) /* Sync. Mode: USCI Mode: 2 */ (0x06) /* Sync. Mode: USCI Mode: 3 */

(0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01)

/* USCI 0 Clock Source Select 1 */ /* USCI 0 Clock Source Select 0 */ /* RX Error interrupt enable */ /* Break interrupt enable */ /* Dormant (Sleep) Mode */ /* Send next Data as Address */ /* Send next Data as Break */ /* USCI Software Reset */

(0x20) (0x10) (0x08) (0x04) (0x02)

/* reserved */ /* reserved */ /* reserved */ /* reserved */ /* reserved */

(0x20)

/* reserved */

#define UCTR #define UCTXNACK #define UCTXSTP #define UCTXSTT #define UCSSEL_0 #define UCSSEL_1 #define UCSSEL_2 #define UCSSEL_3 #define UCBRF3 #define UCBRF2 #define UCBRF1 #define UCBRF0 #define UCBRS2 #define UCBRS1 #define UCBRS0 #define UCOS16 #define UCBRF_0 #define UCBRF_1 #define UCBRF_2 #define UCBRF_3 #define UCBRF_4 #define UCBRF_5 #define UCBRF_6 #define UCBRF_7 #define UCBRF_8 #define UCBRF_9 #define UCBRF_10 #define UCBRF_11 #define UCBRF_12 #define UCBRF_13 #define UCBRF_14 #define UCBRF_15 #define UCBRS_0 #define UCBRS_1 #define UCBRS_2 #define UCBRS_3 #define UCBRS_4 #define UCBRS_5 #define UCBRS_6 #define UCBRS_7

(0x10) (0x08) (0x04) (0x02) (0x00) (0x40) (0x80) (0xC0) (0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01) (0x00) (0x10) (0x20) (0x30) (0x40) (0x50) (0x60) (0x70) (0x80) (0x90) (0xA0) (0xB0) (0xC0) (0xD0) (0xE0) (0xF0) (0x00) (0x02) (0x04) (0x06) (0x08) (0x0A) (0x0C) (0x0E)

/* Transmit/Receive Select/Flag */ /* Transmit NACK */ /* Transmit STOP */ /* Transmit START */ /* USCI 0 Clock Source: 0 */ /* USCI 0 Clock Source: 1 */ /* USCI 0 Clock Source: 2 */ /* USCI 0 Clock Source: 3 */ /* USCI First Stage Modulation Select 3 */ /* USCI First Stage Modulation Select 2 */ /* USCI First Stage Modulation Select 1 */ /* USCI First Stage Modulation Select 0 */ /* USCI Second Stage Modulation Select 2 */ /* USCI Second Stage Modulation Select 1 */ /* USCI Second Stage Modulation Select 0 */ /* USCI 16-times Oversampling enable */ /* USCI First Stage Modulation: 0 */ /* USCI First Stage Modulation: 1 */ /* USCI First Stage Modulation: 2 */ /* USCI First Stage Modulation: 3 */ /* USCI First Stage Modulation: 4 */ /* USCI First Stage Modulation: 5 */ /* USCI First Stage Modulation: 6 */ /* USCI First Stage Modulation: 7 */ /* USCI First Stage Modulation: 8 */ /* USCI First Stage Modulation: 9 */ /* USCI First Stage Modulation: A */ /* USCI First Stage Modulation: B */ /* USCI First Stage Modulation: C */ /* USCI First Stage Modulation: D */ /* USCI First Stage Modulation: E */ /* USCI First Stage Modulation: F */ /* USCI Second Stage Modulation: 0 */ /* USCI Second Stage Modulation: 1 */ /* USCI Second Stage Modulation: 2 */ /* USCI Second Stage Modulation: 3 */ /* USCI Second Stage Modulation: 4 */ /* USCI Second Stage Modulation: 5 */ /* USCI Second Stage Modulation: 6 */ /* USCI Second Stage Modulation: 7 */

#define UCLISTEN #define UCFE #define UCOE #define UCPE #define UCBRK #define UCRXERR #define UCADDR #define UCBUSY #define UCIDLE //#define res //#define res //#define res //#define res #define UCNACKIE #define UCSTPIE #define UCSTTIE #define UCALIE #define UCSCLLOW #define UCGC #define UCBBUSY #define UCNACKIFG #define UCSTPIFG #define UCSTTIFG #define UCALIFG #define UCIRTXPL5 #define UCIRTXPL4 #define UCIRTXPL3 #define UCIRTXPL2 #define UCIRTXPL1 #define UCIRTXPL0 #define UCIRTXCLK #define UCIREN #define UCIRRXFL5 #define UCIRRXFL4 #define UCIRRXFL3 #define UCIRRXFL2 #define UCIRRXFL1 #define UCIRRXFL0 #define UCIRRXPL #define UCIRRXFE

(0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01) (0x02)

/* USCI Listen mode */ /* USCI Frame Error Flag */ /* USCI Overrun Error Flag */ /* USCI Parity Error Flag */ /* USCI Break received */ /* USCI RX Error Flag */ /* USCI Address received Flag */ /* USCI Busy Flag */ /* USCI Idle line detected Flag */

(0x80) /* reserved */ (0x40) /* reserved */ (0x20) /* reserved */ (0x10) /* reserved */ (0x08) /* NACK Condition interrupt enable */ (0x04) /* STOP Condition interrupt enable */ (0x02) /* START Condition interrupt enable */ (0x01) /* Arbitration Lost interrupt enable */ (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01) (0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01) (0x80) (0x40) (0x20) (0x10) (0x08) (0x04) (0x02) (0x01) /* SCL low */ /* General Call address received Flag */ /* Bus Busy Flag */ /* NAK Condition interrupt Flag */ /* STOP Condition interrupt Flag */ /* START Condition interrupt Flag */ /* Arbitration Lost interrupt Flag */ /* IRDA Transmit Pulse Length 5 */ /* IRDA Transmit Pulse Length 4 */ /* IRDA Transmit Pulse Length 3 */ /* IRDA Transmit Pulse Length 2 */ /* IRDA Transmit Pulse Length 1 */ /* IRDA Transmit Pulse Length 0 */ /* IRDA Transmit Pulse Clock Select */ /* IRDA Encoder/Decoder enable */ /* IRDA Receive Filter Length 5 */ /* IRDA Receive Filter Length 4 */ /* IRDA Receive Filter Length 3 */ /* IRDA Receive Filter Length 2 */ /* IRDA Receive Filter Length 1 */ /* IRDA Receive Filter Length 0 */ /* IRDA Receive Input Polarity */ /* IRDA Receive Filter enable */

//#define res //#define res #define UCDELIM1 #define UCDELIM0 #define UCSTOE #define UCBTOE //#define res #define UCABDEN #define UCGCEN #define UCOA9 #define UCOA8 #define UCOA7 #define UCOA6 #define UCOA5 #define UCOA4 #define UCOA3 #define UCOA2 #define UCOA1 #define UCOA0 #define UCSA9 #define UCSA8 #define UCSA7 #define UCSA6 #define UCSA5 #define UCSA4 #define UCSA3 #define UCSA2 #define UCSA1 #define UCSA0

(0x80) /* reserved */ (0x40) /* reserved */ (0x20) /* Break Sync Delimiter 1 */ (0x10) /* Break Sync Delimiter 0 */ (0x08) /* Sync-Field Timeout error */ (0x04) /* Break Timeout error */ (0x02) /* reserved */ (0x01) /* Auto Baud Rate detect enable */ (0x8000) (0x0200) (0x0100) (0x0080) (0x0040) (0x0020) (0x0010) (0x0008) (0x0004) (0x0002) (0x0001) (0x0200) (0x0100) (0x0080) (0x0040) (0x0020) (0x0010) (0x0008) (0x0004) (0x0002) (0x0001) /* I2C General Call enable */ /* I2C Own Address 9 */ /* I2C Own Address 8 */ /* I2C Own Address 7 */ /* I2C Own Address 6 */ /* I2C Own Address 5 */ /* I2C Own Address 4 */ /* I2C Own Address 3 */ /* I2C Own Address 2 */ /* I2C Own Address 1 */ /* I2C Own Address 0 */ /* I2C Slave Address 9 */ /* I2C Slave Address 8 */ /* I2C Slave Address 7 */ /* I2C Slave Address 6 */ /* I2C Slave Address 5 */ /* I2C Slave Address 4 */ /* I2C Slave Address 3 */ /* I2C Slave Address 2 */ /* I2C Slave Address 1 */ /* I2C Slave Address 0 */

/************************************************************ * WATCHDOG TIMER ************************************************************/ #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ #define WDTCTL_ (0x0120) /* Watchdog Timer Control */ DEFW( WDTCTL , WDTCTL_) /* The bit names have been prefixed with "WDT" */ #define WDTIS0 (0x0001) #define WDTIS1 (0x0002) #define WDTSSEL (0x0004)

#define WDTCNTCL #define WDTTMSEL #define WDTNMI #define WDTNMIES #define WDTHOLD #define WDTPW

(0x0008) (0x0010) (0x0020) (0x0040) (0x0080) (0x5A00)

/* WDT-interval times [1ms] coded with Bits 0-2 */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ /* WDT is clocked by fACLK (assumed 32KHz) */ #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ /* Watchdog mode -> reset after expired time */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ /* WDT is clocked by fACLK (assumed 32KHz) */ #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */

#define WDT_ARST_1_9 /* 1.9ms " */

(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)

/* INTERRUPT CONTROL */ /* These two bits are defined in the Special Function Registers */ /* #define WDTIE 0x01 */ /* #define WDTIFG 0x01 */ /************************************************************ * Calibration Data in Info Mem ************************************************************/ /* TLV Calibration Data Structure */ #define TAG_DCO_30 #define TAG_ADC12_1 #define TAG_EMPTY Data */

(0x01) (0x10) (0xFE)

/* Tag for DCO30 Calibration Data */ /* Tag for ADC12_1 Calibration Data */ /* Tag for Empty Data Field in Calibration

#ifndef __DisableCalData #define TLV_CHECKSUM_ (0x10C0) /* TLV CHECK SUM */ READ_ONLY DEFW( TLV_CHECKSUM , TLV_CHECKSUM_) #define TLV_DCO_30_TAG_ (0x10F6) /* TLV TAG_DCO30 TAG */ READ_ONLY DEFC( TLV_DCO_30_TAG , TLV_DCO_30_TAG_) #define TLV_DCO_30_LEN_ (0x10F7) /* TLV TAG_DCO30 LEN */ READ_ONLY DEFC( TLV_DCO_30_LEN , TLV_DCO_30_LEN_) #define TLV_ADC12_1_TAG_ (0x10DA) /* TLV ADC12_1 TAG */ READ_ONLY DEFC( TLV_ADC12_1_TAG , TLV_ADC12_1_TAG_) #define TLV_ADC12_1_LEN_ (0x10DB) /* TLV ADC12_1 LEN */ READ_ONLY DEFC( TLV_ADC12_1_LEN , TLV_ADC12_1_LEN_) #endif #define CAL_ADC_25T85 (0x0007) /* Index for 2.5V/85Deg Cal. Value */ #define CAL_ADC_25T30 (0x0006) /* Index for 2.5V/30Deg Cal. Value */ #define CAL_ADC_25VREF_FACTOR (0x0005) /* Index for 2.5V Ref. Factor */ #define CAL_ADC_15T85 (0x0004) /* Index for 1.5V/85Deg Cal. Value */ #define CAL_ADC_15T30 (0x0003) /* Index for 1.5V/30Deg Cal. Value */ #define CAL_ADC_15VREF_FACTOR (0x0002) /* Index for ADC 1.5V Ref. Factor */ #define CAL_ADC_OFFSET (0x0001) /* Index for ADC Offset */ #define CAL_ADC_GAIN_FACTOR (0x0000) /* Index for ADC Gain Factor */ #define CAL_DCO_16MHZ 16MHz */ #define CAL_BC1_16MHZ 16MHz */ (0x0000) /* Index for DCOCTL Calibration Data for (0x0001) /* Index for BCSCTL1 Calibration Data for

#define CAL_DCO_12MHZ 12MHz */ #define CAL_BC1_12MHZ 12MHz */ #define CAL_DCO_8MHZ 8MHz */ #define CAL_BC1_8MHZ 8MHz */ #define CAL_DCO_1MHZ 1MHz */ #define CAL_BC1_1MHZ 1MHz */

(0x0002) /* Index for DCOCTL Calibration Data for (0x0003) /* Index for BCSCTL1 Calibration Data for (0x0004) /* Index for DCOCTL Calibration Data for (0x0005) /* Index for BCSCTL1 Calibration Data for (0x0006) /* Index for DCOCTL Calibration Data for (0x0007) /* Index for BCSCTL1 Calibration Data for

/************************************************************ * Calibration Data in Info Mem ************************************************************/ #ifndef __DisableCalData #define CALDCO_16MHZ_ (0x10F8) /* DCOCTL Calibration Data for 16MHz */ READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_) #define CALBC1_16MHZ_ (0x10F9) /* BCSCTL1 Calibration Data for 16MHz */ READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_) #define CALDCO_12MHZ_ (0x10FA) /* DCOCTL Calibration Data for 12MHz */ READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_) #define CALBC1_12MHZ_ (0x10FB) /* BCSCTL1 Calibration Data for 12MHz */ READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_) #define CALDCO_8MHZ_ (0x10FC) /* DCOCTL Calibration Data for 8MHz */ READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_) #define CALBC1_8MHZ_ (0x10FD) /* BCSCTL1 Calibration Data for 8MHz */ READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_) #define CALDCO_1MHZ_ (0x10FE) /* DCOCTL Calibration Data for 1MHz */ READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_) #define CALBC1_1MHZ_ (0x10FF) /* BCSCTL1 Calibration Data for 1MHz */ READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_) #endif /* #ifndef __DisableCalData */ /************************************************************ * Interrupt Vectors (offset from 0xFFC0) ************************************************************/ #define RESERVED0_VECTOR (0 * 2u) /* 0xFFC0 Reserved Int. Vector 0 */

#define RESERVED1_VECTOR (1 * 2u) /* 0xFFC2 Reserved Int. Vector 1 */ #define RESERVED2_VECTOR (2 * 2u) /* 0xFFC4 Reserved Int. Vector 2 */ #define RESERVED3_VECTOR (3 * 2u) /* 0xFFC6 Reserved Int. Vector 3 */ #define RESERVED4_VECTOR (4 * 2u) /* 0xFFC8 Reserved Int. Vector 4 */ #define RESERVED5_VECTOR (5 * 2u) /* 0xFFCA Reserved Int. Vector 5 */ #define RESERVED6_VECTOR (6 * 2u) /* 0xFFCC Reserved Int. Vector 6 */ #define RESERVED7_VECTOR (7 * 2u) /* 0xFFCE Reserved Int. Vector 7 */ #define RESERVED8_VECTOR (8 * 2u) /* 0xFFD0 Reserved Int. Vector 8 */ #define RESERVED9_VECTOR (9 * 2u) /* 0xFFD2 Reserved Int. Vector 9 */ #define RESERVED10_VECTOR (10 * 2u) /* 0xFFD4 Reserved Int. Vector 10 */ #define RESERVED11_VECTOR (11 * 2u) /* 0xFFD6 Reserved Int. Vector 11 */ #define RESERVED12_VECTOR (12 * 2u) /* 0xFFD8 Reserved Int. Vector 12 */ #define RESERVED13_VECTOR (13 * 2u) /* 0xFFDA Reserved Int. Vector 13 */ #define DAC12_VECTOR (14 * 2u) /* 0xFFDC DAC12 */ #define DMA_VECTOR (15 * 2u) /* 0xFFDE DMA */ #define USCIAB1TX_VECTOR (16 * 2u) /* 0xFFE0 USCI A1/B1 Transmit */ #define USCIAB1RX_VECTOR (17 * 2u) /* 0xFFE2 USCI A1/B1 Receive */ #define PORT1_VECTOR (18 * 2u) /* 0xFFE4 Port 1 */ #define PORT2_VECTOR (19 * 2u) /* 0xFFE6 Port 2 */ #define RESERVED20_VECTOR (20 * 2u) /* 0xFFDA Reserved Int. Vector 20 */ #define ADC12_VECTOR (21 * 2u) /* 0xFFEA ADC */ #define USCIAB0TX_VECTOR (22 * 2u) /* 0xFFEC USCI A0/B0 Transmit */ #define USCIAB0RX_VECTOR (23 * 2u) /* 0xFFEE USCI A0/B0 Receive */ #define TIMERA1_VECTOR (24 * 2u) /* 0xFFF0 Timer A CC1-2, TA */ #define TIMERA0_VECTOR (25 * 2u) /* 0xFFF2 Timer A CC0 */ #define WDT_VECTOR (26 * 2u) /* 0xFFF4 Watchdog Timer */ #define COMPARATORA_VECTOR (27 * 2u) /* 0xFFF6 Comparator A */ #define TIMERB1_VECTOR (28 * 2u) /* 0xFFF8 Timer B CC1-6, TB */ #define TIMERB0_VECTOR (29 * 2u) /* 0xFFFA Timer B CC0 */ #define NMI_VECTOR (30 * 2u) /* 0xFFFC Non-maskable */ #define RESET_VECTOR (31 * 2u) /* 0xFFFE Reset [Highest Priority] */ /************************************************************ * End of Modules ************************************************************/ #pragma language=default #endif /* #ifndef __msp430x26x */


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