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Cadence


新员工上岗培训 (初级培训)

Zhuzhou 2005.06

1. 2. 3. 4. 5.

Solaris基本命令 CMOS设计流程 如何进入Cadence Schematic输入 Symbol创建

6. Layout绘制 7. Dracula验证 8. Spectre仿真 9. HSPIC

E仿真 10.Verilog仿真

1.Solaris基本命令
主要内容:Solaris基本命令简介 基本个人环境设置

使用Solaris的几个注意点 1. Solaris命令是区分大小写的 2. Solaris的文件也是区分大小写的 3. 以“.”开头的文件一般都是系统环境设置 文件 4. 注意ctrl键,可以减少你浪费的时间

Solaris基本命令
1. ls 列出文件 2. cd 改变工作目录 3. cp 拷贝文件 4. rm 删除文件 5. chmod 改变文件或目录的权限 6. cat ,more 查看文件内容 7. mkdir 建立新目录

8. diff 比较两个文件的内容 9. !!执行前一个刚执行过的命令 10.compress/uncompress 压缩/解压缩命 令 11.who 查看系统的使用者 12.mv 移动文件或重命名 13.clear 清屏 14.man 命令的在线手册 15.kill 杀掉进程

2.CMOS设计流程

全定制流程

1.构想,规格定义 2.设计图输入 3.电路模拟 4.Layout 5.验证

Cadence文件结构
1. display.drf 2. CDL:Circuit Description Language 3. *.tf Technology file 4. *.rul diva验证软件使用的命令文件 5. cds.lib 定义了库的路径,请勿随便删除 6. PDRACULA是DRACULA Preprocessor 7. command file Dracula的命令文件

Cadence文件结构
8. DRACULA会产生下列文件:
.MLG:System fatal errors and logoff .MSM:Warning messages .LOG:Job tracking file .SUM:Job summary file .ERC:ERC check file

9. LOGLVS是用来产生DRACULA的Netlist format

设计目录使用规范

Library结构

Cadence文件格式标准
1.EDIF (Electronic Design Interchange Format) 2.GDSII:由Calma公司所定,常用來描述IC Layout的几何形狀

3. CIF (Caltech Intermediate Format)也是 一种版图交换格式

3.如何进入Cadence
输入icfb&启动Cadence

Library Manager

如何建立一个新的库

如何创建一个新单元

在Library Manager中将看到你新建的单元

4.Schematic输入
The schematic capture flow Creating a schematic view Contents of a schematic Adding component instances Adding pins Adding wires Editing object properties Checking the schematic for errors

Schematic Entry Flow

Terms and Definitions
library A set of design directories that includes ‘cells’ and ‘cellviews’. Library Manager A Cadence tool that allows user to browse and edit a design library. Virtuoso Schematic Editor Schematic editor and symbol generation tool in DFII. cell A basic unit of a design hierarchy described by cell views. cell view A specific view of a cell that includes schematic, symbol or layout. instance A uniquely named placement of a symbol onto a schematic. pin A connection point on a schematic and symbol used for accessing signals.

Contents of a Schematic

Creating a New Cellview
In the CIW or Library Manager, select File—New— Cellview.

Virtuoso Schematic Editor Graphical User Interface

Virtuoso Schematic Editor Window Toolbar

Adding Components
Methods: 1. Schematic toolbar icon 2. Menu bar Add—Instance 3. Bindkey i 4. MMB popup Add—Instance

Adding Component Instances

Connecting Components Using Wires
Use schematic toolbar icon Use command menu: Add—Wire Use bindkey, w Use the MMB popup

Wires and Wire Labels

Editing Components and Properties
Selecting a component, wire, pin, or label Editing the component or property Deleting the component Replacing component with another cell Moving the component

Pins
Pins have a user-defined Name and a Direction (input, output, or input/Output). Pins are one of three types:
Schematic pins provide ports to a schematic. Symbol pins provide ports to a symbol representing a schematic, and are Pin names and directions must match in all cellviews of a cell.

Schematic Checking
During schematic checking, all of the following are performed by default: ■ Update Connectivity This process associates wires and pins with logical connections called nets. ■ Schematic Rules Check ? Logical checks ? Physical checks ? Name checks ■ Cross-View Checker This option checks for pin name and direction consistency between cellviews. Select Check—Rules Setup from a schematic window to edit the rules.Disable any or all of these schematic checking features, if not needed.

Schematic Checking Rules

Virtuoso Schematic Editor Command Summary

5. Symbol创建
Limitations of a flat schematic Advantages of a system hierarchy Using the Automatic Symbol Generation Tool Requirements for the symbol to netlist properly Opening the symbol view for editing Adding shapes to the symbol Editing properties on pins

Terms and Definitions
primitive A component or cell view such as a resistor,capacitor, or transistor that has no hierarchy below this level. flat schematic A schematic containing only primitive components. hierarchy A design using structure or design data at multiple levels. symbol A cell view used in a schematic to replace design data or structure, such as a schematic cell view or behavior.

Limitations of a Flat Schematic
The entire design must be captured with primitives. ■ Repeated structures must be captured for every occurrence. ■ Large designs become inefficient or impractical. ■ Large designs require enormous resources, such as data storage. ■ Edits must be applied to every instance of repeated structure. ■ Difficult to locate or correct design problems.

Advantages of Using a Hierarchy
■ A symbol represents a circuit schematic. ■ A block-level diagram provides a convenient representation of the entire system, a subsystem, a small circuit, or a repeated structure. ■ The entire design can be documented within just handful of schematics. ■ A single schematic design capture is used for repeated cells. ■ Edits or design corrections to repeated structures require only a single correction. ■ Easy to locate a specific device by “browsing” the hierarchy. ■ Team members are assigned blocks that can be captured independently.

Symbol Generation

Characteristics of an Automatically Generated Symbol

6.Layout绘制
Use the LSW (Layer Selection Window) Use the Display Resource Editor Set the Display and Editor options Select shapes Draw shapes Edit shapes Place an instance

Customizing the Drawing Layers

Setting the Drawing Layer
Set the current drawing layer and the visibility of the layers using the LSW.

Setting Valid Drawing Layers

Setting the Display in Your Design Window

Set Area Display

Viewing Your Designs Using Pan and Zoom

Viewing Your Designs

Panning The Pan command lets you move your viewing window to different areas of the design. You can use the Window—Pan command from the menu or use the keypad keys to move around in your design. The arrow keys let you pan vertically, horizontally, or diagonally. The center key centers the design in the window. The center key does not scale the design to fit in the window. It centers the design in the window at the current zoom level. Zooming The Zoom commands let you zoom in or zoom out. You can use the Window—Zoom commands from the menu or use the zoom bindkeys. The bindkey, Shift-z lets you zoom out by a factor of two. The bindkey, Control-z lets you zoom in by a factor of two. The z bindkey prompts you to draw a box around the area you want to display. Zoom—To Sel Set The Zoom—To Sel Set command increases the image to the largest magnification at which the selected objects can be viewed in the cellview window.

Selecting Shapes

The Basic Edit Commands

7.Dracula验证
What is Dracula ? IC Verification tools for
Design Rule Checking(DRC) Electrical Rule Checking(ERC) Layout v.s. Schematic cross checking(LVS) Layout Parameter Extraction(LPE)

Structure of Command File

Define database name, format, I/O information. Define input layer number text sequence, connection Define layer operation verification type...

Description Block
Description Block Data Specification System Information Data Handling Specification
*description indisk = <path>/mydesign.gds system = GDS2 [GDS2,CIF,CADENCE,APPLE,EBES] primary = my_topcell schematic = LVSLOGIC outdisk = check.out printfile = reports program-dir = $DRAC4 keepdata = INQUERY [YES,NO,SMART,INQUERY] cnames-csen = NO [YES,NO] case sensitivity list-error = NO [YES,NO] list error location scale = 0.01 micron resolution = 0.01 micron text-level = 0 flagnon45 = NO [YES,NO] list error location delcell = cellname window = 10 10 500 500 *end

Input Layer Block
Input Layer Block Internal Layer Name Text to Layer association Connection Sequence
*input-layer NNWELL = 2 THIN = 4 MT1 = 16 TEXT 61 VIA = 17 MT2 = 18 TEXT 63 ATTACH MT2 TEXT = TEXT SUBSTRACT = BULK 99 text-sequence= MT1 MT2 GPOLY connect-layer= PSUB NNWELL PDIFF NDIFF GPOLY MT1 MT2 *end

Operation Block
Operation Block Layer Processing Interconnect Definition Design Rules Extraction Commands ERC/LVS Commands
*operation AND GPOLY THIN GATE AND GATE NIMP NGATE AND GATE PIMP PGATE .... CONNECT MT1 GPOLY BY CONT ..... WIDTH GPOLY LT 0.6 OUT D3C 50 ; PO.W.3 EXT[H] GPOLY LT 0.75 OUT D3D 50 ; PO.S.1 EXT[T] GPOLY THIN LT 0.3 OUT D3E 50 ; PO.C.1 ENC[T] GPOLY THIN LT 0.8 OUT D3F 50 ; PO.C.2 ..... ELEMENT MOS[N] NGATE GPOLY NDIFF PSUB ..... MULTILAB OUT ESHORT 49 ;same node with diff label SAMELAB OUT EOPEN 49 ;diff node with same label LVSCHK[SCRA] WPERCENT=1 LPERCENT=1 CAPVAL=5 *end

How to DRC
1.检查版图与工艺规则的一致性 2.基本设计规则包含各层的width,spacing 及不同层之间的spacing、enclosure等关 系 3.在特殊的设计需要下,Design Rule会有 一定的弹性。但设计者需掌握rule violation对电路的影响

Stream out for drc

填入 Run Directory 和 Output File

修改DRC文件
PRIMARY = * INDISK = *.db OUTDISK = *.out PRINTFILE = *

Compiling Command File and Output
PDRACULA: command file interpreter % PDRACULA :/get command_file_name n :/finish(produce unix run file) or :/next(fetch next command file) PDRACULA Output: UNIX run files of jxrun.com , jxsub.com , ats.com, jxsort.com ...

The running procedure of DRC/ERC
After the assignment of the file name and top-cell name of layout in command file, compile command file by % PDRACULA ******************************************************************************* */N* DRACULA3 ( REV. 4.3 / SUN-4 /GENDATE: 6-AUG-95/12 ) *** ( Copyright 1995, Cadence ) *** */N* EXEC TIME =16:07:10 DATE = 4-OCT-97 ******************************************************************************* :/g 9707drc06.com n :/f ** NOTE : PARTIAL DELETIONS OF FILES WILL BE PERFORMED ** CREATING : COMMAND FILE : jxrun.com ** NOTE : THIS JOB HAS 122 STAGES END OF DRACULA COMPILATIONS * .086 Mbytes allocated to the current process. * .045 Mbytes is still in use. * THE END OF PROGRAM TIME = 15:57:48 DATE = 4-OCT-97 * %jxrun.com > drc.log & (Submit thr run file)

Debug DRC

How to LVS
CDL out for lvs

注意:一定要填

run LOGLVS
: LOGLVS : cir netlist : con inv :x 结果会产生 LVSLOGIC.DAT cir *** 是根据cdl out form中Output File 所 填的name . con *** 是 根 据 cdl out form 中 Top Cell Name所填的name .

修改lvs
与DRC的类似。

run PDRACULA
参照 drc 的第3步聚 , ?同的只是 : /g lvs n 而巳 ( jxrun.com>lvs.log & ;?abort,则可check此lvs.log的内容.) 结果产生*.lvs

Debug LVS
這是 inverter 的例子,電晶體的數量有 match.

指電晶體在layout view 中的接 法,其中 X ,Y 為其所在的位置.

指電晶體在schematic view 中的接法,如上 例 VI (Gate) ,GND!(Source),VO(Drain)

注意:LVS做完之后需再做DRC,直到完 全没有错误。

8. Spectre仿真
启动CIW 键入icfb&

建立逻辑图 插入器件,包括PMOS , NMOS ,VDD, GND并设置PMOS,NMOS的宽长比,和模型 名称。

设置PMOS,NMOS的属性

插入激励, VDC,并设置VDC的值为5V,插入VSIN ,设置如 图。

设置激励源:vdd,vsin

在逻辑图中调用ADE

ADE界面

设置Spectre环境

设置模型

设置分析

生成SPICE网表并且RUN

观察结果

最终波形图

9. HSPICES仿真
HspiceS有两种工作模式,一种为图形方式,并且被集成 进cadence的ADE环境。另一种为文本方式需要自己编写 和确认网表文件和激励文件,并单独用看图软件查看结 果。相对来说其文本工作方式的功能更强,在此处为初 级教程不做深入描述。

ADE-HSPICES GUI
HspiceS和前文所述的spectre的ADE-GUI工作环境几乎完全 一致,区别在于选择仿真引擎及设置模型,和设置分析的界 面为HspiceS所独有。

选择仿真引擎

及设置模型
在该模型设置中可以使用LV3的计算模型。

设置分析

最终波形图

10.Verilog_HDL仿真
在第八,九讲中我们主要描述了模拟电路的仿真,本 章主要为数字电路的仿真。 在数字电路的仿真种一般采用功能描述的方式,在功 能描述语言中目前大量被采用的是VHDL和 Verilog_HDL语言两种,在此不作语言的深入培训。

建立dff1

建立dff2的功能描述

建立仿真图

启动Verilog_XL

确定工作目录

仿真界面

选择\simulation\verilog

激励文件

编译

RUN

启动simvision

最终波形

THANK YOU 有问题欢迎大家发邮件到 zhuzhou@e172.com讨论

zhuzhou 2005.06


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