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ALC5670-VB

Multi-Channel Audio Hub/CODEC with Gen.3 Voice DSP and SounzRealTM Post-Processing for Mobile Devices

Datasheet

Rev. 0.91 25 June 2015
Realtek

Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com

ALC5670-VB Datasheet
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ii

Rev. 0.91

ALC5670-VB Datasheet
REVISION HISTORY
Revision 0.9 0.91 Release Date 2015/3/13 2015/6/25 Summary ALC5670-VB First full version release Modify IN1 port pin description Modify IN3 port pin description

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Rev. 0.91

ALC5670-VB Datasheet

Contents
1. 2. 3. 4. 5. GENERAL DESCRIPTION ............................................................................................................................. .................1 FEATURES ............................................................................................................................. ............................................2 POWER/GROUND OPERATION CONDITIONS ........................................................................................................ .3 SYSTEM APPLICATION ............................................................................................................................. ....................3 FUNCTION BLOCK AND MIXER PATH .................................................................................................................... .4 5.1. 5.2. 5.3. 6. 7. FUNCTION BLOCK ............................................................................................................................. ...........................4 AUDIO MIXER PATH............................................................................................................................. ........................5 DIGITAL MIXER PATH ............................................................................................................................. .....................6

PIN ASSIGNMENTS ............................................................................................................................. ............................7 PIN DESCRIPTIONS............................................................................................................................. ............................8 7.1. 7.2. 7.3. 7.4. DIGITAL I/O PINS ............................................................................................................................. ............................8 ANALOG I/O P INS ............................................................................................................................. .........................10 FILTER/REFERENCE............................................................................................................................. .......................11 POWER/GROUND ............................................................................................................................. ...........................11

8.

FUNCTION DESCRIPTION ............................................................................................................................. .............12 8.1. SYSTEM CONNECTION ............................................................................................................................. ...................12 8.2. POWER ............................................................................................................................. ..........................................13 8.3. POWER SUPPLY ON/OFF SEQUENCE ...........................................................................................................................14 8.4. RESET ............................................................................................................................. ...........................................15 8.4.1. Power-On Reset (POR) ............................................................................................................................. ...........15 8.4.2. Software Reset ............................................................................................... .......................................................15 8.5. CLOCKING ............................................................................................................................. .....................................16 8.5.1. Phase-Locked Loop ............................................................................................................................. .................17 8.6. DIGITAL DATA INTERFACE ............................................................................................................................. ...........20 8.6.1. Three I2S/PCM Interface ............................................................................................................................. .........20 8.7. AUDIO DATA P ATH ............................................................................................................................. .......................24 8.7.1. 3 Analog ADCs with 6-Channel Record Path ......................................................................................................24 8.7.2. 4 DACs with 4-Channel Playback Path............................................................................................................... .25 8.7.3. Mixers ............................................................................................................................. ......................................26 8.8. ANALOG AUDIO INPUT PORT ............................................................................................................................. ........27 8.9. ANALOG AUDIO OUTPUT PORT ............................................................................................................................. .....28 8.10. MULTI-FUNCTION P INS ............................................................................................................................. .................29 8.11. DRC AND AGC FUNCTION ............................................................................................................................. ...........32 8.12. SOUNZREAL TM POST-PROCESSING ............................................................................................................................ .38 8.13. EQUALIZER BLOCK ............................................................................................................................. .......................38 8.14. W IND NOISE REDUCTION FILTER ...............................................................................................................................38 8.15. I2C CONTROL INTERFACE ............................................................................................................................. .............41 8.15.1. Address Setting ............................................................................................................................. ...................41 8.15.2. Complete Data Transfer ............................................................................................................................. .....41 8.16. GPIO, INTERRUPT AND JACK DETECTION ................................................................................................................. .43 8.17. PUSH BUTTON DETECTION ............................................................................................................................. ............46 8.18. POWER MANAGEMENT............................................................................................................................. ..................48 8.19. GEN.3 VOICE DSP FUNCTION ............................................................................................................................. .......49 8.20. MULTI-J ACK JACK DETECTION PIN (JD1) ................................................................................................................. .51 4 Rev. 0.91

ALC5670-VB Datasheet
9. REGISTERS LIST ............................................................................................................................. ..............................52 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. 9.7. 9.8. 9.9. 9.10. 9.11. 9.12. 9.13. 9.14. 9.15. 9.16. 9.17. 9.18. 9.19. 9.20. 9.21. 9.22. 9.23. 9.24. 9.25. 9.26. 9.27. 9.28. 9.29. 9.30. 9.31. 9.32. 9.33. 9.34. 9.35. 9.36. 9.37. 9.38. 9.39. 9.40. 9.41. 9.42. 9.43. 9.44. 9.45. 9.46. 9.47. 9.48. 9.49. 9.50. 9.51. 9.52. 9.53. 9.54. REGISTER MAP ............................................................................................................................. .............................52 MX-00H: S/W RESET & DEVICE ID.......................................................................................................................... .57 MX-02H: HEADPHONE OUTPUT CONTROL................................................................................................................ .57 MX-03H: LINE OUTPUT CONTROL .......................................................................................................................... .58 MX-0AH: IN1 PORT CONTROL - 1 ............................................................................................................................ .60 MX-0BH: IN1 PORT CONTROL - 2 ............................................................................................................................ .60 MX-0CH: IN1 PORT CONTROL - 3 ............................................................................................................................ .61 MX-0DH: IN2 INPUT CONTROL ............................................................................................................................. ....61 MX-0EH: IN3 INPUT CONTROL ............................................................................................................................. ....62 MX-0FH: INL & INR VOLUME CONTROL ................................................................................................................ .62 MX-19H: DACL1/R1 DIGITAL VOLUME .................................................................................................................. .63 MX-1AH: DACL2/R2 DIGITAL VOLUME ................................................................................................................. .64 MX-1BH: DACL2/R2 MUTE/UN-MUTE CONTROL .................................................................................................. .66 MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................ .67 MX-1DH: MONO ADC DIGITAL VOLUME CONTROL ................................................................................................ .67 MX-1EH: ADC D IGITAL BOOST GAIN CONTROL ..................................................................................................... .69 MX-1FH: STEREO2 ADC DIGITAL VOLUME CONTROL ............................................................................................ .70 MX-20H: MONO ADC DIGITAL BOOST GAIN CONTROL........................................................................................... .70 MX-26H: STEREO2 ADC DIGITAL M IXER CONTROL ................................................................................................ .71 MX-27H: STEREO1 ADC DIGITAL M IXER CONTROL ................................................................................................ .72 MX-28H: MONO ADC DIGITAL M IXER CONTROL .................................................................................................... .73 MX-29H: STEREO ADC TO DAC DIGITAL M IXER CONTROL.....................................................................................74 MX-2AH: STEREO DAC DIGITAL MIXER CONTROL ................................................................................................. .74 MX-2BH: MONO DAC DIGITAL M IXER CONTROL ................................................................................................... .75 MX-2CH: DAC DIGITAL MIXER CONTROL .............................................................................................................. .76 MX-2DH: VOICE DSP PATH CONTROL 1 .................................................................................................................. .78 MX-2EH: VOICE DSP VOLUME CONTROL................................................................................................................ .79 MX-2FH: INTERFACE DAC/ADC DATA CONTROL................................................................................................... .79 MX-31H: PDM INTERFACE CONTROL ...................................................................................................................... .80 MX-32H: PDM INTERFACE CONTROL ...................................................................................................................... .81 MX-35H: PDM INTERFACE CONTROL ...................................................................................................................... .81 MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................ .81 MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................ .82 MX-3DH: RECMIXR CONTROL 1............................................................................................................................ .82 MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................ .83 MX-3FH: RECMIXM CONTROL 1 ........................................................................................................................... .83 MX-40H: RECMIXM CONTROL 2............................................................................................................................ .84 MX-45H: HPOMIX CONTROL ............................................................................................................................. ......84 MX-4FH: OUTMIXL CONTROL ............................................................................................................................. ...85 MX-52H: OUTMIXR CONTROL ............................................................................................................................. ...85 MX-53H: LOUTMIX CONTROL ............................................................................................................................. ...86 MX-61H: POWER MANAGEMENT CONTROL 1........................................................................................................... .86 MX-62H: POWER MANAGEMENT CONTROL 2........................................................................................................... .87 MX-63H: POWER MANAGEMENT CONTROL 3........................................................................................................... .88 MX-64H: POWER MANAGEMENT CONTROL 4........................................................................................................... .89 MX-65H: POWER MANAGEMENT CONTROL 5........................................................................................................... .90 MX-66H: POWER MANAGEMENT CONTROL 6........................................................................................................... .90 MX-6AH: PRIVATE REGISTER INDEX.........................................................................................................................91 MX-6CH: PRIVATE REGISTER DATA......................................................................................................................... .91 MX-70H: I2S1 DIGITAL INTERFACE CONTROL ......................................................................................................... .92 MX-71H: I2S2 DIGITAL INTERFACE CONTROL ......................................................................................................... .92 MX-72H: I2S3 DIGITAL INTERFACE CONTROL ......................................................................................................... .93 MX-73H: ADC/DAC CLOCK CONTROL ................................................................................................................... .94 MX-74H: ADC/DAC HPF CONTROL ....................................................................................................................... .95 5 Rev. 0.91

ALC5670-VB Datasheet
9.55. 9.56. 9.57. 9.58. 9.59. 9.60. 9.61. 9.62. 9.63. 9.64. 9.65. 9.66. 9.67. 9.68. 9.69. 9.70. 9.71. 9.72. 9.73. 9.74. 9.75. 9.76. 9.77. 9.78. 9.79. 9.80. 9.81. 9.82. 9.83. 9.84. 9.85. 9.86. 9.87. 9.88. 9.89. 9.90. 9.91. 9.92. 9.93. 9.94. 9.95. 9.96. 9.97. 9.98. 9.99. 9.100. 9.101. 9.102. 9.103. 9.104. 9.105. 9.106. 9.107. 9.108. 9.109. MX-75H: DIGITAL M ICROPHONE CONTROL 1........................................................................................................... .96 MX-76H: DIGITAL M ICROPHONE CONTROL 2........................................................................................................... .97 MX-77H: TDM INTERFACE CONTROL 1 ................................................................................................................... .98 MX-78H: TDM INTERFACE CONTROL 2 ................................................................................................................... .99 MX-79H: TDM INTERFACE CONTROL 3 ................................................................................................................. .100 MX-7FH: CLOCK CONTROL 1 ............................................................................................................................. .....101 MX-80H: GLOBAL CLOCK CONTROL ...................................................................................................................... .101 MX-81H: PLL CONTROL 1............................................................................................................................. ..........102 MX-82H: PLL CONTROL 2............................................................................................................................. ..........102 MX-83H: ASRC CONTROL 1 ............................................................................................................................. ......103 MX-84H: ASRC CONTROL 2 ............................................................................................................................. ......104 MX-85H: ASRC CONTROL 3 ............................................................................................................................. ......105 MX-8AH: ASRC CONTROL 4 ............................................................................................................................. .....106 MX-8CH: ASRC CONTROL 5............................................................................................................................. ......107 MX-8EH: HP AMP CONTROL 1 ............................................................................................................................. ...107 MX-8FH: HP AMP CONTROL 2 ............................................................................................................................. ...108 MX-91H: CHARGE PUMP CONTROL ........................................................................................................................ .108 MX-93H: MICBIAS CONTROL ............................................................................................................................. ...109 MX-94H: JD1 CONTROL ............................................................................................................................. .............110 MX-9AH: SLD FUNCTION CONTROL...................................................................................................................... .110 MX-9BH: SLD FUNCTION THRESHOLD CONTROL 1 ............................................................................................... .111 MX-9CH: SLD FUNCTION THRESHOLD CONTROL 2 ............................................................................................... .111 MX-9DH: SLD FUNCTION THRESHOLD CONTROL 3 ............................................................................................... .111 MX-9EH: SLD FLAG ............................................................................................................................. ..................112 MX-AEH: ADC PATH EQ CONTROL 1 ................................................................................................................... .112 MX-AFH: ADC P ATH EQ CONTROL 2 ................................................................................................................... .113 MX-B0H: DAC PATH EQ CONTROL 1 .................................................................................................................... .114 MX-B1H: EQ CONTROL 2............................................................................................................................. ...........115 MX-B2H: DRC CONTROL 1 ............................................................................................................................. ........116 MX-B3H: DRC CONTROL 2 ............................................................................................................................. ........116 MX-B4H: DRC CONTROL 3 ............................................................................................................................. ........117 MX-B5H: DRC CONTROL 4 ............................................................................................................................. ........118 MX-B6H: DRC CONTROL 5 ............................................................................................................................. ........119 MX-B7H: DRC CONTROL 6 ............................................................................................................................. ........120 MX-BBH: JACK DETECTION CONTROL 1 ................................................................................................................ .120 MX-BCH: J ACK DETECTION CONTROL 2 ................................................................................................................ .121 MX-BDH: IRQ CONTROL 1 ............................................................................................................................. ........122 MX-BEH: IRQ CONTROL 2............................................................................................................................. .........123 MX-BFH: IRQ CONTROL 3 ............................................................................................................................. .........124 MX-C0H: GPIO CONTROL 1............................................................................................................................. .......125 MX-C1H: GPIO CONTROL 2............................................................................................................................. .......126 MX-C2H: GPIO CONTROL 3............................................................................................................................. .......127 MX-CDH: DIGITAL PATH CONTROL ....................................................................................................................... .128 MX-CFH: SOUNZREAL TM BASSBACK CONTROL .................................................................................................... .128 MX-D0H: SOUNZREA LTM TRUTREBLE CONTROL 1 ................................................................................................ .129 MX-D1H: SOUNZREAL TM TRUTREBLE CONTROL 2 ........................................................................................... .129 MX-D3H: STEREO1 ADC W IND FILTER CONTROL 1 ..........................................................................................130 MX-D4H: STEREO1 ADC W IND FILTER CONTROL 2 ..........................................................................................131 MX-D6H: HP AMP CONTROL ............................................................................................................................ .131 MX-D9H: SOFT VOLUME & ZCD CONTROL 1 ................................................................................................... .132 MX-DAH: SOFT VOLUME & ZCD CONTROL 2 .................................................................................................. .132 MX-DBH: INLINE COMMAND CONTROL 1 ......................................................................................................... .133 MX-DCH: INLINE COMMAND CONTROL 2 ......................................................................................................... .134 MX-DDH: INLINE COMMAND CONTROL 3 ......................................................................................................... .135 MX-E0H: VOICE DSP CONTROL 1 ..................................................................................................................... .135 6 Rev. 0.91

ALC5670-VB Datasheet
9.110. 9.111. 9.112. 9.113. 9.114. 9.115. 9.116. 9.117. 9.118. 9.119. 9.120. 9.121. 9.122. 9.123. 9.124. 9.125. 9.126. 9.127. 9.128. 9.129. 9.130. 9.131. 9.132. 9.133. 9.134. 9.135. 9.136. 9.137. 9.138. 9.139. 9.140. 9.141. 9.142. 9.143. 9.144. 9.145. 9.146. 9.147. 9.148. 9.149. 9.150. 9.151. 9.152. 9.153. 9.154. 9.155. 9.156. 9.157. 9.158. 9.159. 9.160. 9.161. 9.162. 9.163. 9.164. MX-E1H: VOICE DSP CONTROL 2 ..................................................................................................................... .136 MX-E2H: VOICE DSP CONTROL 3 ..................................................................................................................... .136 MX-E3H: VOICE DSP CONTROL 4 ..................................................................................................................... .136 MX-E4H: VOICE DSP CONTROL 5 ..................................................................................................................... .137 MX-E5H: VOICE DSP CONTROL 6 ..................................................................................................................... .137 MX-ECH: MONO ADC W IND FILTER CONTROL 1 ............................................................................................. .137 MX-EDH: MONO ADC W IND FILTER CONTROL 2 ............................................................................................. .138 MX-EEH: STEREO2 ADC W IND FILTER CONTROL 1 ..........................................................................................139 MX-EFH: STEREO2 ADC W IND FILTER CONTROL 2 ..........................................................................................140 MX-F8H: J ACK DETECTION CONTROL ............................................................................................................... .140 MX-F9H: J ACK DETECTION CONTROL ............................................................................................................... .141 MX-FAH: GENERAL CONTROL 1 ....................................................................................................................... .142 PR-3DH: ADC/DAC RESET CONTROL ............................................................................................................ .143 PR-A4H: DAC_L EQ (LPF:A1) ......................................................................................................................... .143 PR-A5H: DAC_L EQ (LPF:H0)......................................................................................................................... .143 PR-A6H: DAC_R EQ (LPF:A1) ......................................................................................................................... .144 PR-A7H: DAC_R EQ (LPF:H0) .........................................................................................................................144 PR-AEH: DAC_L EQ (BPF2:A1) ...................................................................................................................... .144 PR-AFH: DAC_L EQ (BPF2:A2)....................................................................................................................... .144 PR-B0H: DAC_L EQ (BPF2:H0) ...................................................................................................................... .145 PR-B1H: DAC_R EQ (BPF2:A1) ....................................................................................................................... .145 PR-B2H: DAC_R EQ (BPF2:A2) ....................................................................................................................... .145 PR-B3H: DAC_R EQ (BPF2:H0) ...................................................................................................................... .145 PR-B4H: DAC_L EQ (BPF3:A1) ....................................................................................................................... .146 PR-B5H: DAC_L EQ (BPF3:A2) ....................................................................................................................... .146 PR-B6H: DAC_L EQ (BPF3:H0) ...................................................................................................................... .146 PR-B7H: DAC_R EQ (BPF3:A1) ....................................................................................................................... .146 PR-B8H: DAC_R EQ (BPF3:A2) ....................................................................................................................... .147 PR-B9H: DAC_R EQ (BPF3:H0) ...................................................................................................................... .147 PR-BAH: DAC_L EQ (BPF4:A1) ...................................................................................................................... .147 PR-BBH: DAC_L EQ (BPF4:A2) ...................................................................................................................... .147 PR-BCH: DAC_L EQ (BPF4:H0) ...................................................................................................................... .148 PR-BDH: DAC_R EQ (BPF4:A1) ...................................................................................................................... .148 PR-BEH: DAC_R EQ (BPF4:A2) ...................................................................................................................... .148 PR-BFH: DAC_R EQ (BPF4:H0) ...................................................................................................................... .148 PR-C0H: DAC_L EQ (HPF1:A1) ....................................................................................................................... .149 PR-C1H: DAC_L EQ (HPF1:H0) ...................................................................................................................... .149 PR-C2H: DAC_R EQ (HPF1:A1)....................................................................................................................... .149 PR-C3H: DAC_R EQ (HPF1:H0) ...................................................................................................................... .149 PR-C4H: DAC_L EQ (HPF2:A1) ....................................................................................................................... .150 PR-C5H: DAC_L EQ (HPF2:A2) ....................................................................................................................... .150 PR-C6H: DAC_L EQ (HPF2:H0) ...................................................................................................................... .150 PR-C7H: DAC_R EQ (HPF2:A1)....................................................................................................................... .150 PR-C8H: DAC_R EQ (HPF2:A2)....................................................................................................................... .151 PR-C9H: DAC_R EQ (HPF2:H0) ...................................................................................................................... .151 PR-CAH: DAC_L EQ PRE-VOLUME CONTROL ................................................................................................. .151 PR-CBH: DAC_R EQ PRE-VOLUME CONTROL ................................................................................................. .151 PR-CCH: DAC_L EQ POST-VOLUME CONTROL ............................................................................................... .152 PR-CDH: DAC_R EQ POST-VOLUME CONTROL ............................................................................................... .152 PR-CEH: ADC EQ (LPF:A1) ............................................................................................................................. .152 PR-CFH: ADC EQ (LPF:H0) ............................................................................................................................. .153 PR-D0H: ADC EQ (BPF1:A1) ........................................................................................................................... .153 PR-D1H: ADC EQ (BPF1:A2) ........................................................................................................................... .153 PR-D2H: ADC EQ (BPF1:H0)........................................................................................................................... .153 PR-D3H: ADC EQ (BPF2:A1) ........................................................................................................................... .154 7 Rev. 0.91

ALC5670-VB Datasheet
9.165. 9.166. 9.167. 9.168. 9.169. 9.170. 9.171. 9.172. 9.173. 9.174. 9.175. 9.176. 9.177. 9.178. 9.179. 9.180. 9.181. 9.182. 9.183. 9.184. 9.185. 9.186. 9.187. 9.188. 9.189. 9.190. 9.191. 9.192. 9.193. 9.194. 9.195. 9.196. 9.197. 10. PR-D4H: ADC EQ (BPF2:A2) ........................................................................................................................... .154 PR-D5H: ADC EQ (BPF2:H0)........................................................................................................................... .154 PR-D6H: ADC EQ (BPF3:A1) ........................................................................................................................... .154 PR-D7H: ADC EQ (BPF3:A2) ........................................................................................................................... .155 PR-D8H: ADC EQ (BPF3:H0)........................................................................................................................... .155 PR-D9H: ADC EQ (BPF4:A1) ........................................................................................................................... .155 PR-DAH: ADC EQ (BPF4:A2) ...........................................................................................................................155 PR-DBH: ADC EQ (BPF4:H0) .......................................................................................................................... .156 PR-DCH: ADC EQ (HPF1:A1) .......................................................................................................................... .156 PR-DDH: ADC EQ (HPF1:H0).......................................................................................................................... .156 PR-E1H: ADC EQ PRE-VOLUME CONTROL....................................................................................................... .156 PR-E2H: ADC EQ POST-VOLUME CONTROL ..................................................................................................... .157 PR-E5H: DAC_L B IQUAD EQ (BPF1:H0-1) ...................................................................................................... .157 PR-E6H: DAC_L B IQUAD EQ (BPF1:H0-2) ...................................................................................................... .157 PR-E7H: DAC_L B IQUAD EQ (BPF1:B1-1)....................................................................................................... .157 PR-E8H: DAC_L B IQUAD EQ (BPF1:B1-2)....................................................................................................... .158 PR-E9H: DAC_L B IQUAD EQ (BPF1:B2-1)....................................................................................................... .158 PR-EAH: DAC_L B IQUAD EQ (BPF1:B2-2)...................................................................................................... .158 PR-EBH: DAC_L B IQUAD EQ (BPF1:A1-1)...................................................................................................... .158 PR-ECH: DAC_L B IQUAD EQ (BPF1:A1-2)...................................................................................................... .159 PR-EDH: DAC_L B IQUAD EQ (BPF1:A2-1) ..................................................................................................... .159 PR-EEH: DAC_L B IQUAD EQ (BPF1:A2-2) ...................................................................................................... .159 PR-EFH: DAC_R B IQUAD EQ (BPF1:H0-1) ...................................................................................................... .160 PR-F0H: DAC_R B IQUAD EQ (BPF1:H0-2) ...................................................................................................... .160 PR-F1H: DAC_R B IQUAD EQ (BPF1:B1-1)....................................................................................................... .160 PR-F2H: DAC_R B IQUAD EQ (BPF1:B1-2)....................................................................................................... .160 PR-F3H: DAC_R B IQUAD EQ (BPF1:B2-1)....................................................................................................... .161 PR-F4H: DAC_R B IQUAD EQ (BPF1:B2-2)....................................................................................................... .161 PR-F5H: DAC_R B IQUAD EQ (BPF1:A1-1) ...................................................................................................... .161 PR-F6H: DAC_R B IQUAD EQ (BPF1:A1-2) ...................................................................................................... .161 PR-F7H: DAC_R B IQUAD EQ (BPF1:A2-1) ...................................................................................................... .161 PR-F8H: DAC_R B IQUAD EQ (BPF1:A2-2) ...................................................................................................... .162 MX-FEH: VENDOR ID ........................................................................................................................................162

ELECTRICAL CHARACTERISTICS................................................................................................................... .163

10.1. DC CHARACTERISTICS ............................................................................................................................. ................163 10.1.1. Absolute Maximum Ratings .......................................................................................................................... .163 10.1.2. Recommended Operating Conditions ........................................................................................................... .163 10.1.3. Static Characteristics............................................................................................................................. ........163 10.2. ANALOG PERFORMANCE CHARACTERISTICS ........................................................................................................... .164 10.3. SIGNAL T IMING ............................................................................................................................. ...........................165 10.3.1. I2C Control Interface ............................................................................................................................. ........165 10.3.2. I2S/PCM Interface Master Mode .................................................................................................................. .166 10.3.3. I2S/PCM Interface Slave Mode ..................................................................................................................... .167 10.3.4. Digital Microphone Interface ....................................................................................................................... .168 10.4. PDM INTERFACE T IMING ............................................................................................................................. ............169 11. 12. 12.1. 12.2. 13. APPLICATION CIRCUITS ............................................................................................................................. ........170 PACKAGE INFORMATION ............................................................................................................................. ......172 MECHANICAL D IMENSIONS ............................................................................................................................. .........172 PACKAGE THERMAL INFORMATION ........................................................................................................................ .173 ORDERING INFORMATION ............................................................................................................................. ....174

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ALC5670-VB Datasheet

List of Tables
TABLE 1. DIGITAL I/O P INS ..........................................................................................................................................................8 TABLE 2. ANALOG I/O P INS ........................................................................................................................................................10 TABLE 3. FILTER/REFERENCE .....................................................................................................................................................11 TABLE 4. POWER/GROUND ............................................................................................................................. ............................11 TABLE 5. POWER SUPPLY FOR BEST PERFORMANCE ...................................................................................................................13 TABLE 6. POWER SUPPLY CONDITION FOR POWER DOWN LEAKAGE ..........................................................................................13 TABLE 7. RESET OPERATION ......................................................................................................................................................15 TABLE 8. POWER-ON RESET VOLTAGE .......................................................................................................................................15 TABLE 9. THE RELATIVE OF SYSCLK/BCLK/LRCK .................................................................................................................17 TABLE 10. REGISTER SETTINGS FOR ASRC FUNCTION ON SLAVE MODE ...................................................................................19 TABLE 11. SAMPLE RATE WITH FILTER COEFFICIENT FOR WIND FILTER .....................................................................................39 TABLE 12. ADDRESS SETTING (0X38H) ............................................................................................................................. .........41 TABLE 13. WRITE WORD PROTOCOL ........................................................................................................................................42 TABLE 14. READ WORD PROTOCOL ..........................................................................................................................................42 TABLE 15. REGISTER MAP ..........................................................................................................................................................52 TABLE 16. MX-00H: S/W RESET ................................................................................................................................................57 TABLE 17. MX-02H: HEADPHONE OUTPUT CONTROL ................................................................................................................57 TABLE 18. MX-03H: LINE OUTPUT CONTROL ...........................................................................................................................58 TABLE 19. MX-0DH: IN1 INPUT CONTROL - 1 ...........................................................................................................................60 TABLE 20. MX-0BH: IN1 INPUT CONTROL - 2............................................................................................................................60 TABLE 21. MX-0CH: IN1 INPUT CONTROL - 3............................................................................................................................61 TABLE 22. MX-0DH: IN2 INPUT CONTROL ................................................................................................................................61 TABLE 23. MX-0EH: IN3 INPUT CONTROL .................................................................................................................................62 TABLE 24. MX-0FH: INL & INR VOLUME CONTROL.................................................................................................................62 TABLE 25. MX-19H: DACL1/R1 DIGITAL VOLUME ..................................................................................................................63 TABLE 26. MX-1AH: DACL2/R2 DIGITAL VOLUME..................................................................................................................64 TABLE 27. MX-1BH: DACL2/R2 MUTE/UN-MUTE CONTROL ...................................................................................................66 TABLE 28. MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................67 TABLE 29. MX-1DH: MONO ADC DIGITAL VOLUME CONTROL ................................................................................................67 TABLE 30. MX-1EH: ADC DIGITAL BOOST GAIN CONTROL ......................................................................................................69 TABLE 31. MX-1FH: STEREO2 ADC DIGITAL VOLUME CONTROL .............................................................................................70 TABLE 32. MX-20H: MONO ADC DIGITAL BOOST GAIN CONTROL ...........................................................................................70 TABLE 33. MX-26H: STEREO2 ADC DIGITAL MIXER CONTROL ................................................................................................71 TABLE 34. MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ................................................................................................72 TABLE 35. MX-28H: MONO ADC DIGITAL MIXER CONTROL ....................................................................................................73 TABLE 36. MX-29H: STEREO ADC TO DAC DIGITAL M IXER CONTROL ....................................................................................74 TABLE 37. MX-2AH: STEREO DAC DIGITAL M IXER CONTROL .................................................................................................74 TABLE 38. MX-2BH: MONO DAC DIGITAL MIXER CONTROL....................................................................................................75 TABLE 39. MX-2CH: DAC DIGITAL MIXER CONTROL ...............................................................................................................76 TABLE 40. MX-2DH: VOICE DSP PATH CONTROL 1 ..................................................................................................................78 TABLE 41. MX-2EH: VOICE DSP VOLUME CONTROL ................................................................................................................79 TABLE 42. MX-2FH: INTERFACE DAC/ADC DATA CONTROL ...................................................................................................79 TABLE 43. MX-31H: PDM INTERFACE CONTROL.......................................................................................................................80 TABLE 44. MX-32H: PDM INTERFACE CONTROL.......................................................................................................................81 TABLE 45. MX-35H: PDM INTERFACE CONTROL.......................................................................................................................81 TABLE 46. MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................81 TABLE 47. MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................82 TABLE 48. MX-3DH: RECMIXR CONTROL 1 ............................................................................................................................82 TABLE 49. MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................83 TABLE 50. MX-3FH: RECMIXM CONTROL 1 ............................................................................................................................83 9 Rev. 0.91

ALC5670-VB Datasheet
TABLE 51. MX-40H: RECMIXM CONTROL 2 ........................................................................................................................... .84 TABLE 52. MX-45H: HPOMIX CONTROL ............................................................................................................................. .....84 TABLE 53. MX-4FH: OUTMIXL CONTROL ............................................................................................................................. ..85 TABLE 54. MX-52H: OUTMIXR CONTROL 3 ........................................................................................................................... .85 TABLE 55. MX-53H: LOUTMIX CONTROL ............................................................................................................................. ..86 TABLE 56. MX-61H: POWER MANAGEMENT CONTROL 1 .......................................................................................................... .86 TABLE 57. MX-62H: POWER MANAGEMENT CONTROL 2 .......................................................................................................... .87 TABLE 58. MX-63H: POWER MANAGEMENT CONTROL 3 .......................................................................................................... .88 TABLE 59. MX-64H: POWER MANAGEMENT CONTROL 4 .......................................................................................................... .89 TABLE 60. MX-65H: POWER MANAGEMENT CONTROL 5 .......................................................................................................... .90 TABLE 61. MX-66H: POWER MANAGEMENT CONTROL 6 .......................................................................................................... .90 TABLE 62. MX-6AH: PRIVATE REGISTER INDEX ....................................................................................................................... .91 TABLE 63. MX-6CH: PRIVATE REGISTER DATA ........................................................................................................................ .91 TABLE66. MX-70H: I2S1 DIGITAL INTERFACE CONTROL ......................................................................................................... .92 TABLE 64. MX-71H: I2S2 DIGITAL INTERFACE CONTROL......................................................................................................... .92 TABLE 65. MX-72H: I2S3 DIGITAL INTERFACE CONTROL......................................................................................................... .93 TABLE 66. MX-73H: ADC/DAC CLOCK CONTROL ................................................................................................................... .94 TABLE 67. MX-74H: ADC/DAC HPF CONTROL ....................................................................................................................... .95 TABLE 68. MX-75H: DIGITAL M ICROPHONE CONTROL 1 .......................................................................................................... .96 TABLE 69. MX-76H: DIGITAL M ICROPHONE CONTROL 2 .......................................................................................................... .97 TABLE 70. MX-77H: TDM INTERFACE CONTROL 1................................................................................................................... .98 TABLE 71. MX-78H: TDM INTERFACE CONTROL 2................................................................................................................... .99 TABLE 72. MX-79H: TDM INTERFACE CONTROL 3................................................................................................................. .100 TABLE 73. MX-7FH: CLOCK CONTROL 1............................................................................................................................ ......101 TABLE 74. MX-80H: GLOBAL CLOCK CONTROL ..................................................................................................................... .101 TABLE 75. MX-81H: PLL CONTROL 1 ............................................................................................................................. .........102 TABLE 76. MX-82H: PLL CONTROL 2 ............................................................................................................................. .........102 TABLE 77. MX-83H: ASRC CONTROL 1............................................................................................................................. ......103 TABLE 78. MX-84H: ASRC CONTROL 2............................................................................................................................. ......104 TABLE 79. MX-85H: ASRC CONTROL 3............................................................................................................................. ......105 TABLE 80. MX-8AH: ASRC CONTROL 4 ............................................................................................................................. .....106 TABLE 81. MX-8CH: ASRC CONTROL 5 ............................................................................................................................. .....107 TABLE 82. MX-8EH: HP AMP CONTROL 1 ............................................................................................................................. ..107 TABLE 83. MX-8FH: HP AMP CONTROL 2 ............................................................................................................................. ..108 TABLE 84. MX-91H: CHARGE PUMP CONTROL ....................................................................................................................... .108 TABLE 85. MX-93H: MICBIAS CONTROL ............................................................................................................................. ..109 TABLE 86. MX-94H: JD1 CONTROL ............................................................................................................................. ............110 TABLE 87. MX-9AH: SLD FUNCTION CONTROL ..................................................................................................................... .110 TABLE 88. MX-9BH: SLD FUNCTION THRESHOLD CONTROL 1 .............................................................................................. .111 TABLE 89. MX-9CH: SLD FUNCTION THRESHOLD CONTROL 2 .............................................................................................. .111 TABLE 90. MX-9DH: SLD FUNCTION THRESHOLD CONTROL 3 .............................................................................................. .111 TABLE 91. MX-9EH: SLD FLAG ............................................................................................................................. ..................112 TABLE 92. MX-AEH: ADC PATH EQ CONTROL 1................................................................................................................... .112 TABLE 93. MX-AFH: ADC PATH EQ CONTROL 2 ................................................................................................................... .113 TABLE 94. MX-B0H: DAC PATH EQ CONTROL 1 ................................................................................................................... .114 TABLE 95. MX-B1H: EQ CONTROL 2 ............................................................................................................................. ..........115 TABLE 96. MX-B2H: DRC CONTROL 1 ............................................................................................................................. .......116 TABLE 97. MX-B3H: DRC CONTROL 2 ............................................................................................................................. .......116 TABLE 98. MX-B4H: DRC CONTROL 3 ............................................................................................................................. .......117 TABLE 99. MX-B5H: DRC CONTROL 4 ............................................................................................................................. .......118 TABLE 100. MX-B6H: DRC CONTROL 5 ............................................................................................................................. .....119 TABLE 101. MX-B7H: DRC CONTROL 6 ............................................................................................................................. .....120 TABLE 102. MX-BBH: JACK DETECTION CONTROL 1 ............................................................................................................. .120 TABLE 103. MX-BCH: JACK DETECTION CONTROL 2 ............................................................................................................. .121 TABLE 104. MX-BDH: IRQ CONTROL 1............................................................................................................................. ......122 10 Rev. 0.91

ALC5670-VB Datasheet
TABLE 105. TABLE 106. TABLE 107. TABLE 108. TABLE 109. TABLE 110. TABLE 111. TABLE 112. TABLE 113. TABLE 114. TABLE 115. TABLE 116. TABLE 117. TABLE 118. TABLE 119. TABLE 120. TABLE 121. TABLE 122. TABLE 123. TABLE 124. TABLE 125. TABLE 126. TABLE 127. TABLE 128. TABLE 129. TABLE 130. TABLE 131. TABLE 132. TABLE 133. TABLE 134. TABLE 135. TABLE 136. TABLE 137. TABLE 138. TABLE 139. TABLE 140. TABLE 141. TABLE 142. TABLE 143. TABLE 144. TABLE 145. TABLE 146. TABLE 147. TABLE 148. TABLE 149. TABLE 150. TABLE 151. TABLE 152. TABLE 153. TABLE 154. TABLE 155. TABLE 156. TABLE 157. TABLE 158. TABLE 159. MX-BEH: IRQ CONTROL 2 ............................................................................................................................. ......123 MX-BFH: IRQ CONTROL 3 ............................................................................................................................. ......124 MX-C0H: GPIO CONTROL 1 ............................................................................................................................. ....125 MX-C1H: GPIO CONTROL 2 ............................................................................................................................. ....126 MX-C2H: GPIO CONTROL 3 ............................................................................................................................. ....127 MX-CDH: DIGITAL PATH CONTROL .................................................................................................................... .128 MX-CFH: SOUNZREALTM BASSB ACK CONTROL ............................................................................................... .128 MX-D0H: SOUNZREALTM TRUTREBLE CONTROL 1 ........................................................................................... .129 MX-D1H: SOUNZREALTM L TRUTREBLE CONTROL 2..........................................................................................129 MX-D3H: STEREO1 ADC W IND FILTER CONTROL 1 ........................................................................................... .130 MX-D4H: STEREO1 ADC W IND FILTER CONTROL 2 ........................................................................................... .131 MX-D6H: HP AMP CONTROL............................................................................................................................. ...131 MX-D9H: SOFT VOLUME & ZCD CONTROL 1 ..................................................................................................... .132 MX-DAH: SOFT VOLUME & ZCD CONTROL 2..................................................................................................... .132 MX-DBH: INLINE COMMAND CONTROL 1 ........................................................................................................... .133 MX-DCH: INLINE COMMAND CONTROL 2 ........................................................................................................... .134 MX-DDH: INLINE COMMAND CONTROL 3 ........................................................................................................... .135 MX-E0H: VOICE DSP CONTROL 1 ....................................................................................................................... .135 MX-E1H: VOICE DSP CONTROL 2 ....................................................................................................................... .136 MX-E2H: VOICE DSP CONTROL 3 ....................................................................................................................... .136 MX-E3H: VOICE DSP CONTROL 4 ....................................................................................................................... .137 MX-E4H: VOICE DSP CONTROL 5 ....................................................................................................................... .137 MX-E5H: VOICE DSP CONTROL 6 ....................................................................................................................... .137 MX-ECH: MONO ADC W IND FILTER CONTROL 1 ............................................................................................... .137 MX-EDH: MONO ADC W IND FILTER CONTROL 2 ............................................................................................... .138 MX-EEH: STEREO2 ADC W IND FILTER CONTROL 1 ........................................................................................... .139 MX-EFH: STEREO2 ADC W IND FILTER CONTROL 2............................................................................................ .140 MX-F8H: JACK DETECTION CONTROL ................................................................................................................. .141 MX-F9H: JACK DETECTION CONTROL ................................................................................................................. .141 MX-FAH: GENERAL CONTROL 1.......................................................................................................................... .142 PR-3DH: ADC/DAC RESET CONTROL............................................................................................................... .143 PR-A4H: DAC_L EQ (LPF2:A1) ......................................................................................................................... .143 PR-A5H: DAC_L EQ (LPF2:H0)......................................................................................................................... .143 PR-A6H: DAC_R EQ (LPF2:A1) ......................................................................................................................... .144 PR-A7H: DAC_R EQ (LPF:H0) .......................................................................................................................... .144 PR-AEH: DAC_L EQ (BPF2:A1)......................................................................................................................... .144 PR-AFH: DAC_L EQ (BPF2:A2) ......................................................................................................................... .144 PR-B0H: DAC_L EQ (BPF2:H0)......................................................................................................................... .145 PR-B1H: DAC_R EQ (BPF2:A1) ......................................................................................................................... .145 PR-B2H: DAC_R EQ (BPF2:A2) ......................................................................................................................... .145 PR-B3H: DAC_R EQ (BPF2:H0) ........................................................................................................................ .145 PR-B4H: DAC_L EQ (BPF3:A1) ......................................................................................................................... .146 PR-B5H: DAC_L EQ (BPF3:A2) ......................................................................................................................... .146 PR-B6H: DAC_L EQ (BPF3:H0)......................................................................................................................... .146 PR-B7H: DAC_R EQ (BPF3:A1) ......................................................................................................................... .146 PR-B8H: DAC_R EQ (BPF3:A2) ......................................................................................................................... .147 PR-B9H: DAC_R EQ (BPF3:H0) ........................................................................................................................ .147 PR-BAH: DAC_L EQ (BPF4:A1) ........................................................................................................................ .147 PR-BBH: DAC_L EQ (BPF4:A2)......................................................................................................................... .147 PR-BCH: DAC_L EQ (BPF4:H0) ........................................................................................................................ .148 PR-BDH: DAC_R EQ (BPF4:A1) ........................................................................................................................ .148 PR-BEH: DAC_R EQ (BPF4:A2)......................................................................................................................... .148 PR-BFH: DAC_R EQ (BPF4:H0) ........................................................................................................................ .148 PR-C0H: DAC_L EQ (HPF1:A1) ......................................................................................................................... .149 PR-C1H: DAC_L EQ (HPF1:H0) ........................................................................................................................ .149 11 Rev. 0.91

ALC5670-VB Datasheet
TABLE 160. TABLE 161. TABLE 162. TABLE 163. TABLE 164. TABLE 165. TABLE 166. TABLE 167. TABLE 168. TABLE 169. TABLE 170. TABLE 171. TABLE 172. TABLE 173. TABLE 174. TABLE 175. TABLE 176. TABLE 177. TABLE 178. TABLE 179. TABLE 180. TABLE 181. TABLE 182. TABLE 183. TABLE 184. TABLE 185. TABLE 186. TABLE 187. TABLE 188. TABLE 189. TABLE 190. TABLE 191. TABLE 192. TABLE 193. TABLE 194. TABLE 195. TABLE 196. TABLE 197. TABLE 198. TABLE 199. TABLE 200. TABLE 201. TABLE 202. TABLE 203. TABLE 204. TABLE 205. TABLE 206. TABLE 207. TABLE 208. TABLE 209. TABLE 210. TABLE 211. TABLE 212. TABLE 213. TABLE 214. PR-C2H: DAC_R EQ (HPF1:A1) ......................................................................................................................... .149 PR-C3H: DAC_R EQ (HPF1:H0) ........................................................................................................................ .149 PR-C4H: DAC_L EQ (HPF2:A1) ......................................................................................................................... .150 PR-C5H: DAC_L EQ (HPF2:A2) ......................................................................................................................... .150 PR-C6H: DAC_L EQ (HPF2:H0) ........................................................................................................................ .150 PR-C7H: DAC_R EQ (HPF2:A1) ......................................................................................................................... .150 PR-C8H: DAC_R EQ (HPF2:A2) ......................................................................................................................... .151 PR-C9H: DAC_R EQ (HPF2:H0) ........................................................................................................................ .151 PR-CAH: DAC_L EQ PRE-VOLUME CONTROL ................................................................................................... .151 PR-CBH: DAC_R EQ PRE-VOLUME CONTROL ................................................................................................... .151 PR-CCH: DAC_L EQ POST-VOLUME CONTROL.................................................................................................. .152 PR-CDH: DAC_R EQ POST-VOLUME CONTROL ................................................................................................. .152 PR-CEH: ADC EQ (LPF:A1) ............................................................................................................................. ...152 PR-CFH: ADC EQ (LPF:H0) ............................................................................................................................. ...153 PR-D0H: ADC EQ (BPF1:A1) ............................................................................................................................. .153 PR-D1H: ADC EQ (BPF1:A2) ............................................................................................................................. .153 PR-D2H: ADC EQ (BPF1:H0) ............................................................................................................................. .153 PR-D3H: ADC EQ (BPF2:A1) ............................................................................................................................. .154 PR-D4H: ADC EQ (BPF2:A2) ............................................................................................................................. .154 PR-D5H: ADC EQ (BPF2:H0) ............................................................................................................................. .154 PR-D6H: ADC EQ (BPF3:A1) ............................................................................................................................. .154 PR-D7H: ADC EQ (BPF3:A2) ............................................................................................................................. .155 PR-D8H: ADC EQ (BPF3:H0) ............................................................................................................................. .155 PR-D9H: ADC EQ (BPF4:A1) ............................................................................................................................. .155 PR-DAH: ADC EQ (BPF4:A2)............................................................................................................................. .155 PR-DBH: ADC EQ (BPF4:H0) ............................................................................................................................ .156 PR-DCH: ADC EQ (HPF1:A1)............................................................................................................................. .156 PR-DDH: ADC EQ (HPF1:H0)............................................................................................................................ .156 PR-E1H: ADC EQ PRE-VOLUME CONTROL ......................................................................................................... .156 PR-E2H: ADC EQ POST-VOLUME CONTROL ....................................................................................................... .157 PR-E5H: DAC_L B IQUAD EQ (BPF1:H0-1)......................................................................................................... .157 PR-E6H: DAC_L B IQUAD EQ (BPF1:H0-2)......................................................................................................... .157 PR-E7H: DAC_L B IQUAD EQ (BPF1:B1-1)......................................................................................................... .158 PR-E8H: DAC_L B IQUAD EQ (BPF1:B1-2)......................................................................................................... .158 PR-E9H: DAC_L B IQUAD EQ (BPF1:B2-1)......................................................................................................... .158 PR-EAH: DAC_L B IQUAD EQ (BPF1:B2-2) ........................................................................................................ .158 PR-EBH: DAC_L B IQUAD EQ (BPF1:A1-1) ........................................................................................................ .159 PR-ECH: DAC_L B IQUAD EQ (BPF1:A1-2) ........................................................................................................ .159 PR-EDH: DAC_L B IQUAD EQ (BPF1:A2-1)........................................................................................................ .159 PR-EEH: DAC_L B IQUAD EQ (BPF1:A2-2) ........................................................................................................ .159 PR-EFH: DAC_R B IQUAD EQ (BPF1:H0-1) ........................................................................................................ .160 PR-F0H: DAC_R B IQUAD EQ (BPF1:H0-2)......................................................................................................... .160 PR-F1H: DAC_R B IQUAD EQ (BPF1:B1-1)......................................................................................................... .160 PR-F2H: DAC_R B IQUAD EQ (BPF1:B1-2)......................................................................................................... .160 PR-F3H: DAC_R B IQUAD EQ (BPF1:B2-1)......................................................................................................... .161 PR-F4H: DAC_R B IQUAD EQ (BPF1:B2-2)......................................................................................................... .161 PR-F5H: DAC_R B IQUAD EQ (BPF1:A1-1)......................................................................................................... .161 PR-F6H: DAC_R B IQUAD EQ (BPF1:A1-2)......................................................................................................... .161 PR-F7H: DAC_R B IQUAD EQ (BPF1:A2-1)......................................................................................................... .162 PR-F8H: DAC_R B IQUAD EQ (BPF1:A2-2)......................................................................................................... .162 MX-FEH: VENDOR ID...........................................................................................................................................162 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... .163 RECOMMENDED OPERATING CONDITIONS............................................................................................................ .163 STATIC CHARACTERISTICS ............................................................................................................................. .......163 ANALOG PERFORMANCE CHARACTERISTICS ........................................................................................................ .164 12 Rev. 0.91

ALC5670-VB Datasheet
TABLE 215. TABLE 216. TABLE 217. TABLE 218. TABLE 219. TABLE 220. TABLE 221. I2C TIMING ............................................................................................................................. ...............................166 TIMING OF I2S/PCM MASTER MODE .................................................................................................................... .166 I2S/PCM SLAVE MODE TIMING............................................................................................................................ .167 DIGITAL MICROPHONE INTERFACE T IMING .......................................................................................................... .168 PDM INTERFACE T IMING ............................................................................................................................. .........169 THERMAL INFORMATION ............................................................................................................................. ..........173 ORDERING INFORMATION ............................................................................................................................. .........174

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ALC5670-VB Datasheet

List of Figures
FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. FIGURE 25. FIGURE 26. FIGURE 27. FIGURE 28. FIGURE 29. FIGURE 30. FIGURE 31. FIGURE 32. FIGURE 33. FIGURE 34. FIGURE 35. FIGURE 36. FIGURE 37. FIGURE 38. FIGURE 39. BLOCK DIAGRAM .......................................................................................................................................................4 AUDIO MIXER PATH ...................................................................................................................................................5 DIGITAL MIXER PATH ................................................................................................................................................6 PIN ASSIGNMENTS ......................................................................................................................................................7 GENERAL SYSTEM CONNECTION ..............................................................................................................................12 POWER ON/OFF TIMING ...........................................................................................................................................14 AUDIO CLOCK TREE ............................................................................................................................. ....................16 SYSTEM CONNECTION FOR ASRC FUNCTION ...........................................................................................................18 PCM MONO DATA MODE A FORMAT (BCLK POLARITY=0) ..............................................................................20 PCM MONO DATA MODE A FORMAT (BCLK POLARITY=1) ............................................................................20 PCM MONO DATA MODE B FORMAT (BCLK POLARITY=0) ............................................................................21 PCM STEREO DATA MODE A FORMAT (BCLK POLARITY=0)............................................................................21 PCM TDM DATA MODE A FORMAT (BCLK POLARITY=0) ...............................................................................21 PCM STEREO DATA MODE B FORMAT (BCLK POLARITY=0)..............................................................................22 PCM TDM DATA MODE B FORMAT (BCLK POLARITY=0) .................................................................................22 I2S DATA FORMAT (BCLK POLARITY=0) ............................................................................................................22 I2S TDM DATA FORMAT (BCLK POLARITY=0) ................................................................................................. .23 LEFT-JUSTIFIED DATA FORMAT (BCLK POLARITY=0) ........................................................................................23 LEFT-JUSTIFIED TDM DATA FORMAT (BCLK POLARITY=0) ...............................................................................23 4-CHANNEL RECORDING PATH ................................................................................................................................24 4-CHANNEL P LAYBACK PATH ..................................................................................................................................25 DAC DRC FUNCTION B LOCK ..................................................................................................................................32 ADC AGC FUNCTION BLOCK ..................................................................................................................................32 PLAYBACK DRC OUTPUT CURVE ............................................................................................................................33 RECORD DRC OUTPUT CURVE - 1............................................................................................................................34 RECORD DRC OUTPUT CURVE - 2............................................................................................................................35 DRC/AGC FOR PLAYBACK/RECORDING MODE .......................................................................................................36 DRC/AGC FOR NOISE GATE MODE .........................................................................................................................37 DATA TRANSFER OVER I2C CONTROL INTERFACE ..................................................................................................41 GPIO FUNCTION BLOCK ..........................................................................................................................................43 IRQ FUNCTION BLOCK.............................................................................................................................................44 POWER MANAGEMENT ............................................................................................................................. ................48 I2C CONTROL INTERFACE .......................................................................................................................................165 T IMING OF I2S/PCM MASTER MODE ......................................................................................................................166 I2S/PCM SLAVE MODE TIMING .............................................................................................................................167 DIGITAL MICROPHONE INTERFACE T IMING............................................................................................................168 PDM INTERFACE ....................................................................................................................................................169 APPLICATION CIRCUIT ...........................................................................................................................................171 PACKAGE DIMENSION ............................................................................................................................................172

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ALC5670 Datasheet

1.

General Description

The ALC5670 is a high performance, low power, up to three I2S interface audio CODEC with embedded low power/high performance Voice DSP. Three I2S interface can connect to different devices and let the ALC5670 to be an Audio Hub. Each device can pass through the Audio Hub and then perform as input or output application. Asynchronous Sample Rate Converter (ASRC) provides independent and asynchronous connections to different processors, such as an application processor, baseband processor or wireless transceiver(BT). The ALC5670 features an ultra low power cap-free headphone amplifier. It consumes only less than 5mW power during playback, providing mobile system longer battery life under headphone listening mode. The integrated multi-section DRC(Dynamic Range Controller) and 14-band parametric Equalizer provide further digital sound processing capability of audio playback paths. The multi-section DRC in ALC5670 continuously monitors the DAC output level. When the power level is low, it increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and speaker damage. The 14-band parametric Equalizer contains each channel has 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to user preferences. For microphone recording, the DRC in ALC5670 can be used as AGC(Auto Gain Controller) to maintain a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The filter can detect the level of wind noise and on/off dynamically to keep the recording quality. The ALC5670 also integrates independent 6-band parametric Equalizer for recording path. They can use to compensate microphone device frequency response. ALC5670 embedded a low power, high performance voice processor. The 140MIPS voice processor provides advanced voice processing features, including exceptional noise suppression, echo cancellation and advanced Beam-Forming under low power consumption. The voice processor is optimized for advanced voice processing to improve voice quality for voice communication and recording in noisy environments. ALC5670 builds-in two PDM interface for external speaker amplifiers. The PDM interface supports 128FS clock rate. The PDM interface also supports PDM pattern command to control external PDM speaker amplifier. SounzRealTM post-processing technology is configurable to provide better listening experience. BassBack EXPTM bring LFE(low frequency effect) to listeners without subwoofer needed. TruTreble EXPTM adds processed harmonic tones at high frequency, bringing more melody and details for music listening.

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ALC5670-VB Datasheet

2.
?

Features
Digital Voice DSP ? ? ? Voice communication enhancement (AEC, NS…etc.) Advanced Beam-Forming (Voice Tracking) Stereo Far field pick-up recording (48KHz Sample Rate) TruTreble

?

SounzRealTM post-processing ? Parametric 14 bands equalizer (EQ) – each 7 bands for L/R playback path independent control Parametric 6 bands equalizer (EQ) for recording path Advanced DRC with multi-section compressor function for playback/recording path Signal Level Detection (SLD) wake up technology Wind noise reduction filter One 24bit/8kHz ~ 192kHz I2S/PCM/TDM digital interface Two 24bit/8kHz ~ 192kHz I2S/PCM digital interface Digital asynchronous sampling rate converter (ASRC) function I2C control interface 3 stereo digital microphone interfaces Two digital PDM interfaces (Up to four channel speaker outputs) 4 Digital-to-Analog Converter with 100dBA SNR 3 Analog-to-Digital Converter with 94dBA SNR 3 single-ended analog microphone inputs with pre-amplifiers (+20/24/30/35/40/44/50/52dB) and low noise microphone bias ? MIC input to ADC with 50dB Boost, SNR>66dBA, THD+N<-65dB -84dB THD+N (with 0dB gain path) 94dBA SNR (with 0dB gain path) -85dB THD+N (with 0dB gain path, 10k ohm loading) 100dBA SNR (with 0dB gain path, 10k ohm loading) 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16Ohm)

? ? ? ? ? ? ? ? ? ? ? ? ? ?

?

Stereo line input ? ?

?

Stereo single-ended/mono differential line output ? ?

?

Stereo headphone output and without DC blocking capacitors ? Ultra-Low-Power for headphone playback

?

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ALC5670-VB Datasheet
? ?
? ? ? ? ? ?

Standby power consumption <=5mW (AVDD=DBVDD=CPVDD=1.8V, DCVDD=1.2V, 32Ohm, With I2S clock input) Playback power consumption <=10mW (AVDD=DBVDD=CPVDD=1.8V, DCVDD=1.2V, 32Ohm, With I2S clock input, Po=1mW)

Multiple audio jack insert detection function Headset in-line multi-function control support Power management and enhanced power saving Internal PLL can receive wide range clock input Two adjustable MICBIAS (0.9*MICVDD or 0.75*MICVDD) QFN-48 (6mmx6mm) package

3.

Power/Ground Operation Conditions
DECSRIPTION Digital I/O Power Digital Core Power Analog Power Microphone Bias Power Charge Pump Power Ground MIN 1.71 1.1 1.71 3.0 1.71 TYP 1.8 1.2 1.8 3.3 1.8 0 MAX 3.6 1.4 1.9 3.6 1.9 UNIT V V V V V V

POWER TYPE DBVDD DCVDD AVDD MICVDD CPVDD DGND, AGND, CPGND

4.
? ?

System Application
Smart Phones Tablet

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ALC5670-VB Datasheet

5.

Function Block and Mixer Path
MICVDD DCVDD CPVDD

5.1. Function Block

CPGND
DSP Core Mono Amp

LDO_IN DBVDD

LDO

Digital Core

Digtial I/O

MICBIAS1 MICBIAS2 0.9 * MICVDD 0.75 * MICVDD

DGND AGND CPP1 CPN1 CPP2 CPN2 CPVEE CPVPP

Charge Pump

AVDD
Analog Core

DACREF

AIN

CPVREF

IN1P_RING2 IN1P_SLEEVE
VCM
BST1

DAC_1 ADC_1

HPO_L HPO_R
DAC_2 ADC_2

LOUT

IN2P
VCM
BST2

REC MIXER
ADC_3

ADC Volume High Pass Filter

INL_Vol INR_Vol

Audio Signal Processing & Voice DSP

DAC Volume High Pass Filter

DAC_3

LOUT1L/P LOUT1R/N

DMIC1_L DMIC1_R DMIC2_L DAC_4

IN3P/INL INR

DMIC2_R VCM
BST3

DMIC3_L DMIC3_R

PDM Driver

PDM_SCL2 PDM_DAT2

I2 C Control

SCL SDA GPIO1/IRQ GPIO2/DMIC_SCL DMIC1_SDA

JD1 JD2 JD3 MICBIAS1 MICBIAS2 VREF

Analog JD

MICBIAS / Voltage Detection PLL Reference Voltage

Serial Interface Digital Audio Interface (I2S / PCM / TDM)

DMIC Interface

DMIC2_SDA DMIC3_SDA GPIO7 GPIO10

Figure 1.

Block Diagram

S_CLK_IN S_DAT_IN S_DAT_OUT

BCLK1 LRCK1 DACDAT1 ADCDAT1

BCLK2 LRCK2 DACDAT2 ADCDAT2

MCLK

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Rev. 0.91

ALC5670 Datasheet

5.2. Audio Mixer Path
DACL1 Filter & Digital Volu me -18 ~ 0dB, 3dB/Step Filter & Digital Volu me DACL1 + 12 ~ -34.5dB , 1.5dB/ step VOL INL1 HPMIXL DACR1 + 12 ~ -34.5dB , 1.5dB/ step VOL INR1 DACR1 RECMIXL 0/20/24/30/35/40/44/50/52 HPMIXR Filter & Digital Volu me DACL1 DAC_R1 DACR1 DACL2 INL1 BST1 -18 ~ 0dB, 3dB/Step BST1 0/20/24/30/35/40/44/50/52 Filter & Digital Volu me Gain Gain Gain Gain RECMIXR -34.5 ~ +12dB, 1.5dB/Step INR INL -34.5 ~ +12dB, 1.5dB/Step -18 ~ 0dB, 3dB/Step BST1 BST2 BST3 Filter & Digital Volume Gain Gain Gain ADC_3 Filter & Digital Volume DMIC_ DAT 1/2/3 ADC_2 + 12 ~ -34.5dB , 1.5 dB/ step VOL HPVOLR HPOR Amp OUTMIXL1 0 / -6 dB Gain HPOR HPVOLL HPOL Amp HPVOLR HPVOLL

DACL1

0 / -6 dB Gain

IN1P_RING2 IN1P_SLEEVE
VMID

0/20/24/30/35/40/44/50/52 BST1

BST1 BST2 BST3

DAC_L1

HPOL

Gain Gain Gain Gain

ADC_1

BST1

INL

IN2P
BST2 VMID BST2 DMIC_ DAT 1/2/3

Digital Block ALC/ DRC EQ Digital Volume

BST2 OUTMIXL1 DACR1 Filter & Digital Volu me

DACL1

0 / -6 dB Gain

IN3P/INL INR
VMID BST3

BST2 BST3 INR

OUTMIXL1

LOUT1L/P

1.5dB/ step DAC_L2 DACL2 BST3 INR1 OUTMIXR1 VOL

DACR1

0 / -6 dB Gain

LOUT1R/N

OUTMIXR1 LOUT1

DAC_R2

DACR2

RECMIXM

DACDAT1 ADCDAT1

Figure 2.

DACDAT2 ADCDAT2

Audio Mixer Path

5

Rev. 0.91

ALC5670 Datasheet

5.3. Digital Mixer Path
MX27[9:8] DMIC_L1 DMIC _L2 DMIC_L3 DAC_ MIXL MX27[13] Stereo1_ADC_Mixer_L MX2A[14] MX2A[9] MX2A[12] MX2A[2] MX2A[13]
Gain Gain

ADC_1 MX27[11] ADC_2

SNC II

MX2A[10]

MX27[12] DAC_ MIXL ADC_1 ADC_1 ADC_3 ADC_1 ADC_3 ADC_2 MX27[10] MX27[12] MX27[6] DAC_ MIXR ADC_3 ADC_3 MX27[11] DAC_ MIXR DMIC_R1 DMIC _R2 DMIC_R3 MX27[9:8] MX27[5] MX27[14]

Boost Gain MX1E[15:14]

IF1_DAC1_L VOL MX1C[14:8] MX1C[15] IF2_DAC_ L IF3_DAC_L

MX29[9:8]
VOL

MX29[7] MX29[4]

EQ

DACL1 DACR1 DACL2

Stereo_DAC_MIXL

MX19[15:8]

M _ X2A[8]
Gain

DACL1

ADC_2

ADC_2

EQ
Boost Gain MX1E[13:12] VOL MX1C[6:0] MX1C[7]

DRC
(Share with DAC) IF1_DAC1_R IF2_DAC_R IF3_DAC_ R

MX29[11:10]
VOL

SounzReal
EQ

DRC
(Share with ADC) DACR1 DACL1 DACR2 MX2A[6] MX2A[1] MX2A[4]

MX2A[11]

MX19[7:0] MX29[6] MX29[15]

MX2A[5]
Gain Gain

Stereo_DAC_MIXR

M _ X2A[0]
Gain

DACR1

Stereo1_ADC_Mixer_R

MXCD[1] VAD_ADC TxDP_ADC_R

MX2A[3] MX1B[6:4] DACL1 DACL2 DACL2 DACR2 MX2B[10] MX2B[14] MX2B[12] MX2B[13]
Gain Gain

Stereo2_ADC_Mixer_L Stereo2_ADC_Mixer_R Mono_ADC_Mixer_L MX28[9:8] MX28[11] Mono_ADC_Mixer_R Stereo1_ADC_Mixer_L Stereo1_ADC_Mixer_R MX28[13] Mono_ DAC_ Mixer_L Mono_ DAC_ Mixer_L MX28[12] MX28[14] MX1D[14:8] Boost VOL Gain MX20[15:14] IF1_DAC2_R IF2_DAC_L IF2_DAC_R DACL1 DACR1 Mono_ADC_Mixer_L

MX2D[15:13]

IF1_DAC2_L IF2_DAC_L IF3_DAC_L MXFA[9] MX2D[12:11] L/R Bypass ↓2 ↓3 MX2D[0] RX_0 TX_0 VOL

MX1B[13] MX1A[15:8]

Mono_DAC_MIXL

DACL2

DMIC_L1 DMIC _L2

MX2B[11]
Gain

DSP Down Link Bypass
MX2D[7:6] LR LL RR TxDC_DAC RL MX2D[0]

TxDC_DAC_L

MX2B[9] DACR1 DACR2 DACL2 MX2B[6] MX2B[4] MX2B[2] MX2B[5]
Gain Gain

IF1_DAC2_R IF2_DAC_R IF3_DAC_R TxDC_DAC_R

MX1B[12] VOL MX1A[7:0] DACR2

Mono_DAC_MIXR

DACR2

MX2B[3]
Gain

MX1D[15]

ADC_3 ADC_1 MX28[10]

Voice DSP
Stereo1_ADC_Mixer_L Stereo1_ADC_Mixer_R Mono_ADC_Mixer_L Mono_ADC_Mixer_R Stereo2_ADC_Mixer_L MX2D[1] RX_1 TX_1 MX2D[1] Slot Select MX2E[14:8] VOL VOL MX2E[6:0] Bypass TxDP_ADC_L 2 TxDP_ADC_R 3 MX2D[5:4] Stereo_DAC_MIXL MX2C[11] DACL2 DACR2 Stereo1_ADC_Mixer_L Stereo1_ADC_Mixer_R Mono_ADC_Mixer_L Mono_ADC_Mixer_R IF_ADC2 IF_ADC1 MX2C[5] MX2C[9] TxDP_ADC Stereo_DAC_MIXL MX2C[15] DACL2 DACR2 MX2C[13] MX2C[7]

MX2B[1] MX2C[14]
Gain Gain

MX28[2] ADC_3 ADC_2 Mono_ DAC_ Mixer_R Boost Gain Mono_ DAC_ Mixer _R DMIC_R1 DMIC_R2 DMIC_R3 MX28[1:0] DMIC _L1 DMIC_L2 DMIC_L3 DAC_ MIXL MX26[9:8] MX26[11] MX28[3] MX28[5] MX28[4] MX28[6] MX1D[6:0] VOL MX1D[7] Mono_ADC_Mixer_R

MX2C[12]
Gain

DAC_MIXL

Stereo2_ADC_Mixer_R IF2_DAC_L IF2_DAC_R

DSP Up Link Bypass

MX2D[3:2]

MX2C[6] MX2C[10]
Gain Gain Gain

MX2C[4] MX2C[8]

DAC_MIXR

MX20[13:12]

Stereo_DAC_MIXL Mono_DAC_MIXL

MX31[15] PDM1_L MX31[14]

Stereo2_ADC_Mixer_L Stereo2_ADC_Mixer_R IF_ADC3 Stereo_DAC_MIXR Mono_DAC_MIXR MX31[13] MX31[11] Stereo_DAC_MIXL PDM2_L VAD VAD_ADC Mono_DAC_MIXL Stereo_DAC_MIXR Mono_DAC_MIXR Stereo2_ADC_Mixer_L MX9D[9:8] MX31[9] MX31[10] PDM1_R MX31[12]

Stereo1_ADC_Mixer_L MX26[13] Mono_ADC_Mixer_L Mono_ADC_Mixer_R MX26[12] DAC_ MIXL Boost Gain MX1E[9:8] MX1F[14:8] VOL MX1F[15] MX26[15] Stereo2_ADC_Mixer_L

PDM2_R

MX31[8]

ADC_3 ADC_1 ADC_3 ADC_2 MX26[10] DAC_ MIXR MX26[12]

MX26[14]

MX26[6] MX1F[6:0] VOL

DAC_ MIXR DMIC_R1 DMIC_R2 DMIC_R3 MX26[9:8]

MX26[11] MX26[5]

Boost Gain MX1E[7:6]

MX1F[7]

Stereo2_ADC_Mixer_R

TxDP_ADC

IF1_ADC4

IF1_ADC3

IF_ADC1 MXFA[12]

VAD_ADC

IF1_ADC4

IF_ADC3

IF_ADC2

TxDP_ADC

TxDC_DAC

TxDP_ADC

TxDC_DAC

VAD_ADC

VAD_ADC

IF_ADC1

IF_ADC2

IF_ADC3

IF_ADC1

IF_ADC2

IF_ADC3

MX2F[15] MXFA[11] MXFA[10] IF1_ADC1 IF1_ADC3 IF1_ADC4 IF1_ADC2 IF2_DAC_L IF2_DAC_R IF1_DAC1_R IF1_DAC2_L IF1_DAC1_L IF1_DAC_2 IF1_DAC2_R

MX2F[14:12] IF3_DAC_L IF3_DAC_R IF2_ADC_L IF2_ADC_R IF3_ADC_R IF3_ADC_L

MX2F[2:0]

Slot Select IF1_ADC_0 IF1_ADC_1 IF1_ADC_2 IF1_DAC_0 IF1_DAC_1 IF1_DAC_3 IF1_DAC_4 IF1_DAC_5 IF1_DAC_6 IF1_DAC_7

Slot Select LRLR LLR R IF1_ADC_3 IF1_ADC_4 IF1_ADC_5 IF1_ADC_6 IF1_ADC_7 MX2F[11:10] MX2F[9:8]

LRLR

LLRR

LRLR

LRLR

LLR R IF2_ADC

LLRR

MX2F[7:6]

MX2F[5:4]

IF3_ADC

IF2_DAC

IF3_DAC

IF1_DAC

Digital Interface with TDM

Digital Interface 2
IF1_ADC

Digital Interface 3

DACDAT1 ADCDAT1

DACDAT2 ADCDAT2

Figure 3.

Digital Mixer Path 6 Rev. 0.91

DACDAT3 ADCDAT3

ALC5670 Datasheet

6.

Pin Assignments
SLEEVE_SENSE RING2_SENSE

LOUT1R/N

DACDAT1

ADCDAT2

LOUT1L/P

DACDAT2

BCLK2

LRCK2

CPVEE

CPN2
26

36

35

34

33

32

31

30

29

28

27

25 24 23 22 21 20 19 18

ADCDAT1 LRCK1 BCLK1 MCLK SCL SDA GPIO1/IRQ GPIO2/DMIC_SCL S_DAT_OUT S_CLK_IN S_DAT_IN GPIO7

CPP2 CPN1 CPP1 CPVDD CPVPP HPO_R HPO_L CPVREF JD1 MICVDD MIC_CAP MICBIAS1 IN1P_SLEEVE
17 16 15 14 13 12

37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4

ALC5670 xxxxxxx
5 6 7

ywwvs
8 9 10 11

(Top View)
DBVDD DCVDD IN3P/INL GPIO10 DACREF VREF2 MICBIAS2 INR
7

IN1P_RING2

IN2P

AVDD

AGND

Figure 4.

Pin Assignments

Rev. 0.91

ALC5670-VB Datasheet

7.

Pin Descriptions
Table 1. Digital I/O Pins Type Pin Description Characteristic Definition Schmitt trigger First I2S interface serial data input I 36 First I2S interface serial data output First I2S interface serial bit clock BCLK1 I/O 39 (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state VOL=0.1*DBVDD, VOH=0.9*DBVDD Default state: output type, low state Master: VOL =0.1*DBVDD, V OH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Master: VOL =0.1*DBVDD, V OH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state VOL=0.1*DBVDD, VOH=0.9*DBVDD Default state: output type, low state

7.1. Digital I/O Pins
Name DACDAT1

ADCDAT1

O

37

First I2S interface synchronous signal LRCK1 I/O 38

DACDAT2

I

34

ADCDAT2

O

35

BCLK2

I/O

33

Multi-function pin: Second I2S interface serial data input GPIO function Digital microphone 3 data input Multi-function pin: Second I2S interface serial data output GPIO function Digital microphone 1 data input Multi-function pin: Second I2S interface serial bit clock GPIO function PDM2 interface (clock output) Multi-function pin: Second I2S interface synchronous signal GPIO function PDM2 interface (data output) I2C interface serial data

Master: VOL =0.1*DBVDD, V OH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Master: VOL =0.1*DBVDD, V OH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Open drain structure Default state: input type, floating state

LRCK2

I/O

32

SDA

I/O

42

8

Rev. 0.91

ALC5670-VB Datasheet
Name SCL Type Pin I 41 Description I2C interface clock input I2S interface master clock input MCLK I 40 Multi-function pin: General purpose input and output Interrupt output Multi-function pin: General purpose input and output Digital microphone clock output Multi-function pin: Serial interface, data output Third I2S interface serial bit clock Multi-function pin: Serial interface, clock input Third I2S interface synchronous signal Multi-function pin: Serial interface, data input Third I2S interface serial data input Multi-function pin: General purpose input and output Digital microphone 1 data input PDM2 interface, clock output Third I2S interface serial data output Multi-function pin: General purpose input and output Digital microphone 3 data input PDM2 interface, data output Characteristic Definition Schmitt trigger Default state: input type, floating state Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Output: VOL =0.1*DBVDD, V OH =0.9*DBVDD Input: Schmitt trigger Default state: input type, floating state Output: VOL =0.1*DBVDD, V OH =0.9*DBVDD Input: Schmitt trigger Default state: input type, floating state Output: VOL =0.1*DBVDD, V OH =0.9*DBVDD Input: Schmitt trigger Default state: input type, floating state Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) Default state: input type, floating state Output: VOL =0.1*DBVDD, V OH =0.9*DBVDD Input: Schmitt trigger Default state: input type, floating state

GPIO1/IRQ

I/O

43

GPIO2/ DMIC_SCL

I/O

44

S_DAT_OUT

I/O

45

S_CLK_IN

I

46

S_DAT_IN

I

47

GPIO7

I/O

48

Output: VOL =0.1*DBVDD, V OH =0.9*DBVDD Input: Schmitt trigger Default state: input type, floating state Total: 18 Pins

GPIO10

I/O

1

9

Rev. 0.91

ALC5670-VB Datasheet

7.2. Analog I/O Pins
Name LOUTR/N Type Pin O 29 Table 2. Analog I/O Pins Description Characteristic Definition Line output type Analog output Single-ended output, right channel Differential output, negative channel Line output type Analog output Single-ended output, left channel Differential output, positive channel Multi-function pin: Analog input Single-ended input for analog microphone Digital input (Only can accept 1.8V digital 3 signal input) (VIL=0.35*1.8V, VIH=0.65*1.8V) Left channel line input Digital microphone 1 data input Analog input Multi-function pin: Second jack detection pin Digital JD threshold: VIL = 0.2V, VIH = 1.2V microphone 2 data input Digital input (Only can accept 1.8V digital signal input) (VIL=0.35*1.8V, VIH=0.65*1.8V) Multi-function pin: Analog input Single-ended input for analog microphone JD threshold: VIL = 0.2V, VIH = 1.2V 2 Third jack detection pin Analog input for analog microphone 1 Analog input Analog input for analog microphone 1 Analog input For analog microphone 1 compensation For analog microphone 1 compensation Analog jack detection function JD1 I 17 Analog input Analog input Multi-level jack detection pin JD threshold: Vt1 = 1.485V Vt2 = 1.925V Vt3 = 2.7V Analog output Analog output Total: 12 Pins

LOUTL/P

O

28

IN3P/INL

I

4

INR

I

5

IN2P IN1P_RING2 IN1P_SLEEV E RING2_SENS E SLEEVE_SE NSE

I I I I I

6 12 13 31 30

HPO_R HPO_L

O O

20 19

Headphone amplifier output Right channel Headphone amplifier output Left channel

10

Rev. 0.91

ALC5670-VB Datasheet

7.3. Filter/Reference
Name MICBIAS1 MIC_CAP MICBIAS2 VREF2 DACREF CPVREF CPN1 CPP1 CPN2 CPP2 Table 3. Filter/Reference Type Pin Description Characteristic Definition O 14 Bias voltage output for microphone Programmable analog DC output 15 Microphone input reference voltage 4.7uF capacitor to analog ground O 10 Bias voltage output for microphone Programmable analog DC output O 9 Second internal reference voltage 4.7uF capacitor to analog ground O 8 DAC/ADC reference voltage 4.7uF capacitor to analog ground 18 Headphone reference ground Headphone ground 24 First charge pump bucket capacitor 2.2uf capacitor to CPP1 23 First charge pump bucket capacitor 2.2uf capacitor to CPN1 26 Second charge pump bucket capacitor 2.2uf capacitor to CPP2 25 Second charge pump bucket capacitor 2.2uf capacitor to CPN2 Total: 10 Pins

7.4. Power/Ground
Name MICVDD AVDD AGND CPVDD CPVEE CPVPP DCVDD DBVDD DGND Table 4. Power/Ground Type Pin Description Characteristic Definition P 16 Analog power for MICBIAS 3.0V ~ 3.3V (Default 3.3V is recommended) P 7 Analog power 1.71V ~ 1.9V (Default 1.8V is recommended) P 11 Analog ground Analog power for headphone charge 1.71V ~ 1.9V (Default 1.8V is recommended) P 22 pump P 27 Charge pump negative voltage output 2.2uf capacitor to analog ground P 21 Charge pump positive voltage output 2.2uf capacitor to analog ground Digital power for digital core. 1.1V~1.3V P 3 (Internal LDO generated) P 2 Digital power for digital I/O buffer 1.71V~3.3V (Default 1.8V is recommended) P 49* Digital ground Exposed-Pad Total: 8 Pins

11

Rev. 0.91

ALC5670-VB Datasheet

8.

Function Description

8.1. System Connection
3.3V
1uF

DCVDD Digital I/O Power (1.8~3.3V) DBVDD

MICVDD DACREF AVDD

4.7uF

1.8V 1.8V

I2C-SDA I2C-SCL GPIO1/IRQ LRCK1 SoC (Host) BCLK1 DACDAT1 ADCDAT1 MCLK LRCK2 BCLK2 DACDAT2 ADCDAT2

CPVDD

IN1P_RING2 HP-OUT-L HP-OUT-R IN1P_SLEEVE
2.2K

3 1 5 6 2 4

HP-JD

2.2K

MICBIAS1
4.7uF

ALC5670

MICBIAS2
4.7uF

1.8V
Digital Microphone ADC

GPIO2/DMIC_SCL IN3N PDM_SCL CPP1
2.2uF

ADC

PDM_SDA

External PDM Amp

CPN1 CPP2
2.2uF

CPN2 CPVEE
2.2uF

LOUT-R LOUT-L

To alternative Speaker amplifier To alternative Speaker amplifier (*Used for 3rd and 4th speaker output, or speaker amplifier has higher power)

CPVPP
2.2uF

VREF
4.7uF

JD1 MIC-CAP
4.7uF

HP-JD

DGND
Digital GND Analog GND

AGND CPGND

Figure 5.

General System Connection 12 Rev. 0.91

ALC5670-VB Datasheet

8.2. Power
There are different power types in ALC5670. DBVDD is for digital I/O power, DCVDD is for digital core power, AVDD is for analog power, CPVDD is for charge pump power, MICVDD is for MICBIAS power. The power supplier limit condition are DBVDD >= DCVDD and MICVDD > AVDD = CPVDD, AVDD > DCVDD, and for the best performance, our design setting is shown as below.
Table 5. Power Supply for Best Performance DBVDD DCVDD AVDD CPVDD 1.8V 1.2V 1.8V 1.8V

Power Setting

MICVDD 3.3V

*1.2V DCVDD was generated by internal LDO.

To prevent all power down leakage, there are three settings for power supply. At these conditions, the leakage will be smaller. The detail setting is shown as following table.
Table 6. Power Supply Condition for Power Down Leakage Power DBVDD DCVDD AVDD CPVDD MICVDD Setting-1 Setting-2 Supplied N/A Supplied N/A Supplied N/A Supplied N/A Supplied N/A

13

Rev. 0.91

ALC5670-VB Datasheet

8.3. Power Supply On/Off Sequence
To prevent pop noise and make sure function work normally, following power on and off sequence are recommended.
Power On Sequence: 1. DBVDD/AVDD/CPVDD=1.8V power supply on 2. DBVDD power supply on (This step is required if DBVDD is supplied higher than 1.8V) 3. MICVDD power supply on 4. Initialize voice DSP of ALC5670. 5. Power down voice DSP of ALC5670.

6. S/W driver start to initial codec settings.
Power Off Sequence: 1. Power down voice DSP of ALC5670. 2. Power down all Codec function (Write 0x0000?h to register MX-00?h) 3. MICVDD power supply off 4. DBVDD power supply off (This step is required if DBVDD is supplied higher than 1.8V) 5. DBVDD/AVDD/CPVDD=1.8V power supply off

DBVDD=AVDD=CPVDD=1.8V

If DBVDD=3.3V

MICVDD=3.3V

Codec Initial & DSP Initial

> 300ms > 200ms

Figure 6.

Power On/Off Timing 14 Rev. 0.91

ALC5670-VB Datasheet

8.4. Reset
There are 2 types of reset operation: power on reset (POR) and register reset.
Reset Type POR Register Reset Table 7. Reset Operation Trigger Condition CODEC Response Monitor digital power supply voltage reach Reset all hardware logic and all registers to default values. VPOR Write MX-00h Reset all registers to default values except some specify control registers and logic.

8.4.1.

Power-On Reset (POR)

When powered on, DCVDD passes through the VPOR band of the ALC5670 (VPOR_ON ~VPOR_OFF). A power on reset (POR) will generate an internal reset signal (POR reset ?LOW?) to reset the whole chip.
Symbol VPOR_ON VPOR_OFF Min Table 8. Power-On Reset Voltage Typical Max 0.9 0.5 Unit V V

Note: 1.VPOR_OFF must be below VPOR_ON 2. ToC = 25oC 3. When DCVDD is supplied 1.2V

8.4.2.

Software Reset

When MX-00h is wrote, all registers become to default value.

15

Rev. 0.91

ALC5670-VB Datasheet

8.5. Clocking
The system clock of ALC5670 can be selected from MCLK or PLL. MCLK is always provided externally while the reference clock of PLL can be selected from MCLK, BCLK1/2/3. The driver should arrange the clock of each block and setup each divider. The Clk_sys_i2s1/2/3=256*Fs provides clocks into stereo DAC/ADC filter that can be selected from MCLK or PLL. Refer to Audio SYSCLK The Clk_sys_i2s1/2/3=256*Fs provides clocks into mono DAC/ADC filter that can be selected from MCLK, PLL, refer to Audio SYSCLK When enable ASRC (Asynchronous Sample Rate Converter) function, the clock sources from MCLK and BCLK1 (or BCLK2) are allowed to be asynchronous. The Realtek ASRC technology can ensure data accuracy and keep audio performance under clock source asynchronous. When ALC5670 at master mode, the clock source from MCLK will be divided and be sent to external device. The ratio of BCLK and LRCK can set by register – MX-73.
MX80[15:14]

MCLK
MX80[3]

Clk_sys
MX80[13:11]

MX73[14:12]

DIV_F1
MX73[10:8]

Clk_sys_i2s1(256FS)

MCLK

÷ 2

Inter. Clock DIV_F2
MX73[6:4]

(Slave) (Slave) (Slave) PLL
MX81 & MX82

Clk_sys_i2s2(256FS)

PLL

System Clock

DIV_F3

Clk_sys_i2s3(256FS)

MX70[15]

BCLK1

BCLK1(Master) Master Mode LRCK/BCLK Ratio
MX73[15]

Filter_Clk1 (256FS)

LRCK1

MX70[15]

LRCK1(Master)

LRCK1(Slave)

MX71[15]

BCLK2

BCLK2(Master) Master Mode LRCK/BCLK Ratio
MX73[11]

Clk_sys_i2s2(256FS)

MX71[15]

LRCK2

LRCK2(Master)

LRCK2(Slave)
MX72[15]

BCLK3

BCLK3(Master) Master Mode LRCK/BCLK Ratio
MX73[7]

Clk_sys_i2s3(256FS)

MX72[15]

LRCK3

LRCK3(Master)

LRCK3(Slave)

Figure 7.

Audio Clock Tree Rev. 0.91

16

ALC5670-VB Datasheet

8.5.1.

Phase-Locked Loop

A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The source of the PLL can be set to MCLK, BCLK1, BCLK2 or BCLK3 by setting register. The S/W driver can set up the PLL to output a frequency to match the requirement of system clock. The PLL transmit formula as below: FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2} These three I2S/PCM audio digital interfaces are used to send data to 4 DACs or to receive data from a stereo ADC. These three I2S/PCM audio digital interfaces can be configured to Master mode or Slave mode. Master Mode Under master mode, BCLK and LRCK are configured as output. If I2S SYSCLK is selected from MCLK source, sel_sysclk1 (MX-80[15:14]) should set as 00?b. If selected from PLL output, sel_sysclk1 should set as 01?b. PLL?s source is suggested to provide frequency from 2.048MHz to 40MHz. The driver should set each divider (MX-77 & MX-73) to arrange the clock distribution. Refer to Audio Clock Tree, for details.
Register Settings MX-77[11:10]=00?b, I2S1 MX-73[11]=0?b, I2S2 MX-77[11:10]=11?b, I2S1 MX-73[11]=1?b, I2S2 MX-77[11:10]=00?b, I2S1 MX-73[11]=0?b, I2S2 MX-77[11:10]=11?b, I2S1 MX-73[11]=1?b, I2S2 Table 9. The relative of SYSCLK/BCLK/LRCK MCLK BCLK 256*FS=12.288MHz 32*FS=1.536MHz 256*FS=12.288MHz 256*FS=11.2896MHz 256*FS=11.2896MHz 64*FS=3.072MHz 32*FS=1.4112MHz 64*FS=2.8224MHz LRCK FS=48KHz FS=48KHz FS=44.1KHz FS=44.1KHz

Example for master mode: Target format: Sample Rate: 48 KHz Channel Length: 32 bits LRCK=48KHz BCLK=3.072MHz (64 * 48KHz) MCLK clock request: MCLK=12.288MHz (256 * 48 KHz) Register settings: Set MX-FA[0] to “1” Set MX-61[15] to “1” // For MCLK input clock getting control // Enable I2S-1

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Set MX-70[15] to “0” // Enable Master mode Set MX-77[11:10] to “11” // Select 64*FS for BCLK in master mode Set MX-73[14:12] to “000” // Select I2S-1 pre-divider

Slave Mode Under slave mode BCLK and LRCK are configured as input. The SYSCLK can be input from MCLK, and BCLK can be synchronous or asynchronous to MCLK. If the SYSCLK is selected from BCLK, the internal PLL should generate 256*FS as internal system clock. And the driver should set each divider to arrange the clock distribution. Refer to Audio Clock Tree, for details. If an asynchronous MCLK input for BCLK and LRCK, you can turn on ASRC function for this case. As below figure shown, the MCLK is from external oscillator that clock is no relation (or asynchronous) with SOC and BT or 3G BaseBand. For the connection for SOC and BT can connect directly to Codec and let Codec as slave mode and SOC/BT as master mode. For the clock requirement of MCLK must large than 512*FS as SYSCLK that FS is sample rate. If the MCLK is smaller than 512*FS, that can use internal PLL to generate higher than 512*FS clock.

Codec I2S-1 as Slave Mode With ASRC I2S-1 as Slave Mode With ASRC

MCLK

OSC SOC BT/3G BB

Figure 8.

System Connection for ASRC Function

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Table 10. Register Settings for ASRC Function on Slave Mode Condition: Codec as Slave Mode MCLK = 12MHz Frame Rate = 64*FS Target Sample Rate (FS) = 48KHz Item Register Settings PLL Settings MX-81 = 0x1481?h MX-82 = 0x5000?h I2S-1 to DAC1 MX-83 = 0x8000?h MX-84 = 0x0020?h I2S-2 to DAC2 MX-83 = 0x1800?h MX-84 = 0xC000?h AMIC to Stereo ADC Filter MX-83 = 0x8000?h to I2S-1 MX-84 = 0x0800?h AMIC to Mono ADC Filter MX-83 = 0x1800?h to I2S-2 MX-84 = 0x3800?h DMIC1 to Stereo ADC Filter MX-83 = 0x8200?h to I2S-1 DMIC2 to Mono ADC Filter MX-83 = 0x1900?h to I2S-2 MX-84 = 0x3800?h

Note PLL settings to generate 512*FS (24.576MHz) for SYSCLK For DAC1 playback ASRC settings For DAC2 playback ASRC settings For AMIC to Stereo ADC Filter record ASRC settings For AMIC to Mono ADC Filter record ASRC settings For DMIC1 to Stereo ADC Filter record ASRC settings For DMIC2 to Mono ADC Filter record ASRC settings

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8.6. Digital Data Interface
8.6.1. Three I2S/PCM Interface
The three I2S/PCM interface can be configured as master mode or slave mode. Four audio data formats are supported: ? PCM mode ? Left justified mode ? I2S mode ? TDM mode (Max. BCLK Rate is 12.288MHz)
1/Fs

LRCK

BLCK

DACDAT/ ADCDAT

1 MSB

2

n-1 n LSB

Figure 9.

PCM MONO Data Mode A Format (BCLK POLARITY=0)

1/Fs

LRCK

BLCK DACDAT/ ADCDAT

1 MSB

2

n-1 n LSB

Figure 10.

PCM MONO Data Mode A Format (BCLK POLARITY=1)

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1/Fs

LRCK

BLCK DACDAT/ ADCDAT

1 MSB

2

n-1 n LSB

Figure 11.

PCM MONO Data Mode B Format (BCLK POLARITY=0)

1/ Fs

LRCK

BLCK DACDAT/ ADCDAT

1 MSB

2

3

n -1 n

1

2

3

n -1 n

LSBMSB Left-Channel

LSB Right-Channel

Figure 12.

PCM Stereo Data Mode A Format (BCLK POLARITY=0)

1/ Fs

LRCK

BLCK

DACDAT / ADCDAT

1 2 MSB

------

n 1 2

------

n 1 2

------

n

1 2 MSB

------

n X X X

X

1 2 MSB

LSB MSB

LSB MSB

LSB

LSB Don’t Care

Channel-1

Channel-2

Channel-3

Channel-8

Figure 13.

PCM TDM Data Mode A Format (BCLK POLARITY=0)

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1/ Fs

LRCK

BLCK

DACDAT/ ADCDAT

1 MSB

2

3

n -1 n

1

2

3

n -1 n LSB

LSBMSB Left-Channel Right-Channel

Figure 14. PCM Stereo Data Mode B Format (BCLK POLARITY=0)

1/ Fs

LRCK

BLCK

DACDAT / ADCDAT

1 2 MSB

------

n 1 2

------

n 1 2

------

n

1 2 MSB

------

n X X X X

X 1 2 MSB

LSB MSB

LSB MSB

LSB

LSB Don’t Care

Channel-1

Channel-2

Channel-3

Channel-8

Figure 15. PCM TDM Data Mode B Format (BCLK POLARITY=0)

1/ Fs

Left Channel LRCK

Right Channel

BLCK

DACDAT/ ADCDAT

1 MSB

2

n-1

n LSB

1 MSB

2

n-1 n LSB

Figure 16. I2S Data Format (BCLK POLARITY=0)

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1/ Fs

LRCK

BLCK

DACDAT / ADCDAT

1 2 MSB

------

n

1 2 MSB

------

n X X X

X

1 2 MSB

------

n

1 2 MSB

------

n X X X

X

LSB

LSB Don’t Care

LSB

LSB Don’t Care

Channel-1

Channel-8

Channel-1

Channel-8

Figure 17. I2S TDM Data Format (BCLK POLARITY=0)

1/ Fs

Left Channel LRCK

Right Channel

BLCK

DACDAT/ ADCDAT

1 MSB

2

n-1

n LSB

1 MSB

2

n-1

n LSB

Figure 18. Left-Justified Data Format (BCLK POLARITY=0)

1/ Fs

LRCK

BLCK

DACDAT / ADCDAT

1 2 MSB

------

n

1 2 MSB

------

n X X X

X 1 2 MSB

------

n

1 2 MSB

------

n X X X

X

LSB

LSB Don’t Care

LSB

LSB Don’t Care

Channel-1

Channel-8

Channel-1

Channel-8

Figure 19. Left-Justified TDM Data Format (BCLK POLARITY=0)

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8.7. Audio Data Path
The ALC5670 provides 4-channel analog DACs for playback and 3-channel analog ADCs for recording.

8.7.1.

3 Analog ADCs with 6-Channel Record Path

There are three analog ADCs and with up to 6-channel recording path. You can use two analog microphones pass to analog ADCs and four digital microphones to reach 6-channel recording. Or use three digital microphone interfaces to reach 6-channel recording. These 6-channel data can through I2S1 interface for recording. The I2S1 interface supports TDM interface and up to 8-CH, 24-bit/CH recording. The full scale input of analog ADC is around 0.55Vrms. In order to save power, the left and right analog ADC can be powered down separately by setting pow_adc_l (MX-61[2]), pow_adc_r (MX-61[1]) and pow_adc_3 (MX-61[3]). And the volume control of the stereo ADC is also separately controlled by ad_gain_l (MX-1C[14:8]) and ad_gain_r (MX-1C[6:0]).

DMIC1_L DMIC2_L DMIC3_L DAC_MIXL DAC_MIXL Analog ADC_L Analog ADC_3 DMIC1_R DMIC2_R DMIC3_R DAC_MIXR DAC_MIXR Analog ADC_R Analog ADC_3 CH2 IF_ADC1_R CH1 IF_ADC1_L

DMIC1_L DMIC2_L DMIC3_L Mono_DAC_MIXL Mono_DAC_MIXL Analog ADC_L Analog ADC_3 CH3 IF_ADC2_L

DMIC1_L DMIC2_L DMIC3_L DAC_MIXL DAC_MIXL Analog ADC_L Analog ADC_3 CH5 IF_ADC3_L

Stereo1 ADC Digital Mixer

DMIC1_R DMIC2_R DMIC3_R Mono_DAC_MIXR Mono_DAC_MIXR Analog ADC_R Analog ADC_3

Mono ADC Digital Mixer

DMIC1_R DMIC2_R DMIC3_R DAC_MIXR

Stereo2 ADC Digital Mixer

CH4

IF_ADC2_R

DAC_MIXR Analog ADC_R Analog ADC_3

CH6

IF_ADC3_L

ADCDAT1

IF_ADC1_L

IF_ADC1_R

IF_ADC2_L

IF_ADC2_R

IF_ADC3_L

IF_ADC3_R

TDM Format

Figure 20. 4-Channel Recording Path

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8.7.2.

4 DACs with 4-Channel Playback Path

There are four analog DACs and with up to 4-channel playback path. Two I2S interfaces provide four channels data to analog DACs. And analog DAC can output audio signal to speaker output, headphone output or line output. That also can use I2S1 TDM interface to support 4-channel playback. The full scale output of analog DAC is around 1Vrms at line output port. In order to save power, the four analog DACs can be powered down separately by setting pow_dac_l_1 (MX-61[12]), pow_dac_r_1 (MX-61[11]), pow_dac_l_2 (MX-61[7]) and pow_dac_r_2 (MX-61[6]). And the digital volume control of the four DACs are also separately controlled by vol_dac1_l (MX-19[15:8]), vol_dac1_r (MX-19[7:0]), vol_mono_dacl (MX-1A[15:8] and vol_mono_dacr (MX-1A[7:0]).

L CH1 IF1_DAC I2S1 Analog DACL1 IF1_DAC

L CH1 I2S1 TDM Analog DACL1

R CH2 Analog DACR1

R CH2 Analog DACR1

L

CH3

Analog DACL2

L

CH3

Analog DACL2

IF2_DAC

I2S2

I2S1 TDM

R

CH4

Analog DACR2

R

CH4

Analog DACR2

Figure 21. 4-Channel Playback Path

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8.7.3.

Mixers

The ALC5670 has digital and analog mixers build-in. ? Output mixer - OUTMIXL/R The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly for headphone output and line output. Each input path has it?s mute control to the mixer block in MX-45. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R ? Record mixer – RECMIXL/R There are three recording mixers in ALC5670. These analog mixers can do mixing for analog inputs. The mixer output is for ADC input. Each input path has it?s mute control to the mixer block in MX-3B ~ MX-40. pow_recmixl, pow_recmixr and pow_recmixm can be used to power on/off RECMIXL/R/M. ? HP mixer – HPMIXL/R The stereo analog mixer can do mixing for headphone volume and DAC output. The mixer output directly output to external headphone device. Each input path has it?s mute control to the mixer block in MX-45. ? Digital mixer There are twelve digital mixers in ALC5670. Six digital mixers are assigned for ADC recording. These six mixers can mix analog line input, analog microphone input and digital microphone input then output to I2S interface to other device. Another four digital mixers are assigned for DAC playback. These mixers can mix digital data from I2S interface or ADC data from external analog signal. The mixed data is output to analog DAC and output port to drive external device. The other two mixers are used for DA-AD processing. The incoming data from two I2S interfaces (DACDAT) uses these two mixers to do mixing and output to I2S interface (ADCDAT).

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8.8. Analog Audio Input Port
The ALC5670 has two type analog input ports: microphone input and line input. ? IN1P_RING2/IN1P_SLEEVE The port is a microphone type input port. The input port only can be configured as single-ended mode. The microphone input port has its microphone bias and microphone boost. The low noise microphone bias can improve recording performance and enhance recording quality. Build-in short current detection scheme can be used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and pow_micbias1 can be used to power down the microphone bias 1. ? IN2P The IN2P is a singled-end analog input port. It has multi-steps microphone boost gain set by sel_bst2 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst2 can be used to power down the MIC2 boost. ? IN3P/INL, INR The IN3P/INL is a dual type input port: microphone input and line input. Microphone input is only support single-ended input. Multi-steps microphone boost gain set by sel_bst3 (MX-0E[15:12]) is easy to use for microphone application. Pow_bst3 can be used to power down the MIC3 boost. If as line input, it has volume control for tuning by MX-0F[12:8] and MX-0F[4:0].

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8.9. Analog Audio Output Port
The ALC5670 supports two type output ports: ? HPO_L/R The headphone output of ALC5670 is a stereo output with cap-free type headphone amplifier. It does not need to connect external capacitor and can connect to earphone device directly. The headphone output source can mix from output mixer (HPMIX) and DAC by setting MX-45. The front stage of headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB with 1.5dB/step by MX-02. En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for Headphone Amplifier. ?

Line_OUT_L/R The output type is line type output. The output is a stereo single ended output or mono differential. The input can be selected from OUTMIX or DAC output by setting MX-53[15:12]. The front stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by MX-53[11].

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8.10. Multi-Function Pins
There are eight multi-function pins in ALC5670. For different functions of each pin are controlled by register. You need to set the right register settings for each multi-function pins by your application. ? GPIO1/IRQ – Pin 43

The pin default is GPIO function. It can change to IRQ output, write MX-C0[15] to 1?b will switch to IRQ function. ? GPIO2/DMIC_SCL – Pin 44

The pin default is GPIO function. It can change to DMIC clock output, write MX-C0[14] to 1?b will switch to DMIC clock output function. ? IN3P/INL/DMIC1_DAT – Pin 4

The pin can as analog microphone positive input or as line input. If as analog microphone input function needs to power on the power – MX-64[13] & MX64[4]. If as analog input function needs to power on the power – MX-66[9] & MX66[8]. Digital microphone input function: 1. Power down analog microphone input and line input. 2. Mute IN3 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR). 3. Change IN3P pin share function, set MX-75[1:0] to 01?b. 4. Turn on digital microphone function – MX-75[14] = 1?b ? INR/INR/DMIC2_DAT/JD2 – Pin 5

There are four functions share this pin. For each function switching shows below: Analog microphone input function, power on MX-64[13] & MX-64[4] and power off other functions. Analog line input function, power on MX-66[9] & MX-66[8] and power off other functions. Digital microphone input function: 1. Power down analog microphone input, line input and JD2 function 2. Mute IN3 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR). 3. Change INR pin share function, set MX-75[10] to 1?b. 4. Turn on digital microphone function – MX-75[14] = 1?b Jack detection function: 1. Power down analog microphone input, line input and digital microphone function. 2. Mute IN3 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR). 3. Turn on JD2 power – MX-64[1] = 1?b

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? IN2P/JD3 – Pin 6 The pin is pin share with analog input pin or jack detection pin. Analog microphone input function, power on MX-64[14] & MX-64[5] and power off other functions. Jack detection function: 1. Power down analog microphone input function. 2. Mute IN2 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR). 3. Turn on JD2 power – MX-64[1] = 1?b ? BCLK2/GPIO3/PDM_SCL2 – Pin 33

MX-C0[8] use to control pin33 is BCLK2 function or GPIO function. MX-C0[12] use to control pin33 is PDM_SCL2 function or GPIO function. ? LRCK2/GPIO4 – Pin 32

MX-C0[8] use to control pin32 is LRCK2 function or GPIO function. MX-C0[11] use to control pin32 is PDM_DAT2 function or GPIO function. ? DACDAT2/GPIO5/DMIC3_SDA – Pin 34

MX-C0[8] use to control pin34 is LRCK2 function or GPIO function. MX-C0[7] use to control pin34 is GPIO function or DMIC_SDA3 function. ? ADCDAT2/GPIO6/DMIC1_SDA – Pin 35

MX-C0[8] use to control pin35 is LRCK2 function or GPIO function. MX-C0[6] use to control pin35 is GPIO function or DMIC_SDA1 function. ? BCLK3/S_DAT_OUT – Pin 45

MX-C0[10] use to control pin45 is I2S or S_DAT_OUT function. ? LRCK3/S_SCL_IN – Pin 46

MX-C0[10] use to control pin46 is I2S or S_SCL_IN function. ? DACDAT3/S_DAT_IN – Pin 47

MX-C0[10] use to control pin47 is I2S or S_DAT_IN function. ? ADCDAT3/GPIO7/DMIC1_SDA/PDM_SCL1 – Pin 48

Pin48 as GPIO7/DMIC1_SDA/PDM_SCL1 function: Disable I2S3 by set MX-61[13] to “0”. MX-C0[5:4] use to control pin48 is GPIO or DMIC1_SDA or PDM_SCL1 function.
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Pin48 as I2S function: Set MX-C0[5:4] to “01”. Enable I2S3 by set MX-61[13] to “1”. ? GPIO10/DMIC3_SDA/PDM_DAT1 – Pin 1

MX-C0[1:0] use to control pin1 is GPIO or DMIC3_SDA or PDM_DAT1 function.

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8.11. DRC and AGC Function
The Dynamic Range Controller (DRC) dynamically adjusts the input signal and let the output signal achieve the target level. The ALC5670 supports playback DRC for DAC path, and the DRC can also be used as AGC(Auto Gain Controller) for ADC path. The control register is at MX-B4[15:14]. The function block is shown as below. The signal input pass through the Pre-Gain first, then DRC volume and Post-Gain then output. The Pre-Gain is use to enlarge the input signal. The DRC volume is use to attenuate the signal after detected by DRC. The Post-Gain is use to fine tune the signal after pass DRC tuning.

0 ~ 28.5dB, 1.5/step MXB5[4:0]

-95.625 ~ 0dB 0.375/step

-11.625 ~ 12dB, 0.375/step MXB5[13:8]

I2C Interface

Pre-Gain

DRC Volume

Post-Gain

DAC

DRC
1. Limiter level 2. Attack / Release time 3. Zero data

Figure 22. DAC DRC Function Block

0 ~ 28.5dB, 1.5/step MXB5[4:0]

-95.625 ~ 0dB 0.375/step

-11.625 ~ 12dB, 0.375/step MXB5[13:8]

Analog Pre-Boost

ADC

Pre-Gain

AGC Volume

Post-Gain

I2S Interface

AGC
1. Limiter level 2. Attack / Release time 3. Noise gate

Figure 23. ADC AGC Function Block

The ALC5670 supports multi-section DRC function. That has multiple slope curve can be tuned by registers for output dynamic range. For the output curve of playback and record have different behaviors and descripted as below.

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DRC Output Curve - Playback Mode: The below figure shows DRC output curve for DAC playback application. Alc_thmax(MX-B7[5:0]): The parameter limits the maximum output level when 0dB full scale input. The limit range is from 0dBFS to -23.625dBFS. Ratio_1(MX-B5[6:5]): The parameter determines the slope begin from start point. There are 4 slopes can be selected. Alc_thmax2(MX-B7[11:6]): The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS. Ratio_2(MX-B5[15:14]): The parameter determines the slope begin from first knee. There are 4 slopes can be selected. The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thmin to calculate. Alc_thmin(MX-B2[5:0]): The parameter determines the third knee from previous curve. The range is from -60dBFS to -94.5dBFS. Ratio_3(MX-B5[1:0]): The slope is determined by third knee and end point. The end point is determined by boost gain on MX-B3[11:6] register.
Vout (db) Segment_thmin
0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60

Segment2

Segment1

alc_thmax=-6db (REG.) Start Point ration_2=? (REG.) ratio_1=? (REG.) 1st Knee 2nd Knee

3rd Knee

-72 -78 -84

boost_gain = 12db (REG.) -90 End Point
-95.625 -90 -84 -78 -72 -66 -60 -54 -48 -42 -36 -30 -24 -18 -12 -6 0

ration_3 (H/W)

-66

Vin (db)

alc_thmin = -60db (REG.)

Knee (H/W)

alc_thmax2 = -12db (REG.)

Figure 24. Playback DRC Output Curve

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DRC Output Curve - Record Mode 1: The below figure shows DRC output curve for ADC record application. Alc_thmax(MX-B7[5:0]): The parameter limits the maximum output level when 0dB full scale input. The limit range is from 0dBFS to -23.625dBFS. Ratio_1(MX-B5[6:5]): The parameter determines the slope begin from start point. There are 4 slopes can be selected. Alc_thmax2(MX-B7[11:6]): The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS. Ratio_2(MX-B5[15:14]): The parameter determines the slope begin from first knee. There are 4 slopes can be selected. The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thnoise to calculate. Alc_thnoise(MX-B6[4:0]): The parameter determines the third knee from previous curve. The range is from -24dBFS to -70.5dBFS. Noise_gate_ratio(MX-B5[1:0]): The parameter determines the slope begin from third knee. There are 4 slopes can be selected. The end point is determined by third knee and noise_gate_ratio.
Vout (db) Segment_noise_gate
0 -6 -12

Segment2

Segment1

alc_thmax=-6db (REG.) Start Point 1st Knee 2nd Knee ratio_2=? (REG.) ratio_1=? (REG.)
-6 0

-18 -24 -30 -36 -42 -48 -54

3rd Knee

-66 -72 -78 -84

boost_gain = 12db (REG.) -90
-95.625

End Point
-90 -84 -78 -72 -66 -60 -54 -48 -42 -36 -30 -24 -18 -12

noise_gate_ratio=2 (REG.)

-60

Vin (db)

alc_thnoise = -48db (REG.)

Knee (H/W)

alc_thmax2 = -12db (REG.)

Figure 25. Record DRC Output Curve - 1

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DRC Output Curve - Record Mode 2: The below figure shows another DRC output curve for ADC record application. Alc_thmax(MX-B7[5:0]): The parameter limits the maximum output level when 0dB full scale input. The limit range is from 0dBFS to -23.625dBFS. Ratio_1(MX-B5[6:5]): The parameter determines the slope begin from start point. There are 4 slopes can be selected. Alc_thmax2(MX-B7[11:6]): The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS. Ratio_2(MX-B5[15:14]): The parameter determines the slope begin from first knee. There are 4 slopes can be selected. The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thnoise to calculate. Alc_thnoise(MX-B6[4:0]): The parameter determines the third knee from previous curve. The range is from -24dBFS to -70.5dBFS. From third knee to fourth knee is a noise drop function by enable noise gate drop mode at MX-B5[4]. The drop level is determined by boost_gain (MX-B3[11:6]) and alc_noise_gate_exp (MX-B6[15:12]). Noise_gate_ratio(MX-B5[1:0]): The parameter determines the slope begin from fourth knee. There are 4 slopes can be selected. The end point is determined by fourth knee and noise_gate_ratio.
Vout (db) Segment_noise_gate
0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84

Segment2

Segment1

alc_thmax=-6db (REG.) 1st Knee 2nd Knee 3rd Knee boost_gain = 12db alc_noise_gate_exp = 6db 4th Knee ratio_2=? (REG.) ratio_1=? (REG.) Start Point

Drop_all = 12 + 6 =18db

boost_gain = 12db (REG.)

-90

End Point
-95.625 -90 -84 -78 -72 -66 -60

noise_gate_ratio=2 (REG.)

-54

-48 -42

-36

-30

-24

-18

-12

-6

0

Vin (db)

alc_thnoise = -48db (REG.) Knee (H/W)

alc_thmax2 = -12db (REG.)

Figure 26. Record DRC Output Curve - 2

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Playback/Recording Mode: For DAC playback or ADC recording mode, when the input signal exceeds target threshold, the signal will decrease “DRC/AGC Digital Volume” (0.375dB/step at every zero-crossing) until drop to target level then keep the digital volume. When input signal is below the target threshold, the signal will step-up “DRC/AGC Digital Volume” (0.375dB/step every zero-crossing) until return to original level. If want to return to the target level, need to set the pre-gain to achieve. Fine tune parameters: ? Limiter Threshold: 0 ~ -46.5dB, 1.5dB/step, MX-B7[5:0] ? Attack Rate: T=(4*2^n)/sample rate, n = MX-B4[12:8] ? Recovery Rate: T=(4*2^n)/sample rate, n = MX-B4[4:0]

Input signal Target Level

Volume 0dB

Attack Rate

Recovery Rate

Output signal

Figure 27. DRC/AGC for Playback/Recording Mode

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Noise Gate Mode: The Noise Gate Function is use to reduce the noise floor for DAC path or ADC path. When input signal is below noise gate level, the input signal will be reduced by DRC/AGC volume in order to suppress the background noise. The reducing level can be set by register. And when input signal is above noise gate, the input signal will be boosted to target level. Fine tune parameters: ? Noise Gate Threshold: -36 ~ -82.5dB, 1.5dB/step, MX-B6[4:0] ? Noise Gate Attack Rate: T=(4*2^n)/sample rate, n = PR-06[4:0] ? Noise Gate Recovery Rate: T=(4*2^n)/sample rate, n = PR-02[12:8] ? Reducing Noise Level: 0 ~ 45dB, 3dB/step, MX-B6[15:12]

Input signal Target Level Noise Gate

Volume 0dB

Attack Rate

Recovery Rate

Attack Rate

Recovery Rate

Noise Reduction Output signal Target Level Noise Gate

Figure 28. DRC/AGC for Noise Gate Mode

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8.12. SounzRealTM Post-Processing
The Realtek?s SounzRealTM post-processing is composed of: ? ? TruTreble BassBack

8.13. Equalizer Block
The equalizer block cascades 7 bands of equalizer to each channel to tailor the frequency characteristics of embedded speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer includes two high pass filters, three band pass filters, one low pass filter and one biquad filter. One high pass filter cascaded in the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter with gain control can adjust the Bass strength. Three bands of band pass filters are used to emulate environment sounds, e.g., ?Pub?, ?Live?, ?Rock?,… etc.. The gain, center frequency and bandwidth of each filter are all programmable. One biquad filter can switch to high-pass, low-pass or band-pass filter by register settings.

8.14. Wind Noise Reduction Filter
The wind filter is implemented by a high pass filter equalizer. The wind filter is mainly for ADC recording used. The cut-off freqnecy of wind filter is programmable and is varied accroding to different sample rate. The filter is used to remove DC offset at normal condition, and to remove wind noise at application mode. There are three wind filters for three ADC filters: Stereo 1 ADC Wind Filter => MX-D3 & MX-D4 Mono ADC Wind Filter => MX-EC & MX-ED Stereo 2 ADC Wind Filter => MX-EE & MX-EF

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Wind filter setting procedure (For Stereo 1 ADC Filter): Step1: Disable wind filter – MX-D3[15] Step2: Select filter coarse coefficient – MX-D3[14:12] and MX-D3[10:8] Step3: Select filter fine coefficient – MX-D4[13:8] and MX-D4[5:0] Step4: Enable wind filter – MX-D3[15]
For the formula of Fc calculation is also shown as: Fc = (Fs * tan-1(a/(2-a))) / π Where: Sample rate = 8K/12K/16K (MX-D3[14:12] and [10:8]), a = 2-6 + n * 2-6 (n is MX-D4[13:8] & MX-D4[5:0]) Sample rate = 24K/32K (MX-D3[14:12] and [10:8]), a = 2 -7 + n * 2-7 (n is MX-D4[13:8] & MX-D4[5:0]) Sample rate = 44.1K/48L (MX-D3[14:12] and [10:8]), a = 2 -8 + n * 2-8 (n is MX-D4[13:8] & MX-D4[5:0]) Sample rate = 88.2K/96L (MX-D3[14:12] and [10:8]), a = 2 -9 + n * 2-9 (n is MX-D4[13:8] & MX-D4[5:0]) Sample rate = 176.4K/192L (MX-D3[14:12] and [10:8]), a = 2 -10 + n * 2-10 (n is MX-D4[13:8] & MX-D4[5:0]) Table 11. Sample Rate with filter coefficient for Wind Filter L & R Channel Sample Rate Setting 8K 16K 32K 44.1K 20.0 40.1 39.9 27.4 40.4 80.8 80.2 55.0 61.1 122.2 120.7 82.7 82.1 164.2 161.6 110.5 103.4 206.9 202.8 138.4 125.1 250.2 244.4 166.4 147.1 294.3 286.2 194.5 169.5 339.0 328.4 222.7 192.2 384.4 371.0 251.1 215.2 430.5 413.8 279.5 238.7 477.4 457.0 308.1 262.4 524.9 500.5 336.8 286.6 573.2 544.4 365.6 311.1 622.3 588.6 394.5 336.0 672.1 633.2 423.5 361.3 722.6 678.1 452.6 386.9 773.9 723.3 481.9 413.0 826.0 768.9 511.2 439.4 878.9 814.9 540.7 466.2 932.5 861.2 570.3 493.5 987.0 907.8 600.0 521.1 1042.2 954.9 629.8 549.1 1098.2 1002.2 659.7 577.5 1155.0 1050.0 689.8 606.3 1212.7 1098.1 719.9 635.5 1271.1 1146.6 750.2 665.1 1330.3 1195.5 780.6 695.2 1390.4 1244.7 811.1 725.6 1451.2 1294.3 841.8 39

PR-6E[11:6] n 000000?b, 0 000001?b, 1 000010?b, 2 000011?b, 3 000100?b, 4 000101?b, 5 000110?b, 6 000111?b, 7 001000?b, 8 001001?b, 9 001010?b, 10 001011?b, 11 001100?b, 12 001101?b, 13 001110?b, 14 001111?b, 15 010000?b, 16 010001?b, 17 010010?b, 18 010011?b, 19 010100?b, 20 010101?b, 21 010110?b, 22 010111?b, 23 011000?b, 24 011001?b, 25 011010?b, 26 011011?b, 27 011100?b, 28

48K 29.8 59.9 90.0 120.3 150.6 181.1 211.7 242.5 273.3 304.3 335.4 366.6 397.9 429.4 460.9 492.6 524.5 556.4 588.5 620.7 653.0 685.5 718.1 750.8 783.6 816.6 849.6 882.9 916.2 Rev. 0.91

ALC5670-VB Datasheet
PR-6E[11:6] n 011101?b, 29 011110?b, 30 011111?b, 31 100000?b, 32 100001?b, 33 100010?b, 34 100011?b, 35 100100?b, 36 100101?b, 37 100110?b, 38 100111?b, 39 101000?b, 40 101001?b, 41 101010?b, 42 101011?b, 43 101100?b, 44 101101?b, 45 101110?b, 46 101111?b, 47 110000?b, 48 110001?b, 49 110010?b, 50 110011?b, 51 110100?b, 52 110101?b, 53 110110?b, 54 110111?b, 55 111000?b, 56 111001?b, 57 111010?b, 58 111011?b, 59 111100?b, 60 111101?b, 61 111110?b, 62 111111?b, 63 8K 756.4 787.6 819.3 851.3 883.7 916.6 949.8 983.3 1017.3 1051.6 1086.3 1121.4 1156.8 1192.6 1228.7 1265.1 1301.8 1338.8 1376.1 1413.7 1451.5 1489.6 1528.0 1566.5 1605.3 1644.2 1683.3 1722.5 1761.9 1801.4 1841.0 1880.7 1920.4 1960.2 2000.0 L & R Channel Sample Rate Setting 16K 32K 44.1K 1512.9 1344.3 872.5 1575.3 1394.7 903.4 1638.6 1445.4 934.4 1702.7 1496.5 965.5 1767.5 1548.0 996.8 1822.3 1599.9 1028.1 1899.6 1652.2 1059.6 1966.7 1704.9 1091.2 2034.7 1757.9 1122.9 2103.3 1811.4 1154.8 2172.7 1865.2 1186.7 2242.9 1919.5 1218.8 2313.7 1974.1 1251.0 2385.2 2029.1 1283.4 2457.4 2084.6 1315.8 2530.2 2140.4 1348.4 2603.6 2196.6 1381.1 2677.7 2253.3 1414.0 2752.3 2310.3 1447.0 2827.5 2367.7 1480.0 2903.1 2425.5 1513.3 2979.3 2483.8 1546.6 3056.0 2542.4 1580.1 3133.1 2601.5 1613.7 3210.6 2660.9 1647.4 3288.4 2720.8 1681.3 3366.6 2781.0 1715.3 3445.1 2841.7 1749.4 3523.9 2902.7 1783.6 3602.9 2964.2 1818.0 3682.1 3026.1 1852.5 3761.4 3088.3 1887.1 3840.8 3151.0 1921.9 3920.4 3214.1 1956.8 4000.0 3277.5 1991.8 48K 949.7 983.3 1017.0 1050.9 1084.9 1119.0 1153.3 1187.7 1222.2 1256.9 1291.7 1326.6 1361.7 1396.9 1432.2 1467.7 1503.3 1539.0 1574.9 1610.9 1647.1 1683.4 1719.8 1756.4 1793.1 1830.0 1867.0 1904.1 1941.4 1978.8 2016.3 2054.0 2091.9 2129.9 2168.0

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8.15. I2C Control Interface
I2C is a 2-wire (SCL/SDA) half-duplex serial communication interface, supporting only slave mode. SCL is used for clock and SDA is for data. SCL clock supports up to 400KHz rate and SDA data is a open drain structure. The input has built-in spike filter and can remove less than 50ns spike at SCL and SDA.

8.15.1. Address Setting
Table 12. (MSB) 0 0 1 Address Setting (0x38h) BIT 1 1 0 0 (LSB) R/W

8.15.2. Complete Data Transfer
Data Transfer over I2C Control Interface

Figure 29. Data Transfer Over I2C Control Interface

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Write WORD Protocol
Table 13. Write WORD Protocol
1 S 7 Device Address 1 1 8 Register Address 1 A 8 Data Byte High 1 A 8 Data Byte Low 1 A 1 P

Wr A

Read WORD Protocol
Table 14. Read WORD Protocol
1 S 7 Device Address 1 1 8 Register Address 1 A S 7 Device Address 1 Rd A 8 Data Byte High 1 A 8 Data Byte Low 1 1 Wr A NA P

S: Start Condition Slave Address: 7-bit Device Address Wr: 0 for Write Command Rd: 1 for Read Command Command Code: 8-bit Register Address

A: 0 for ACK, 1 for NACK Data Byte: 16-bit Mixer data ?: Master-to-Slave ???: Slave-to-Master

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8.16. GPIO, Interrupt and Jack Detection
The ALC5670 supports 8 GPIOs – GPIO1/GPIO2/GPIO3/GPIO4/GPIO5/GPIO6/GPIO7/GPIO 10. For GPIO function, the GPIO can be configured to input or output. For input type, the internal circuit can read pin status and report to register table. For output type, the internal circuit can drive this pin to high or low to control external device. In GPIO function, the pin polarity can be controlled by register at output type.
MX-C1[0] MX-C1[3]

MX-C1[1] High Low MX-BF[8]

MX-C1[4]

GPIO1
EN_OBUF

High Low MX-BF[7]

GPIO2
EN_OBUF

EN_IBUF MX-C1[2]

EN_IBUF MX-C1[5]

MX-C1[7] High Low MX-BF[7]

MX-C1[6]

MX-C1[10]

MX-C1[9]

GPIO3
EN_OBUF

High Low MX-BF[5]

GPIO4
EN_OBUF

EN_IBUF MX-C1[8]

EN_IBUF MX-C1[11]

MX-C1[13] High Low MX-BF[9]

MX-C1[12]

MX-C2[1]

MX-C2[0]

GPIO5
EN_OBUF

High Low MX-BF[10]

GPIO6
EN_OBUF

EN_IBUF MX-C1[14]

EN_IBUF MX-C2[2]

MX-C2[4] High Low MX-BF[11]

MX-C2[3]

MX-C2[13]

MX-C2[12]

GPIO7
EN_OBUF

High Low MX-BE[2]

GPIO10
EN_OBUF

EN_IBUF MX-C2[5]

EN_IBUF MX-C2[14]

Figure 30. GPIO Function Block

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For the jack detection function, there are 6 GPIOs (GPIO3/4/5/6/7/10) can be configured as jack detection pins and also have JD1, JD2 and JD3 can as jack detection pin. For GPIO jack detection pin source selection is controlled by MX-BB[15:13] & MX-BC[11:9]. For each JD status is sta_gpio_jd1 – MX-BF[4] and sta_gpio_jd2 – MX-BE[3]. For JD1, it can detect two ports. Which JD statuses are sta_jd1_1 – MX-BF[12] & sta_jd1_2 – MX-BF[13]. For JD2, it can detect one port. Which JD status is sta_jd2 – MX-BF[14]. For JD3, it can detect one port. Which JD status is sta_jd2 – MX-BF[15].
MX-BB[15:13] GPIO3 GPIO4 GPIO5 GPIO6 Sta_gpio_jd1 GPIO10 GPIO7 Sta_gpio_jd2 MX-BC[11:9]

For IRQ function as shown on below figure. When either status is trigged, the GPIO will output a flag as interrupt signal.
MX-BE[10] MX-BE[12] MX-BE[14] Sta_micbias2_ovcd_internal MX-BC[11:9] MX-BD[10] GPIO7 Sticky Control GPIO10 MX-BD[11] MX-BD[12] Sticky Control

MX-BB[15:13] MX-BD[13] GPIO3 GPIO4 GPIO5 GPIO6 MX-BD[7] MX-BD[8] MX-BD[9] Sticky Control Sta_jd1_1_internal MX-BD[4] MX-BD[5] MX-BD[6] Sta_jd1_2_internal Sticky Control Sticky Control MX-BD[14] MX-BD[15]

MX-BD[1]

MX-BD[2] MX-BD[3]

OR Gate

IRQ

Sta_jd2_internal

Sticky Control

MX-BE[11]

MX-BE[13] MX-BE[15]

Sta_micbias1_ovcd_internal

Sticky Control

MX-BF[0]

MX-BF[1] MX-BF[3]

Sta_inline_command_internal

Sticky Control

MX-BE[4]

MX-BE[5] MX-BE[6]

Sta_vad_hold_internal

Sticky Control

MX-BC[6]

MX-BC[7] MX-BC[8]

Sta_jd3_internal

Sticky Control

Figure 31. IRQ Function Block

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In general, the IRQ output needs to combine with JD function. When JD is trigger, IRQ will output a flag to host to notice S/W driver. The S/W driver will do some settings by system design. The behavior flow chard as following:
Initial Settings (For JD and IRQ)

Device Plug-In

JD Triggered

IRQ Flag Output to Host

S/W Driver Settings

Clear JD Status for Next JD Trigger

The MICBIAS supports short current detection function. When MICBIAS circuit detects over-current happen, MICBIAS circuit will generate an over-current flag. The flag can generate an interrupt signal to notice host and let S/W do follow-up processes. The jack detect function can be used to turn-on or turn-off the related output ports. When jack detect pin is trigged, the selected output ports will be turn-on or turn-off. For example on HP and LOUT auto switch when JD is trigger. Setting procedure: 1. Select JD status source: use sta_jd1_1 as JD source. MX-F8[2:0] = 001?b & MX-F9[11:9] = 001?b 2. Set JD status polarity for HP and LOUT MX-BB[11:10] = 10?b, JD status low to trigger HPO MX-BB[3:2] = 11?b, JD status high to trigger LOUT 3. When JD status is low, HP_OUT is un-mute and LOUT is mute. When JD status is low go high, HP is mute and LOUT is un-mute. Note: For HP and LOUT port switch function, driver need to turn-on DAC to HP path and DAC to LOUT path first.

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8.17. Push Button Detection
The ALC5670 has built-in push button detection circuit inside. It can supports up to three push buttons. Each button support three behaviors and shows on register (MX-DBh) – one click, double click and hold. The push button event will also cause an interrupt to IRQ output to notice external host.

U C D

Ring2 U 220 Sleeve 20 C D MIC
R R

620

R

Sleeve

Ring

Tip

Ring2

Push Button Resistance Up button, R2 Center button, R1 Down button, R3

Resistance Range 150 ~ 280 Ohm 0 ~ 50 Ohm 550 ~ 650 Ohm

Recommend Value 220 Ohm 20 Ohm 620 Ohm

Push Button Detection Status: Button # Up button Button Behavior One click Double click Hold One click Double click Hold One click Double click Hold Register Status MX-DBh[15] MX-DBh[14] MX-DBh[13] MX-DBh[12] MX-DBh[11] MX-DBh[10] MX-DBh[9] MX-DBh[8] MX-DBh[7]

Center button

Down button

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Push Button Detection Flow Chart:
Initial Settings
(Power-On)

Push Button Trigger
(Press push button)

IRQ Output
(Codec issue a interrupt)

Status?
(Codec driver check codec register status)

Configuration
(Codec driver set settings by push button event)

Clear Status for Next Push Button Trigger

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8.18. Power Management
ALC5670 detailed Power Management control registers are supported in MX-61h, 62h, 63h, 64h, 65h and 66h. Each particular block will only be active when each bit MX-61h, 62h, 63h, 64h, 65h and 66h is set to enable.
MX-61

I2S-1 Power

I2S-2/3 Power

ADC3 Power

DACL1/R1 Power

DACL2/R2 Power

ADCL/R Power

MX-62

DAC Digital Filter

ADC Digital Filter

DSP Power

PDM Power

MX-63

Analog MBias Power

Analog Vref Power

Headphone Amp Power

LOUT Mixer Power

MX-64

MIC BST1/2 Power

MIC BST3 Power

JD Power

MICBIAS1/2 Power

PLL Power

MX-65

OUTMIXL Power

OUTMIXR Power

RECMIXL Power

RECMIXR Power

MX-66

HPMIXL Power

HPMIXR Power

INLVOL Power

INRVOL Power

Figure 32. Power Management 48 Rev. 0.91

ALC5670-VB Datasheet

8.19. Gen.3 Voice DSP Function
The on-chip Voice Processor provides microphone beam-forming with voice tracking to allow for acoustic echo cancellation, far-field pickup, stationary and non-stationary noise suppression, and voice recognition rate enhancement.

Data Input/Output

Data Interface

Voice Provessor

Control Interface Command Control

Dual-Core DSP SRAM ROM Accelerators

PLL/Clock Gen

Power Management

Master Clock

VDD / VSS

Acoustic Echo Cancellation: The voice DSP suppresses echo effectively under all occasions, and the performance of which could be easily optimized for different types of acoustics set-up and applications for tablet computers. The AEC performs robustly under prolonged double talk periods and provides a face-to-face like conversation in full-duplex without any cut-off, drop-out, howling, voice level pumping, and annoying echoes. Noise Suppression: The advanced noise suppression is specifically designed for tablets to benefit users that invoke voice communication applications on these devices. Ambient noise pickup is reduced by the advanced microphone array beam-forming which could run in 2- or 3- microphone configurations. The technology further reduces both stationary noise and non-stationary noises, and enhances user experiences in video
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and voice chats. Noise reduction is available on both downstream and upstream signals and is highly effectively against hums, fan-noises, tones, background babbles, and a variety of unwanted interferences. 48kHz Stereo Recording with Far-Field Pickup The vioce DSP provides specific pure 48kHz audio recording with FFP technology. It can suppress stationary noise for each channel with 24kHz bandwidth. Far-Field Pickup technology is also considered in this mode for long distance audio catch up with high signal to noise ratio. The dual feature sculpture the tablet computer to be a real stereo recording device with stationary noise suppression for long distance range. Voice Recognition Rate Enhancement The advanced voice processing could be configured to run in Voice Recognition Rate Enhancement mode which would perform beam-forming, acoustic echo cancellation and other processing in a way that helps to improve recognition rates in poor signal-to-noise conditions for the common commercial voice recognition engines. Advanced Beam-Forming The advanced beam-forming algorithm performs Voice Tracking which could follow the incidence angle of the talkers? voice and hence reduces background noise pick-up and reverberations. It also allows for exceptional widened talking angle in handheld mode to accommodate for a wide variety of user holding positions, and avoids any annoying voice drop-outs and fade-outs.

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8.20. Multi-Jack Jack Detection Pin (JD1)
The JD1 pin supports up to two ports jack detection. When supports two ports jack detection, the external pull-high voltage is 3.3V. When supports one ports jack detection, the external pull-high voltage is 1.8V. The application schematic as shows below:

3.3V

1.8V

VDD 0.5 R Vt1=1.485V VDD VDD

CP1

R

CP2
Port-1 Port-2 Vt2=1.95V VDD 0.5 R Vt3=2.7V Port-1 Vt2=0.9V

CP2

VDD

R

CP3

Mode-0

Mode-1

MX-94h: JD1 Control
Name reserved Sel_mode_jd1 Bits 15:2 1:0 Read/Write R/W R/W Reset State Description 0 ?h Reserved 0 ?h JD1 Mode Control 00?b: Mode-0, two port jack detection 01?b: Mode-1, one port jack detection Others: Reserved

MX-BFh: JD1 Status
Name sta_jd1_2 (Port-2) sta_jd1_1 (Port-1) Bits 13 Read/Write R Reset State Description 0 ?h Status of JD1_2 Jack detection . Read: Return status of Jack Detect Select output Write: Write ?0? to clear stick bit 0 ?h Status of JD1_1 Jack detection . Read: Return status of Jack Detect Select output Write: Write ?0? to clear stick bit

12

R

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9.

Registers List

ALC5670 register map as shown as following and accessing unimplemented registers, will return a 0.

9.1. Register Map
Type Reset Name S/W Reset HPOUT LOUT IN1 IN1 IN1 IN2 IN3 INL/INR DACL1/R1 DACL2/R2-1 DACL2/R2-2 ADC ADC ADC ADC ADC ADC ADC ADC ADC DAC DAC DAC Voice DSP Voice DSP Copy Mode Table 15. Register Map Description S/W Reset & Device ID Headphone Output Volume & Mute/Un-Mute Line Output Volume & Mute/Un-Mute IN1 Control 1 IN1 Control 2 IN1 Control 3 IN2 Mode and Gain Boost Control IN3 Mode and Gain Boost Control INL/INR Volume Control DACL1/R1 Digital Volume Control DACL2/R2 Digital Volume Control DACL2/R2 Digital Mute/Un-Mute Control Stereo1 ADCL/R Digital Volume & Mute/Un-Mute Control Mono ADCL/R Digital Path Volume Control ADC Boost Gain for DMIC Stereo2 ADCL/R Digital Volume & Mute/Un-Mute Control ADC Boost Gain for DMIC Stereo2 ADC Digital Mixer Control Stereo1 ADC Digital Mixer Control Mono ADC Digital Mixer Control ADC to DAC Digital Mixer Control DAC Stereo Digital Mixer Control DAC Mono Digital Mixer Control DAC Stereo to Mono Mixer Control Voice DSP Path Control Voice DSP Volume Control ADC/DAC Data Copy Mode Control PDM Interface Control PDM Interface Control PDM Interface Control PDM Interface Control RECMIXL Gain Control RECMIXL Gain & Selection Control RECMIXR Gain Control RECMIXR Gain & Selection Control RECMIXM Gain Control RECMIXM Gain & Selection Control HPOMIX Gain & Selection Control OUTMIXL Selection Control OUTMIXR Selection Control 52 Register Address MX-00h MX-02h MX-03h MX-0Ah MX-0Bh MX-0Ch MX-0Dh MX-0Eh MX-0Fh MX-19h MX-1Ah MX-1Bh MX-1Ch MX-1Dh MX-1Eh MX-1Fh MX-20h MX-26h MX-27h MX-28h MX-29h MX-2Ah MX-2Bh MX-2Ch MX-2Dh MX-2Eh MX-2Fh MX-31h MX-32h MX-33h MX-35h MX-3Bh MX-3Ch MX-3Dh MX-3Eh MX-3Fh MX-40h MX-45h MX-4Fh MX-52h Reset State 0x0004?h 0x8888?h 0x8888?h 0x0001?h 0x0827?h 0x0000?h 0x0008?h 0x0000?h 0x0808?h 0xAFAF?h 0xAFAF?h 0x0000?h 0x2F2F?h 0x2F2F?h 0x0000?h 0x2F2F?h 0x0000?h 0x7860?h 0x7860?h 0x7871?h 0x8080?h 0x5656?h 0x5454?h 0xAAA0?h 0x0000?h 0x2F2F?h 0x1002?h 0x5F00?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x007F?h 0x0000?h 0x007F?h 0x0000?h 0x001F?h 0x600F?h 0x0073?h 0x00D3?h Rev. 0.91

Digital Gain/Volume

Digital Mixer

PDM RECMIXL-1 RECMIXL-2 RECMIXR-1 RECMIXR-2 RECMIXM-1 RECMIXM-2 HPOMIX OUTMIXL OUTMIXR

Input Mixer

Output Mixer

ALC5670-VB Datasheet
Type Name LOUTMIX Management1 Management2 Management3 Management4 Management5 Management6 PR Index PR Data I2S1 Port Ctrl I2S2 Port Ctrl ADC/DAC Clock ADC/DAC HPF Description LOUTMIX Gain & Selection Control I2S & DAC & ADC Power Control Digital Filter & DSP & SPK Power Control VREF & MBias & LOUTMIX & HP Power Control MICBST & MICBIAS & PLL & JD Power Control OUTMIX & RECMIX Power Control MICBIAS & OUTVOL & HPOVOL & INVOL Power Control PR Register Index PR Register Data I2S-1 Interface Control I2S-2 Interface Control ADC/DAC Clock Control ADC/DAC HPF Control Digital Microphone Control Digital Microphone Control TDM Interface Control TDM Interface Control TDM Interface Control DSP Clock Control Global Clock Control PLL Control 1 PLL Control 2 ASRC Control 1 ASRC Control 2 ASRC Control 3 ASRC Control 4 ASRC Control 5 HP Output De-Pop Control 1 HP Output De-Pop Control 2 Charge Pump Control HP Amp Control MICBIAS Control JD1 Control ADC EQ Control 1 ADC EQ Control 2 DAC EQ Control 1 DAC EQ Control 2 DAC_L EQ (LPF: a1) DAC_L EQ (LPF: H0) DAC_R EQ (LPF: a1) DAC_R EQ (LPF: H0) DAC_L EQ (BPF2: a1) DAC_L EQ (BPF2: a2) 53 Register Address Reset State MX-53h 0xF000?h MX-61h MX-62h MX-63h MX-64h MX-65h MX-66h MX-6Ah Mx-6Ch MX-70h MX-71h MX-73h MX-74h MX-75h MX-76h MX-77h MX-78h MX-79h MX-7Fh MX-80h MX-81h MX-82h MX-83h MX-84h MX-85h MX-8Ah MX-8Ch MX-8Eh MX-8Fh MX-91h MX-D6h MX-93h MX-94h MX-AE MX-AF MX-B0h MX-B1h PR-A4h PR-A5h PR-A6h PR-A7h PR-AEh PR-AFh 0x0000?h 0x0000?h 0x00C0?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x8000?h 0x8000?h 0x1114?h 0x0E00?h 0x1505?h 0x0015?h 0x0C00?h 0x4000?h 0x0123?h 0x1100?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0007?h 0x0004?h 0x1100?h 0x0C06?h 0x0400?h 0x0000?h 0x0000h 0x6000?h 0x0000?h 0x6000?h 0x0000?h 0x1C10?h 0x01F4?h 0x1C10?h 0x01F4?h 0xC882?h 0x1C10?h Rev. 0.91

Power Management

PR Register

Digital Interface

Digital MIC TDM Clock Clock PLL PLL ASRC ASRC ASRC ASRC ASRC HP MICBIAS JD1 ADC EQ ADC EQ DAC EQ DAC EQ EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter

Global Clock

HP Amp MICBIAS JD1

EQ

ALC5670-VB Datasheet
Type Name EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter Description DAC_L EQ (BPF2: H0) DAC_R EQ (BPF2: a1) DAC_R EQ (BPF2: a2) DAC_R EQ (BPF2: H0) DAC_L EQ (BPF3: a1) DAC_L EQ (BPF3: a2) DAC_L EQ (BPF3: H0) DAC_R EQ (BPF3: a1) DAC_R EQ (BPF3: a2) DAC_R EQ (BPF3: H0) DAC_L EQ (BPF4: a1) DAC_L EQ (BPF4: a2) DAC_L EQ (BPF4: H0) DAC_R EQ (BPF4: a1) DAC_R EQ (BPF4: a2) DAC_R EQ (BPF4: H0) DAC_L EQ (HPF1: a1) DAC_L EQ (HPF1: H0) DAC_R EQ (HPF1: a1) DAC_R EQ (HPF1: H0) DAC_L EQ (HPF2: a1) DAC_L EQ (HPF2: a2) DAC_L EQ (HPF2: H0) DAC_R EQ (HPF2: a1) DAC_R EQ (HPF2: a2) DAC_R EQ (HPF2: H0) DAC_L EQ Pre-Volume Control DAC_R EQ Pre-Volume Control DAC_L EQ Post-Volume Control DAC_R EQ Post-Volume Control ADC EQ (LPF: a1) ADC EQ (LPF: H0) ADC EQ (BPF1: a1) ADC EQ (BPF1: a2) ADC EQ (BPF1: H0) ADC EQ (BPF2: a1) ADC EQ (BPF2: a2) ADC EQ (BPF2: H0) ADC EQ (BPF3: a1) ADC EQ (BPF3: a2) ADC EQ (BPF3: H0) ADC EQ (BPF4: a1) ADC EQ (BPF4: a2) ADC EQ (BPF4: H0) ADC EQ (HPF1: a1) ADC EQ (HPF1: H0) ADC EQ Pre-Volume Control ADC EQ Post-Volume Control DAC_L Biquad EQ (BPF1: h0-1) DAC_L Biquad EQ (BPF1: h0-2) DAC_L Biquad EQ (BPF1: b1-1) 54 Register Address PR-B0h PR-B1h PR-B2h PR-B3h PR-B4h PR-B5h PR-B6h PR-B7h PR-B8h PR-B9h PR-BAh PR-BBh PR-BCh PR-BDh PR-BEh PR-BFh PR-C0h PR-C1h PR-C2h PR-C3h PR-C4h PR-C5h PR-C6h PR-C7h PR-C8h PR-C9h PR-CAh PR-CBh PR-CCh PR-CDh PR-CEh PR-CFh PR-D0h PR-D1h PR-D2h PR-D3h PR-D4h PR-D5h PR-D6h PR-D7h PR-D8h PR-D9h PR-DAh PR-DBh PR-DCh PR-DDh PR-E1h PR-E2h PR-E5h PR-E6h PR-E7h Reset State 0x01F4?h 0xC882?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0x1C10?h 0x01F4?h 0x1C10?h 0x01F4?h 0x2000?h 0x0000?h 0x1FF1?h 0x2000?h 0x0000?h 0x1FF1?h 0x0800?h 0x0800?h 0x0800?h 0x0800?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0xE904?h 0x1C10?h 0x01F4?h 0x1C10?h 0x01F4?h 0x0800?h 0x0800?h 0x0000?h 0x0000?h 0x0000?h Rev. 0.91

ALC5670-VB Datasheet
Type Name EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter EQ-Parameter DRC/AGC DRC/AGC DRC/AGC DRC/AGC DRC/AGC DRC/AGC DRC/AGC JD JD Jack Detection JD JD IRQ IRQ IRQ IRQ GPIO GPIO GPIO GPIO TM BassBack SounzReal Post-Processin TruTreble g TruTreble Stereo1 Stereo1 Mono Wind Filter Mono Stereo2 Stereo2 Description DAC_L Biquad EQ (BPF1: b1-2) DAC_L Biquad EQ (BPF1: b2-1) DAC_L Biquad EQ (BPF1: b2-2) DAC_L Biquad EQ (BPF1: a1-1) DAC_L Biquad EQ (BPF1: a1-2) DAC_L Biquad EQ (BPF1: a2-1) DAC_L Biquad EQ (BPF1: a2-2) DAC_R Biquad EQ (BPF1: h0-1) DAC_R Biquad EQ (BPF1: h0-2) DAC_R Biquad EQ (BPF1: b1-1) DAC_R Biquad EQ (BPF1: b1-2) DAC_R Biquad EQ (BPF1: b2-1) DAC_R Biquad EQ (BPF1: b2-2) DAC_R Biquad EQ (BPF1: a1-1) DAC_R Biquad EQ (BPF1: a1-2) DAC_R Biquad EQ (BPF1: a2-1) DAC_R Biquad EQ (BPF1: a2-2) DRC/AGC Control 1 DRC/AGC Control 2 DRC/AGC Control 3 DRC/AGC Control 4 DRC/AGC Control 5 DRC/AGC Control 6 Jack Detection Control Jack Detection Control Jack Detection Control Jack Detection Control IRQ Control 1 IRQ Control 2 IRQ Control 3 GPIO Control 1 GPIO Control 2 GPIO Control 3 BassBack Control TruTreble Control 1 TruTreble Control 2 Stereo1 ADC Wind Filter Control 1 Stereo1 ADC Wind Filter Control 2 Mono ADC Wind Filter Control 1 Mono ADC Wind Filter Control 2 Stereo2 ADC Wind Filter Control 1 Stereo2 ADC Wind Filter Control 2 Soft Volume and ZCD Control 1 SVOL & ZCD SVOL & ZCD Soft Volume and ZCD Control 2 Inline Command Control 1 InLine Inline Command Control 2 Command Inline Command Control 3 Voice DSP Control 1 Voice DSP Control 2 Voice DSP Voice DSP Control 3 Voice DSP Control 4 55 Register Address PR-E8h PR-E9h PR-EAh PR-EBh PR-ECh PR-EDh PR-EEh PR-EFh PR-F0h PR-F1h PR-F2h PR-F3h PR-F4h PR-F5h PR-F6h PR-F7h PR-F8h MX-B2h MX-B3h MX-B4h MX-B5h MX-B6h MX-B7h MX-BBh MX-BCh MX-F8h MX-F9h MX-BDh MX-BEh MX-BFh MX-C0h MX-C2h MX-C3h MX-CFh MX-D0h MX-D1h MX-D3h MX-D4h MX-ECh MX-EDh MX-EEh MX-EFh MX-D9h MX-DAh MX-DBh MX-DCh MX-DDh MX-E0h MX-E1h MX-E2h MX-E3h Reset State 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x001F?h 0x2206?h 0x1F00?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h 0x0013?h 0x0680?h 0x1C17?h 0xAA20?h 0x0000?h 0xAA20?h 0x0000?h 0xAA20?h 0x0000?h 0x0809?h 0x0000?h 0x0001?h 0x0049?h 0x0003?h 0x0000?h 0x0000?h 0x0000?h 0x0000?h Rev. 0.91

ALC5670-VB Datasheet
Type Name Description Voice DSP Control 5 Voice DSP Control 6 General Control 1 ADC/DAC RESET Control Vendor ID Register Address MX-E4h MX-E5h MX-FAh PR-3D MX-FEh Reset State 0x0000?h 0x0000?h 0x0090?h 0x2808?h 0x10EC?h

General Control Vendor ID

ID

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ALC5670-VB Datasheet

9.2. MX-00h: S/W Reset & Device ID
Default: 0004?h
Table 16. MX-00h: S/W Reset Port Name Bits Read/Write Reset State Description 15:3 R 0?h Reserved Reserved 2:1 R 0?h Device_id ALC5670 0 R 0 ?h Reserved Reserved Note: Writes to this register will reset all registers to their default values.

9.3. MX-02h: Headphone Output Control
Default: 8888?h
Name mu_hpo_l Bits 15 Table 17. MX-02h: Headphone Output Control Read/Write Reset State Description R/W 1 ?h Mute Control for Left Headphone Output Port (HPOL) 0?b: Un-Mute 1?b: Mute Reserved vol_hpol 14 13:8 R R/W 0?h 8?h Reserved Left Headphone Channel Volume Control (HPOVOLL) ?? 00?h: +12dB … 08?h: 0dB … 27?h: -46.5dB, with 1.5dB/step mu_hpo_r 7 R/W 1 ?h Mute Control Right Headphone Output Port (HPOR) 0?b: Un-Mute 1?b: Mute Reserved Vol_hpor 6 5:0 R R/W 0?h 8?h Reserved Right Headphone Channel Volume Control (HPOVOLR)?? 00?h: +12dB … 08?h: 0dB … 27?h: -46.5dB, with 1.5dB/step ?Volume Table

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ALC5670-VB Datasheet
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 A B C D E F 12 10.5 9 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F -12 -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24 -25.5 -27 -28.5 -30 -31.5 -33 -34.5 32 33 34 35 36 37 38 39 20 21 22 23 24 25 26 27 -36 -37.5 -39 -40.5 -42 -43.5 -45 -46.5

9.4. MX-03h: LINE Output Control
Default: 8888?h
Name Mu_lout_l Bits 15 Table 18. MX-03h: LINE Output Control Read/Write Reset State Description R/W 1 ?h Mute Control for Left Line Output Port(LOUTL) 0?b: Un-Mute 1?b: Mute R/W 0?h LOUT Differential Mode Control 0?b: Disable (Single-ended mode) 1?b: Enable (Differential mode) R/W 08?h Left Output Volume Control (OUTVOLL) ?? 00?h: +12dB … 08?h: 0dB … Mu_lout_r 7 R/W 1 ?h 27?h: -46.5dB, with 1.5dB/step Mute Control for Right Line Output Port (LOUTR) 0?b: Un-Mute 1?b: Mute Reserved

En_dfo1

14

Vol_outl

13:8

Reserved

6

R

0?h

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ALC5670-VB Datasheet
Name Vol_outr Bits 5:0 Read/Write R/W Reset State Description 08?h Right Output Volume Control ?? 00?h: +12dB … 08?h: 0dB … 27?h: -46.5dB, with 1.5dB/step ?Volume Table DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 A B C D E F 12 10.5 9 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F -12 -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24 -25.5 -27 -28.5 -30 -31.5 -33 -34.5 32 33 34 35 36 37 38 39 20 21 22 23 24 25 26 27 -36 -37.5 -39 -40.5 -42 -43.5 -45 -46.5

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ALC5670-VB Datasheet

9.5. MX-0Ah: IN1 Port Control - 1
Default: 0001?h
Name Sel_bst1 Bits 15:12 Table 19. MX-0Dh: IN1 Input Control - 1 Read/Write Reset State Description R/W 0 ?h IN1 Boost Control (BST1) 0000?b: Bypass 0001?b: +20dB 0010?b: +24dB 0011?b: +30dB 0100?b: +35dB 0101?b: +40dB 0110?b: +44dB 0111?b: +50dB 1000?b: +52dB Others : Reserved R/W R/W 0 ?h 0 ?h Reserved IN1 Port Enable Control 0?b: Disable 1?b: Enable reserved 1:0 R/W 1 ?h Reserved

reserved En_bst1

11:3 2

9.6. MX-0Bh: IN1 Port Control - 2
Default: 0827?h
Name Reserved Manual_tri_in1 Bits 15:13 12 Table 20. MX-0Bh: IN1 Input Control - 2 Read/Write Reset State Description R 0 ?h Reserved R/W 0 ?h Manual Trigger For IN1 Port 0?b: Low trigger 1?b: High trigger Capless Power Gating with IN1 Control 0?b: Register control 1?b: Auto mode Reserved IN1 Port Mode Control 0?b: Auto mode 1?b: Manual mode reserved 6:0 R/W 27?h Reserved

Capless_gat_en

11

R/W

1 ?h

reserved Reg_mode

10:8 7

R/W R/W

0 ?h 1 ?h

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ALC5670-VB Datasheet

9.7. MX-0Ch: IN1 Port Control - 3
Default: 0000?h
Name Reserved In1_result Bits 15:3 2:0 Table 21. MX-0Ch: IN1 Input Control - 3 Read/Write Reset State Description R 0 ?h Reserved R 0 ?h IN1 Port Final Status 001?b: Type1 010?b: Type2 100?b: Type3

9.8. MX-0Dh: IN2 Input Control
Default: 0008?h
Name Reserved Sel_bst2 Bits 15:12 11:8 Table 22. MX-0Dh: IN2 Input Control Read/Write Reset State Description R 0 ?h Reserved R/W 0 ?h IN2 Boost Control (BST2) 0000?b: Bypass 0001?b: +20dB 0010?b: +24dB 0011?b: +30dB 0100?b: +35dB 0101?b: +40dB 0110?b: +44dB 0111?b: +50dB 1000?b: +52dB Others : Reserved Reserved

Reserved

7:0

R

8?h

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ALC5670-VB Datasheet

9.9. MX-0Eh: IN3 Input Control
Default: 0000?h
Name Sel_bst3 Bits 15:12 Table 23. MX-0Eh: IN3 Input Control Read/Write Reset State Description R/W 0 ?h IN3 Boost Control (BST3) 0000?b: Bypass 0001?b: +20dB 0010?b: +24dB 0011?b: +30dB 0100?b: +35dB 0101?b: +40dB 0110?b: +44dB 0111?b: +50dB 1000?b: +52dB Others : Reserved R/W 0 ?h Reserved

Reserved

11:0

9.10. MX-0Fh: INL & INR Volume Control
Default: 0808?h
Name reserved Vol_inl Bits 15:13 12:8 Table 24. MX-0Fh: INL & INR Volume Control Read/Write Reset State Description R 0 ?h Reserved R/W 8 ?h INL Channel Volume Control ?? 00?h: +12dB … 08?h: 0dB … Reserved Vol_inr 7:5 4:0 R R/W 0 ?h 8 ?h 1F?h: -34.5dB, with 1.5dB/step Reserved INR Channel Volume Control ?? 00?h: +12dB … 08?h: 0dB … 1F?h: -34.5dB, with 1.5dB/step ?Volume Table: DEC HEX Boost Gain DEC HEX Boost Gain 0 1 0 1 12 10.5 16 17 10 11 -12 -13.5 Rev. 0.91

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ALC5670-VB Datasheet
2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 A B C D E F 9 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 18 19 20 21 22 23 24 25 26 27 28 29 30 31 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F -15 -16.5 -18 -19.5 -21 -22.5 -24 -25.5 -27 -28.5 -30 -31.5 -33 -34.5

9.11. MX-19h: DACL1/R1 Digital Volume
Default: AFAF?h
Name vol_dac1_l Bits 15:8 Table 25. MX-19h: DACL1/R1 Digital Volume Read/Write Reset State Description R/W AF?h DAC1 Left Channel Digital Volume?? 00?h: -65.625dB … AF?h: 0dB, with 0.375dB/Step vol_dac1_r 7:0 R/W AF?h DAC1 Right Channel Digital Volume?? 00?h: -65.625dB … AF?h: 0dB, with 0.375dB/Step

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ALC5670-VB Datasheet

9.12. MX-1Ah: DACL2/R2 Digital Volume
Default: AFAF?h
Name vol_dac2_l Bits 15:8 Table 26. MX-1Ah: DACL2/R2 Digital Volume Read/Write Reset State Description R/W AF?h DAC2 Left Channel Digital Volume?? 00?h: -65.625dB … AF?h: 0dB, with 0.375dB/Step vol_dac2_r 7:0 R/W AF?h DAC2 Right Channel Digital Volume?? 00?h: -65.625dB … AF?h: 0dB, with 0.375dB/Step ?Volume Table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 -65.625 -65.25 -64.875 -64.5 -64.125 -63.75 -63.375 -63 -62.625 -62.25 -61.875 -61.5 -61.125 -60.75 -60.375 -60 -59.625 -59.25 -58.875 -58.5 -58.125 -57.75 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A -45.75 -45.375 -45 -44.625 -44.25 -43.875 -43.5 -43.125 -42.75 -42.375 -42 -41.625 -41.25 -40.875 -40.5 -40.125 -39.75 -39.375 -39 -38.625 -38.25 -37.875 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F -25.875 -25.5 -25.125 -24.75 -24.375 -24 -23.625 -23.25 -22.875 -22.5 -22.125 -21.75 -21.375 -21 -20.625 -20.25 -19.875 -19.5 -19.125 -18.75 -18.375 -18 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 -6 -5.625 -5.25 -4.875 -4.5 -4.125 -3.75 -3.375 -3 -2.625 -2.25 -1.875 -1.5 -1.125 -0.75 -0.375 0 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9

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22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 -57.375 -57 -56.625 -56.25 -55.875 -55.5 -55.125 -54.75 -54.375 -54 -53.625 -53.25 -52.875 -52.5 -52.125 -51.75 -51.375 -51 -50.625 -50.25 -49.875 -49.5 -49.125 -48.75 -48.375 -48 -47.625 -47.25 -46.875 -46.5 -46.125 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 -37.5 -37.125 -36.75 -36.375 -36 -35.625 -35.25 -34.875 -34.5 -34.125 -33.75 -33.375 -33 -32.625 -32.25 -31.875 -31.5 -31.125 -30.75 -30.375 -30 -29.625 -29.25 -28.875 -28.5 -28.125 -27.75 -27.375 -27 -26.625 -26.25 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E -17.625 -17.25 -16.875 -16.5 -16.125 -15.75 -15.375 -15 -14.625 -14.25 -13.875 -13.5 -13.125 -12.75 -12.375 -12 -11.625 -11.25 -10.875 -10.5 -10.125 -9.75 -9.375 -9 -8.625 -8.25 -7.875 -7.5 -7.125 -6.75 -6.375 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

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ALC5670-VB Datasheet

9.13. MX-1Bh: DACL2/R2 Mute/Un-Mute Control
Default: 0000?h
Name reserved Mu_dac2_l Bits 15:14 13 Table 27. MX-1Bh: DACL2/R2 Mute/Un-Mute Control Read/Write Reset State Description R 0 ?h Reserved R/W 0 ?h Mute Control for Left DAC2 Volume 0?b: Un-Mute 1?b: Mute Mu_dac2_r 12 R/W 0 ?h Mute Control for Right DAC2 Volume 0?b: Un-Mute 1?b: Mute reserved Sel_dacl2 11:7 6:4 R R/W 0 ?h 1 ?h Reserved Select DACL2 Data Source 000?b: IF1_DAC2_L 001?b: IF2_DAC_L 010?b: Reserved 011?b: TxDC_DAC_L 100?b: Reserved 101?b: VAD_ADC or TxDP_ADC_R Others: Reserved reserved Sel_dacr2 3 2:0 R R/W 0 ?h 1 ?h Reserved Select DACR2 Data Source 000?b: IF1_DAC2_R 001?b: IF2_DAC_R 010?b: Reserved 011?b: TxDC_DAC_R 100?b: TxDP_DAC_L Others: Reserved

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9.14. MX-1Ch: Stereo1 ADC Digital Volume Control
Default: 2F2F?h
Name Mu_adc_vol_l Bits 15 Table 28. MX-1Ch: Stereo1 ADC Digital Volume Control Read/Write Reset State Description R/W 0 ?h Mute Control for Stereo1 ADC Left Volume Channel 0?b: Un-Mute 1?b: Mute Ad_gain_l 14:8 R/W 2F?h Stereo1 ADC Left Channel Volume Control 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step Mu_adc_vol_r 7 R/W 0 ?h Mute Control for Stereo1 ADC Right Volume Channel 0?b: Un-Mute 1?b: Mute Ad_gain_r 6:0 R/W 2F?h Stereo1 ADC Right Channel Volume Control 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step

9.15. MX-1Dh: Mono ADC Digital Volume Control
Default: 2F2F?h
Name reserved Mono_ad_gain_l Bits 15 14:8 Table 29. MX-1Dh: Mono ADC Digital Volume Control Read/Write Reset State Description R 0 ?h Reserved R/W 2F?h Mono ADC Left Channel Volume Control ?? 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step

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Rev. 0.91

ALC5670-VB Datasheet
reserved Mono_ad_gain_r 7 6:0 R R/W 0 ?h 2F?h Reserved Mono ADC Right Channel Volume Control ?? 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step ?Volume Table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain -17.625 -7.875 1.875 0 0 26 1A 52 34 -17.25 -7.5 2.25 1 1 27 1B 53 35 2 2 -16.875 28 1C -7.125 54 36 2.625 -16.5 -6.75 3 3 3 29 1D 55 37 -16.125 -6.375 3.375 4 4 30 1E 56 38 -15.75 -6 3.75 5 5 31 1F 57 39 -15.375 -5.625 4.125 6 6 32 20 58 3A 7 7 -15 33 21 -5.25 59 3B 4.5 -14.625 -4.875 4.875 8 8 34 22 60 3C 9 9 -14.25 35 23 -4.5 61 3D 5.25 -13.875 -4.125 5.625 10 A 36 24 62 3E -13.5 -3.75 6 11 B 37 25 63 3F -13.125 -3.375 6.375 12 C 38 26 64 40 -12.75 -3 6.75 13 D 39 27 65 41 14 E -12.375 40 28 -2.625 66 42 7.125 -12 -2.25 7.5 15 F 41 29 67 43 16 10 -11.625 42 2A -1.875 68 44 7.875 17 11 -11.25 43 2B -1.5 69 45 8.25 -10.875 -1.125 8.625 18 12 44 2C 70 46 -10.5 -0.75 9 19 13 45 2D 71 47 20 14 -10.125 46 2E -0.375 72 48 9.375 21 15 -9.75 47 2F 0 73 49 9.75 22 16 -9.375 48 30 0.375 74 4A 10.125 23 17 -9 49 31 0.75 75 4B 10.5 24 18 -8.625 50 32 1.125 76 4C 10.875 25 19 -8.25 51 33 1.5 77 4D 11.25 DEC HEX Boost Gain 11.625 78 4E 12 79 4F 80 50 12.375 12.75 81 51 13.125 82 52 13.5 83 53 13.875 84 54 85 55 14.25 14.625 86 56 87 57 15 15.375 88 58 15.75 89 59 16.125 90 5A 16.5 91 5B 92 5C 16.875 17.25 93 5D 94 5E 17.625 95 5F 18 18.375 96 60 18.75 97 61 98 62 19.125 99 63 19.5 100 64 19.875 101 65 20.25 102 66 20.625 103 67 21 DEC HEX Boost Gain 21.375 104 68 21.75 105 69 106 6A 22.125 22.5 107 6B 22.875 108 6C 23.25 109 6D 23.625 110 6E 111 6F 24 24.375 112 70 113 71 24.75 25.125 114 72 25.5 115 73 25.875 116 74 26.25 117 75 118 76 26.625 27 119 77 120 78 27.375 121 79 27.75 28.125 122 7A 28.5 123 7B 124 7C 28.875 125 7D 29.25 126 7E 29.625 127 7F 30

68

Rev. 0.91

ALC5670-VB Datasheet

9.16. MX-1Eh: ADC Digital Boost Gain Control
Default: 0000?h
Name Stereo1_ad_boost_ gain_l Bits 15:14 Table 30. MX-1Eh: ADC Digital Boost Gain Control Read/Write Reset State Description R/W 0 ?h Stereo1 ADC Left Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB Stereo1_ad_boost_ gain_r 13:12 R/W 0 ?h Stereo1 ADC Right Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB Stereo1_ad_comp_ gain 11:10 R/W 0 ?h Stereo1 ADC Compensation Gain 00?b: 0dB 01?b: 1dB 10?b: 2dB 11?b: 3dB Stereo2_ad_boost_ gain_l 9:8 R/W 0 ?h Stereo2 ADC Left Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB Stereo2_ad_boost_ gain_r 7:6 R/W 0 ?h Stereo2 ADC Right Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB Stereo2_ad_comp_ gain 5:4 R/W 0 ?h Stereo2 ADC Compensation Gain 00?b: 0dB 01?b: 1dB 10?b: 2dB 11?b: 3dB reserved 3:0 R/W 0 ?h Reserved

69

Rev. 0.91

ALC5670-VB Datasheet

9.17. MX-1Fh: Stereo2 ADC Digital Volume Control
Default: 2F2F?h
Name Mu_adc2_vol_l Bits 15 Table 31. MX-1Fh: Stereo2 ADC Digital Volume Control Read/Write Reset State Description R/W 0 ?h Mute Control for Stereo2 ADC Left Volume Channel 0?b: Un-Mute 1?b: Mute Ad2_gain_l 14:8 R/W 2F?h Stereo2 ADC Left Channel Volume Control 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step Mu_adc2_vol_r 7 R/W 0 ?h Mute Control for Stereo2 ADC Right Volume Channel 0?b: Un-Mute 1?b: Mute Ad2_gain_r 6:0 R/W 2F?h Stereo2 ADC Right Channel Volume Control 00?h: -17.625dB … 2F?h: 0dB … 7F?h: +30dB, with 0.375dB/Step

9.18. MX-20h: Mono ADC Digital Boost Gain Control
Default: 0000?h
Name Bits mono_ad_boost_ga 15:14 in_l Table 32. MX-20h: Mono ADC Digital Boost Gain Control Read/Write Reset State Description R/W 0 ?h Mono ADC Left Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB

70

Rev. 0.91

ALC5670-VB Datasheet
mono_ad_boost_ga 13:12 in_r R/W 0 ?h Mono ADC Right Channel Digital Boost Gain 00?b: 0dB 01?b: 12dB 10?b: 24dB 11?b: 36dB mono_ad_comp_ga 11:10 in R/W 0 ?h Mono ADC Compensation Gain 00?b: 0dB 01?b: 1dB 10?b: 2dB 11?b: 3dB Reserved 9:0 R 0?h Reserved

9.19. MX-26h: Stereo2 ADC Digital Mixer Control
Default: 7860?h
Name Sel_stereo2_lr_mix Bits 15 Table 33. MX-26h: Stereo2 ADC Digital Mixer Control Read/Write Reset State Description R/W 0 ?h Mixing Control for Stereo2 ADC Left channel 0?b: L 1?b: L+R R/W 1 ?h Mute Source1 to Stereo2 ADC Left Channel 0?b:UnMute 1?b:Mute R/W 1 ?h Mute Source2 to Stereo2 ADC Left Channel 0?b:UnMute 1?b:Mute R/W 1 ?h Select Stereo2 ADC L/R Channel Source 1 0?b: DAC_MIXL / DAC_MIXR 1?b: ADC1 R/W 1 ?h Select Stereo2 ADC L/R Channel Source 2 0?b: DAC_MIXL / DAC_MIXR 1?b: DMIC1/DMIC2/DMIC3 R/W 0 ?h Select Stereo2 ADC Filter Source 0?b: ADC1 => Left channel ADC2 => Right channel 1?b: ADC3 => Left channel ADC3 => Right channel R/W 0 ?h Select Stereo2 DMIC Source 00?b: DMIC1 01?b: DMIC2 10?b: DMIC3 11?b: Reserved R 0 ?h Reserved

mu_stereo2_adcl1

14

mu_stereo2_adcl2

13

sel_stereo2_adc1

12

sel_stereo2_adc2

11

Sel_stereo2_adc

10

Sel_stereo2_dmic

9:8

reserved

7

71

Rev. 0.91

ALC5670-VB Datasheet
mu_stereo2_adcr1 6 R/W 1 ?h Mute Source1 to Stereo2 ADC Right Channel 0?b:UnMute 1?b:Mute Mute Source2 to Stereo2 ADC Right Channel 0?b:UnMute 1?b:Mute reserved

mu_stereo2_adcr2

5

R/W

1 ?h

reserved

4:0

R

0 ?h

9.20. MX-27h: Stereo1 ADC Digital Mixer Control
Default: 7860?h
Name reserved mu_stereo1_adcl1 Bits 15 14 Table 34. MX-27h: Stereo1 ADC Digital Mixer Control Read/Write Reset State Description R 0 ?h Reserved R/W 1 ?h Mute Source 1 to Stereo1 ADC Left Channel 0?b:UnMute 1?b:Mute R/W 1 ?h Mute Source 2 to Stereo1 ADC Left Channel 0?b:UnMute 1?b:Mute R/W 1 ?h Select Stereo1 ADC L/R Channel Source 1 0?b: DAC_MIXL / DAC_MIXR 1?b: ADC1 R/W 1 ?h Select Stereo1 ADC L/R Channel Source 2 0?b: DAC_MIXL / DAC_MIXR 1?b: DMIC1/DMIC2/DMIC3 R/W 0 ?h Select Stereo1 ADC Filter Source 0?b: ADC1 => Left channel ADC2 => Right channel 1?b: ADC3 => Left channel ADC3 => Right channel R/W 0 ?h Select Stereo1 DMIC Source 00?b: DMIC1 01?b: DMIC2 10?b: DMIC3 11?b: Reserved R 0 ?h Reserved R/W 1 ?h Mute Source 1 to Stereo1 ADC Right Channel 0?b:UnMute 1?b:Mute R/W 1 ?h Mute Source 2 to Stereo1 ADC Right Channel 0?b:UnMute 1?b:Mute R 0 ?h reserved R/W 0 ?h DMIC3 Data Source Selection 0?b: DMIC3_SDA 1?b: S_DAT_IN

mu_stereo1_adcl2

13

sel_stereo1_adc1

12

sel_stereo1_adc2

11

Sel_stereo1_adc

10

Sel_stereo1_dmic

9:8

reserved mu_stereo1_adcr1

7 6

mu_stereo1_adcr2

5

reserved Sel_dmic3_data

4:1 0

72

Rev. 0.91

ALC5670-VB Datasheet

9.21. MX-28h: Mono ADC Digital Mixer Control
Default: 7871?h
Name reserved mu_mono_adcl1 Bits 15 14 Table 35. MX-28h: Mono ADC Digital Mixer Control Read/Write Reset State Description R Reserved 0?h R/W 1 ?h Mute Source 1 to Mono ADC Left channel 0?b:UnMute 1?b:Mute R/W 1 ?h Mute Source 2 to Mono ADC Left channel 0?b:UnMute 1?b:Mute R/W 1 ?h Select Mono ADC Left channel source 1 0?b: Mono_DAC_Mixer_L 1?b: ADC1 R/W 1 ?h Select Mono ADC Left channel source 2 0?b: Mono_DAC_Mixer_L 1?b: DMIC1_L or DMIC2_L or DMIC3_L R/W 0 ?h Select Mono ADC Left Channel Analog ADC Source 0?b: ADC1 1?b: ADC3 R/W 0 ?h Select Mono Left Channel DMIC Source 00?b: DMIC1_L 01?b: DMIC2_L 10?b: DMIC3_L 11?b: Reserved R 0 ?h Reserved R/W 1 ?h Mute Source 1 to Mono ADC Right channel 0?b:UnMute 1?b:Mute R/W 1 ?h Mute Source 2 to Mono ADC Right channel 0?b:UnMute 1?b:Mute R/W 1 ?h Select Mono ADC Right channel source 1 0?b: Mono_DAC_Mixer_R 1?b: ADC2 R/W 0 ?h Select Mono ADC Right channel source 2 0?b: Mono_DAC_Mixer_R 1?b: DMIC1_R or DMIC2_R or DMIC3_R R/W 0 ?h Select Mono ADC Right Channel Analog ADC Source 0?b: ADC2 1?b: ADC3 R/W 1 ?h Select Mono Right Channel DMIC Source 00?b: DMIC1_R 01?b: DMIC2_R 10?b: DMIC3_R 11?b: Reserved

mu_mono_adcl2

13

sel_mono_adcl1

12

sel_mono_adcl2

11

sel_mono_adc_l

10

Sel_mono_dmic_l

9:8

Reserved mu_mono_adcr1

7 6

mu_mono_adcr2

5

sel_mono_adcr1

4

sel_mono_adcr2

3

sel_mono_adc_r

2

Sel_mono_dmic_r

1:0

73

Rev. 0.91

ALC5670-VB Datasheet

9.22. MX-29h: Stereo ADC to DAC Digital Mixer Control
Default: 8080?h
Table 36. MX-29h: Stereo ADC to DAC Digital Mixer Control Name Bits Read/Write Reset State Description Mu_stereo1_adc_mix 15 R/W 1 ?h Mute Stereo1 ADC to DAC1 Left Channel er_l 0?b:UnMute 1?b:Mute Mu_dac1_l 14 R/W 0 ?h Mute IF1 DAC Left Channel 0?b:UnMute 1?b:Mute reserved 13:12 R 0 ?h Reserved Sel_dacr1 11:10 R/W 0 ?h DACR1 Source Selection 00?b: IF1_DAC1_R 01?b: IF2_DAC_R 10?b: Reserved 11?b: Reserved Sel_dacl1 9:8 R/W 0 ?h DACL1 Source Selection 00?b: IF1_DAC1_L 01?b: IF2_DAC_L 10?b: Reserved 11?b: Reserved Mu_stereo1_adc_mix 7 R/W 1 ?h Mute Stereo1 ADC to DAC1 Right Channel er_r 0?b:UnMute 1?b:Mute Mu_dac1_r 6 R/W 0 ?h Mute IF1 DAC Right Channel 0?b:UnMute 1?b:Mute reserved 5:0 R 0 ?h reserved

9.23. MX-2Ah: Stereo DAC Digital Mixer Control
Default: 5656?h
Name Bits reserved 15 mu_stereo_dacl1_mix 14 l gain_dacl1_to_stereo _l 13 Table 37. MX-2Ah: Stereo DAC Digital Mixer Control Read/Write Reset State Description R 0 ?h Reserved R/W 1 ?h Mute Stereo DAC1 Left channel 0?b:UnMute 1?b:Mute R/W 0 ?h Gain Control for DACL1 to Stereo Left Mixer 0?b: 0dB 1?b: -6dB R/W 1 ?h Mute Stereo DAC2 Left channel 0?b:UnMute 1?b:Mute Rev. 0.91

mu_stereo_dacl2_mix 12 l

74

ALC5670-VB Datasheet
Name gain_dacl2_to_stereo _l Mu_snc_to_dac_l Bits 11 Read/Write R/W Reset State Description 0 ?h Gain Control for DACL2 to Stereo Left Mixer 0?b: 0dB 1?b: -6dB 1 ?h Mute SNC_L to DACL1 0?b: UnMute 1?b: Mute 1 ?h Mute Stereo DAC1 Right channel to Left Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACR1 to Stereo Left Mixer 0?b: 0dB 1?b: -6dB 0 ?h reserved 1 ?h Mute Stereo DAC1 Right channel 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACR1 to Stereo Right Mixer 0?b: 0dB 1?b: -6dB 1 ?h Mute Stereo DAC2 Right channel 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACR2 to Stereo Right Mixer 0?b: 0dB 1?b: -6dB 1 ?h Mute SNC_R to DACR1 0?b: UnMute 1?b: Mute 1 ?h Mute Stereo DAC1 Left channel to Right Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACL1 to Stereo Right Mixer 0?b: 0dB 1?b: -6dB

10

R/W

mu_stereo_dacr1_mi xl gain_dacr1_to_stereo _l reserved mu_stereo_dacr1_mi xr gain_dacr1_to_stereo _r mu_stereo_dacr2_mi xr gain_dacr2_to_stereo _r Mu_snc_to_dac_r

9

R/W

8

R/W

7 6

R R/W

5

R/W

4

R/W

3

R/W

2

R/W

mu_stereo_dacl1_mix r gain_dacl1_to_stereo _r

1

R/W

0

R/W

9.24. MX-2Bh: Mono DAC Digital Mixer Control
Default: 5454?h
Name Bits reserved 15 mu_mono_dacl1_mix 14 l gain_mono_l_dacl1 13 Table 38. MX-2Bh: Mono DAC Digital Mixer Control Read/Write Reset State Description R 0 ?h Reserved R/W 1 ?h Mute DAC1 Left channel to Mono DAC Left Mixer 0?b:UnMute 1?b:Mute R/W 0 ?h Gain Control for DAC1 Left channel to Mono DAC Left Mixer 0?b: 0dB 1?b: -6dB 75 Rev. 0.91

ALC5670-VB Datasheet
Name Bits mu_mono_dacl2_mix 12 l gain_mono_l_dacl2 11 Read/Write R/W Reset State Description 1 ?h Mute DAC2 Left channel to Mono DAC Left Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DAC2 Left channel to Mono DAC Left Mixer 0?b: 0dB 1?b: -6dB 1 ?h Mute DAC2 Right channel to Mono DAC Left Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DAC2 Right channel to Mono DAC Left Mixer 0?b: 0dB 1?b: -6dB 0 ?h reserved 1 ?h Mute DAC1 Right channel to Mono DAC Right Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DAC1 Right channel to Mono DAC Right Mixer 0?b: 0dB 1?b: -6dB 1 ?h Mute DAC2 Right channel to Mono DAC Right Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DAC2 Right channel to Mono DAC Right Mixer 0?b: 0dB 1?b: -6dB 1?h Mute DAC2 Left channel to Mono DAC Right Mixer 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DAC2 Left channel to Mono DAC Right Mixer 0?b: 0dB 1?b: -6dB 0 ?h reserved

R/W

mu_mono_dacr2_mix l gain_mono_l_dacr2

10

R/W

9

R/W

reserved 8:7 mu_mono_dacr1_mix 6 r gain_mono_r_dacr1 5

R R/W

R/W

mu_mono_dacr2_mix r gain_mono_r_dacr2

4

R/W

3

R/W

mu_mono_dacl2_mix r gain_mono_r_dacl2

2

R/W

1

R/W

reserved

0

R

9.25. MX-2Ch: DAC Digital Mixer Control
Default: AAA0?h
Name Bits Mu_stereomixl_to_da 15 cmixl Table 39. MX-2Ch: DAC Digital Mixer Control Read/Write Reset State Description R/W 1 ?h Mute Stereo_DAC_Mixer_L to DAC_MIXL 0?b:UnMute 1?b:Mute

76

Rev. 0.91

ALC5670-VB Datasheet
Name Bits gain_stereomixl_to_d 14 acmixl Mu_dacl2_to_dacmix l gain_dacl2_to_dacmi xl Mu_stereomixr_to_da cmixr gain_stereomixr_to_d acmixr Mu_dacr2_to_dacmix r gain_dacr2_to_dacmi xr Mu_dacr2_to_dacmix l gain_dacr2_to_dacmi xl Mu_dacl2_to_dacmix r gain_dacl2_to_dacmi xr reserved 13 Read/Write R/W Reset State Description 0 ?h Gain Control for Stereo_DAC_Mixer_L to DAC_MIXL 0?b: 0dB 1?b: -6dB 1 ?h Mute DACL2 to DAC_MIXL 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACL2 to DAC_MIXL 0?b: 0dB 1?b: -6dB 1 ?h Mute Stereo_DAC_Mixer_R to DAC_MIXR 0?b:UnMute 1?b:Mute 0 ?h Gain Control for Stereo_DAC_Mixer_R to DAC_MIXR 0?b: 0dB 1?b: -6dB 1 ?h Mute DACR2 to DAC_MIXR 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACR2 to DAC_MIXR 0?b: 0dB 1?b: -6dB 1 ?h Mute DACR2 to DAC_MIXL 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACR2 to DAC_MIXL 0?b: 0dB 1?b: -6dB 1 ?h Mute DACL2 to DAC_MIXR 0?b:UnMute 1?b:Mute 0 ?h Gain Control for DACL2 to DAC_MIXR 0?b: 0dB 1?b: -6dB 0 ?h Reserved

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3:0

R

77

Rev. 0.91

ALC5670-VB Datasheet

9.26. MX-2Dh: Voice DSP Path Control 1
Default: 0000?h
Name Sel_rxdp_in Table 40. MX-2Dh: Voice DSP Path Control 1 Bits Read/Write Reset State Description 15:13 R/W 0 ?h RxDP Input Selection 000?b: IF2_DAC_L/R 001?b: IF1_DAC2_L/R 010?b: Stereo1_ADC_Mixer_L/R 011?b: Stereo2_ADC_Mixer_L/R 100?b: Mono_ADC_Mixer_L 101?b: Mono_ADC_Mixer_R 110?b: DACL1/R1 (After EQ/ALC/ SounzRealTM) 111?b: Reserved 12:11 R/W 0 ?h Select SRC to RxDP 00?b: Bypass 01?b: /2 10?b: /3 11?b: Reserved 10 R 0 ?h Reserved 9:8 R/W 0 ?h TxDP Output Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 7:6 R/W 0 ?h TxDC Output Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 5:4 R/W 0 ?h Select SRC to TxDP 00?b: Bypass (Stereo signal) 01?b: /2 (Mono signal) 10?b: /3 (Mono signal) 11?b: Reserved 3:2 R/W 0 ?h TXDP TDM Channel Slot Selection to Stereo Channel 00?b: Slot 0/1 01?b: Slot 2/3 10?b: Slot 4/5 11?b: Slot 6/7 1 R/W 0 ?h Select DSP Uplink Bypass 0?b: Pass DSP 1?b: Bypass DSP 0 R/W 0 ?h Select DSP Downlink Bypass 0?b: Pass DSP 1?b: Bypass DSP

Sel_src_to_rxdp

Reserved Sel_txdp_data

Sel_txdc_data

Sel_src_to_txdp

Sel_tdm_txdp_slot

Sel_dsp_ul_bypass

Sel_dsp_dl_bypass

78

Rev. 0.91

ALC5670-VB Datasheet

9.27. MX-2Eh: Voice DSP Volume Control
Default: 2F2F?h
Name Reserved Vol_txdp_l Bits 15 14:8 Table 41. MX-2Eh: Voice DSP Volume Control Read/Write Reset State Description R 0 ?h Reserved R/W 2F?h Mono ADC left channel digital volume in 0.375 dB step 00?h: -17.625dB 2F?h: 0dB 7F?h: 30dB, 0.375dB/Step R 0 ?h Reserved R/W 2F?h Mono ADC right channel digital volume in 0.375 dB step 00?h: -17.625dB 2F?h: 0dB 7F?h: 30dB, 0.375dB/Step

Reserved Vol_txdp_r

7 6:0

9.28. MX-2Fh: Interface DAC/ADC Data Control
Default: 1002?h
Name Bits Sel_if1_adc2_data_in 15 Table 42. MX-2Fh: Interface DAC/ADC Data Control Read/Write Reset State Description R/W 0 ?h Select Interface1 ADC2 Data Input 0?b: IF_ADC2 1?b: VAD_ADC 14:12 R/W 1 ?h Select Interface2 ADC Data Input 000?b: IF_ADC1 001?b: IF_ADC2 010?b: IF_ADC3 011?b: TxDC_DAC 100?b: TxDP_ADC 101?b: VAD_ADC 110?b: Reserved 111?b: Reserved 11:10 R/W 0 ?h Select Interface2 DAC Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 9:8 R/W 0 ?h Select Interface2 ADC Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 7:6 R/W 0 ?h Select Interface3 DAC Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 79 Rev. 0.91

Sel_if2_adc_data_in

sel_if2_dac_data

sel_if2_adc_data

sel_if3_dac_data

ALC5670-VB Datasheet
Name sel_if3_adc_data Bits 5:4 Read/Write R/W Reset State Description 0 ?h Select Interface3 ADC Data Swap 00?b: L/R 01?b: R/L 10?b: L/L 11?b: R/R 0?h Reserved 2?h Select Interface3 ADC Data Input 000?b: IF_ADC1 001?b: IF_ADC2 010?b: IF_ADC3 011?b: TxDC_DAC 100?b: TxDP_ADC 101?b: VAD_ADC 110?b: Reserved 111?b: Reserved

reserved Sel_if3_adc_data_in

3 2:0

R R/W

9.29. MX-31h: PDM Interface Control
Default: 5500?h
Table 43. MX-31h: PDM Interface Control Bits Read/Write Reset State Description 15:12 R/W 5?h Reserved 11 R/W 0 ?h Select PDM2 Left channel source 0?b: Mono_DAC_MIXL 1?b: Stereo_DAC_MIXL mu_pdm2_l 10 R/W 1 ?h Mute PDM2 Left channel data 0?b: UnMute 1?b: Mute sel_pdm2_r 9 R/W 0 ?h Select PDM2 Right channel source 0?b: Mono_DAC_MIXR 1?b: Stereo_DAC_MIXR mu_pdm2_r 8 R/W 1 ?h Mute PDM2 Right channel data 0?b: UnMute 1?b: Mute reserved 7:6 R 0 ?h Reserved Sel_pdm_pattern_ctrl 5 R/W 0 ?h Select PDM Pattern Command Control 0?b: 64 times 1?b: 128 times Gain_pdm_in 4 R/W 0 ?h PDM Gain Control 0?b: -6dB 1?b: 0dB Reserved 3:0 R 0 ?h Reserved Name reserved sel_pdm2_l

80

Rev. 0.91

ALC5670-VB D

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