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FE2.1 Data Sheet (Rev. 1.01)


USB 2.0 7-Port Hub Data Sheet Rev. 1.01

FE2.1 USB 2.0 HIGH SPEED 7-PORT HUB CONTROLLER
_______________________Data Sheet_______________________
INTRODUCTION
The FE2.

1 is a highly integrated, high quality, high performance, low power consumption, yet low overall cost solution for USB 2.0 High Speed 7-Port Hub. It adopts Multiple Transaction Translator (MTT) architecture to explore the maximum possible throughput. Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming. The whole design is based on state-machine-control to reduce the response delay time; no micro controller is used in this chip. To guarantee high quality, the whole chip is covered by Test Scan Chain – include even the high speed (480MHz) modules, so that all the logic components could be fully tested before shipping. Special Build-In-Self-Test mode is designed to exercise all high, full, and low speed Analog Front End (AFE) components in the packaging and testing stages as well. Low power consumption is achieved by using 0.18μm technology and comprehensive power/clock control mechanism. Most part of the chip will not be clocked unless needed.

FEATURES
? Low power consumption □ 155 mA when seven downstream facing ports enabled in High-Speed mode; □ 66 mA when one downstream facing port enabled in High-Speed mode; Fully compliant with Universal Serial Bus Specification Revision 2.0 (USB 2.0); □ Upstream facing port supports HighSpeed (480MHz) and Full-Speed (12MHz) modes; □ 7 downstream facing ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.5MHz) modes; Integrated USB 2.0 Transceivers; Integrated upstream 1.5KΩ pull-up, downstream 15KΩ pull-down, and serial resisters; Integrated 5V to 3.3V and 1.8V regulator. Integrated Power-On-Reset circuit; Integrated 12MHz Oscillator with feedback resister and crystal load capacitor; Integrated 12MHz-to-480MHz Phase Lock Loop (PLL); Multiple Transaction Translator (MTT) – □ One TT for each downstream port;
1

?

? ?

? ? ? ? ?

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01



? ?

?

?

Alternate Interface 0 for Single-TT, and Alternate Interface 1 for Multiple-TT; □ Each TT could handle 64 periodic Start-Split transactions, 32 periodic Complete-Split transactions, and 6 none-periodic transactions; Support Self-Powered Mode only; Board configured options – □ Ganged or Individual Power Control Mode select; □ Global, Multiple Ganges, or Individual Over-Current Protection Mode select; □ Removable or Non-Removable Downstream Devices configuration; □ Number of Downstream Ports; EEPROM configured options – □ Vendor ID, Product ID, & Device Release Number; □ Removable or Non-Removable Downstream Devices configuration; □ Serial Number; and □ Number of Downstream Ports; Comprehensive status indicators support: □ Standard downstream port status indicators (Green and Amber LED control for each downstream port); □ Hub Active/Suspend indicator LED.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

BLOCK DIAGRAM
To Downstream Devices To Upstream Host/Hub

Downstream PHY #1

Downstream PHY #2

?????

Downstream PHY #7

Upstream PHY

Routing Switch

USB Multi-port Transceiver Macro Cell
12M Hz Crystal 3.3V & 1.8V Regulator OSC Over Current Detection Power Switch Control POR PLL (x40) Data Transmit Data Recovery & Elasticity Buffer Upstream Port Controller

Downstream Port Controllers

USB 2.0 Hub Controlle r

SIE

Transaction Translator Full/Low-Speed Handler

Transaction Translator High-Speed Handler

Hub Controller

EEPROM , Hub Activity LED Port Indicators

Unified Transaction Translator Buffer (14KB)

LED Controller

Fig. 1: Block Diagram

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

PACKAGE I – 64-PIN LQFP
(Body Size: 10x10 mm)

PIN ASSIGNMENT
PWRJ[2] PWRJ[1] PWRJ[5] PWRJ[6] PWRJ[7] OVCJ[2] OVCJ[1] OVCJ[5] OVCJ[6] OVCJ[7] VBUSM

XRSTJ

LED[6]

LED[7]

VD33

64

LED[5] DRV TESTJ LED[1] LED[2] LED[3] VD18 LED[4] VDD5 VD33_O VSS PWRJ[3] OVCJ[3] PWRJ[4] OVCJ[4] VD33

VSS
49 48

1

DP7 DM7 VD33 DP6 DM6 VSS DP5

FE2.1

DM5 VD33 DPU DMU VSS VD18 REXT VD33

16 17 32

33

VD18_O

VSS

DM2

VSS

DP2

DM1

DP1

VD33

VD_PLL

DM4

DP4

DM3

DP3

VD33

XIN

Fig. 2: 64-pin LQFP Pin Assignment

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VS_PLL

XOUT

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

PACKAGE II – 48-PIN LQFP
(Body Size: 7x7 mm)

PIN ASSIGNMENT
VBUSM OVCJ1 OVCJ5 XRSTJ LED[5] LED[6] LED[7]

PWRJ

VD33

48

DRV TESTJ LED[1] LED[2] LED[3] VD18 LED[4] VDD5 VD33_O VSS DM4 DP4

DM7
37 36

VSS

DP7

1

VD33 DP6 DM6 DP5 DM5

FE2.1

VD33 DPU DMU VD18 REXT VD33

12 13 24

25

VD18_O

DM3

DP3

VD33

DP1

VD_PLL

XIN

Fig. 3: 48-pin LQFP Pin Assignment

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VS_PLL

DM2

DP2

DM1

VD33

XOUT

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

PIN DESCRIPTION TABLE
Pin Name 64-pin 48-pin Type LQFP LQFP Pin# Pin#
LED[5] DRV TESTJ 1 2 3 48 1 2 O O

Function

Note

LED Control for the 5th Downstream Facing Port Status. Driving Control for all LED. Otherwise, SDA, Serial Data/Address pin for external Serial EEPROM.

IO-PU Test Mode Enable during hardware reset, active low.

LED[1] LED[2] LED[3] VD18 LED[4] VDD5 VD33_O VSS

4 5 6 7, 36 8 9 10

3 4 5 6, 28 7 8 9

O/ O/ I-PU O/ I-PU P O/ I-PU P P P

LED Control for the 1st Downstream Facing Port Status, and LED Control for the 2nd Downstream Facing Port Status, and Non-Removable Device Configuration bit 0. LED Control for the 3rd Downstream Facing Port Status, and Non-Removable Device Configuration bit 1. 1.8V power input. LED Control for the 4th Downstream Facing Port Status, and Non-Removable Device Configuration bit 2. 5V power input for integrated 5V→3.3V regulator. 3.3V power output from 5V→3.3V integrated regulator – a 10μF decoupling capacitor is required. Ground.

4 3 3

IO-PU SCL, Serial Clock pin for external Serial EEPROM.

3

11, 19, 10, 39 25, 37, 43, 49

PWRJ[3] OVCJ[3] PWRJ[4] OVCJ[4] VD33

12 13 14 15

― ― ― ―

OD I-PU OD I-PU

Power Enable for 3rd Downstream Facing Port, active low. Over-current Detect for 3rd Downstream Facing Port, active low. 1 Power Enable for 4th Downstream Facing Port, active low. Over-current Detect for 4th Downstream Facing Port, active low. 1 3.3V Power Input.

16, 22, 15, 20, P 28, 34, 26, 31, 40, 46, 36, 42 56

DM4 DP4

17 18

11 12

UTD UTD

The D- pin of the 4th Downstream Facing Port. The D+ pin of the 4th Downstream Facing Port.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

DM3 DP3 DM2 DP2 DM1 DP1 VD_PLL XIN XOUT VS_PLL VD18_O REXT DMU DPU DM5 DP5 DM6 DP6 DM7 DP7 XRSTJ VBUSM PWRJ[7] OVCJ[7] PWRJ[6] OVCJ[6] PWRJ[5] OVCJ[5] PWRJ[1] OVCJ[1] PWRJ[2]

20 21 23 24 26 27 29 30 31 32 33 35 38 39 41 42 44 45 47 48 50 51 52 53 54 55 57 58 59 60 61

13 14 16 17 18 19 21 22 23 24 25 27 29 30 32 33 34 35 37 38 40 41 ― ― ― ― ― 43 44 45 ―

UTD UTD UTD UTD UTD UTD P OSC OSC P P A UTU UTU UTD UTD UTD UTD UTD UTD I I OD/ I-PU I-PU OD/ I-PU I-PU OD I-PU OD I OD

The D- pin of the 3rd Downstream Facing Port. The D+ pin of the 3rd Downstream Facing Port. The D- pin of the 2nd Downstream Facing Port. The D+ pin of the 2nd Downstream Facing Port. The D- pin of the 1st Downstream Facing Port. The D+ pin of the 1st Downstream Facing Port. 1.8V Power for PLL. 12 MHz Crystal Oscillator input 12 MHz Crystal Oscillator output. Ground for PLL. 1.8V power output from 3.3V→1.8V integrated regulator – a 10μF decoupling capacitor is required. A 2.7K? (± 1%) resister should be connected to VSS to provide internal bias reference. The D- pin of the Upstream Facing Port. The D+ pin of the Upstream Facing Port. The D- pin of the 5th Downstream Facing Port. The D+ pin of the 5th Downstream Facing Port. The D- pin of the 6th Downstream Facing Port. The D+ pin of the 6th Downstream Facing Port. The D- pin of the 7th Downstream Facing Port. The D+ pin of the 7th Downstream Facing Port. External Reset, active low, is an optional source of chip reset signal. The minimum low pulse width is 10 μs. The VBUS Monitor of upstream facing port. Power Enable for 7th Downstream Facing Port, active low, and Power Control Mode Configuration bit 1. Over-current Detect for 7th Downstream Facing Port, active low. 1 Power Enable for 6th Downstream Facing Port, active low, and Power Control Mode Configuration bit 1. Over-current Detect for 6th Downstream Facing Port, active low. 1 Power Enable for 5th Downstream Facing Port, active low. Over-current Detect for 5th Downstream Facing Port, active low. 1 Power Enable for 1st Downstream Facing Port, active low. Over-current Detect for 1st Downstream Facing Port, active low. 1, 3 Power Enable for 2nd Downstream Facing Port, active low.
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2

2

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

OVCJ[2] LED[7] LED[6]

62 63 64

― 46 47

I-PU O/ I-PU O/ I-PU

Over-current Detect for 2nd Downstream Facing Port, active low. 1 LED Control for the 7th Downstream Facing Port Status, and Number of Ports Configuration bit 0. LED Control for the 6th Downstream Facing Port Status, and Number of Ports Configuration bit 1. 3 3

Note 1. Pins OVCJ[7:2] are equipped with optional internal pull-up resisters. When certain OVCJ pin is not required by currently configured over-current protection mode, its internal pull-up resister will be applied so that pin can be left as unconnected on the board. Otherwise, when certain OVCJ pin is used by currently configured over-current protection mode, its pull-up resister will be removed so that it could be used to monitor either 3.3V or 5V input from external application circuit. 2. During power up configuration stage, pins PWRJ[7:6] are used as input with internal pull-up resisters. Once passed that stage, they will be configured as open drain output. 3. During power up configuration stage, pins LED[4:2] and LED[7:6] are used as input with internal pull-up resister. Once passed that stage, they will be configured as CMOS output. 4. During power up configuration stage, pin LED[1] is used as CMOS tristate I/O to work with the external EEPROM as serial clock. Once passed that stage, it is used as CMOS output. Type Abbreviation – I: Schmitt Trigger Input, 5V-Tolerant; I-PU : Input with Controllable Internal Pull-Up, 5V-Tolerant when pull-up resisters is disabled; IO-PU : CMOS 3-state Output with Input and Internal Pull-Up; OD : Open Drain Output; O: CMOS Output; A: Analog I/O; P: Power/Ground; OSC : Crystal Oscillator with internal bias resister and load capacitor; UTU : USB High Speed and Full Speed Transceiver; UTD : USB High Speed, Full Speed, and Low Speed Transceiver.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

CONFIGURABLE OPTIONS
The FE2.1 is a highly versatile design that can be configured to meet many varieties of implementation requirement in a rather easy way. The behavior of FE2.1 can be configured by either board design selected options or through contents of external EEPROM. LED Indicators, Number of Downstream Facing Port, and Non-Removable Devices According to USB 2.0 Specification, the status of each downstream port is shown by two LED indicators – the Green and Amber LED. FE2.1 supports the full function as specified by DRV and LED[7:1] pins. Figure 4 shows how these port status indicators be connected, together with the external EEPROM and the Hub Active Indicator (the Red LED).

TESTJ

SDA SCL
Green

A0 A1 A2

FE2.1
LED[1]

EEPROM Port 1 Indicators
Green

Amber

LED[2]
Green

Port 2 Indicators
Amber Green

LED[3]
Amber

Port 3 Indicators Port 4 Indicators

LED[4]
Green Amber

LED[5]
Amber Green

Port 5 Indicators Port 6 Indicators
Green Amber

LED[6] LED[7]
Amber

Port 7 Indicators

DRV
Red

Hub Active Indicator

Fig. 4: LED and EEPROM Connections The optional Hub Active Indicator is only turned on when the hub is configured by the host, and turned off when the hub is either set into suspend mode, disconnected, or powered off by the host. Any of these fifteen LED's could be removed without effecting the normal function of the hub.
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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

The LED[7:1] pins could also be used to configure the number of downstream facing port and nonremovable downstream devices. These option selections are sampled and loaded each time after chip reset. If an alternate configuration is intended, the corresponding pins should be tied to ground as shown in the following table. Otherwise, denoted as Normal in the following tables, they could be either left floating or connected to the LED's as shown by figure 4. Usable Downstream Facing Port 4, 3, 2, 1 5, 4, 3, 2, 1 6, 5, 4, 3, 2, 1 7, 6, 5, 4, 3, 2, 1 LED[7]
Tied-to-Ground Normal Tied-to-Ground Normal

LED[6]
Tied-to-Ground Tied-to-Ground Normal Normal

Setting the number of Downstream Facing Port by tying any of LED[7:6] to ground will change the bNbrPorts field (3rd byte) of Hub Descriptor as response to host's GetHubDescriptor request. Henceforth the ports beyond the specified number will not be recognized nor activated by the host. Non-Removable Downstream Facing Ports None 2 3, 2 3, 2, 1 4, 3, 2, 1 5, 4, 3, 2, 1 6, 5, 4, 3, 2, 1 7, 6, 5, 4, 3, 2, 1 LED[4] LED[3] LED[2]

Normal Normal Normal Normal Tied-to-Ground Tied-to-Ground Tied-to-Ground Tied-to-Ground

Normal Normal Tied-to-Ground Tied-to-Ground Normal Normal Tied-to-Ground Tied-to-Ground

Normal Tied-to-Ground Normal Tied-to-Ground Normal Tied-to-Ground Normal Tied-to-Ground

The Non-Removable Downstream Facing Ports setting is reported in the bit-map of DeviceRemovable field of Hub Class Descriptor. When a downstream facing port is configured as unusable or non-removable, its corresponding LED pin will be disabled. In other words, those LED pins should be either tied to ground based on the selected configuration, or left floating. The only exception is LED[1], which would be still used as SCL, Serial Clock pin for external EEPROM, should it exist.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

Figure 5 depicts an example that enable 5 downstream facing ports only, with port 3 and 2 as nonremovable device. As shown, the LED[4] is connected to the LED's, LED[2] left floating, and LED[3] tied to ground, so that the FE2.1 would recognize that port 3 and 2 are non-removable devices. The LED[6] is tied to ground and LED[7] left floating, thus the FE2.1 will report to system that only 5 ports are available in this hub.

TESTJ

SDA SCL
Green

A0 A1 A2

FE2.1
LED[1]

EEPROM Port 1 Indicators

Amber

LED[2] LED[3]
Green

LED[4]
Green Amber

Port 4 Indicators Port 5 Indicators
Amber

LED[5] LED[6] LED[7] DRV
Red

Hub Active Indicator

Fig. 5: LED Board Configuration Example If the external EEPROM is not required, the TESTJ should be left floating. If the Hub Active Indicator is not required, the LED and its serial resister should be removed together. If the port status LED's are not required, LED[5:4, 1] could be all left floating with all their related Green/Amber LED's and resisters removed.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

Power Control and Over-current Protection The FE2.1 supports optional power switches that control delivery of power downstream facing ports by way of a set of active low, open drain, control pins, PWRJ[7:1]. With external pull-up resisters to either 5V or 3.3V, system designers could choice from a wide variety of circuit to implement the power switches. As self-powered hub, over-current protection is a must for safety reasons. The FE2.1 provides a set of input pins, OVCJ[7:1], to monitor status of external over-current detection circuit. The over-current status will than be reported to the host hub driver by FE2.1. Depends on the power control mode actually selected, the unused OVCJ pins will be internally pull-up and left unconnected on board. The FE2.1 supports three types of power control modes, namely Individual Mode, Multiple Gangs Mode, and Ganged Mode. These modes could be configured by tying either or both of PWRJ[7:6] to ground according to the following table.

Power PWRJ[7] PWRJ[6] Control Mode Individual Mode Multiple Gangs Mode Ganged Mode
Normal Tied-toGround Tied-toGround Normal Normal Tied-toGround

wHubCharacteristics
D1..D0 D4..D3

PWRJ [N]

OVCJ [N]

Availability

01 00 00

01 01 00

1, 2, 3, 4, 1, 2, 3, 4, LQFP-64 5, 6, 7 5, 6, 7 1 1 1, 5 1 LQFP-64, LQFP-48 LQFP-64

In the Individual Mode, the power switch of each port is controlled individually, and the over-current status is reported on a per-port basis. That is, for each port N, the power switch is controlled by PWRJ[N], and the over-current status is monitored by OVCJ[N]. In the Ganged Mode, the power switch to all ports are controlled by one single PWRJ[1], and the overcurrent is monitored by OVCJ[1]. Therefore, when host issues SetPortFeature(PORT_POWER) to any of the downstream facing port, the PWRJ[1] will go active, and only when all ports are in poweredoff state that PWRJ[1] will be turned inactive. Since there is only one OVCJ input, all downstream facing ports will be marked as over-current simultaneously and set to powered-off state. The Multiple Gangs Mode has one more over-current status pin, OVCJ[5], then the Ganged Mode. If
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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

OVCJ[1] goes low, downstream facing port 1, 2, 3, and 4 would be marked as over-current. If OVCJ[5] goes low, downstream facing port 5, 6, and 7 would be marked as over-current. Since there is only one PWRJ pin, all ports will be switched to powered-off state at once. This is the only mode supported by LQFP-48 package of FE2.1. The power control mode selection is reported to the host software through the wHubCharacteristics field, the 4th and 5th byte, of Hub Descriptor, which describes the hub's operational characteristics. Two bit-fields would be effected – “D1..D0” for Logical Power Switching Mode, and “D4..D3” for Overcurrent Protection Mode. In “D1..D0”, 00 means ganged power switching (all ports' power at the once,) and 01 means individual port power switching. In “D4..D3”, 00 represents global over-current protection, and 01 represents individual port over-current protection. Figure 6 demonstrates a LQFP-64 implementation of Individual Mode design with dual-channel power distribution switches. In this case, 3,3V pull-up are used for PWRJ/Enable pins to meet the requirement of the specific switches used.

3.3V 5V MIC2026-2 ENA OUTA IN FLGA FLGB GND ENB OUTB MIC2026-2 ENA OUTA IN FLGA FLGB GND ENB OUTB MIC2026-2 ENA OUTA IN FLGA FLGB GND ENB OUTB 3.3V MIC2026-2 ENA OUTA IN FLGA FLGB GND ENB OUTB

OVCJ[1] OVCJ[2] OVCJ[3] OVCJ[4] OVCJ[5] OVCJ[6] OVCJ[7] FE2.1 PWRJ[1] PWRJ[2] PWRJ[3] PWRJ[4] PWRJ[5] PWRJ[6] PWRJ[7]

To VBUS of Port 1 To VBUS of Port 2 To VBUS of Port 3 To VBUS of Port 4 To VBUS of Port 5 To VBUS of Port 6 To VBUS of Port 7

Fig. 6: LQFP-64 Individual Power Control Mode Example Figure 7 demonstrates LQFP-64 implementations of Multiple Gangs Mode and Ganged Mode with
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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

polymeric PTC and MOSFET switches. In these cases, 5V pull-up are used instead.

5V Source OVCJ[1] OVCJ[2] OVCJ[3] OVCJ[4] OVCJ[5] OVCJ[6] OVCJ[7] FE2.1 PWRJ[1] PWRJ[2] PWRJ[3] PWRJ[4] PWRJ[5] PWRJ[6] PWRJ[7]

Poly meric PTC 3.5A

5V Source 5V Source OVCJ[1] OVCJ[2] OVCJ[3] OVCJ[4] OVCJ[5] OVCJ[6] OVCJ[7] FE2.1 To VBUS of all downstream facing ports Ganged Mode Selected PWRJ[1] PWRJ[2] PWRJ[3] PWRJ[4] PWRJ[5] PWRJ[6] PWRJ[7]

Poly meric PTC 2A

2A

5V

5V To VBUS of port 1, 2, 3, & 4 To VBUS of port 5, 6, & 7 Multiple Ganges Mode Selected

Fig. 7: LQFP-64 Power Control Mode Examples And Figure 8 shows LQFP-48 implementation for Multiple Gangs Mode – the only mode supported by LQFP-48 package.

5V Source 5V Source FE2.1 (LQFP48) OVCJ1 OVCJ5 PWRJ

Poly meric PTC 2A

2A

5V

To VBUS of port 1, 2, 3, & 4 To VBUS of port 5, 6, & 7

Fig. 8: LQFP-48 Power Control Example

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

EEPROM CONTENTS

Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 ~ 0x17 0x18 0x19 0x1A 0x1B 0x1C

Contents 0x40 0x1A Vendor ID (Low) Vendor ID (High) Product ID (Low) Product ID (High) Device Release (Low) Device Release (High) Device Serial Number Constant, low byte of check code Constant, high byte of check code

Note

Low byte of Vendor ID, idVendor field of Standard Device Descriptor High byte of Vendor ID, idVendor field of Standard Device Descriptor Low byte of Product ID, idProduct field of Standard Device Descriptor High Byte of Product ID, idProduct field of Standard Device Descriptor Low byte of Device Release Number, must be Binary Coded Decimal, bcdDevice field of Standard Device Descriptor High byte of Device Release Number, must be Binary Coded Decimal, bcdDevice field of Standard Device Descriptor Device's Serial Number – the contents of string descriptor describing the device's serial number. 0x00 Number of Downstream Ports, bNbrPorts field of Hub Descriptor. 0x00 DeviceRemovable field of Hub Descriptor – Indicates if a port has a removable device attached. If bit N is set to 1, then the device on downstream facing port N is non-removable. Otherwise, it is removable. Bit 0 is reserved and should be 0. 0x00 Bit 0: Port Indicators Support, bit 7 of wHubCharacteristics field of Hub Descriptor – 0: Port Indicators are not supported on its downstream facing ports and PORT_INDICATOR request has no effect. 1: Port Indicators are supported on its downstream facing ports and PORT_INDICATOR request controls the indicators. Bit 1: Identifies a Compound Device, bit 2 of wHubCharacteristics field of Hub Descriptor – 0: Hub is not part of a compound device. 1: Hub is part of a compound device. Bit 2: Maximum current requirements of the Hub Controller electronics, bHubContrCurrent field of Hub Descriptor – 0: 200mA. 1: 500mA. Bit 3 to 7, reserved, must be 0's. The 8-bit sum of all value from 0x00 to 0x1E.

Length of Serial Number Length of effective “Device Serial Number” stored in 0x08 to 0x17. Filling Port Number Filling Device Removable

0x1D 0x1E

Filling Device Attributes

0x1F

Check Sum

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

The first two bytes are the check code for the existence of EEPROM, their value must be 0x1A40. Any other value would cause the EEPROM loading mechanism of FE2.1 to conclude that the contents of this EEPROM is unusable, and use default values instead. The string descriptor for device's serial number could be defined by Device Serial Number and Length of Serial Number fields of the EEPROM, address 0x08 to 0x18. Length of Serial Number field, address 0x18, define the number of digits, while Device Serial Number field, address 0x08 to 0x17, specify the serial number in ASCII code. The space after the specified number of digits should be filled with Null, 0x00. For example, suppose the serial number is “A090108F4”, then the EEPROM should be like: 0x08 0x10 0x18 0x41 (A) 0x34 (4) 0x09 0x30 (0) 0x39 (9) 0x30 (0) 0x31 (1) 0x30 (0) 0x38 (8) 0x46 (F)

0x00 (Null) 0x00 (Null) 0x00 (Null) 0x00 (Null) 0x00 (Null) 0x00 (Null) 0x00 (Null)

The last byte, address 0x1F, is a checksum made up of the sum of all value from 0x00 to 0x1E. The numbers must match to render the contents of the EEPROM usable. Otherwise, the loading mechanism of FE2.1 would discard the value from EEPROM and use default values instead.

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Power Supply Voltage TS
VDD5 VD33 VD18 & VD_PLL

Symbol

Min. -55 -0.5 -0.5 -0.5 -2000 -200 -200

Max. +150 +6.0 +4.0 +2.5 2000 200 200 ?C V

Unit

ESD Human Body Mode ESD Machine Mode Latch Up RECOMMENDED OPERATING RANGES Parameter Operating temperature Case Temperature (LQFP-64 package) Case Temperature (LQFP-48 package) Operating voltage TA TC64 TC48
VDD5 VD33 VD18 & VD_PLL

V V mA

Symbol 0 0 0

Min.

Typ.

Max. 70 110 105

Unit ?C ?C ?C V

4.5 3.0 1.62 -0.3 2.0 1.45 1.44 0.89 2.4 39

5.0 3.3 1.8

5.5 3.6 1.98 0.8 5.5

LOW level voltage of digital input HIGH level voltage of digital input Threshold voltage of digital input Low-to-High level of schmitt-trigger input High-to-Low level of schmitt-trigger input LOW level voltage of digital output@4mA HIGH level voltage of digital output@4mA Internal Pull-Up Resister Range

VIL VIH VTH VT+ VTVOL VOH RPU

V V V V V V V KΩ

1.58 1.5 0.94

1.74 1.56 0.99 0.4

65

116

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USB 2.0 7-Port Hub Data Sheet Rev. 1.01

POWER CONSUMPTION
DC SUPPLY CURRENT Symbol Active ports I_suspend 7

Condition Host Suspend Full-Speed High-Speed High-Speed 6 Full-Speed High-Speed High-Speed 5 Full-Speed High-Speed High-Speed 4 Full-Speed High-Speed High-Speed 3 Full-Speed High-Speed High-Speed 2 Full-Speed High-Speed High-Speed 1 Full-Speed High-Speed High-Speed No active Full-Speed High-Speed 7x Full-Speed 7x High-Speed 7x Full-Speed 6x Full-Speed 6x High-Speed 6x Full-Speed 5x Full-Speed 5x High-Speed 5x Full-Speed 4x Full-Speed 4x High-Speed 4x Full-Speed 3x Full-Speed 3x High-Speed 3x Full-Speed 2x Full-Speed 2x High-Speed 2x Full-Speed 1x Full-Speed 1x High-Speed 1x Full-Speed Device

Typ. 600 36 155 53 36 140 53 36 125 53 35 111 52 35 96 52 35 82 52 35 66 52 35 52

Unit uA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

Icc

Note: The power consumption is measured when the bus is in IDLE state – there is no activities other than the Start-Of-Frame (SOF) and INTERRUPT-IN packets for the hub itself on the bus. The peak power consumption varies depending upon the system configuration, type of operations, and over-all bus utilization.
Jul. 16, 2009 Subject to Change Without Notice 18

USB 2.0 7-Port Hub Data Sheet Rev. 1.01

PACKAGE I
64-pin LQFP (Body Size: 10x10 mm)

Jul. 16, 2009

Subject to Change Without Notice

19

USB 2.0 7-Port Hub Data Sheet Rev. 1.01

PACKAGE II
48-pin LQFP (Body Size: 7x7 mm)

TERMINUS TECHNOLOGY INC. 1052, 10F, NO. 3-2, YUANQU ST. NANGANG TAIPEI, TAIWAN, ROC
Jul. 16, 2009 Subject to Change Without Notice 20


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