On this page… Automated HDL Code Generation in the Hardware Development Process Summary of Key Features
Automated HDL Code Generation in the Hardware Developm
Simulink? HDL Coder? software lets you generate hardware description language (HDL) code based on Simulink? models and Stateflow? finite-state machines. The coder brings the Model-Based Design approach into the domain of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) development. Using the coder, system architects and designers can spend more time on fine-tuning algorithms and models through rapid prototyping and experimentation and less time on HDL coding. Typically, you use a Simulink model to simulate a design intended for realization as an ASIC or FPGA. Once satisfied that the model meets design requirements, you run the Simulink HDL Coder compatibility checker utility to examine model semantics and blocks for HDL code generation compatibility. You then invoke the coder, using either the command line or the graphical user interface. The coder generates VHDL or Verilog code that implements the design embodied in the model. Usually, you also generate a corresponding test bench. You can use the test bench with HDL simulation tools to drive the generated HDL code and evaluate its behavior. The coder generates scripts that automate the process of compiling and simulating your code in these tools. You can also use EDA Simulator Link?, software from MathWorks? to cosimulate generated HDL entities within a Simulink model. The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation. The design and test process is fully iterative. At any point, you can return to the original model, make modifications, and regenerate code. When the design and test phase of the project has been completed, you can easily export the generated HDL code to synthesis and layout tools for hardware realization. The coder generates synthesis scripts for the Synplify? family of synthesis tools.
Extending the Code Generation Process There are a number of ways to extend the code generation process. You can direct many details of the code generation process by setting code generation options in the HDL Coder pane of the Configuration Parameters dialog box or the Model Explorer. You can also set code generation options as parameter/value pairs passed to the makehdl and makehdltb functions. You can also specify how code is generated for a selected block or sets of blocks within the model. The coder provides alternate HDL block implementations for a variety of blocks. The HDL Block Properties dialog box lets you select from among implementations optimized for characteristics such as speed, chip area, or low latency. The HDL Block Properties dialog box also lets you set implementation parameters that specify further details of the code generated for a block. You can also select implementations and apply implementation parameters to large groups of blocks programmatically. The coder provides utility functions such as hdlfind_system and hdlset_param for this purpose. In some cases, block-specific optimizations may introduce latencies (delays) or numeric computations (for example, saturation or rounding operations) in the generated code that are not in the original model. To help you evaluate such cases, the coder creates a generated model — a Simulink model that corresponds exactly to the generated HDL code. This generated model lets you run simulations that produce results that are bit-true to the HDL code, and whose timing is cycle-accurate with respect to the HDL code. You can interface generated HDL code to existing or legacy HDL code. One way to do this is to use a subsystem in your model as a placeholder for an HDL entity, and generate ablack box interface (comprising I/O port definitions only) to that entity. Another way is to generate a cosimulation interface by placing an HDL Cosimulation block in your model.
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Summary of Key Features
Generation of target-independent, synthesizable HDL code from Simulink models, MATLAB code, and Stateflow charts
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Support for Mealy and Moore finite-state machines and control logic implementations Generation of test benches and EDA Simulator Link cosimulation models Resource sharing and subsystem-level retiming options for area-speed tradeoffs Simulink model optimization using timing constraint information and HDL synthesis tools Code-to-model and model-to-code traceability for DO-254 Legacy code integration