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OV5640


datasheet
PRODUCT SPECIFICATION 1/4" color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

OV5640

OV5640

color CMOS QSXGA (5 megapix

el) image sensor with OmniBSI? technology

00Copyright ? 2011 OmniVision Technologies, Inc. All rights reserved.
This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc. to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.

Trademark Information
OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniBSI is a trademark of OmniVision Technologies, Inc. All other trademarks used herein are the property of their respective owners.

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology
datasheet (CSP3) PRODUCT SPECIFICATION version 2.03 may 2011

To learn more about OmniVision Technologies, visit www.ovt.com. OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI.

i

00applications
cellular phones toys PC multimedia digital still cameras

ordering information
OV05640-A71A (color, lead-free) 71-pin CSP3

00features
1.4 ?m x 1.4 ?m pixel with OmniBSI technology for high performance (high sensitivity, low crosstalk, low noise, improved quantum efficiency) optical size of 1/4" automatic image control functions: automatic exposure control (AEC), automatic white balance (AWB), automatic band filter (ABF), automatic 50/60 Hz luminance detection, and automatic black level calibration (ABLC) programmable controls for frame rate, AEC/AGC 16-zone size/position/weight control, mirror and flip, cropping, windowing, and panning image quality controls: color saturation, hue, gamma, sharpness (edge enhancement), lens correction, defective pixel canceling, and noise canceling support for output formats: RAW RGB, RGB565/555/444, CCIR656, YUV422/420, YCbCr422, and compression support for video or snapshot operations support for internal and external frame synchronization for frame exposure mode support for LED and flash strobe mode support for horizontal and vertical sub-sampling, binning support for minimizing artifacts on binned image support for data compression output support for anti-shake standard serial SCCB interface digital video port (DVP) parallel output interface and dual lane MIPI output interface embedded 1.5V regulator for core power programmable I/O drive capability, I/O tri-state configurability support for black sun cancellation support for images sizes: 5 megapixel, and any arbitrary size scaling down from 5 megapixel support for auto focus control (AFC) with embedded AF VCM driver embedded microcontroller suitable for module size of 8.5 x 8.5 x <6mm with both CSP and RW packaging

00key specifications (typical)
active array size: 2592 x 1944 power supply: core: 1.5V ± 5% (with embedded 1.5V regulator) analog: 2.6 ~ 3.0V (2.8V typical) I/O: 1.8V / 2.8V power requirements: active: 140 mA standby: 20 ?A temperature range: operating: -30°C to 70°C junction temperature (see table 8-1) stable image: 0°C to 50°C junction temperature (see table 8-1) output formats: 8-/10-bit RGB RAW output lens size: 1/4" lens chief ray angle: 24° (see figure 10-2) input clock frequency: 6~27 MHz 05.26.2011 PRODUCT SPECIFICATION max S/N ratio: 36 dB (maximum) dynamic range: 68 dB @ 8x gain maximum image transfer rate: QSXGA (2592x1944): 15 fps 1080p: 30 fps 1280x960: 45 fps 720p: 60 fps VGA (640x480): 90 fps QVGA (320x240): 120 fps sensitivity: 600 mV/Lux-sec shutter: rolling shutter / frame exposure maximum exposure interval: 1964 x tROW pixel size: 1.4 ?m x 1.4 ?m dark current: 8 mV/s @ 60°C junction temperature image area: 3673.6 ?m x 2738.4 ?m package dimensions: 5985 ?m x 5835 ?m

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

iii

00table of contents
1 signal descriptions 2 system level description 2.1 overview 2.2 architecture 2.3 format and frame rate 2.4 I/O control 2.5 system clock control 2.6 SCCB interface 2.7 power up sequence 2.7.1 power up with internal DVDD 2.7.2 power up with external DVDD source 2.8 reset 2.9 hardware and software standby 3 block level description 3.1 pixel array structure 3.2 binning 3.3 VCM driver 3.3.1 output current control mode 4 image sensor core digital functions 4.1 mirror and flip 4.2 image windowing 4.3 test pattern 4.4 50/60Hz detection 4.4.1 overview 4.5 AEC/AGC algorithms 4.5.1 overview 4.5.2 average-based algorithm 4.6 AEC/AGC steps 4.6.1 auto exposure control (AEC) 4.6.2 manual exposure control 4.6.3 auto gain control (AGC) 4.6.4 manual gain control 4.7 black level calibration (BLC) 1-1 2-1 2-1 2-1 2-4 2-5 2-7 2-7 2-10 2-10 2-11 2-13 2-13 3-1 3-1 3-2 3-3 3-3 4-1 4-1 4-2 4-5 4-5 4-5 4-6 4-6 4-6 4-11 4-11 4-11 4-12 4-12 4-13

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

4.8 light frequency selection 4.9 digital gain 4.10 strobe flash and frame exposure 4.10.1 strobe flash control 4.10.2 frame exposure (FREX) mode 4.10.3 FREX strobe flash control 4.11 one time programmable (OTP) memory 5 image sensor processor digital functions 5.1 ISP general controls 5.2 lens correction (LENC) 5.3 auto white balance (AWB) 5.4 raw gamma 5.5 defect pixel cancellation (DPC) 5.6 color interpolation (CIP) 5.7 color matrix (CMX) 5.8 UV average 5.9 scaling 5.10 UV adjust 5.10.1 manual mode 5.10.2 auto mode 5.11 special digital effects (SDE) 5.12 ISP format 5.13 draw window 6 image sensor output interface digital functions 6.1 compression engine 6.1.1 compression mode 1 timing 6.1.2 compression mode 2 timing 6.1.3 compression mode 3 timing 6.1.4 compression mode 4 timing 6.1.5 compression mode 5 timing 6.1.6 compression mode 6 timing 6.1.7 compression mode control 6.2 system control 6.3 microcontroller unit (MCU) 6.4 frame control (FC) 6.5 format description

4-14 4-14 4-15 4-15 4-17 4-18 4-19 5-1 5-1 5-4 5-6 5-8 5-9 5-10 5-11 5-12 5-12 5-13 5-13 5-13 5-15 5-16 5-16 6-1 6-1 6-1 6-1 6-2 6-2 6-3 6-3 6-4 6-5 6-8 6-9 6-10

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

v

6.6 digital video port (DVP) 6.6.1 overview 6.6.2 DVP timing 6.7 mobile industry processor interface (MIPI) 7 register tables 7.1 system and IO pad control [0x3000 ~ 0x3052] 7.2 SCCB control [0x3100 ~ 0x3108] 7.3 SRB control [0x3200 ~ 0x3211] 7.4 AWB gain control [0x3400 ~ 0x3406] 7.5 AEC/AGC control [0x3500 ~ 0x350D] 7.6 VCM control [0x3600 ~ 0x3606] 7.7 timing control [0x3800 ~ 0x3821] 7.8 AEC/AGC power down domain control [0x3A00 ~ 0x3A25] 7.9 strobe control [0x3B00 ~ 0x3B0C] 7.10 50/60Hz detector control [0x3C00 ~ 0x3C1E] 7.11 OTP control [0x3D00 ~ 0x3D21] 7.12 MC control [0x3F00 ~ 0x3F0D] 7.13 BLC control [0x4000 ~ 0x4033] 7.14 frame control [0x4201 ~ 0x4202] 7.15 format control [0x4300 ~ 0x430D] 7.16 JPEG control [0x4400 ~ 0x4431] 7.17 VFIFO control [0x4600 ~ 0x460D] 7.18 DVP control [0x4709 ~ 0x4745] 7.19 MIPI control [0x4800 ~ 0x4837] 7.20 ISP frame control [0x4901 ~ 0x4902] 7.21 ISP top control [0x5000 ~ 0x5063] 7.22 AWB control [0x5180 ~ 0x51D0] 7.23 CIP control [0x5300 ~ 0x530F] 7.24 CMX control [0x5380 ~ 0x538B] 7.25 gamma control [0x5480 ~ 0x5490] 7.26 SDE control [0x5580 ~ 0x558C] 7.27 scale control [0x5600 ~ 0x5606] 7.28 AVG control [0x5680 ~ 0x56A2] 7.29 LENC control [0x5800 ~ 0x5849] 7.30 AFC control [0x6000 ~ 0x603F]

6-15 6-15 6-18 6-20 7-1 7-1 7-7 7-8 7-9 7-10 7-10 7-11 7-13 7-16 7-17 7-19 7-21 7-23 7-25 7-26 7-31 7-33 7-34 7-38 7-41 7-41 7-46 7-48 7-49 7-50 7-51 7-53 7-54 7-56 7-61

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

8 operating specifications 8.1 absolute maximum ratings 8.2 functional temperature 8.3 DC characteristics 8.4 AC characteristics 9 mechanical specifications 9.1 physical specifications 9.2 IR reflow specifications 10 optical specifications 10.1 sensor array center 10.2 lens chief ray angle (CRA)

8-1 8-1 8-1 8-2 8-4 9-1 9-1 9-2 10-1 10-1 10-2

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

vii

00list of figures
figure 1-1 figure 2-1 figure 2-2 figure 2-3 figure 2-4 figure 3-1 figure 3-2 figure 3-3 figure 3-4 figure 3-5 figure 4-1 figure 4-2 figure 4-3 figure 4-4 figure 4-5 figure 4-6 figure 4-7 figure 4-8 figure 4-9 figure 4-10 figure 4-11 figure 5-1 figure 6-1 figure 6-2 figure 6-3 figure 6-4 figure 6-5 figure 6-6 figure 6-7 figure 8-1 figure 9-1 figure 9-2 pin diagram OV5640 block diagram reference design schematic power up timing with internal DVDD power up timing with external DVDD source sensor array region color filter layout example of 2x2 binning VCM block diagram 1/4 to 3/4 scale settling time (directly jump mode, VDD = 3.0V) sink current vs. code (VDD = 3.0V, reg 0x30A5 = 0x05, VCM resistance = 23ohms) mirror and flip samples image windowing image windowing configuration test pattern desired convergence average-based window definition xenon flash mode LED 1 & 2 mode - one pulse output LED 1 & 2 mode - multiple pulse output LED 3 mode FREX modes UV adjust graph compression mode 1 timing compression mode 2 timing compression mode 3 timing compression mode 4 timing compression mode 5 timing compression mode 6 timing DVP timing diagram SCCB interface timing package specifications IR reflow ramp rate requirements 1-4 2-2 2-3 2-11 2-12 3-1 3-2 3-3 3-6 3-6 4-1 4-2 4-3 4-5 4-7 4-9 4-15 4-16 4-16 4-17 4-17 5-14 6-1 6-1 6-2 6-2 6-3 6-3 6-18 8-5 9-1 9-2

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

figure 10-1 figure 10-2

sensor array center chief ray angle (CRA)

10-1 10-2

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

ix

00list of tables
table 1-1 signal descriptions table 2-1 format and frame rate table 2-2 driving capability and direction control for I/O pads table 2-3 group sharing registers table 2-4 group write register table 3-1 binning-related registers table 3-2 VCM driver control table 3-3 VCM control registers table 3-4 single step mode table 3-5 multi-code step mode table 4-1 mirror and flip registers table 4-2 image windowing registers table 4-3 test pattern selection control table 4-4 AEC/AGC control functions table 4-5 AEC/AGC control functions table 4-6 timing control functions table 4-7 BLC control functions table 4-8 light frequency registers table 4-9 flashlight modes table 4-10 FREX strobe control functions table 4-11 OTP control functions table 5-1 ISP general control registers table 5-2 LENC control registers table 5-3 AWB control registers table 5-4 raw gamma control registers table 5-5 DPC control registers table 5-6 CIP control registers table 5-7 CMX control registers table 5-8 UV average register table 5-9 UV average register table 5-10 SDE control registers table 5-11 ISP format control registers 1-1 2-4 2-5 2-7 2-8 3-2 3-4 3-4 3-5 3-5 4-1 4-3 4-5 4-6 4-8 4-9 4-13 4-14 4-15 4-18 4-19 5-1 5-4 5-6 5-8 5-9 5-10 5-11 5-12 5-12 5-15 5-16

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 5-12 draw window registers table 6-1 compression control registers table 6-2 system control registers table 6-3 MCU control registers table 6-4 FC control registers table 6-5 FORMAT control registers table 6-6 DVP control registers table 6-7 DVP timing specifications table 6-8 MIPI transmitter registers table 7-1 system and IO pad control registers table 7-2 SCCB control registers table 7-3 SRB control registers table 7-4 AWB gain control registers table 7-5 AEC/AGC control registers table 7-6 VCM control registers table 7-7 timing control registers table 7-8 AEC/AGC power down domain control registers table 7-9 strobe registers table 7-10 5060Hz detector registers table 7-11 OTP control functions table 7-12 MC registers table 7-13 BLC registers table 7-14 frame control registers table 7-15 format control registers table 7-16 JPEG control registers table 7-17 VFIFO registers table 7-18 DVP control registers table 7-19 MIPI transmitter registers table 7-20 ISP frame control registers table 7-21 ISP top control registers table 7-22 AWB registers table 7-23 CIP control registers table 7-24 CMX control registers table 7-25 gamma control registers table 7-26 SDE control registers

5-16 6-4 6-5 6-8 6-9 6-10 6-15 6-18 6-20 7-1 7-7 7-8 7-9 7-10 7-10 7-11 7-13 7-16 7-17 7-19 7-21 7-23 7-25 7-26 7-31 7-33 7-34 7-38 7-41 7-41 7-46 7-48 7-49 7-50 7-51

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

xi

table 7-27 scale registers table 7-28 AVG registers table 7-29 LENC control registers table 7-30 AFC control registers table 8-1 absolute maximum ratings table 8-2 functional temperature table 8-3 DC characteristics (-30°C < TJ < 70°C) table 8-4 AC characteristics (TA = 25°C, VDD-A = 2.8V) table 8-5 timing characteristics table 8-6 SCCB interface timing specifications table 9-1 package dimensions table 9-2 reflow conditions table 10-1 CRA versus image height plot

7-53 7-54 7-56 7-61 8-1 8-1 8-2 8-4 8-4 8-5 9-1 9-2 10-2

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

1-1

1 signal descriptions
table 1-1 lists the signal descriptions and their corresponding pin numbers for the OV5640 image sensor. The package information is shown in section 9.

table 1-1
pin number
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C10 C11

signal descriptions (sheet 1 of 3)
signal name
VCMSINK AVDD AGND DGND NC NC NC DVDD AGND NC DGND VCMSINK VCMGND VCMGND DVDD NC NC NC DGND AVDD VN DVDD DGND NC VH AVDD

pin type
I/O power ground ground – – – power ground – ground I/O I/O I/O power – – – ground power reference power ground – reference power

description
analog I/O power for analog circuit ground for analog circuit ground for digital circuit no connect no connect no connect power for digital circuit ground for analog circuit no connect ground for digital circuit analog I/O analog I/O analog I/O power for digital circuit no connect no connect no connect ground for digital circuit power for analog circuit internal analog reference power for digital circuit ground for digital circuit no connect internal analog reference power for analog circuit

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 1-1
pin number
D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 I1 I2 I8 I9 I10 I11 J1 J2 J3 J4

signal descriptions (sheet 2 of 3)
signal name
PWDN DVDD NC AGND STROBE RESETB NC NC GPIO0 FREX NC SGND GPIO1 DOGND SIOC SIOD VSYNC HREF D3 XVCLK PCLK DGND D6/MCN D7/MCP PVDD DVDD DVDD DOVDD DOVDD DOGND

pin type
input power – ground I/O input – – I/O I/O – ground I/O ground input I/O I/O I/O I/O input I/O ground I/O I/O power power power power power ground

description
power down (active high with internal pull-down resistor) power for digital circuit no connect ground for analog circuit strobe output reset (active low with internal pull-up resistor) no connect no connect GPIO port 0 frame exposure / mechanical shutter no connect ground for sensor circuit GPIO port 1 ground for I/O circuit SCCB input clock SCCB data DVP VSYNC output DVP HREF output DVP data output port 3 system input clock DVP PCLK output ground for digital circuit DVP data output port 6/ MIPI TX clock lane negative output DVP data output port 7/ MIPI TX clock lane positive output power for PLL circuit power for digital circuit power for digital circuit power for I/O circuit power for I/O circuit ground for I/O circuit

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

1-3

table 1-1
pin number
J5 J6 J7 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K11

signal descriptions (sheet 3 of 3)
signal name
D2 NC EVDD D8/MDN1 D9/MDP1 DOGND DVDD DOVDD DOVDD D1/GPIO3 D0/GPIO2 D4/MDN0 D5/MDP0 EGND EGND

pin type
I/O – reference I/O I/O ground power power power I/O I/O I/O I/O ground ground

description
DVP data output port 2 no connect power for MIPI TX circuit DVP data output port 8/ MIPI TX second data lane negative output DVP data output port 9/ MIPI TX second data lane positive output ground for I/O circuit power for digital circuit power for I/O circuit power for I/O circuit DVP data output port 1/ GPIO port 3 DVP data output port 0/ GPIO port 2 DVP data output port 4/ MIPI TX first data lane negative output DVP data output port 5/ MIPI TX first data lane positive output ground for MIPI TX circuit ground for MIPI TX circuit

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

figure 1-1

pin diagram
A2 B1 C1
DVDD

A3 B3 C3
NC

A4
AGND

A5
DGND

A6
NC

A7
NC

A8
NC

A9
DVDD

A10
AGND

A11
NC

VCMSINK AVDD

B2 C2
DGND

B4

B5

B6
NC

B7
NC

B8
NC

B9
DGND

B10
AVDD

B11
VN

DGND VCMSINK VCMGND VCMGND DVDD

C10
VH

C11
AVDD

D1
PWDN

D2
DVDD

D10
NC

D11
AGND

E1 F1
GPIO0

E2 F2
FREX

E10

E11
NC

STROBE RESETB

OV5640

NC

F10
NC

F11
SGND

G1
GPIO1

G2
DOGND

G10
SIOC

G11
SIOD

H1
VSYNC

H2
HREF

H10
D3

H11
XVCLK

I1
PCLK

I2
DGND

I8 J3 K3 J4 K4 J5
D2

I9 J9

I10 J10

I11
DVDD

D6/MCN D7/MCP PVDD

J1
DVDD

J2 K2

J6
NC

J7
EVDD

J11
DOGND

DOVDD DOVDD DOGND

D8/MDN1 D9/MDP1

K1
DVDD

K5

K6

K7

K8
EGND

K11
EGND
5640 CSP DS 1 1

DOVDD DOVDD D1/GPIO3 D0/GPIO4 D4/MDN0 D5/MDP0

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-1

2 system level description
2.1 overview
The OV5640 (color) image sensor is a low voltage, high-performance, 1/4-inch 5 megapixel CMOS image sensor that provides the full functionality of a single chip 5 megapixel (2592x1944) camera using OmniBSI? technology in a small footprint package. It provides full-frame, sub-sampled, windowed or arbitrarily scaled 8-bit/10-bit images in various formats via the control of the Serial Camera Control Bus (SCCB) interface. The OV5640 has an image array capable of operating at up to 15 frames per second (fps) in 5 megapixel resolution with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control, defective pixel canceling, noise canceling, etc., are programmable through the SCCB interface or embedded microcontroller. The OV5640 also includes a compression engine for increased processing power. In addition, OmniVision image sensors use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. The OV5640 has an embedded microcontroller, which can be combined with an internal autofocus engine and programmable general purpose I/O modules (GPIO) for external autofocus control. It also provides an anti-shake function with an internal anti-shake engine. For identification and storage purposes, the OV5640 also includes a one-time programmable (OTP) memory. The OV5640 supports both a digital video parallel port and a serial MIPI port.

2.2 architecture
The OV5640 sensor core generates streaming pixel data at a constant frame rate, indicated by HREF and VSYNC. figure 2-1 shows the functional block diagram of the OV5640 image sensor. The timing generator outputs signals to access the rows of the image array, precharging and sampling the rows of the array in series. In the time between pre-charging and sampling a row, the charge in the pixels decreases with the time exposed to the incident light. This is known as exposure time. The exposure time is controlled by adjusting the time interval between precharging and sampling. After the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. Following analog processing is the ADC which outputs 10-bit data for each pixel in the array.

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

figure 2-1

OV5640 block diagram

OV5640
image sensor core column sample/hold
row select

image sensor processor

image output interface

compression engine

DVP

MIPI

image array

AMP

10-bit ADC

formatter

D[9:0] MCP/N MDP/N[1:0]

50/60 Hz auto detection

gain control

control register bank timing generator and system control logic MIPI interface SCCB interface micro controller

PLL

FIFO

ISP

VCM

VSYNC

STROBE

PWDN

XVCLK

RESETB

GPIO[3:0]

HREF

FREX

PCLK

SIOD

SIOC

5640_DS_2_1

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-3

figure 2-2

reference design schematic
DOVDD EVDD DVDD

C9 0.1μF-0603

C1 1μF-0603

D1

D0

D2

K6 D4/MDN0

K7 D5/MDP0

EVDD

D6/MCN

D7/MCP

C2 1μF-0603

10-0603 RESETB

A7

A8

C3

K2

K3

K4

K5

K8

J2

J3

J4

J5

J7

J6

I8

I9

DOVDD

D4/MDN0

D5/MDP0

D6/MCN

DOVDD

DOVDD

DOVDD

DOGND

D1/GPIO3

D0/GPIO2

D7/MCP

D3 D5 D7 D9

1 3 5 7 9 13 15 17 19 21 23 25 27 29 31 11

2 4 6 8 10 12

D2 D4 D6 D8 SIOD SIOC

0-0603

A6 K1 J1 I2 I1 HREF VSYNC GPIO1 GPIO0 FREX STROBE RESETB PWDN H2 H1 G2 G1 F1 F2 E1 E2 D1 D2 C1 B8

NC DVDD DVDD DGND PCLK HREF VSYNC DOGND GPIO1 GPIO0 FREX STROBE RESETB PWDN DVDD DVDD
VCMSINK VCMSINK

NC NC DGND D8/MDN1 D9/MDP1 EGND PVDD

F10
R2

B9 J9 J10 K11 I10 J11 I11 H10 H11 G10 G11 F11 D11 C11 E11 D3 XCLK SIOC SIOD R5 0-0603 PVDD C8 0.1μF-0603 D8/MDN1 D9/MDP1 PVDD

R4

CON32A

HREF VSYNC VDD PCLK

14 16 18 22 24 26 28 30 32 20

OV5640 CSP BSI

J1

DVDD D3 XVCLK SIOC SIOD SGND AGND AVDD NC

D1 GPIO1 STROBE

D0 GPIO0 VCMSINK FREX

PGND Do not assemble R1 and R2.

NC
DGND DGND

VCMGND

VCMGND

DGND

AGND

AGND

DVDD

DVDD

AVDD

AVDD

VN

VH

NC

NC

NC

A2

A3

A4

A5

A9

A10

B7

B6

C2

B1

B2

B4

B3

B5

C10

B11

A11

D10

B10

NC

EVDD DVDD R13 0-0603 PVDD AVDD AVDD R12 0-0603

AGND

AGND

C7 0.1μF-0603

VN

VH

C6 0.1μF-0603

C5 0.1μF-0603

C3 0.1μF-0603

VCMSINK

VCMGND

C4 0.1μF-0603

DGND

DVDD

PGND is system ground (power ground - GND). AGND and DGND are sensor analog and digital grnd. Connect different ground plants to a single point. AVDD L2 L3 VDD 2.8V 3.3μH-1206 L1 3.3μH-1206 D9 FB-0805
10μF/6V-EIA-A 10μF/6V-EIA-A C15 0.1μF-0603 C12 0.1μF-0603

DVDD 1.5V 3.3μH-1206

DOVDD

R6 R7 R8 R9

0-0603 0-0603 0-0603 0-0603 0-0603 0-0603

D9/MDP1 6 D7/MCP D6/MCN 4 3
J2 HEADER6X1

AGND VCMGND DGND

1 2 3

2
10μF/6V-EIA-A

1
C14 1μF-0603

VIN GND

OUT

3 L4

D8 D7 D6

D8/MDN1 5

C10 0.1μF-0603

D5 R10 D4 R11

D5/MDP0 2 D4/MDN0 1

AGND C11

DGND C16

DGND C13

J3 HEADER3X1

U2 XC6206P152PR 1.5V

AGND

PGND

5640_CSP_DS_2_2

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

XCLK R3

0-0603

U1

DOGND

R1

E10

10-0603

PCLK

NC

NC

D2

NC

EVDD

EGND

NC

PWDN

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

2.3 format and frame rate
table 2-1
format
5 Mpixel

format and frame rate
resolution
2592x1944

frame rate
15 fps

scaling method
full resolution (dummy 16 pixel horizontal, 8 lines) 2608x1952 with dummy subsampling in vertical and horizontal 1296x968 supports 2x2 binning cropping from full resolution 1936x1088 with dummy pixels cropping 2592x1944 to 2560x1440 subsampling in vertical and horizontal 1296x728 with dummy supports 2x2 binning subsampling from 1280x960 648x484 with dummy supports 2x2 binning subsampling from 1280x960 324x242 with dummy supports 2x2 binning

pixel clock
96/192 MHz

1280x960

1280x960

45 fps

96/192 MHz

1080p

1920x1080

30 fps

96/192 MHz

720p

1280x720

60 fps

96/192 MHz

VGA

640x480

90 fps

48/96 MHz

QVGA

320x240

120 fps

24/48 MHz

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-5

2.4 I/O control
The OV5640 I/O pad direction and driving capability can be easily adjusted. table 2-2 lists the driving capability and direction control registers of the I/O pads.

table 2-2
function

driving capability and direction control for I/O pads (sheet 1 of 2)
register default value R/W description
Bit[7:6]: output drive capability 00: 1x 01: 2x 10: 3x 11: 4x input/output control for the D[9:0] pins 0: input 1: output

output drive capability control

0x302C

0x02

RW

D[9:0] I/O control

0x3017[3:0], 0x3018[7:2]

0x00

RW

D9 share with MD2P pin for MIPI D8 share with MD2N pin for MIPI D7 share with MCP pin for MIPI D6 share with MCN pin for MIPI D5 share with MD1P pin for MIPI D4 share with MD1N pin for MIPI output selection for the D[9:0] pins 0: normal data path 1: register-controlled value D[9:0] output value D[9:0] input value Bit[6]: input/output control for the VSYNC pin 0: input 1: output output selection for the VSYNC pin 0: normal data path 1: register-controlled value VSYNC output value VSYNC input value input/output control for the HREF pin 0: input 1: output

D[9:0] output select

0x301D[3:0], 0x301E[7:2] 0x301A[3:0], 0x301B[7:2] 0x3051[3:0], 0x3052[7:2]

0x00

RW

D[9:0] output value D[9:0] input value

0x00 –

RW R

VSYNC I/O control

0x3017

0x00

RW

Bit[6]: VSYNC output select 0x301D 0x00 RW

VSYNC output value VSYNC input value

0x301A 0x3051

0x00 –

RW R

Bit[6]: Bit[6]: Bit[5]:

HREF I/O control

0x3017

0x00

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 2-2
function

driving capability and direction control for I/O pads (sheet 2 of 2)
register default value R/W description
Bit[5]: output selection for the HREF pin 0: normal data path 1: register-controlled value HREF output value HREF input value input/output control for the PCLK pin 0: input 1: output output selection for the PCLK pin 0: normal data path 1: register-controlled value PCLK output value PCLK input value

HREF output select

0x301D

0x00

RW

HREF output value HREF input value

0x301A 0x3051

0x00 –

RW R

Bit[5]: Bit[5]: Bit[4]:

PCLK I/O control

0x3017

0x00

RW

Bit[4]: PCLK output select 0x301D 0x00 RW

PCLK output value PCLK input value

0x301A 0x3051

0x00 –

RW R

Bit[4]: Bit[4]:

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-7

2.5 system clock control
The OV5640 PLL allows for an input clock frequency ranging from 6~27 MHz and has a maximum VCO frequency of 800 MHz. MipiClk is for the MIPI and SysClk is for the internal clock of the Image Signal Processing (ISP) block. The PLL can be bypassed by setting register 0x3039[7] to 1.

2.6 SCCB interface
The Serial Camera Control Bus (SCCB) interface controls the image sensor operation. Refer to the OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port. Group write is supported in order to update a group of registers in the same frame. These registers are guaranteed to be written prior to the internal latch at the frame boundary. The OV5640 supports up to four groups. These groups share 1 KB RAM and the size of each group is programmable by adjusting the start address. The group hold start addresses range from 0x40 to 0x7F, where the unit is 16 bytes.

table 2-3
address
0x3200 0x3201 0x3202 0x3203

group sharing registers
register name
GROUP ADDR0 GROUP ADDR1 GROUP ADDR2 GROUP ADDR3

default value
0x40 0x4A 0x54 0x5E

R/W
RW RW RW RW

description
Start Address for Group0 {group_addr0[7:0], 4’h0} Start Address for Group1 {group_addr1[7:0], 4’h0} Start Address for Group2 {group_addr2[7:0], 4’h0} Start Address for Group3 {group_addr3[7:0], 4’h0}

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

The group write function is controlled by register 0x3212.

table 2-4
address

group write register
register name default value R/W description
SRM Group Access Bit[7]: Group launch enable Bit[6]: Test mode access group Bit[5]: Group launch Bit[4]: Group hold end Bit[3:0]: Group id 0xx: Group for register access 011: Group to hold register address of embedded line SOF 100: Group to hold register address of embedded line EOF 101: Test mode for store register value to memory 110: Test mode for restore register value from memory 111: Group for write mask address SRM Group Status Bit[7]: Store default Bit[6]: Restore Bit[5]: Group hold Bit[4]: Group launch Bit[3]: Group write Bit[2:0]: Group select

0x3212

SRM GROUP ACCESS



W

0x3213

SRM GROUP STATUS



R

The SCCB will enter group write mode after writing to register 0x3212 with a valid group ID. The subsequent registers will be held to the buffer specified by the group_id instead of writing to the registers. Make sure the number of registers does not exceed the capacity of the group. Setting group_hold_end to 1 will exit the group write mode. After that, setting both group_launch and group_launch_en to 1 will write the buffered values to the real registers. Multiple groups of registers can be prepared before writing to the real registers but be sure the correct group_id is specified when the group write is launched. The following is an example demonstrating the group write operation: 78 78 78 78 3212 3600 3601 3212 00 00 01 10 End group0 Enable group0 Write registers to be held in group0

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-9

78 78 78 78

3212 3602 3603 3212

01 02 03 11

Enable group1 Write registers to be held in group1 End group1 Other direct register access Enable group2 Write registers to be held in group2 End group2 Launch group0 Other direct register access Enable group3 Write registers to be held in group3 End group3 Launch group1 Launch group2 Launch group3

......................... 78 78 78 78 78 3212 3604 3605 3212 3212 02 04 05 12 A0

......................... 78 78 78 78 78 78 78 3212 3606 3607 3212 3212 3212 3212 03 06 07 13 A1 A2 A3

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

2.7 power up sequence
Based on the system power configuration (1.8V or 2.8V for I/O power, using external DVDD or internal DVDD, requiring access to the I2C during power up period or not), the power up sequence will differ. If 1.8V is used for I/O power, using the internal DVDD is preferred. If 2.8V is used for I/O power, due to a high voltage drop at the internal DVDD regulator, there is a potential heat issue. Hence, for a 2.8V power system, OmniVision recommends using an external DVDD source. Due to the higher power down current when using an external DVDD source, OmniVision strongly recommends cutting off all powers, including the external DVDD, when the sensor is not in use in the case of 2.8V I/O and external DVDD.

2.7.1 power up with internal DVDD
For powering up with the internal DVDD and I2C access during the power ON period, the following conditions must occur: 1. 2. 3. 4. 5. 6. 7. when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable PWDN is active high with an asynchronized design (does not need clock) PWDN pin tied to digital ground if it is not controlled. if PWDN pin is controlled as below, for PWDN to go low, power must first become stable (AVDD to PWDN ≥ 5 ms) RESETB is active low with an asynchronized design master clock XVCLK should provide at least 1 ms before host accesses the sensor’s registers host can access I2C bus (if shared) during entire period. 20ms after RESETB goes high, host can access the sensor's registers to initialize sensor

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-11

figure 2-3

power up timing with internal DVDD
power on t0 power off

DOVDD t2 t3

t5 >=0ms t6 t 1

AVDD PWDN

RESETB

t

4

XVCLK SCCB

note t ≥ 0ms, delay from DOVDD stable to AVDD stable, it is recommended to power up AVDD shortly 0 after DOVDD has been powered up t1 ≥ 0ms, delay from XVCLK off to AVDD off t2 ≥ 5ms, delay from AVDD stable to sensor power up stable, PWDN can be pulled low after this point, XVCLK can be turned on after power on t ≥ 1ms, delay from sensor power up stable to RESETB pull up 3 t4 ≥ 20ms, delay from RESETB pull high to SCCB initialization t ≥ 0ms, delay from AVDD off to DOVDD off 5 t6 ≥ 0ms, delay from RESETB pull low to AVDD off 5640_DS_2_2

2.7.2 power up with external DVDD source
For powering up with an external DVDD source and I2C access during the power ON period, the following conditions must occur: 1. 2. 3. 4. 5. 6. 7. 8. when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable when AVDD and DVDD are turned ON, make sure AVDD becomes stable before DVDD becomes stable PWDN is active high with an asynchronized design (does not need clock), PWDN pin tied to digital ground if it is not controlled if PWDN pin is controlled as below, for PWDN to go low, power must first become stable (DVDD to PWDN ≥ 5 ms) all powers are cut off when the camera is not in use (power down mode is not recommended) RESETB is active low with an asynchronized design master clock XVCLK should provide at least 1 ms before host accesses the sensor’s registers host can access I2C bus (if shared) during entire period. 20ms after RESETB goes high, host can access the sensor's registers to initialize sensor

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

figure 2-4

power up timing with external DVDD source

DOVDD first, then AVDD, followed by DVDD, and rising time is less than 5 ms t0 DOVDD t AVDD t DVDD power on period PWDN RESETB 2 t3 1 t 7 t6 cut off power

t5

t4

XVCLK SCCB

note t ≥ 0 ms: delay from DOVDD stable to AVDD stable, it is recommended to power up AVDD shortly after DOVDD 0 has been powered up t1 ≥ 0 ms: delay from AVDD stable to DVDD stable t2 ≥ 5 ms: delay from DVDD stable to sensor power up stable t ≥ 1ms, delay from sensor power up stable to RESETB pull up 3 t4 ≥ 20ms, delay from RESETB pull high to SCCB initialization t ≥ 0ms, delay from AVDD off to DOVDD off 5 t6 ≥ 0ms, delay from RESETB pull low to DVDD off t7 ≥ 0ms, delay from XVCLK off to DVDD off
5640_DS_2_3

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

2-13

2.8 reset
The OV5640 sensor includes a RESETB pin that forces a complete hardware reset when it is pulled low (GND). The OV5640 clears all registers and resets them to their default values when a hardware reset occurs. A reset can also be initiated through the SCCB interface by setting register 0x3008[7] to high. Manually applying a hard reset upon power up is required even though on-chip reset is included. The hard reset is active low with an asynchronized design. The reset pulse width should be greater than or equal to 1 ms.

2.9 hardware and software standby
Two suspend modes are available for the OV5640: ? ? hardware standby SCCB software standby

To initiate hardware standby mode, the PWDN pin must be tied to high (while in MIPI mode, set register 0x300E[4:3] to 2’b11 before the PWDN pin is set to high). When this occurs, the OV5640 internal device clock is halted and all internal counters are reset and registers are maintained. Executing a software standby through the SCCB interface suspends internal circuit activity but does not halt the device clock. All register content is maintained in standby mode.

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PRODUCT SPECIFICATION

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

3-1

3 block level description
3.1 pixel array structure
The OV5640 sensor has an image array of 2624 columns by 1964 rows (5,153,536 pixels). figure 3-1 shows a cross-section of the image sensor array. The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 5,153,536 pixels, 5,038,848 (2592x1944) are active pixels and can be output. The other pixels are used for black level calibration and interpolation. The sensor array design is based on a field integration readout system with line-by-line transfer and an electronic shutter with a synchronous pixel readout scheme.

figure 3-1

sensor array region color filter layout
columns
16 17 18 19 ... 2607 2608 2609 2610 2611 ... 2623 0 1 2 3 ... 15

0 1 2 3 ... 7 8 B Gb B Gb B Gb 9 Gr R Gr R Gr R 10 B Gb B Gb B Gb 11 Gr R Gr R Gr R 12 B Gb B Gb B Gb 13 Gr R Gr R Gr R 14 B Gb B Gb B Gb 15 Gr R Gr R Gr R 16 B Gb B Gb B Gb 17 Gr R Gr R Gr R ... B Gb B Gb B Gb 1957 Gr R Gr R Gr R 1958 B Gb B Gb B Gb 1959 Gr R Gr R Gr R 1960 B Gb B Gb B Gb 1961 Gr R Gr R Gr R 1962 B Gb B Gb B Gb 1963 Gr R Gr R Gr R B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

black line

rows

B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

dummy line

B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

active line

B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

B Gb B Gb B Gb R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R
Gr

dummy line

dummy column

active column

dummy column
5640_DS_3_1

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

3.2 binning
Binning mode is usually used for subsampling. During subsampling, information is periodically dropped when data is output. When the binning function is ON, voltage levels of adjacent pixels are averaged before being sent to the ADC. If the binning function is OFF, the pixels, which are not output, are merely skipped. The OV5640 supports 2x2, 1x2, and 2x1 binning. figure 3-2 illustrates 2x2 binning, where the voltage levels of four (2x2) adjacent same-color pixels are averaged before entering the ADC. In OV5640, vertical binning will automatically turn on when in vertical-subsampled formats.

figure 3-2

example of 2x2 binning
2x2 green pixels are 2x2 blue pixels are binned to 1 blue pixel binned to 1 green pixel B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R BG GR B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R BG GR

BG GR

BG GR

2x2 green pixels are binned to 1 green pixel

2x2 red pixels are binned to 1 red pixel
5640_DS_3_2

table 3-1
address
0x3821

binning-related registers
register name
TIMING TC REG21

default value
0x00

R/W
RW

description
Bit[0]: Horizontal binning enable

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

3-3

3.3 VCM driver
figure 3-3 VCM block diagram
Vvcm

voice coil motor RVCM current sinking pad RP1 Vds resistor Rs = 3.3 Ω VCM GND PAD RP2

5640_DS_3_3

The maximum SINK current can be estimated as: ? ? ? ? ISINK = (Vvcm - Vds) / (Rs + Rvcm + Rp1 + Rp2) Vds is the transistor headroom Rp1 and Rp2 are the resistance in the current path RVCM is the resistance of the voice coil motor.

The OV5640 VCM driver is a single 10-bit DAC with 100 mA output current sink capability. It is designed for linear control of the VCM. The DAC is controlled via the SCCB interface with clock rates up to 400 Hz. The OV5640 VCM driver provides three types of output current control modes that allow users to adjust transient response of the sinking current.

3.3.1 output current control mode
The OV5640 VCM driver uses 4 bits (S3, S2, S1, and S0) to control the output current response. 1. 2. S[3:0] = X000: S[3:0] = 0001 to 0111: Directly jump mode: code directly jumps to target code. Output current transient response time (see table 3-2.) Single step mode: code increases/decreases by a single step. Single step time durations are 50?s, 100?s, 200?s, 400?s, 800?s, 1600?s, and 3200?s, which are controlled by S2, S1, and S0 (see table 3-4.) Multi-code steps mode: Code increases/decreases in multi-code steps. If the target code and the current code have a difference larger than 128, the 64-code step is applied first. When the difference in between target and current codes is no more than 128 but larger than 16, the 16-code step is used. When the difference is less than 16, it will directly jump to the target code. Single step time options are 50?s, 100?s, 200?s, 400?s, 800?s, 1600?s, and 3200?s, which are controlled by S2, S1, and S0, (see table 3-5.)

3.

S[3:0] = 1001 to 1111:

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 3-2
function

VCM driver control
register description
Bit[3:0]: Current transient response control x000: mode 0 0001~0111: mode 1 1001~1111: mode 2 0x3603[5:0]: 0x3602[7:4]: D[9:4] D[3:0]

current transient response control

0x3602

10-bit DAC code

0x3603[5:0], 0x3602[7:4] 0x3605[3:0], 0x3606[7:0]

clock divider

divide external clock to obtain a 20 KHz clock for VCM control block VCM control clock = external clock / Rdiv[11:0]

table 3-3
address
0x3603

VCM control registers
register name
VCM[15:8]

default value
0x01

R/W
RW

description
Bit[7]: PD Bit[5:0]: D[9:4] Bit[7:4]: D[3:0] Bit[3]: S3 Bit[2:0]: S[2:0] Bit[3:0]: Rdiv[11:8] Bit[7:0]: Rdiv[7:0] Bit[2:0]: VCM output current control 000: 0.71 * Id 001: 0.77 * Id 010: 0.83 * Id 011: 0.91 * Id 100: 1.00 * Id 101: 1.11 * Id 110: 1.25 * Id 111: 1.43 * Id

0x3602 0x3605 0x3604

VCM[7:0] SLEW[11:8] SLEW[7:0]

0x50 0x46 0x05

RW RW RW

0x3606

VCM CURRENT

0x00

RW

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PRODUCT SPECIFICATION

version 2.03

3-5

table 3-4
mode

single step mode
S3
0 0 0

S2
0 0 0 1 1 1 1

S1
0 1 1 0 0 1 1

S0
1 0 1 0 1 0 1

single step transition time
50?s 100?s 200?s 400?s 800?s 1600?s 3200?s

full scale transition time (1023 steps)
51.15ms 102.3ms 204.6ms 409.2ms 818.4ms 1.637s 3.274s

single step mode

0 0 0 0

table 3-5
mode

multi-code step mode
S3
1 1 1

S2
0 0 0 1 1 1 1

S1
0 1 1 0 0 1 1

S0
1 0 1 0 1 0 1

single step transition time
50?s 100?s 200?s 400?s 800?s 1600?s 3200?s

full scale transition time (22 steps)a
1.1ms 2.2ms 4.4ms 8.8ms 17.6ms 35.2ms 70.4ms

single step mode

1 1 1 1

a.

a full scale transition includes fourteen 64-code steps, seven 16-code steps and one directly jump step.

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

figure 3-4
1.00E-01 9.50E-02 9.00E-02 8.50E-02 8.00E-02 7.50E-02 7.00E-02 6.50E-02 6.00E-02 5.50E-02 5.00E-02

1/4 to 3/4 scale settling time (directly jump mode, VDD = 3.0V)

output current (mA)

1.25E-03

1.27E-03

1.29E-03

1.31E-03

1.33E-03

1.35E-03

1/4 to 3/4 scale settling time (VDD = 3.0V)

5640_DS_3_4

figure 3-5
100 90 80 70
IOUT (mA)

sink current vs. code (VDD = 3.0V, reg 0x30A5 = 0x05, VCM resistance = 23ohms)

60 50 40 30 20 10 0
1024 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 0

CODE

5640_DS_3_5

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

1.37E-03

4-1

4 image sensor core digital functions
4.1 mirror and flip
The OV5640 provides Mirror and Flip readout modes, which respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1). In flip, the OV5640 does not need additional settings because the ISP block will auto-detect whether the pixel is in the red line or blue line and make the necessary adjustments.

figure 4-1

mirror and flip samples

F
original image

F
mirrored image

flipped image

mirrored and flipped image
5640_DS_4_1

table 4-1
address
0x3820

mirror and flip registers
register name
TIMING TC REG20

default value
0x40

R/W
RW

description
Timing control Bit[2]: ISP vflip Bit[1]: Sensor vflip Timing Control Bit[2]: ISP mirror Bit[1]: Sensor mirror

0x3821

TIMING TC REG21

0x00

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

F

F

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

4.2 image windowing
The OV5640 uses registers 0x3800 ~ 0x3814 for image windowing. figure 4-2 illustrates how the registers define the windowing size. Physical pixel size is the total pixel array size we have in the sensor. The ISP input size is the total pixel data read from pixel array. Typically, the larger ISP input size is, the less maximum frame rate can be reached. The data output size is the image output size of OV5640. This size is windowed from ISP input size and is defined by x_offset and y_offset as figure 4-2 shows.

figure 4-2

image windowing
(0, 0) Y_ADDR_ST {0x3802, 0x3803}
X_ADDR_ST {0x3800, 0x3801}

Y_OFFSET {0x3812, 0x3813}
X_OFFSET {0x3810, 0x3811}

data output size X_OUTPUT_SIZE {0x3808, 0x3809} X_ADDR_END {0x3804, 0x3805}

ISP input size

physical pixel size (X_ADDR_MAX, Y_ADDR_MAX)
5640_DS_4_2

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

Y_ADDR_END {0x3806, 0x3807}

Y_OUTPUT_SIZE {0x380A 0x380B}

version 2.03

4-3

figure 4-3 shows the windowing configuration when scaling function is enabled. The pre-scaling image size is the ISP input size subtracted by two times of offsets for both horizontal and vertical.

figure 4-3
(0, 0)

image windowing configuration

Y_ADDR_ST {0x3802, 0x3803}
X_ADDR_ST {0x3800, 0x3801}

Y_OFFSET {0x3812, 0x3813}
X_OFFSET {0x3810, 0x3811} X_OFFSET {0x3810, 0x3811}

data output size (after scaling) X_OUTPUT_SIZE {0x3808, 0x3809}

pre-scaling size Y_OFFSET {0x3812, 0x3813} X_ADDR_END {0x3804, 0x3805} ISP input size

physical pixel size
5640_DS_4_3

(X_ADDR_MAX, Y_ADDR_MAX)

table 4-2
address
0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808

image windowing registers (sheet 1 of 2)
register name
TIMING HS TIMING HS TIMING VS TIMING VS TIMING HW TIMING HW TIMING VH TIMING VH TIMING DVPHO

default value
0x00 0x00 0x00 0x00 0x0A 0x3F 0x07 0x9F 0x0A

R/W
RW RW RW RW RW RW RW RW RW

description
Bit[3:0]: X address start high byte[11:8] high byte Bit[7:0]: X address start low byte[7:0] low byte Bit[2:0]: Y address start high byte[10:8] high byte Bit[7:0]: Y address start low byte[7:0] low byte Bit[3:0]: X address end high byte[11:8] high byte Bit[7:0]: X address end low byte[7:0] low byte Bit[2:0]: Y address end high byte[10:8] high byte Bit[7:0]: Y address end low byte[7:0] low byte Bit[3:0]: DVP output horizontal width[11:8] high byte

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Y_OUTPUT_SIZE {0x380A, 0x380B}

Y_ADDR_END {0x3806, 0x3807}

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 4-2
address
0x3809 0x380A 0x380B 0x380C 0x380D 0x380E 0x380F 0x3810 0x3811 0x3812 0x3813

image windowing registers (sheet 2 of 2)
register name
TIMING DVPHO TIMING DVPVO TIMING DVPVO TIMING HTS TIMING HTS TIMING VTS TIMING VTS TIMING HOFFSET TIMING_HOFFSET TIMING VOFFSET TIMING VOFFSET

default value
0x20 0x07 0x98 0x0B 0x1C 0x07 0xB0 0x00 0x10 0x00 0x04

R/W
RW RW RW RW RW RW RW RW RW RW RW

description
Bit[7:0]: DVP output horizontal width[7:0] low byte Bit[2:0]: DVP output vertical height[10:8] high byte Bit[7:0]: DVP output vertical height[7:0] low byte Bit[3:0]: Total horizontal size[11:8] high byte Bit[7:0]: Total horizontal size[7:0] low byte Bit[7:0]: Total vertical size[15:8] high byte Bit[7:0]: Total vertical size[7:0] low byte Bit[3:0]: ISP horizontal offset[11:8] high byte Bit[7:0]: ISP horizontal offset[7:0] low byte Bit[2:0]: ISP vertical offset[10:8] high byte Bit[7:0]: ISP vertical offset[7:0] low byte

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4.3 test pattern
For testing purposes, the OV5640 offers one type of test pattern, color bar.

figure 4-4

test pattern

color bar

table 4-3
address

test pattern selection control
register name default value R/W description
Bit[7]: Color bar enable 0: Test disable 1: Color bar enable Bit[3:2]: Color bar style 00: Standard eight color bar 01: Gradual change at vertical mode 1 10: Gradual change at horizontal 11: Gradual change at vertical mode 2

0x503D

PRE ISP TEST SETTING 1

0x00

RW

4.4 50/60Hz detection
4.4.1 overview
When the integration time is not an integer multiple of the period of light intensity, the image will flicker. The function of the detector is to detect whether the sensor is under a 50 Hz or 60 Hz light source so that the basic step of integration time can be determined. Contact your local OmniVision FAE for auto detection settings.

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

4.5 AEC/AGC algorithms
4.5.1 overview
The Auto Exposure Control (AEC) and Auto Gain Control (AGC) allows the image sensor to adjust the image brightness to a desired range by setting the proper exposure time and gain applied to the image. Besides automatic control, exposure time and gain can be set manually from external control. The related registers are listed in table 4-4.

table 4-4
address
0x3500 0x3501

AEC/AGC control functions
register name
AEC PK EXPOSURE AEC PK EXPOSURE

default value
0x00 0x02

R/W
RW RW

description
Exposure Output Bit[3:0]: Exposure [19:16] Exposure Output Bit[7:0]: Exposure [15:8] Exposure Output Bit[7:0]: Exposure [7:0] Lower four bits are a fraction of a line; they should be 0 since OV5640 does not support fraction line exposure AEC Manual Mode Control Bit[1]: AGC manual 0: Auto enable 1: Manual enable Bit[0]: AEC manual 0: Auto enable 1: Manual enable Real Gain Bit[1:0]: Real gain[9:8] Real Gain Bit[7:0]: Real gain[7:0] AEC VTS Output Bit[7:0]: VTS[15:8] high bits AEC VTS Output Bit[7:0]: VTS[7:0] low bits

0x3502

AEC PK EXPOSURE

0x00

RW

0x3503

AEC PK MANUAL

0x00

RW

0x350A 0x350B 0x350C 0x350D

AEC PK REAL GAIN AEC PK REAL GAIN AEC PK VTS AEC PK VTS

0x00 0x10 0x00 0x00

RW RW RW RW

4.5.2 average-based algorithm
The average-based AEC controls image luminance using registers (0x3A0F), (0x3A10), (0x3A1B), and (0x3A1E). In average-based mode, the value of register (0x3A0F) indicates the high threshold value, and the value of register (0x3A10) indicates the low threshold value. The value of register (0x3A1B) indicates the high threshold value for image change from stable state to unstable state and the value of register (0x3A1E) indicates the low threshold value for image change from stable state to unstable state. When the target image luminance average value AVG READOUT (0x56A1)

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is within the range specified by registers (0x3A1B) and (0x3A1E), the AEC keeps the image exposure and gain. When register AVG READOUT (0x56A1) is greater than the value in register (0x3A1B), the AEC will decrease the image exposure and gain until it falls into the range of {0x3A10, 0x3A0F}. When register AVG READOUT (0x56A1) is less than the value in register (0x3A1E), the AEC will increase the image exposure and gain until it falls into the range of {0x3A10, 0x3A0F}. Accordingly, the value in register (0x3A0F) should be greater than the value in register (0x3A10). The gap between the values of registers (0x3A1B) and (0x3A1E) controls the image stability. The AEC function supports both manual and auto speed selections in order to bring the image exposure into the range set by the values in registers (0x3A0F) and (0x3A10). For manual mode, the speed supports both normal and fast speed selection. AEC set to normal mode will allow for the slowest step increment or decrement in the image exposure to maintain the specified range. AEC set to fast mode will provide for an approximate ten-step increment or decrement in the image exposure to maintain the specified range. For auto mode, the speed step will automatically be adjusted according to the difference between the target and present values. The auto ratio of steps can be set by register bits AVG READOUT (0x56A1); thus, the AEC speed can be adjusted automatically by the image average value or controlled manually. Register (0x3A11) and register (0x3A1F) controls the fast AEC range in manual speed selection made. If the target image AVG READOUT (0x56A1) is greater than (0x3A11), AEC will decrease by half. If register AVG READOUT (0x56A1) is less than (0x3A1F), AEC will double. As shown in desired convergence, the AEC/AGC convergence uses two regions, the inner stable operating region and the outer control zone, which defines the convergence step size of fast and slow conditions.

figure 4-5

desired convergence

desired convergence

control zone

stable operating region

5640_DS_4_4

As for auto mode, the AEC will automatically calculate the steps needed based on the difference between target and current values. So, the outer control zone is meaningless for this mode.

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table 4-5
address
0x3A0F 0x3A10 0x3A11 0x3A1B 0x3A1E 0x3A1F

AEC/AGC control functions
register name
AEC CTRL0F AEC CTRL10 AEC CTRL11 AEC CTRL1B AEC CTRL1E AEC CTRL1F

default value
0x78 0x68 0xD0 0x78 0x68 0x40

R/W
RW RW RW RW RW RW

description
Stable Range High Limit (enter) Bit[7:0]: WPT Stable Range Low Limit (enter) Bit[7:0]: BPT Step Manual Mode, Fast Zone High Limit Bit[7:0]: vpt_high Stable Range High Limit (go out) Bit[7:0]: WPT2 Stable Range Low Limit (go out) Bit[7:0]: BPT2 Step Manual Mode, Fast Zone Low Limit Bit[7:0]: vpt_low

For the average-based AEC/AGC algorithm, the measured window is horizontally and vertically adjustable and divided by sixteen (4x4) zones (see figure 4-6). Each zone (or block) is 1/16th of the image and has a 4-bit weight in calculating the average luminance (YAVG). The 4-bit weight could be n/16 where n is from 0 to 15. The final YAVG is the weighted average of the sixteen zones. 4.5.2.1 average luminance (YAVG) Auto exposure time calculation is based on a frame brightness average value. By properly setting x_start, x_end, y_start, and y_end as shown in figure 4-6, a 4x4 grid average window is defined. It will automatically divide each zone into 4x4 zones. The average value is the weighted average of the 16 sections. table 4-6 lists the corresponding registers.

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figure 4-6

average-based window definition
sensor array size X start HW Y X

1 5 VH sensor array size Y 9 13

2 6 10 14

3 7 11 15

4 8 12 16 average window size

end

5640_DS_4_6

table 4-6
address
0x3810 0x3811 0x3812 0x3813 0x3808 0x3809 0x380A 0x380B 0x501D

timing control functions (sheet 1 of 2)
register name
TIMING HOFFSET TIMING_HOFFSET TIMING VOFFSET TIMING VOFFSET TIMING DVPHO TIMING DVPHO TIMING DVPVO TIMING DVPVO ISP MISC

default value
0x00 0x04 0x11 0x11 0x07 0x98 0x0B 0x1C 0x00

R/W
RW RW RW RW RW RW RW RW RW

description
Bit[3:0]: ISP horizontal offset[11:8] high byte Bit[7:0]: ISP Horizontal offset[7:0] low byte Bit[3:0]: ISP vertical offset[11:8] high byte Bit[7:0]: ISP vertical offset[7:0] low byte Bit[3:0]: DVP output horizontal width[11:8] high byte Bit[7:0]: DVP output horizontal width[7:0] low byte Bit[3:0]: DVP output vertical height[11:8] high byte Bit[7:0]: DVP output vertical height[7:0] low byte Bit[4]: Average size manual enable

0x5680

X START

0x00

RW

Bit[3:0]: x start[11:8] Horizontal start position for average window high byte, valid when 0x501D[4]=1 Bit[7:0]: x start[7:0] Horizontal start position for average window low byte, valid when 0x501D[4]=1

0x5681

X START

0x00

RW

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table 4-6
address

timing control functions (sheet 2 of 2)
register name default value R/W description
Bit[2:0]: y start[10:8] Vertical start position for average window low byte, valid when 0x501D[4]=1 Bit[7:0]: y start[7:0] Vertical start position for average window low byte, valid when 0x501D[4]=1 Bit[3:0]: Window X [11:8] Horizontal end position for average window high byte, valid when 0x501D[4]=1 Bit[7:0]: Window X [7:0] Horizontal end position for average window low byte, valid when 0x501D[4]=1. Bit[2:0]: Window Y [10:8] Vertical end position for average window high byte, valid when 0x501D[4]=1 Bit[7:0]: Window Y [7:0] Vertical end position for average window low byte, valid when 0x501D[4]=1 Bit[7:4]: Window 01 weight Bit[3:0]: Window 00 weight Bit[7:4]: Window 03 weight Bit[3:0]: Window 02 weight Bit[7:4]: Window 11 weight Bit[3:0]: Window 10 weight Bit[7:4]: Window 13 weight Bit[3:0]: Window 12 weight Bit[7:4]: Window 21 weight Bit[3:0]: Window 20 weight Bit[7:4]: Window 23 weight Bit[3:0]: Window 22 weight Bit[7:4]: Window 31 weight Bit[3:0]: Window 30 weight Bit[7:4]: Window 33 weight Bit[3:0]: Window 32 weight

0x5682

Y START

0x00

RW

0x5683

Y START

0x00

RW

0x5684

X WINDOW

0x10

RW

0x5685

X WINDOW

0xA0

RW

0x5686

Y WINDOW

0x0C

RW

0x5687

Y WINDOW

0x78

RW

0x5688 0x5689 0x568A 0x568B 0x568C 0x568D 0x568E 0x568F

WEIGHT00 WEIGHT01 WEIGHT02 WEIGHT03 WEIGHT04 WEIGHT05 WEIGHT06 WEIGHT07

0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11

RW RW RW RW RW RW RW RW

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4.6 AEC/AGC steps
The AEC and AGC work together to obtain adequate exposure/gain based on the current environmental illumination. In order to achieve the best SNR, extending the exposure time is always preferred rather than raising the gain when the current illumination is getting brighter. Vice versa, under dark conditions, the action to decrease the gain is always taken prior to shortening the exposure time.

4.6.1 auto exposure control (AEC)
The function of the AEC is to calculate the integration time of the next frame and send the information to the timing control block. Based on the statistics of previous frames, the AEC is able to determine whether the integration time should increase, decrease, fast increase, fast decrease, or remain the same. To avoid image flickering under a periodic light source, the integration time can be adjusted in steps of integer multiples of the period of the light source. This new AEC step system is called the banding filter, suggesting that the exposure time is not continuous but falls in some steps. 4.6.1.1 banding mode ON with AEC In Banding ON mode, the exposure time will fall in steps of integer multiples of the period of light intensity. This design is to reject image flickering when the light source is not steady but periodical. For a given light flickering frequency, the band step can be expressed in units of row period. Band Step = 'period of light intensity' × 'frame rate' × 'rows per frame'. The band steps for 50Hz and 60Hz light sources can be set in registers {0x3A08[1:0], 0x3A09[7:0]} and {0x3A0A[1:0], 0x3A0B[7:0]}, respectively. When auto-banding is ON, if the next integration time is less than the minimum band step, banding will automatically turn OFF. It will turn ON again when the next integration time becomes larger than the minimum band. If auto banding is disabled, the minimum integration time is one band step. Auto banding can be set in register bit 0x3A00[5]. 4.6.1.2 banding mode OFF with AEC When banding mode is OFF, integration time increases/decreases as normal. It is not necessarily multiples of band steps. 4.6.1.3 night mode The OV5640 supports long integration time such as 1 frame, 2 frames, 3 frames, 4 frames, 5 frames, 6 frames, 7 frames, and 8 frames in dark conditions.This is achieved by slowing down the original frame rate and waiting for exposure. Night mode ceiling can be set in register bits {0x3A02[7:0], 0x3A03[7:0], 0x3A14[7:0], 0x3A15[7:0]}. Night mode can be disabled by setting register bit 0x3A00[2] to 0. Also, when in night mode, the increase and decrease step can be based on band or frames, depending on register 0x3A05[6]. The minimum increase/decrease step can be one band. The step can be based both on bands and frames.

4.6.2 manual exposure control
To manually change exposure value, you must first set both 0x3503[0], where 0x3503[0] enables manual exposure control. In auto exposure mode, the extra exposure values (larger than 1 frame) in registers 0x350C/0x350D automatically change. In manual exposure mode, these registers will not automatically change. The manually set

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exposure in registers 0x3500~0x3502 must be less than the maximum exposure value in {0x380E, 0x380F} + {0x350C,0x350D}. The exposure value in registers 0x3500~0x3502 is in units of line*16 - the low 4 bits (0x3502[3:0]) is the fraction of line, the maximum value in {0x380E + 0x380F} + {0x350C, 0x350D} is in unit of line. If the manually set exposure value is less than one pre-defined frame period (e.g., 1/15 second in 15fps), there is no need to change 0x380E/0x380F. If the exposure value needs to be set beyond the pre-defined frame period; in other words, if the frame period needs to be extended to extend exposure time, then the maximum frame value in 0x380E/0x380F needs to be set first, then the exposure can be set in registers 0x3500~0x3502 accordingly.

4.6.3 auto gain control (AGC)
Unlike prolonging integration time, increasing gain will amplify both signal and noise. Thus, AGC usually starts after AEC is full. However, in cases where adjacent AEC step changes are too large (>1/16), AGC steps should be inserted in between; otherwise, the integration time will keep switching between two adjacent steps and the image flickers. 4.6.3.1 integration time between 1~16 rows When integration time is less than 16 rows, the changes between adjacent AEC steps are larger than 1/16, which may possibly make the image oscillate between two AEC levels; thus, some AGC steps are added in between. 4.6.3.2 gain insertion between AEC banding steps When banding mode is ON, the integration time changes in step of the period of light intensity. For the first 16 band steps, since the exposure time change between adjacent steps is larger than 1/16, AGC steps are inserted to ensure image stability. 4.6.3.3 gain insertion between night mode steps Between night mode steps (e.g., integration time = 1 frame and 2 frames), AGC steps are inserted to ensure no adjacent step change is larger than 1/16. 4.6.3.4 when AEC reaches maximum When AEC reaches its maximum step while the image is still too dark, the gain starts to increase until the new frame average falls into the stable range or AGC reaches its maximum step. The AGC ceiling can be set in {0x3A18[9:8], 0x3A19[7:0]}.

4.6.4 manual gain control
To manually change gain, first set register bit 0x3503[1] to enable manual control, then change the values in 0x350A/0x350B for the manual gain. The OV5640 has a maximum of 64x gain.

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4.7 black level calibration (BLC)
The pixel array contains several optically shielded (black) lines. These lines are used as reference for black level calibration. There are three main functions of the BLC: ? ? ? Combining two ADC data paths into one data path Adjusting all normal pixel values based on the values of the black levels Applying multiplication to all pixel values based on digital gain

Black level adjustments can be made with registers 0x4000 through 0x4013.

table 4-7
address
0x4000

BLC control functions
register name
BLC CTRL00

default value
0x89

R/W
RW

description
BLC Control 00 Bit[0]: BLC enable Bit[7]: Format change enable BLC update when format changes

0x4002

BLC CTRL02

0x45

RW Bit[7]:

0x4003

BLC CTRL03

0x08

RW

BLC redo enable Write 1 into it will trigger a BLC redo N frames begin, N is 0x4003[5:0] Bit[6]: BLC freeze Bit[5:0]: Manual frame number Bit[1]: BLC always update 0: Normal freeze 1: BLC always update;

0x4005

BLC CTRL05

0x18

RW

0x4009

BLACK LEVEL

0x10

RW

Bit[7:0]: BLC black level target at 10-bit range

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4.8 light frequency selection
The OV5640 can detect the light flickering frequency. When this function is enabled, the sensor can detect the light frequency and select the corresponding banding filter value. To remove banding, the banding filter should be turned on and the banding filter value should be set to the appropriate value.

table 4-8
address
0x3C01

light frequency registers
register name
5060HZ_CTRL1

default value
0x00

R/W
RW

description
Bit[7]: Band manual enable 0: Auto 1: Manual Band value manual setting 0: 60 Hz light 1: 50 Hz light Band50/60 0: 60 Hz light 1: 50 Hz light

Bit[2]: 0x3C00 5060HZ_CTRL2 0x00 RW Bit[0]: 0x3C0C 5060HZ_CTRLC – R

4.9 digital gain
The OV5640 supports 1/2/4 digital gain. Normally, the gain is controlled automatically by the automatic gain control (AGC) block.

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4.10 strobe flash and frame exposure
4.10.1 strobe flash control
The strobe signal is programmable. It supports both LED and Xenon modes. The polarity of the pulse can be changed. The strobe signal is enabled (turned high/low depending on the pulse’s polarity) by requesting the signal via the SCCB interface. Flash modules are triggered by the rising edge by default or by the falling edge if the signal polarity is changed. It supports the following flashlight modes (see table 4-9).

table 4-9
mode
xenon LED 1 LED 2 LED 3

flashlight modes
output
one-pulse pulse pulse continuous

AEC / AGC
no no no yes

AWB
no no yes yes

4.10.1.1 xenon flash control After a strobe request is submitted, the strobe pulse will be activated at the beginning of the third frame (see figure 4-7). The third frame will be correctly exposed. The pulse width can be changed in Xenon mode between 1H and 4H, depending on register 0x3B00[3:2], where H is one row period.

figure 4-7

xenon flash mode
vertical blanking

exposure time

data out

strobe request

strobe pulse correctly exposed frame

request here strobe pulse

zoomed

1H

5640_DS_4_7

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4.10.1.2 LED 1 & 2 mode Two frames after the strobe request is submitted, the third frame is correctly exposed. The strobe pulse will be activated only one time if the strobe end request is set correctly (see figure 4-8). If end request is not sent, the strobe signal is activated intermittently until the strobe end request is set (see figure 4-9). The number of skipped frames is programmable using registers {0x3A1C, 0x3A1D}.

figure 4-8

LED 1 & 2 mode - one pulse output
frame in vertical blanking is skipped

exposure time

data out

strobe request start strobe pulse correctly exposed frame request here the number of skipped frames is programmable
5640_DS_4_8

end

figure 4-9

LED 1 & 2 mode - multiple pulse output
frame in vertical blanking is skipped

exposure time

data out

strobe request start strobe pulse correctly exposed frame request here the number of skipped frames is programmable

5640_DS_4_9

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4.10.1.3 LED 3 mode In LED 3 mode, the strobe signal stays active until the strobe end request is sent (see figure 4-10).

figure 4-10

LED 3 mode
vertical blanking

exposure time

data out

strobe request start strobe signal correctly exposed frame request here request here end

5640_DS_4_10

4.10.2 frame exposure (FREX) mode
In FREX mode, whole frame pixels start integration at the same time, rather than integrating row by row. After the user-defined exposure time (registers {0x3B04, 0x3B05}), the shutter closes, preventing further integration and the image begins to read out. After the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next FREX request. The OV5640 supports two modes of FREX (see figure 4-11): ? ? mode 1 - frame exposure and shutter control requests come from the external system via the FREX pin. The sensor will send a strobe output signal to control the flash light. mode 2 - frame exposure request comes from the external system via the I2C register 0x3B08[0]. The sensor will output two signals, shutter control signal through the FREX pin and strobe signal through the STROBE pin.

figure 4-11

FREX modes
mode 1 FREX sensor STROBE

mode 2 FREX I2C sensor STROBE
560DS_4_11

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In mode 1, the FREX pin is configured as an input while it is configured as an output in mode 2. In both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe function. When in rolling shutter mode, the strobe function and this FREX/shutter control function do not work at the same time.

4.10.3 FREX strobe flash control
See table 4-10 for FREX strobe control functions.

table 4-10
address

FREX strobe control functions (sheet 1 of 2)
register name default value R/W description
Strobe Control Bit[7]: Strobe request ON/OFF 0: OFF/BLC 1: ON Bit[6]: Strobe pulse reverse Bit[3:2]: width_in_xenon Bit[1:0]: Strobe mode 00: Xenon 01: LED 1 10: LED 2 11: LED 3 Bit[7:0]: FREX exposure time[23:16] Bit[4:0]: Shutter delay time[12:8] Bit[7:0]: Shutter delay time[7:0] Unit: 64x sclk cycle Bit[7:0]: FREX exposure time [15:8] Bit[7:0]: FREX exposure time [7:0] Unit: Tline Bit[7:4]: FREX frame delay Bit[3:0]: Strobe width[3:0] Bit[1:0]: FREX mode selection 00: FREX strobe mode0 01: FREX strobe mode1 1x: Rolling strobe FREX Request FREX HREF Delay

0x3B00

STROBE CTRL

0x00

RW

0x3B01 0x3B02 0x3B03 0x3B04 0x3B05 0x3B06

FREX EXPOSURE 02 FREX SHUTTER DELAY 01 FREX SHUTTER DELAY 00 FREX EXPOSURE 01 FREX EXPOSURE 00 FREX CTRL 07

0x00 0x08 0x00 0x04 0x00 0x04

RW RW RW RW RW RW

0x3B07

FREX MODE

0x08

RW

0x3B08 0x3B09

FREX REQUEST FREX HREF DELAY

0x00 0x02

RW RW

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table 4-10
address

FREX strobe control functions (sheet 2 of 2)
register name default value R/W description
Bit[2:0]: FREX precharge length 000: 1/16 Tline 001: 1/8 Tline 010: 1/4 Tline 011: 1/2 Tline 100: 1 Tline 101: 2 Tline 110: 4 Tline 111: 8 Tline Bit[7:0]: Strobe width[19:12] Bit[7:0]: Strobe width[11:4]

0x3B0A

FREX RST LENGTH

0x04

RW

0x3B0B 0x3B0C

STROBE WIDTH STROBE WIDTH

0x00 0x3D

RW RW

4.11 one time programmable (OTP) memory
The OV5640 supports a maximum of 256 bits of one-time programmable (OTP) memory to store chip identification and manufacturing information.

table 4-11
address

OTP control functions
register name default value R/W description
Bit[7]: Bit[1]: 0x00 RW Bit[0]: Bit[7]: Bit[1]: 0x00 RW Bit[0]: OTP program busy OTP program speed 0: Fast 1: Slow OTP program enable OTP read busy OTP read speed 0: Fast 1: Slow OTP read enable

0x3D20

OTP PROGRAM CTRLa

0x3D21

OTP READ CTRLa

0x3D00 0x3D01 0x3D02 0x3D03 0x3D04 0x3D05 0x3D06

OTP DATA00b OTP OTP DATA01b DATA02b

0x00 0x00 0x00 0x00 0x00 0x00 0x00

RW RW RW RW RW RW RW

OTP Dump/Load Data00 OTP Dump/Load Data01 OTP Dump/Load Data02 OTP Dump/Load Data03 OTP Dump/Load Data04 OTP Dump/Load Data05 OTP Dump/Load Data06

OTP DATA03b OTP DATA04b OTP DATA05 OTP DATA06

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PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 4-11
address
0x3D07 0x3D08 0x3D09 0x3D0A 0x3D0B 0x3D0C 0x3D0D 0x3D0E 0x3D0F 0x3D10 0x3D11 0x3D12 0x3D13 0x3D14 0x3D15 0x3D16 0x3D17 0x3D18 0x3D19 0x3D1A 0x3D1B 0x3D1C 0x3D1F 0x3D1E 0x3D1F a. b.

OTP control functions
register name
OTP DATA07 OTP DATA08 OTP DATA09 OTP DATA0A OTP DATA0B OTP DATA0C OTP DATA0D OTP DATA0E OTP DATA0F OTP DATA10 OTP DATA11 OTP DATA12 OTP DATA13 OTP DATA14 OTP DATA15 OTP DATA16 OTP DATA17 OTP DATA18 OTP DATA19 OTP DATA1A OTP DATA1B OTP DATA1C OTP DATA1D OTP DATA1E OTP DATA1F

default value
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

R/W
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

description
OTP Dump/Load Data07 OTP Dump/Load Data08 OTP Dump/Load Data09 OTP Dump/Load Data0a OTP Dump/Load Data0b OTP Dump/Load Data0c OTP Dump/Load Data0d OTP Dump/Load Data0e OTP Dump/Load Data0f OTP Dump/Load Data10 OTP Dump/Load Data11 OTP Dump/Load Data12 OTP Dump/Load Data13 OTP Dump/Load Data14 OTP Dump/Load Data15 OTP Dump/Load Data16 OTP Dump/Load Data17 OTP Dump/Load Data18 OTP Dump/Load Data19 OTP Dump/Load Data1a OTP Dump/Load Data1b OTP Dump/Load Data1c OTP Dump/Load Data1d OTP Dump/Load Data1e OTP Dump/Load Data1f

AVDD must be 2.1V ± 5% when writing/programming OTP, otherwise there will be reliability issues. There is no such limitation when reading OTP under normal operating conditions. 0x3D00~0x3D04 are reserved for omnivision internal use only

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

5-1

5 image sensor processor digital functions
5.1 ISP general controls
The ISP module provides lens correction, gamma, de-noise, sharpen, auto focus, etc. These functions are enabled by registers 0x5000 ~ 0x5005.

table 5-1
address

ISP general control registers (sheet 1 of 3)
register name default value R/W description
ISP Control 00 Bit[7]: LENC correction enable 0: Disable 1: Enable Bit[5]: RAW gamma enable 0: Disable 1: Enable Bit[2]: Black pixel cancellation enable 0: Disable 1: Enable Bit[1]: White pixel cancellation enable 0: Disable 1: Enable Bit[0]: Color interpolation (CIP) enable 0: Disable 1: Enable ISP Control 01 Bit[7]: Special Digital Effects (SDE) enable 0: Disable 1: Enable Bit[5]: Scaling enable 0: Disable 1: Enable Bit[2]: UV average enable 0: Disable 1: Enable Bit[1]: Color matrix enable 0: Disable 1: Enable Bit[0]: Auto white balance (AWB) enable 0: Disable 1: Enable

0x5000

ISP CONTROL 00

0x06

RW

0x5001

ISP CONTROL 01

0x01

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 5-1
address

ISP general control registers (sheet 2 of 3)
register name default value R/W description
ISP Control 03 Bit[2]: Bin enable 0: Disable 1: Enable Bit[1]: Draw window for AFC enable 0: Disable 1: Enable Bit[0]: Solarize enable 0: Disable 1: Enable ISP Control 05 Bit[6]: AWB bias manual enable 0: Disable 1: Enable Bit[5]: AWB bias on enable 0: Disable 1: Enable Bit[4]: AWB bias plus enable 0: Disable 1: Enable Bit[2]: LENC bias on enable 0: Disable 1: Enable Bit[1]: GMA bias on enable 0: Disable 1: Enable Bit[0]: LENC bias manual enable 0: Disable 1: Enable Bit[6]: Scale ratio manual enable

0x5003

ISP CONTROL 03

0x08

RW

0x5005

ISP CONTROL 05

0x36

RW

0x501E

ISP MISC

0x00

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

5-3

table 5-1
address

ISP general control registers (sheet 3 of 3)
register name default value R/W description
RGB Dither Control Bit[6]: Dither register control selection enable 0: From register control 1: From system control Bit[5:4]: R channel register control when 0x501E[6] = 0 00: Not allowed 01: RGB444 10: RGB565/555 11: Not allowed Bit[3:2]: G channel register control when 0x501E[6] = 0 00: Not allowed 01: RGB444 10: RGB565/555 11: Not allowed Bit[1:0]: B channel register control when 0x501E[6] = 0 00: Not allowed 01: RGB444 10: RGB565/555 11: Not allowed

0x5020

DITHER CTRL 0

0x00

RW

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proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

5.2 lens correction (LENC)
The main purpose of the LENC is to compensate for lens imperfection. According to the area where each pixel is located, the module calculates a gain for the pixel, correcting each pixel with its gain calculated to compensate for the light distribution due to lens curvature. The LENC correcting curve automatic calculation according sensor gain is also added so that the LENC can adapt with the sensor gain. Also, the LENC supports the subsample function in both horizontal and vertical directions. Contact your local OmniVision FAE for lens correction settings (registers 0x5800~0x5849).

table 5-2
address
0x5000 0x583E 0x583F 0x5840

LENC control registers (sheet 1 of 2)
register name
ISP CONTROL 00 MAX GAIN MIN GAIN MIN Q

default value
0x06 0x40 0x20 0x18

R/W
RW R/W R/W R/W

description
Bit[7]: LENC correction enable 0: Disable 1: Enable

Bit[7:0]: Maximum gain Bit[7:0]: Minimum gain Bit[6:0]: Minimum Q Bit[3]: Add BLC enable 0: Disable BLC add back function 1: Enable BLC add back function BLC enable 0: Disable BLC function 1: Enable BLC function Gain manual enable Auto Q enable 0: Used constant Q (0x40) 1: Used calculated Q

Bit[2]: 0x5841 LENC CTRL59 0x0D R/W Bit[1]: Bit[0]:

0x5842

BR HSCALE

0x01

RW

Bit[2:0]: br h scale[10:8] Reciprocal of horizontal step for BR channel. BR channel in whole image is divided into 5x5 blocks. The step is used to point to the border of the adjacent block Bit[7:0]: br h scale[7:0] Reciprocal of horizontal step for BR channel. BR channel in whole image is divided into 5x5 blocks. The step is used to point to the border of the adjacent block Bit[2:0]: br v scale[10:8] Reciprocal of vertical step for BR channel. BR channel in whole image is divided into 5x5 blocks. The step is used to point to the border of the adjacent block

0x5843

BR HSCAL

0x2B

RW

0x5844

BR VSCALE

0x01

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

5-5

table 5-2
address

LENC control registers (sheet 2 of 2)
register name default value R/W description
Bit[7:0]: br v scale[7:0] Reciprocal of vertical step for BR channel. BR channel in whole image is divided into 5x5 blocks. The step is used to point to the border of the adjacent block Bit[2:0]: g h scale[10:8] Reciprocal of horizontal step for G channel. G channel in whole image is divided into 6x6 blocks. The step is used to point to the border of the adjacent block Bit[7:0]: g h scale[7:0] Reciprocal of horizontal step for G channel. G channel in whole image is divided into 6x6 blocks. The step is used to point to the border of the adjacent block Bit[2:0]: g v scale[10:8] Reciprocal of vertical step for G channel. G channel in whole image is divided into 6x6 blocks. The step is used to point to the border of the adjacent block Bit[7:0]: g v scale[7:0] Reciprocal of vertical step for G channel. G channel in whole image is divided into 6x6 blocks. The step is used to point to the border of the adjacent block

0x5845

BR VSCALE

0x8D

RW

0x5846

G HSCALE

0x01

RW

0x5847

G HSCAL

0x8F

RW

0x5848

G VSCALE

0x01

RW

0x5849

G VSCALE

0x09

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

5.3 auto white balance (AWB)
The main function of Auto White Balance (AWB) is the process of removing unrealistic color casts so that objects which appear white in person are rendered white in the image or video. Thus, the AWB makes sure that the white color is always a white color in different color temperatures. It supports manual white balance and auto white balance. For auto white balance, simple AWB and advanced AWB methods are supplied. Advance AWB takes into account the color temperature of a light source. For advanced AWB settings, contact your local OmniVision FAE.

table 5-3
address
0x5001

AWB control registers (sheet 1 of 2)
register name
ISP CONTROL 01

default value
0x01

R/W
RW

description
Bit[0]: Auto white balance enable 0: Disable 1: Enable Step local Step fast Slop 8x Slop 4x One zone AVG all

0x5181

AWB CONTROL 01

0x58

RW

Bit[7:6]: Bit[5:4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]:

0x5182

AWB CONTROL 02

0x11

RW

Bit[7:4]: Maximum local counter Bit[3:0]: Maximum fast counter Bit[7]: AWB simple enable 0: AWB advance 1: AWB simple Bit[6]: YUV enable 1: Simple YUV enable Bit[5]: AWB preset Bit[4]: AWB simf Bit[3:2]: AWB win Bit[7:6]: Bit[5]: Bit[4:2]: Bit[1:0]: Counter area selection G enable Counter limit control Counter threshold

0x5183

AWB CONTROL 03

0x90

RW

0x5184

AWB CONTROL 04

0x25

RW

0x5185

AWB CONTROL 05

0x24

RW

Bit[7:4]: Stable range unstable Threshold for unstable to stable change Bit[3:0]: Stable range stable Threshold for stable to un-stable change Advanced AWB Control Registers Bit[7:0]: AWB top limit Bit[7:0]: AWB bottom limit Bit[7:0]: Red limit

0x5186~ 0x5190 0x5191 0x5192 0x5193

AWB CONTROL AWB CONTROL 17 AWB CONTROL 18 AWB CONTROL 19

– 0xFF 0x00 0xF0

– RW RW RW

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version 2.03

5-7

table 5-3
address
0x5194 0x5195

AWB control registers (sheet 2 of 2)
register name
AWB CONTROL 20 AWB CONTROL 21

default value
0xF0 0xF0

R/W
RW RW

description
Bit[7:0]: Green limit Bit[7:0]: Blue limit Bit[5]: AWB freeze Bit[3:2]: AWB simple selection 00: AWB simple from after AWB gain 01: AWB simple from after RAW GMA 10: AWB simple from after AWB gain 11: AWB simple from after RAW GMA Bit[1]: Fast enable Bit[0]: AWB bias stat Bit[7:0]: Local limit Bit[3]: Bit[2]: Local limit select Simple stable select

0x5196

AWB CONTROL 22

0x03

RW

0x5197 0x519E 0x519F 0x51A0 0x51A1 0x51A2 0x51A3 0x51A4 0x51A5 0x51A6 0x51A7

AWB CONTROL 23 AWB CONTROL 30 AWB CURRENT R GAIN AWB CURRENT R GAIN AWB CURRENT G GAIN AWB CURRENT G GAIN AWB CURRENT B GAIN AWB CURRENT B GAIN AWB AVERAGE B AWB AVERAGE B AWB AVERAGE B

0x02 0x00 – – – – – – – – –

RW RW R R R R R R R R R

Bit[3:0]: Current R setting[11:8] Bit[7:0]: Current R setting[7:0] Bit[3:0]: Current G setting[11:8] Bit[7:0]: Current G setting[7:0] Bit[3:0]: Current B setting[11:8] Bit[7:0]: Current B setting[7:0] Bit[7:0]: Average r[9:2] Bit[7:0]: Average g[9:2] Bit[7:0]: Average b[9:2] Bit[5]: Bit[4]: Bit[3]: Bit[2:1]: R large G large B large Current type

0x51D0

AWB CONTROL74



R

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

5.4 raw gamma
The main purpose of the Gamma (GMA) function is to compensate for the non-linear characteristics of the sensor. GMA converts the pixel values according to the Gamma curve to compensate the sensor output under different light strengths. The non-linear gamma curve is approximately constructed with different linear functions. Raw gamma compensates the image in the RAW domain.

table 5-4
address
0x5000

raw gamma control registers
register name
ISP CONTROL 00

default value
0x06

R/W
RW

description
Bit[5]: Raw gamma enable 0: Disable GMA 1: Enable GMA Special digital effect enable 0: Disable 1: Enable

Bit[7]: 0x5001 0x5481 0x5482 0x5483 0x5484 0x5485 0x5486 0x5487 0x5488 0x5489 0x548A 0x548B 0x548C 0x548D 0x548E 0x548F 0x5490 ISP CONTROL 01 GAMMA YST00 GAMMA YST01 GAMMA YST02 GAMMA YST03 GAMMA YST04 GAMMA YST05 GAMMA YST06 GAMMA YST07 GAMMA YST08 GAMMA YST09 GAMMA YST0A GAMMA YST0B GAMMA YST0C GAMMA YST0D GAMMA YST0E GAMMA YST0F 0x01 0x26 0x35 0x48 0x57 0x63 0x6E 0x77 0x80 0x88 0x96 0xA3 0xAF 0xC5 0xD7 0xE8 0x0F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Bit[7:0]: Y yst 00 Bit[7:0]: Y yst 01 Bit[7:0]: Y yst 02 Bit[7:0]: Y yst 03 Bit[7:0]: Y yst 04 Bit[7:0]: Y yst 05 Bit[7:0]: Y yst 06 Bit[7:0]: Y yst 07 Bit[7:0]: Y yst 08 Bit[7:0]: Y yst 09 Bit[7:0]: Y yst 0A Bit[7:0]: Y yst 0B Bit[7:0]: Y yst 0C Bit[7:0]: Y yst 0D Bit[7:0]: Y yst 0E Bit[7:0]: Y yst 0F

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5-9

5.5 defect pixel cancellation (DPC)
Due to processes and other reasons, pixel defects in the sensor array will occur. Thus, these bad or wounded pixels will generate wrong color values. The main purpose of Defect Pixel Cancellation (DPC) function is to remove the effect caused by these bad or wounded pixels. Also, some special functions are available for those pixels located at the image boundary. To remove the defect pixel effect correctly, the proper threshold should first be determined.

table 5-5
address

DPC control registers
register name default value R/W description
Bit[2]: Black pixel cancellation enable 0: Disable 1: Enable White pixel cancellation enable 0: Disable 1: Enable

0x5000

ISP CONTROL 00

0x06

RW

Bit[1]:

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

5.6 color interpolation (CIP)
The CIP functions include de-noising of raw images, RAW to RGB interpolation, and edge enhancement. In sensor RAW format, each pixel will be either R, G or B. CIP will calculate the other two color values using the neighboring pixel of the same color. Thus, we can get the full RGB information for each pixel. For edge enhancement, the OV5640 provides both manual and auto modes.

table 5-6
address
0x5000

CIP control registers
register name
ISP CONTROL 00 CIP SHARPENMT THRESHOLD 2 CIP SHARPENMT OFFSET1 CIP SHARPENMT OFFSET2 CIP DNS THRESHOLD 1 CIP DNS THRESHOLD 2 CIP DNS OFFSET1 CIP DNS OFFSET2 CIP CTRL CIP SHARPENTH THRESHOLD 1 CIP SHARPENTH THRESHOLD 2 CIP SHARPENTH OFFSET1 CIP SHARPENTH OFFSET2 CIP EDGE MT AUTO CIP DNS THRESHOLD AUTO CIP SHARPEN THRESHOLD AUTO

default value
0x06

R/W
RW

description
Bit[0]: Color interpolation enable 0: Disable 1: Enable

0x5301

0x48

RW

Color Interpolation Sharpen MT Threshold 2 CIP Sharpen MT Offset1 (Y edge mt manual setting when 0x5308[6]=1) CIP Sharpen MT Offset2 CIP DNS Threshold 1 CIP DNS Threshold 2 CIP DNS Offset1 (DNS threshold manual setting when 0x5308[4]=1) CIP DNS Offset2 Bit[6]: CIP edge MT manual enable Bit[4]: CIP DNS manual enable Bit[2:0]: CIP threshold for BR sharpen CIP Sharpen TH Threshold 1 CIP Sharpen TH Threshold 2 CIP Sharpen TH Offset1 (Sharpen threshold manual setting when 0x5308[6]=1) CIP Sharpen TH Offset2 CIP Edge MT Auto Read CIP DNS Threshold Auto Read CIP Sharpen Threshold Auto Read

0x5302 0x5303 0x5304 0x5305 0x5306 0x5307 0x5308

0x18 0x0E 0x08 0x48 0x09 0x16 0x25

RW RW RW RW RW RW RW

0x5309 0x530A

0x08 0x48

RW RW

0x530B 0x530C 0x530D 0x530E 0x530F

0x04 0x06 – – –

RW RW R R R

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5-11

5.7 color matrix (CMX)
The main purpose of the Color Matrix (CMX) function is to cancel out crosstalk and convert color space. Given the color correction matrix, CCM, and RGB to YUV conversion matrix, RGB2YUV, the combined matrix is: CMX = cmx00 cmx10 cmx20 R G B cmx01 cmx11 cmx21 R0 G0 B0 cmx02 cmx12 cmx22 = RGB2YUV × CCM × 1 -0.25 0.75 1 -0.25 -0.25 1 0.75 -0.25

where

= CCM

The CMX is then normalized by 20x5394[3:0].

table 5-7
address
0x5001

CMX control registers (sheet 1 of 2)
register name
ISP CONTROL 01

default value
0x01

R/W
RW

description
Bit[1]: Color matrix enable 0: Disable 1: Enable CMX precision switch 0: 1.7 mode 1: 2.6 mode CMX1 for Y

Bit[1]: 0x5380 0x5381 0x5382 0x5383 0x5384 0x5385 0x5386 0x5387 0x5388 0x5389 0x538A CMX CTRL CMX1 CMX2 CMX3 CMX4 CMX5 CMX6 CMX7 CMX8 CMX9 CMXSIGN 0x00 0x20 0x64 0x08 0x30 0x90 0xC0 0xA0 0x98 0x08 0x01 RW RW RW RW RW RW RW RW RW RW RW Bit[1]:

Bit[7:0]: CMX2 for Y Bit[7:0]: CMX3 for Y Bit[7:0]: CMX4 for U Bit[7:0]: CMX5 for U Bit[7:0]: CMX6 for U Bit[7:0]: CMX7 for V Bit[7:0]: CMX8 for V Bit[7:0]: CMX9 for V Cmxsign Bit[0]: CMX9 sign

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 5-7
address

CMX control registers (sheet 2 of 2)
register name default value R/W description
Cmxsign Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: CMX8 sign CMX7 sign CMX6 sign CMX5 sign CMX4 sign CMX3 sign CMX2 sign CMX1 sign

0x538B

CMXSIGN

0x98

RW

5.8 UV average
The main function of the UV average is to average the U/V channel value using special filters.

table 5-8
address
0x5001

UV average register
register name
ISP CONTROL 01

default value
0x4F

R/W
RW

description
Bit[2]: UV average enable 0: Disable 1: Enable

5.9 scaling
The main purpose of the scaling function is to zoom out the image. According to the new width and new height of the new image, the module uses the values of several pixels to generate the values of one pixel. The values of some pixels are divided and used in two or more adjacent pixels. The scaling function supports up to 32x scale.

table 5-9
address
0x5001

UV average register (sheet 1 of 2)
register name
ISP CONTROL 01

default value
0x01

R/W
RW

description
Bit[5]: Scale enable 0: Disable 1: Enable

proprietary to OmniVision Technologies

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version 2.03

5-13

table 5-9
address

UV average register (sheet 2 of 2)
register name default value R/W description
Bit[6:4]: HDIV RW DCW scale times 000: DCW 1 time 001: DCW 2 time 010: DCW 4 time 100: DCW 8 time 101: DCW 16 time Others: DCW 16 time Bit[2:0]: VDIV RW DCW scale times 000: DCW 1 time 001: DCW 2 time 010: DCW 4 time 100: DCW 8 time 101: DCW 16 time Others: DCW 16 time XSC High Bits XSC Low Bits YSC High Bits YSC Low Bits Bit[3:0]: Voffset

0x5601

SCALE CTRL 1

0x00

RW

0x5602 0x5603 0x5604 0x5605 0x5606

SCALE CTRL 2 SCALE CTRL 3 SCALE CTRL 4 SCALE CTRL 5 SCALE CTRL 6

0x02 0x00 0x02 0x00 0x00

RW RW RW RW RW

5.10 UV adjust
The main function of the UV adjust is to adjust the U/V channel value according to sensor gain. It supports both manual and auto modes. The UV adjust function is integrated in SDE. The main function of the UV adjust is to adjust the U/V channel value according to sensor gain. It supports both manual and auto modes

5.10.1 manual mode
By setting SDE CTRL 0 [1] (0x5580) to 1 and SDE CTRL 8 0x5588[6] to 1, UV adjust is controlled only by register SAT U (0X5583[7:0] and SAT V (0x5584[7:0]] for U and V gains.

5.10.2 auto mode
When the UV adjust is set for auto mode(0x5580[1]=1 and 0x5588[6]=0), the UV adjust curve parameters (see figure 5-1) should be entered into the corresponding registers. The UV adjust parameters, UV adj th1, UV adj th2, and offset low, offset high should be entered into the registers to set the curve. To get these values, first set the values of UV adj th1, UV adj th2, offset low and offset high. Then, calculate the values of a and k as follows: k = (offset high - offset low) / (UV adj th2 - UV adj th1) a = offset high + (offset high - offset low)/(UV adj th2 - UV adj th1)

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

Registers to be changed: ? ? ? ? UV adj th1[8:0] = registers 0x5589[7:0] UV adj th2[8:0] = registers {0x558A[0], 0x558B[7:0]} offset high = register 0x5583[7:0] (when 0x5580[1]=1 and 0x5588[6]=0) offset low = register 0x5584[7:0] (when 0x5580[1]=1 and 0x5588[6]=0)

figure 5-1

UV adjust graph

offset_high

UV adjust in

y = a - kx

offset_low

UV adj th1 AGC gain

UV adj th2
5640_DS_5_1

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5-15

5.11 special digital effects (SDE)
The Special Digital Effects (SDE) functions include hue/saturation control, brightness, contrast, etc. SDE also supports negative, black/white, sepia, greenish, blueish, redish, solarize and other image effects.

table 5-10
address
0x5001 0x5581 0x5582

SDE control registers
register name
ISP CONTROL 01 SDE CTRL1 SDE CTRL2

default value
0x01 0x80 0x00

R/W
RW RW RW

description
Bit[7]: Special digital effect enable 0: Disable 1: Enable

Bit[7:0]: Hue cos coefficient Bit[7:0]: Hue sin coefficient Bit[7:0]: Saturation U when 0x5580[1]=1 and 0x5588[6]=1, max value for UV adjust when 0x5580[1]=1 and 0x5588[6]=0; or fixed U when 0x5580[3]=1 Bit[7:0]: Saturation V when 0x5580[1]=1 and 0x5588[6]=1, min value for UV adjust when 0x5580[1]=1 and 0x5588[6]=0; or Vreg when 0x5580[4]=1 Bit[7:0]: Yoffset for contrast when 0x5044[3]=1; or fixed Y when 0x5580[7]=1 Bit[7:0]: Y gain for contrast Bit[7:0]: Y bright for contrast Bit[6]: Bit[5]: Bit[4]: Bit[3]: UV adjust manual enable Sign5 for hue V, cos Sign4 for hue U, cos Sign3 Y bright sign for contrast 0: Keep Y bright sign 1: Negative Y bright sign Sign2 Y offset sign for contrast when 0x5044[3]=1 0: Keep Y offset sign 1: Negative Y offset sign Sign1 for hue V, sin Sign0 for hue U, sin

0x5583

SDE CTRL3

0x40

RW

0x5584

SDE CTRL4

0x40

RW

0x5585 0x5586 0x5587

SDE CTRL5 SDE CTRL6 SDE CTRL7

0x00 0x20 0x00

RW RW RW

0x5588

SDE CTRL8

0x01

RW

Bit[2]:

Bit[1]: Bit[0]: 0x5589 0x558A 0x558B 0x558C SDE CTRL9 SDE CTRL10 SDE CTRL11 SDE CTRL12 0x01 0x01 0xFF – RW RW RW R

Bit[7:0]: UV adjust threshold 1 Valid when 0x5580[1]=1 Bit[0]: UV adjust threshold 2[8] Valid when 0x5580[1]=1

Bit[7:0]: UV adjust threshold 2[7:0] Valid when 0x5580[1]=1 Bit[7:0]: UV adjust value read out

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

5.12 ISP format
table 5-11
address

ISP format control registers
register name default value R/W description
Format MUX Control Bit[2:0]: Format selection 000: ISP YUV422 001: ISP RGB 010: ISP dither 011: ISP RAW (DPC) 100: SNR RAW 101: ISP RAW (CIP)

0x501F

FORMAT MUX CONTROL

0x00

RW

5.13 draw window
The draw window module is used to display a window on top of live video. It is usually used by autofocus to display a focus window.

table 5-12
address
0x5003

draw window registers (sheet 1 of 2)
register name
ISP CONTROL 03

default value
0x08

R/W
RW

description
Bit[1]: Draw window for AFC enable 0: Disable 1: Enable

0x501F

FORMAT MUX CONTROL

0x00

RW

Bit[2:0]: Format select 000: ISP YUV422 001: ISP RGB 010: ISP dither 011: ISP RAW (DPC) 100: SNR RAW 101: ISP RAW (CIP) Bit[0]: Draw window control 0: No fixed Y 1: Fixed Y

0x5027

DRAW WINDOW CONTROL 00 DRAW WINDOW LEFT POSITION CONTROL DRAW WINDOW LEFT POSITION CONTROL DRAW WINDOW RIGHT POSITION CONTROL DRAW WINDOW RIGHT POSITION CONTROL

0x02

RW

0x5028 0x5029 0x502A 0x502B

0x04 0x90 0x05 0x90

RW RW RW RW

Bit[3:0]: Draw window left[11:8] high byte Bit[7:0]: Draw window left[7:0] low byte Bit[3:0]: Draw window right[11:8] high byte Bit[7:0]: Draw window right[7:0] low byte

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5-17

table 5-12
address
0x502C 0x502D 0x502E 0x502F

draw window registers (sheet 2 of 2)
register name
DRAW WINDOW TOP POSITION CONTROL DRAW WINDOW TOP POSITION CONTROL DRAW WINDOW BOTTOM POSITION CONTROL DRAW WINDOW BOTTOM POSITION CONTROL DRAW WINDOW HORIZONTAL BOUNDARY WIDTH CONTROL DRAW WINDOW HORIZONTAL BOUNDARY WIDTH CONTROL DRAW WINDOW VERTICAL BOUNDARY WIDTH CONTROL DRAW WINDOW VERTICAL BOUNDARY WIDTH CONTROL DRAW WINDOW Y CONTROL DRAW WINDOW U CONTROL DRAW WINDOW V CONTROL

default value
0x03 0x6C 0x04 0x2C

R/W
RW RW RW RW

description
Bit[2:0]: Draw window top[10:8] high byte Bit[7:0]: Draw window top[7:0] low byte Bit[2:0]: Draw window bottom[10:8] high byte Bit[7:0]: Draw window bottom[7:0] low byte Bit[3:0]: Draw window horizontal boundary width[11:8] high byte Bit[7:0]: Draw window horizontal boundary width[7:0] low byte Bit[2:0]: Draw window vertical boundary width[10:8] high byte Bit[7:0]: Draw window vertical boundary width[7:0] low byte Bit[7:0]: Fixed Y for draw window Bit[7:0]: Fixed U for draw window Bit[7:0]: Fixed V for draw window

0x5030

0x00

RW

0x5031

0x14

RW

0x5032

0x00

RW

0x5033

0x14

RW

0x5034 0x5035 0x5036

0x80 0x2A 0x14

RW RW RW

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6-1

6 image sensor output interface digital functions
6.1 compression engine
6.1.1 compression mode 1 timing
The whole frame has only one line. PCLK will be gated when there is no valid image data transmitted.

figure 6-1
HREF

compression mode 1 timing

PCLK
5640 DS 6 1

6.1.2 compression mode 2 timing
Compression data is transmitted with programmable line width. PCLK is free running. The last line may contain dummy data to match the width. By default, the line number varies from frame to frame. The user can set register 4600[5] (0x4600) to ensure every frame has a fixed line number (programmable).

figure 6-2
HREF

compression mode 2 timing

VSYNC
5640_DS_6_2

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6.1.3 compression mode 3 timing
Compression data is transmitted with programmable width. The last line width maybe different from the other line (there is no dummy data). In each frame, the line number may be different.

figure 6-3
HREF

compression mode 3 timing

VSYNC
5640_DS_6_3

6.1.4 compression mode 4 timing
The width and height are fixed in each frame. The first two bytes are valid data length in every line, followed by valid image data. Dummy data (0xFF) may be used as padding at each line end if the current valid image data is less than the line width.

figure 6-4

compression mode 4 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK valid data length D[9:2]
Len_h Len_l data

valid data
data data data FF

dummy data
FF FF FF

5640_DS_6_4

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6-3

6.1.5 compression mode 5 timing
The width and height are fixed in each frame. Every line begins with valid image data. Dummy data may be used as padding at each line end if the current valid image data is less than the line width. The last two bytes of every line is valid data length.

figure 6-5

compression mode 5 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK valid data length
FF Len_h Len_l
5640_DS_6_5

valid data D[9:2]
data data data data FF

dummy data
FF FF

6.1.6 compression mode 6 timing
The width and height are fixed in each frame. Every line begins with valid image data. Dummy data may be used as padding at each line end if the current valid image data less than the line width.

figure 6-6

compression mode 6 timing
VSYNC to HREF delay

VSYNC

HREF

PCLK

valid data D[9:2]
data data data data FF FF FF FF FF FF

dummy data
5640_DS_6_6

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6.1.7 compression mode control

table 6-1
address
0x3821

compression control registers (sheet 1 of 2)
register name
COMPRESSION ENABLE

default value
0x00

R/W
RW

description
Bit[5]: Bit[5]: JPEG enable JPEG output fixed height enable 0: In JPEG mode2 JPEG height is different in each frame 1: In JPEG mode2 JPEG height is fixed in each frame

0x4600

VFIFO CTRL00

0x80

RW

0x4602 0x4603 0x4604 0x4605 0x460C 0x460D

VFIFO HSIZE VFIFO HSIZE VFIFO VSIZE VFIFO HSIZE VFIFO CTRL0C VFIFO CTRL0D

0x04 0x00 0x03 0x00 0x20 0x00

RW RW RW RW RW RW

JPEG Output Width High Byte JPEG Output Width Low Byte JPEG Output Height High Byte JPEG Output Height Low Byte Bit[7:4]: JPEG dummy data pad speed JPEG PAD Dummy Data Bit[2:0]: JPEG mode select 001: JPEG mode 1 010: JPEG mode 2 011: JPEG mode 3 100: JPEG mode 4 101: JPEG mode 5 110: JPEG mode 6 HREF Minimum Blanking in JPEG Mode23 DVP JPEG Mode456 Skip Line Number Bit[7]: input_format 0: YUV420 1: YUV422 Bit[6:0]: JFIFO read speed control Bit[7:4]: SFIFO output buffer speed control Bit[3]: Read SRAM enable when blanking 0: Disable 1: Enable Bit[2]: Read SRAM at first blanking 0: Disable 1: Enable Bit[1:0]: SFIFO read speed control

0x4713

JPG MODE SELECT

0x02

RW

0x471F 0x4723

DVP HREF CTRL DVP CTRL23

0x40 0x00

RW RW

0x4400

JPEG CTRL00

0x81

RW

0x4401

JPEG CTRL01

0x01

RW

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6-5

table 6-1
address

compression control registers (sheet 2 of 2)
register name default value R/W description
Bit[7]: Bit[6]: Bit[5]: Bit[4]: jfifo_pwrdn SFIFO pwrdn Header output enable Enable gated clock 0: Disable gated clock 1: Enable gated clock Bit[3]: Substitute 0xFF to 0xFE in QT Bit[2:0]: Quantization rounding Bias: set value = Bias/8 Bit[0]: JFIFO overflow indicator

0x4404

JPEG CTRL04

0x24

RW

0x4417

JFIFO OVERFLOW



R

6.2 system control
System control registers include clock, reset control, and PLL configure. Individual modules can be reset or clock gated by setting the appropriate registers.

table 6-2
address

system control registers (sheet 1 of 3)
register name default value R/W description
Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset BIST Bit[6]: Reset MCU program memory Bit[5]: Reset MCU Bit[4]: Reset OTP Bit[3]: Reset STB Bit[2]: Reset d5060 Bit[1]: Reset timing control Bit[0]: Reset array control Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset AWB registers Bit[6]: Reset AFC Bit[5]: Reset ISP Bit[4]: Reset FC Bit[3]: Reset S2P Bit[2]: Reset BLC Bit[1]: Reset AEC registers Bit[0]: Reset AEC

0x3000

SYSTEM RESET00

0x30

RW

0x3001

SYSTEM RESET01

0x08

RW

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table 6-2
address

system control registers (sheet 2 of 3)
register name default value R/W description
Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset VFIFO Bit[5]: Reset format Bit[4]: Reset JFIFO Bit[3]: Reset SFIFO Bit[2]: Reset JPG Bit[1]: Reset format MUX Bit[0]: Reset average Reset for Individual Block (0: enable block; 1: reset block) Bit[5]: Reset digital gain compensation Bit[4]: Reset SYNC FIFO Bit[3]: Reset PSRAM Bit[2]: Reset ISP FC Bit[1]: Reset MIPI Bit[0]: Reset DVP Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable BIST clock Bit[6]: Enable MCU program memory clock Bit[5]: Enable MCU clock Bit[4]: Enable OTP clock Bit[3]: Enable STROBE clock Bit[2]: Enable D5060 clock Bit[1]: Enable timing control clock Bit[0]: Enable array control clock Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable AWB register clock Bit[6]: Enable AFC clock Bit[5]: Enable ISP clock Bit[4]: Enable FC clock Bit[3]: Enable S2P clock Bit[2]: Enable BLC clock Bit[1]: Enable AEC register clock Bit[0]: Enable AEC clock Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable PSRAM clock Bit[6]: Enable FMT clock Bit[5]: Enable JPEG 2x clock Bit[3]: Enable JPEG clock Bit[1]: Enable format MUX clock Bit[0]: Enable average clock

0x3002

SYSTEM RESET02

0x1C

RW

0x3003

SYSTEM RESET03

0x00

RW

0x3004

CLOCK ENABLE00

0xCF

RW

0x3005

CLOCK ENABLE01

0xF7

RW

0x3006

CLOCK ENABLE02

0xE3

RW

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6-7

table 6-2
address

system control registers (sheet 3 of 3)
register name default value R/W description
Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable digital gain compensation clock Bit[6]: Enable SYNC FIFO clock Bit[5]: Enable ISPFC SCLK clock Bit[4]: Enable MIPI PCLK clock Bit[3]: Enable MIPI clock Bit[2]: Enable DVP PCLK clock Bit[1]: Enable VFIFO PCLK clock Bit[0]: Enable VFIFO SCLK clock System Control Bit[7]: Software reset Bit[6]: Software power down Bit[6:4]: PLL charge pump control Bit[3:0]: MIPI bit mode 0x8: 8-bit mode 0xA: 10-bit mode Bit[7:4]: System clock divider Slow down all clocks Bit[3:0]: Scale divider for MIPI MIPI PCLK/SERCLK can be slowed down Bit[7:0]: PLL multiplier (4~252) Can be any integer for 4~127 and only even integer for 128~252 Bit[4]: PLL root divider 0: Bypass 1: Divided by 2 Bit[3:0]: PLL pre-divider 1, 2, 3, 4, 6, 8 Bit[7]: PLL bypass

0x3007

CLOCK ENABLE03

0xFF

RW

0x3008

SYSTEM CTROL0

0x02

RW

0x3034

SC PLL CONTRL0

0x1A

RW

0x3035

SC PLL CONTRL1

0x11

RW

0x3036

SC PLL CONTRL2

0x69

RW

0x3037

SC PLL CONTRL3

0x03

RW

0x3039

SC PLL CONTRL 5

0x00

RW

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6.3 microcontroller unit (MCU)
The MCU firmware can be downloaded by writing to registers starting from 0x8000. A total of 4 KB of program memory can be used for program storage. Before downloading the firmware, the user must enable the MCU clock by setting register 0x3000[5] to 1’b1. After downloading the firmware, set register 0x3000[5] to 1’b0 to enable the MCU. The MCU interrupts are triggered by several internal signals for firmware development.

table 6-3
address
0x3F00

MCU control registers (sheet 1 of 2)
register name
MC CTRL 00

default value
0x00

R/W
RW

description
Bit[0]: MCU soft reset 1: Reset MCU

0x3F01

MC INTERRUPT MASK0

0x00

RW

Mask0 for Interrupt (0: disable interrupt bit; 1: enable interrupt bit) Bit[7]: JFIFO over flow Bit[6]: JFIFO end of image Bit[5]: ISP end of frame Bit[4]: ISP start of frame Bit[3]: AFC done Bit[2]: AWB done Bit[1]: VFIFO full Bit[0]: VFIFO empty Mask1 for Interrupt (0: disable interrupt bit; 1: enable interrupt bit) Bit[7]: AEC done Bit[6]: ISP average done Bit[5]: AEC trigger Bit[4]: JPG over size Bit[3]: SRM operation start Bit[2]: SRM operation done Bit[1]: DVP frame counter change Bit[0]: BLC start of frame Bit[7:0]: Set high byte for SCCB address that will trigger interrupt when read Bit[7:0]: Set low byte for SCCB address that will trigger interrupt when read Bit[7:0]: Set high byte for SCCB address that will trigger interrupt when written Bit[7:0]: Set low byte for SCCB address that will trigger interrupt when written

0x3F02

MC INTERRUPT MASK1

0x00

RW

0x3F03 0x3F04 0x3F05 0x3F06

MC READ INTERRUPT ADDRESS MC READ INTERRUPT ADDRESS MC WRITE INTERRUPT ADDRESS MC WRITE INTERRUPT ADDRESS

0x70 0x00 0x70 0x04

RW RW RW RW

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table 6-3
address

MCU control registers (sheet 2 of 2)
register name default value R/W description
Interrupt0 Status Indicator Bit[5]: ISP EOF Bit[4]: ISP SOF Bit[2]: AWB done Bit[1]: VFIFO full Bit[0]: VFIFO empty Interrupt1 Status Indicator Bit[7]: AEC done Bit[6]: Average done Bit[5]: AEC trigger Bit[3]: MIPI turn around Bit[2]: MIPI low power contention detect Bit[0]: BLC SOF

0x3F0C

MC INTERRUPT0 STATUS

0x00

RW

0x3F0D

MC INTERRUPT1 STATUS

0x00

RW

6.4 frame control (FC)
Frame control (FC) is used to mask some specified frame by setting the appropriate registers.

table 6-4
address

FC control registers
register name default value R/W description
Control Passed Frame Number When both ON and OFF numbers are set to 0x00, frame control is in bypass mode Bit[3:0]: Frame ON number Control Masked Frame Number When both ON and OFF numbers are set to 0x00, frame control is in bypass mode Bit[3:0]: Frame OFF number

0x4201

FRAME CONTROL 00

0x00

RW

0x4202

FRAME CONTROL 01

0x00

RW

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6.5 format description
Format control converts the internal data format into the desired output format including YUV, RGB, or RAW.

table 6-5
address

FORMAT control registers (sheet 1 of 5)
register name default value R/W description
Format Control 00 Bit[7:4]: Output format of formatter module 0x0: RAW Bit[3:0]: Output sequence 0x0: BGBG... / GRGR... 0x1: GBGB... / RGRG... 0x2: GRGR... / BGBG... 0x3: RGRG... / GBGB... 0x4~0xF: Not allowed 0x1: Y8 Bit[3:0]: Does not matter 0x2: YUV444/RGB888 (not available for full resolution) Bit[3:0]: Output sequence 0x0: YUVYUV..., or GBRGBR... 0x1: YVUYVU..., or GRBGRB... 0x2: UYVUYV..., or BGRBGR... 0x3: VYUVYU..., or RGBRGB... 0x4: UVYUVY..., or BRGBRG... 0x5: VUYVUY..., or RBGRBG... 0x6~0xE: Not allowed 0xF: UYVUYV..., or BGRBGR... 0x3: YUV422 Bit[3:0]: Output sequence 0x0: YUYV... 0x1: YVYU... 0x2: UYVY... 0x3: VYUY... 0x4~0xE: Not allowed 0xF: UYVY... 0x4: YUV420 Bit[3:0]: Output sequence 0x0: YYYY... / YUYV... 0x1: YYYY... / YVYU... 0x2: YYYY... / UYVY... 0x3: YYYY... / VYUY... 0x4: YUYV... / YYYY...

0x4300

FORMAT CONTROL 00

0xF8

RW

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table 6-5
address

FORMAT control registers (sheet 2 of 5)
register name default value R/W description
0x5: YVYU... / YYYY... 0x6: UYVY... / YYYY... 0x7: VYUY... / YYYY... 0x8~0xE: Not allowed 0xF: YYYY... / UYVY... YUV420 (for MIPI only) Bit[3:0]: Output sequence 0x0~0xD: Not allowed 0xE: VYYVYY... / UYYUYY... 0xF: UYYUYY... / VYYVYY... RGB565 Bit[3:0]: Output sequence 0x0: {b[4:0],g[5:3]}, {g[2:0],r[4:0]} 0x1: {r[4:0],g[5:3]}, {g[2:0],b[4:0]} 0x2: {g[4:0],r[5:3]}, {r[2:0],b[4:0]} 0x3: {b[4:0],r[5:3]}, {r[2:0],g[4:0]} 0x4: {g[4:0],b[5:3]}, {b[2:0],r[4:0]} 0x5: {r[4:0],b[5:3]}, {b[2:0],g[4:0]} 0x6~0xE: Not allowed 0xF: {g[2:0],b[4:0]}, {r[4:0],g[5:3]} RGB555 format 1 Bit[3:0]: Output sequence 0x0: {b[4:0],g[4:2]}, {g[1:0],1'b0,r[4:0]} 0x1: {r[4:0],g[4:2]}, {g[1:0],1'b0,b[4:0]} 0x2: {g[4:0],r[4:2]}, {r[1:0],1'b0,b[4:0]} 0x3: {b[4:0],r[4:2]}, {r[1:0],1'b0,g[4:0]} 0x4: {r[4:0],b[4:2]}, {b[1:0],1'b0,g[4:0]} 0x5: {g[4:0],b[4:2]}, {b[1:0],1'b0,r[4:0]} 0x6~0xE: Not allowed 0xF: {g[1:0],1'b0,b[4:0]}, {r[4:0],g[4:2]} RGB555 format 2 Bit[3:0]: Output sequence 0x0: {1'b0,b[4:0],g[4:3]}, {g[2:0],r[4:0]}

0x5:

0x6:

0x7:

0x8:

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table 6-5
address

FORMAT control registers (sheet 3 of 5)
register name default value R/W description
0x1: {1'b0,r[4:0],g[4:2]}, {g[2:0],b[4:0]} 0x2: {1'b0,g[4:0],r[4:2]}, {r[2:0],b[4:0]} 0x3: {1'b0,b[4:0],r[4:2]}, {r[2:0],g[4:0]} 0x4: {1'b0,r[4:0],b[4:2]}, {b[2:0],g[4:0]} 0x5: {1'b0,g[4:0],b[4:2]}, {b[2:0],r[4:0]} 0x6: {b[4:0],1'b0,g[4:3]}, {g[2:0],r[4:0]} 0x7: {r[4:0],1'b0,g[4:2]}, {g[2:0],b[4:0]} 0x8: {g[4:0],1'b0,r[4:2]}, {r[2:0],b[4:0]} 0x9: {b[4:0],1'b0,r[4:2]}, {r[2:0],g[4:0]} 0xA: {r[4:0],1'b0,b[4:2]}, {b[2:0],g[4:0]} 0xB: {g[4:0],1'b0,b[4:2]}, {b[2:0],r[4:0]} 0xC~0xF: Not allowed 0x9: RGB444 format 1 Bit[3:0]: Output sequence 0x0: {1'b0,b[3:0],2'h0,g[3]}, {g[2:0],1'b0,r[3:0]} 0x1: {1'b0,r[3:0],2'h0,g[3]}, {g[2:0],1'b0,b[3:0]} 0x2: {1'b0,g[3:0],2'h0,r[3]}, {r[2:0],1'b0,b[3:0]} 0x3: {1'b0,b[3:0],2'h0,r[3]}, {r[2:0],1'b0,g[3:0]} 0x4: {1'b0,r[3:0],2'h0,b[3]}, {b[2:0],1'b0,g[3:0]} 0x5: {1'b0,g[3:0],2'h0,b[3]}, {b[2:0],1'h0,r[3:0]} 0x6: {b[3:0],1'b0,g[3:1]}, {g[0],2'h0,r[3:0],1'b0} 0x7: {r[3:0],1'b0,g[3:1]}, {g[0],2'h0,b[3:0],1'b0} 0x8: {g[3:0],1'b0,r[3:1]}, {r[0],2'h0,b[3:0],1'b0} 0x9: {b[3:0],1'b0,r[3:1]}, {r[0],2'h0,g[3:0],1'b0} 0xA: {r[3:0],1'b0,b[3:1]}, {b[0],2'h0,g[3:0],1'b0} 0xB: {g[3:0],1'b0,b[3:1]}, {b[0],2'h0,r[3:0],1'b0} 0xC~0xE: Not allowed

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6-13

table 6-5
address

FORMAT control registers (sheet 4 of 5)
register name default value R/W description
0xF: {g[0],2'h2,b[3:0],1'b1}, {r[3:0],1'b1,g[3:1]} 0xA: RGB444 format 2 Bit[3:0]: Output sequence 0x0: {4'b0,b[3:0]}, {g[3:0],r[3:0]} 0x1: {4'b0,r[3:0]}, {g[3:0],b[3:0]} 0x2: {4'b0,b[3:0]}, {r[3:0],g[3:0]} 0x3: {4'b0,r[3:0]}, {b[3:0],g[3:0]} 0x4: {4'b0,g[3:0]}, {b[3:0],r[3:0]} 0x5: {4'b0,g[3:0]}, {r[3:0],b[3:0]} 0x6: {b[3:0],g[3:0],2'h0}, {r[3:0],b[3:0],2'h0,g[3: 0],r[3:0],2'h0} 0x7: {r[3:0],g[3:0],2'h0}, {b[3:0],r[3:0],2'h0,g[3: 0],b[3:0],2'h0} 0x8: {b[3:0],r[3:0],2'h0}, {g[3:0],b[3:0],2'h0,r[3: 0],g[3:0],2'h0} 0x9: {r[3:0],b[3:0],2'h0}, {g[3:0],r[3:0],2'h0,b[3: 0],g[3:0],2'h0} 0xA: {g[3:0],b[3:0],2'h0}, {r[3:0],g[3:0],2'h0,b[3: 0],r[3:0],2'h0} 0xB: {g[3:0],r[3:0],2'h0}, {b[3:0],g[3:0],2'h0,r[3: 0],b[3:0],2'h0} 0xC~0xF: Not allowed 0xB~0xE: Not allowed 0xF: Bypass formatter module (not recommended) Bit[3:0]: Output format 0x8: Raw 0x9: YUV422 0xA: YUV444 0xE: VYYVYY.../UYYUYY 0xF: UYYUYY.../VYYVYY

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 6-5
address

FORMAT control registers (sheet 5 of 5)
register name default value R/W description
Format Control 01 Bit[1:0]: YUV422 UV control 00: U/V generated from average 01: U/V generated from first pixel 10: Not valid 11: U/V generated from second pixel Bit[1:0]: Y max clip value[9:8] Bit[7:0]: Y max clip value[7:0] Bit[1:0]: Y min clip value[9:8] Bit[7:0]: Y min clip value[7:0] Bit[1:0]: U max clip value[9:8] Bit[7:0]: U max clip value[7:0] Bit[1:0]: U min clip value[9:8] Bit[7:0]: U min clip value[7:0] Bit[1:0]: V max clip value[9:8] Bit[7:0]: V max clip value[7:0] Bit[1:0]: V min clip value[9:8] Bit[7:0]: V min clip value[7:0]

0x4301

FORMAT CONTROL 01

0x00

RW

0x4302 0x4303 0x4304 0x4305 0x4306 0x4307 0x4308 0x4309 0x430A 0x430B 0x430C 0x430D

YMAX VALUE YMAX VALUE YMIN VALUE YMIN VALUE UMAX VALUE UMAX VALUE UMIN VALUE UMIN VALUE VMAX VALUE VMAX VALUE VMIN VALUE VMIN VALUE

0x03 0xFF 0x00 0x00 0x03 0xFF 0x00 0x00 0x03 0xFF 0x00 0x00

RW RW RW RW RW RW RW RW RW RW RW RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

6-15

6.6 digital video port (DVP)
6.6.1 overview
The Digital Video Port (DVP) provides 10-bit parallel data output in all formats supported and extended features including compression mode, HSYNC mode, CCIR656 mode, and test pattern output. The DVP is also used to receive the video data from an external camera, which will be sent out through the OV5640 MIPI interface.

table 6-6
address
0x4709 0x470A 0x470B 0x4711

DVP control registers (sheet 1 of 3)
register name
DVP VYSNC WIDTH0 DVP VYSNC WIDTH1 DVP VYSNC WIDTH2 PAD LEFT CTRL

default value
0x02 0x00 0x01 0x00

R/W
RW RW RW RW

description
VSYNC Width Line Unit Bit[7:0]: VSYNC width PCLK unit[15:8] Bit[7:0]: VSYNC width PCLK unit[7:0] HSYNC Mode Left Padding Pixel Counter Add padding data at start of a line HSYNC Mode Right Padding Pixel Counter Add padding data at end of a line Bit[2:0]: JPEG mode select 001: JPEG mode 1 010: JPEG mode 2 011: JPEG mode 3 100: JPEG mode 4 101: JPEG mode 5 110: JPEG mode 6 Bit[3:0]: CCIR656 dummy line number Control dummy line number at beginning of the frame Bit[1:0]: CCIR656 EAV/SAV option Bit[0]: HSYNC mode enable

0x4712

PAD RIGHT CTRL

0x00

RW

0x4713

JPG MODE SELECT

0x02

RW

0x4715

656 DUMMY LINE

0x00

RW

0x4719 0x471B

CCIR656 CTRL HSYNC CTRL00

0x00 0x02

RW RW

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PRODUCT SPECIFICATION

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 6-6
address

DVP control registers (sheet 2 of 3)
register name default value R/W description
Bit[1:0]: vsync_mode 00: VSYNC positive edge trigger by end of field, negative edge trigger by start of frame 01: VSYNC positive edge trigger by end of frame, the width define by register 10: VSYNC positive edge trigger by start of field, the width define by register HREF Minimum Blanking in JPEG Mode23 Bit[3:0]: Vertical start delay between video output and video input Bit[3:0]: Vertical end delay between video output and video input DVP JPEG Mode456 Skip Line Number SYNC code selection 0: Automatically generate SYNC code 1: SYNC code from register setting 0x4732~4735 Bit[6]: f value in CCIR656 SYNC code when fixed f value Bit[5]: Fixed f value Bit[4:3]: Blank toggle data options 00: Toggle data is 1'h040/1'h200 01: Use register setting 0x4736~0x4738 10: Blanking data always keep 0 Bit[1]: Clip data disable Bit[0]: CCIR656 mode enable Bit[0]: Blanking toggle data order option Bit[7]:

0x471D

DVP VSYNC CTRL

0x01

RW

0x471F 0x4721 0x4722 0x4723

DVP HREF CTRL VERTICAL START OFFSET VERTICAL END OFFSET DVP CTRL23

0x40 0x00 0x00 0x00

RW RW RW RW

0x4730

CCIR656 CTRL00

0x00

RW

0x4731 0x4732 0x4733 0x4734

CCIR656 CTRL01 CCIR656 FS CCIR656 FE CCIR656 LS

0x00 0x01 0x0F 0x00

RW RW RW RW

CCIR656 Sync Code Frame Start CCIR656 Sync Code Frame End CCIR6656 Sync Code Line Start

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

6-17

table 6-6
address
0x4735 0x4736 0x4737 0x4738

DVP control registers (sheet 3 of 3)
register name
CCIR656 LE CCIR656 CTRL6 CCIR656 CTRL7 CCIR656 CTRL8

default value
0x00 0x00 0x00 0x00

R/W
RW RW RW RW

description
CCIR656 Sync Code line End Bit[3:2]: Toggle data0[9:8] Bit[1:0]: Toggle data1[9:8] Bit[7:0]: Toggle data0[7:0] Bit[7:0]: Toggle data1[7:0] Bit[5]: PCLK polarity 0: Active low 1: Active high Gate PCLK under VSYNC Gate PCLK under HREF HREF polarity 0: Active low 1: Active high VSYNC polarity 0: Active low 1: Active high Test pattern enable Test pattern select 0: Output test pattern 0 1: Output test pattern 1 Test pattern 8-bit/10-bit 0: 10-bit test pattern 1: 8-bit test pattern

0x4740

POLARITY CTRL00

0x20

RW

Bit[3]: Bit[2]: Bit[1]:

Bit[0]:

Bit[2]: Bit[1]: 0x4741 TEST PATTERN 0x00 RW Bit[0]:

0x4745

DATA ORDER

0x00

RW

Bit[2:1]: DVP order option for debug 00: D[9:0] 10: {D[7:0], D[9:8]} x1: {D[1:0], D[9:2]} Bit[0]: Output data order 0: Normal output 1: Reverse output data bit order

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

6.6.2 DVP timing

figure 6-7

DVP timing diagram
(1)

VSYNC (2) (3) (4) (7) HREF (6) (8) (9) (5)

HSYNC

D[9:0]

invalid data
5640_DS_6_7

table 6-7

DVP timing specifications (sheet 1 of 2)
timing
(1) (2) (3) (4) (5) (6) (7) (8) (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) 5596992 tp 5688 tp 48276 tp 2844 tp 14544 tp 2592 tp 252 tp 0 tp 252 tp 5596992 tp 5688 tp 2506164 tp 2844 tp 14544 tp 1920 tp 924 tp 0 tp 924 tp 5596992 tp 5688 tp 2165204 tp 2844 tp 14544 tp 1600 tp 1244 tp 0 tp 1244 tp

The timing values shown in table 6-7 may vary depending upon register settings.

note

mode

5 megapixel 2592x1944

1080p 1920x1080

UXGA 1600x1200

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

6-19

table 6-7
mode

DVP timing specifications (sheet 2 of 2)
timing
(1) (2) (3) (4) (5) (6) (7) (8) (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) 5596992 tp 5688 tp 3530644 tp 2844 tp 14544 tp 1280 tp 1564 tp 0 tp 1564 tp 5596992 tp 5688tp 2825588 tp 2844 tp 583344tp 1024 tp 1820 tp 0 tp 1820 tp 5596992 tp 5688 tp 4213844 tp 2844 tp 14544 tp 640 tp 2204 tp 0 tp 2204 tp

720p 1280x720

XGA 1024x768

VGA 640x480

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PRODUCT SPECIFICATION

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

6.7 mobile industry processor interface (MIPI)
MIPI provides a single uni-directional clock lane and two bi-directional data lane solution for communication links between components inside a mobile device. The two data lanes have full support for HS (uni-direction) and LP (bi-direction) data transfer mode. Contact your local OmniVision FAE for more details.

table 6-8
address

MIPI transmitter registers (sheet 1 of 3)
register name default value R/W description
MIPI Control 00 Bit[5]: Clock lane gate enable 0: Clock lane is free running 1: Gate clock lane when no packet to transmit Bit[4]: Line sync enable 0: Do not send line short packet for each line 1: Send line short packet for each line Bit[3]: Lane select 0: Use lane1 as default data lane 1: Use lane2 as default data lane Bit[2]: Idle status 0: MIPI bus will be LP00 when no packet to transmit 1: MIPI bus will be LP11 when no packet to transmit MIPI Control 01 Bit[4]: PH bit order for ECC 0: {DI[7:0],WC[7:0],WC[15:8]} 1: {DI[0:7],WC[0:7],WC[8:15]} Bit[3]: PH byte order for ECC 0: {DI,WC_l,WC_h} 1: {DI,WC_h,WC_l} Bit[2]: PH byte order2 for ECC 0: {DI,WC} 1: {WC,DI} Bit[7]: MIPI lane1 disable 1: Disable MIPI data lane1 Lane1 will be LP00 MIPI lane1 disable 1: Disable MIPI data lane1 Lane1 will be LP00 LPX Global timing select 0: Auto calculate t_lpx_o in pclk2x domain, unit clk2x 1: Use lp_p_min[7:0]

0x4800

MIPI CTRL 00

0x04

RW

0x4801

MIPI CTRL 01

0x04

RW

Bit[6]: 0x4805 MIPI CTRL 05 0x10 RW Bit[5]:

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

6-21

table 6-8
address

MIPI transmitter registers (sheet 2 of 3)
register name
MIPI DATA ORDER

default value

R/W

description
Bit[2]: Bit order reverse Bit[1:0]: Bit position adjust 01: {data[7:0],data[9:8]} 10: {data[1:0],data[9:2]} High Byte of Minimum Value of hs_zero Unit ns Low Byte of Minimum Value of hs_zero hs_zero_real = hs_zero_min_o + Tui*ui_hs_zero_min_o High Byte of Minimum Value of hs_trail Unit ns Low Byte of Minimum Value of hs_trail hs_trail_real = hs_trail_min_o + Tui*ui_hs_trail_min_o High Byte of Minimum Value of clk_zero Low Byte of Minimum Value of clk_zero clk_zero_real = clk_zero_min_o + Tui*ui_clk_zero_min_o High Byte of Minimum Value of clk_prepare Unit ns Low Byte of Minimum Value of clk_prepare clk_prepare_real = clk_prepare_min_o + Tui*ui_clk_prepare_min_o High Byte of Minimum Value of clk_post Unit ns Low Byte of Minimum Value of clk_post clk_post_real = clk_post_min_o + Tui*ui_clk_post_min_o High Byte of Minimum Value of clk_trail Unit ns Low Byte of Minimum Value of clk_trail clk_trail_real = clk_trail_min_o + Tui*ui_clk_trail_min_o High Byte of Minimum Value of lpx_p Unit ns Low Byte of Minimum Value of lpx_p lpx_p_real = lpx_p_min_o + Tui*ui_lpx_p_min_o High Byte of Minimum Value of hs_prepare Unit ns Low Byte of Minimum Value of hs_prepare hs_prepare_real = hs_prepare_min_o + Tui*ui_hs_prepare_min_o

0x480A

0x00

RW

0x4818 0x4819 0x481A 0x481B 0x481C 0x481D 0x481E

MIN HS ZERO H MIN HS ZERO L MIN MIPI HS TRAIL H MIN MIPI HS TRAIL L MIN MIPI CLK ZERO H MIN MIPI CLK ZERO L MIN MIPI CLK PREPARE H MIN MIPI CLK PREPARE L MIN CLK POST H MIN CLK POST L MIN CLK TRAIL H MIN CLK TRAIL L MIN LPX PCLK H MIN LPX PCLK L MIN HS PREPARE H MIN HS PREPARE L

0x00 0x96 0x00 0x3C 0x01 0x86 0x00

RW RW RW RW RW RW RW

0x481F

0x3C

RW

0x4820 0x4821 0x4822 0x4823 0x4824 0x4825 0x4826

0x00 0x56 0x00 0x3C 0x00 0x32 0x00

RW RW RW RW RW RW RW

0x4827

0x32

RW

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 6-8
address
0x4828 0x4829 0x482A 0x482B 0x482C 0x482D 0x482E 0x482F 0x4830 0x4831 0x4832 0x4837

MIPI transmitter registers (sheet 3 of 3)
register name
MIN HS EXIT H MIN HS EXIT L MIN HS ZERO/UI MIN HS TRAIL/UI MIN CLK ZERO/UI MIN CLK PREPARE/UI MIN CLK POST/UI MIN CLK TRAIL/UI MIN LPX PCLK/UI MIN HS PREPARE/UI MIN HS EXIT/UI PCLK PERIOD

default value
0x00 0x64 0x05 0x04 0x00 0x00 0x34 0x00 0x00 0x04 0x00 0x10

R/W
RW RW RW RW RW RW RW RW RW RW RW RW

description
High Byte of Minimum Value of hs_exit Unit ns Low Byte of Minimum Value of hs_exit hs_exit_real = hs_exit_min_o + Tui*ui_hs_exit_min_o Minimum UI Value of hs_zero Unit UI Minimum UI Value of hs_trail Unit UI Minimum UI Value of clk_zero Unit UI Minimum UI Value of clk_prepare Unit UI Minimum UI Value of clk_post Unit UI Minimum UI Value of clk_trail Unit UI Minimum UI Value of lpx_p(pclk2x domain) Unit UI Minimum UI Value of hs_prepare Unit UI Minimum UI Value of hs_exit Unit UI The period of pixel clock, pclk_div=1, and 1 bit decimal

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-1

7 register tables
The following tables provide descriptions of the device control registers contained in the OV5640. For all registers enable/disable bits, ENABLE = 1 and DISABLE = 0.

7.1 system and IO pad control [0x3000 ~ 0x3052]
table 7-1
address

system and IO pad control registers (sheet 1 of 7)
register name default value R/W description
Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset BIST Bit[6]: Reset MCU program memory Bit[5]: Reset MCU Bit[4]: Reset OTP Bit[3]: Reset STB Bit[2]: Reset d5060 Bit[1]: Reset timing control Bit[0]: Reset array control Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset AWB registers Bit[6]: Reset AFC Bit[5]: Reset ISP Bit[4]: Reset FC Bit[3]: Reset S2P Bit[2]: Reset BLC Bit[1]: Reset AEC registers Bit[0]: Reset AEC Reset for Individual Block (0: enable block; 1: reset block) Bit[7]: Reset VFIFO Bit[6]: Debug mode Bit[5]: Reset format Bit[4]: Reset JFIFO Bit[3]: Reset SFIFO Bit[2]: Reset JPG Bit[1]: Reset format MUX Bit[0]: Reset average

0x3000

SYSTEM RESET00

0x30

RW

0x3001

SYSTEM RESET01

0x08

RW

0x3002

SYSTEM RESET02

0x1C

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-1
address

system and IO pad control registers (sheet 2 of 7)
register name default value R/W description
Reset for Individual Block (0: enable block; 1: reset block) Bit[7:6]: Debug mode Bit[5]: Reset digital gain compensation Bit[4]: Reset SYNC FIFO Bit[3]: Reset PSRAM Bit[2]: Reset ISP FC Bit[1]: Reset MIPI Bit[0]: Reset DVP Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable BIST clock Bit[6]: Enable MCU program memory clock Bit[5]: Enable MCU clock Bit[4]: Enable OTP clock Bit[3]: Enable STROBE clock Bit[2]: Enable D5060 clock Bit[1]: Enable timing control clock Bit[0]: Enable array control clock Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable AWB register clock Bit[6]: Enable AFC clock Bit[5]: Enable ISP clock Bit[4]: Enable FC clock Bit[3]: Enable S2P clock Bit[2]: Enable BLC clock Bit[1]: Enable AEC register clock Bit[0]: Enable AEC clock Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable PSRAM clock Bit[6]: Enable FMT clock Bit[5]: Enable JPEG 2x clock Bit[3]: Enable JPEG clock Bit[2]: Debug mode Bit[1]: Enable format MUX clock Bit[0]: Enable average clock

0x3003

SYSTEM RESET03

0x00

RW

0x3004

CLOCK ENABLE00

0xCF

RW

0x3005

CLOCK ENABLE01

0xF7

RW

0x3006

CLOCK ENABLE02

0xE3

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-3

table 7-1
address

system and IO pad control registers (sheet 3 of 7)
register name default value R/W description
Clock Enable Control (0: disable clock; 1: enable clock) Bit[7]: Enable digital gain compensation clock Bit[6]: Enable SYNC FIFO clock Bit[5]: Enable ISPFC SCLK clock Bit[4]: Enable MIPI PCLK clock Bit[3]: Enable MIPI clock Bit[2]: Enable DVP PCLK clock Bit[1]: Enable VFIFO PCLK clock Bit[0]: Enable VFIFO SCLK clock System Control Bit[7]: Software reset Bit[6]: Software power down Bit[5:0]: Debug mode Debug Mode Chip ID High Byte Chip ID Low Byte Debug Mode MIPI Control 00 Bit[7:5]: mipi_lane_mode 000: One lane mode 001: Two lane mode Others: Debug mode Bit[4]: MIPI TX PHY power down 0: Debug mode 1: Power down PHY HS TX Bit[3]: MIPI RX PHY power down 0: Debug mode 1: Power down PHY LP RX module Bit[2]: mipi_en 0: DVP enable 1: MIPI enable Bit[1:0]: Debug mode Debug Mode Input/Output Control (0: input; 1: output) Bit[7:2]: Debug mode Bit[1]: Strobe output enable Bit[0]: SIOD output enable

0x3007

CLOCK ENABLE03

0xFF

RW

0x3008

SYSTEM CTROL0

0x02

RW

0x3009 0x300A 0x300B 0x300C~ 0x300D

DEBUG MODE CHIP ID HIGH BYTE CHIP ID LOW BYTE DEBUG MODE

– 0x56 0x40 –

– R R –

0x300E

MIPI CONTROL 00

0x58

RW

0x300F~ 0x3015

DEBUG MODE





0x3016

PAD OUTPUT ENABLE 00

0x00

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-1
address

system and IO pad control registers (sheet 4 of 7)
register name default value R/W description
Input/Output Control (0: input; 1: output) Bit[7]: FREX output enable Bit[6]: VSYNC output enable Bit[5]: HREF output enable Bit[4]: PCLK output enable Bit[3:0]: D[9:6] output enable Input/Output Control (0: input; 1: output) Bit[7:2]: D[5:0] output enable Bit[1]: GPIO1 output enable Bit[0]: GPIO0 output enable PAD Output Value Bit[7]: MIPI data lane option Bypass latch in MIPI PHY Bit[6]: MIPI lane2 state in sleep mode 0: LP00 1: LP11 Bit[5]: MIPI lane1 state in sleep mode 0: LP00 1: LP11 Bit[4]: MIPI CLK lane state in sleep mode 0: LP00 1: LP11 Bit[3:2]: Debug mode Bit[1]: Strobe Bit[0]: SIOD GPIO Output Value 01 Bit[7]: FREX Bit[6]: VSYNC Bit[5]: HREF Bit[4]: PCLK Bit[3:0]: D[9:6] GPIO Output Value 02 Bit[7:2]: D[5:0] Bit[1]: GPIO1 Bit[0]: GPIO0 Output Selection for GPIO Bit[7:2]: Debug mode Bit[1]: IO strobe select Bit[0]: IO SIOD select Output Selection for GPIO Bit[7]: FREX select Bit[6]: VSYNC select Bit[5]: HREF select Bit[4]: PCLK select Bit[3:0]: IO D[9:6] select

0x3017

PAD OUTPUT ENABLE 01

0x00

RW

0x3018

PAD OUTPUT ENABLE 02

0x00

RW

0x3019

PAD OUTPUT VALUE 00

0x00

RW

0x301A

PAD OUTPUT VALUE 01

0x00

RW

0x301B

PAD OUTPUT VALUE 02

0x00

RW

0x301C

PAD SELECT 00

0x00

RW

0x301D

PAD SELECT 01

0x00

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-5

table 7-1
address

system and IO pad control registers (sheet 5 of 7)
register name default value R/W description
Output Selection for GPIO Bit[7:2]: IO D[5:0] select Bit[1]: IO GPIO1 select Bit[0]: IO GPIO0 select Debug Mode Bit[7:4]: Process 0xA: FSI 0xB: BSI Bit[3:0]: Chip revision Debug Mode Pad Control Bit[7:6]: Output drive capability 00: 1x 01: 2x 10: 3x 11: 4x Bit[5:2]: Debug mode Changing this value is not allowed Bit[1]: FREX enable Bit[0]: Debug mode Changing this value is not allowed System Control Registers Changing these values is not recommended PWC Control Bit[7:4]: Debug mode Bit[3]: Bypass regulator Bit[2:0]: Debug mode System Control Registers Changing these values is not recommended Bit[7]: Debug mode Bit[6:4]: PLL charge pump control Bit[3:0]: MIPI bit mode 0x8: 8-bit mode 0xA: 10-bit mode Others: Debug mode Bit[7:4]: System clock divider Slow down all clocks Bit[3:0]: Scale divider for MIPI MIPI PCLK/SERCLK can be slowed down

0x301E

PAD SELECT 02

0x00

RW

0x301F

DEBUG MODE





0x302A

CHIP REVISION

0xB0

R

0x302B

DEBUG MODE





0x302C

PAD CONTROL 00

0x02

RW

0x302D~ 0x3030

SYSTEM CONTROL



RW

0x3031

SC PWC

0x00

RW

0x3032~ 0x3033

SYSTEM CONTROL



RW

0x3034

SC PLL CONTRL0

0x1A

RW

0x3035

SC PLL CONTRL1

0x11

RW

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PRODUCT SPECIFICATION

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-1
address

system and IO pad control registers (sheet 6 of 7)
register name default value R/W description
Bit[7:0]: PLL multiplier (4~252) Can be any integer from 4~127 and only even integers from 128~252 Bit[7:5]: Debug mode Bit[4]: PLL root divider 0: Bypass 1: Divided by 2 Bit[3:0]: PLL pre-divider 1,2,3,4,6,8 System Control Registers Changing these values is not recommended Bit[7]: PLL bypass Bit[6:0]: Debug mode Bit[7]: PLLS bypass Bit[6:0]: Debug mode Bit[7:5]: Debug mode Bit[4:0]: PLLS multiplier Bit[7]: Debug mode Bit[6:4]: PLLS charge pump control Bit[3:0]: PLLS system divider Bit[7:6]: Debug mode Bit[5:4]: PLLS pre-divider 00: /1 01: /1.5 10: /2 11: /3 Bit[3]: Debug mode Bit[2]: PLLS root divider 0: /1 1: /2 Bit[1:0]: PLLS seld5 00: /1 01: /1 10: /2 11: /2.5 System Control Registers Changing these values is not recommended

0x3036

SC PLL CONTRL2

0x69

RW

0x3037

SC PLL CONTRL3

0x03

RW

0x3038 0x3039 0X303A 0x303B

SYSTEM CONTROL SC PLL CONTRL 5 SC PLLS CTRL0 SC PLLS CTRL1

– 0x00 0x00 0x19

RW RW RW RW

0x303C

SC PLLS CTRL2

0x11

RW

0x303D

SC PLLS CTRL3

0x30

RW

0x303E~ 0x304F

SYSTEM CONTROL



RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-7

table 7-1
address

system and IO pad control registers (sheet 7 of 7)
register name default value R/W description
Read Pad Value Bit[7:5]: Debug mode Bit[4]: FREX Bit[3]: PWDN Bit[2]: Debug mode Bit[1]: SIOC Bit[0]: Debug mode Read Pad Value Bit[7]: OTP memory out Bit[6]: VSYNC Bit[5]: HREF Bit[4]: PCLK Bit[3:0]: D[9:6] Pad Input Status Bit[7:2]: D[5:0] Bit[1]: GPIO1 Bit[0]: GPIO0

0x3050

IO PAD VALUE



R

0x3051

IO PAD VALUE



R

0x3052

IO PAD VALUE



R

7.2 SCCB control [0x3100 ~ 0x3108]
table 7-2
address
0x3100 0x3101

SCCB control registers (sheet 1 of 2)
register name
SCCB_ID SCCB SYSTEM CTRL0

default value
0x78 –

R/W
RW RW

description
SCCB Slave ID SCCB Control Registers Changing these values is not allowed Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Debug mode MIPI SC reset SRB reset SCCB slave reset rst_pon_sccb Debug mode MIPI PHY reset PLL reset

0x3102

SCCB SYSTEM CTRL0

0x00

RW

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OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-2
address

SCCB control registers (sheet 2 of 2)
register name default value R/W description
PLL Clock Select Bit[7:2]: Debug mode Changing this value is not allowed Bit[1]: Select system input clock 0: From pad clock 1: From PLL Bit[0]: Debug mode Changing this value is not allowed SCCB Control Registers Changing these values is not allowed Pad Clock Divider for SCCB Clock Bit[7:6]: Debug mode Bit[5:4]: PCLK root divider 00: PCLK = pll_clki 01: PCLK = pll_clki/2 10: PCLK = pll_clki/4 11: PCLK = pll_clki/8 Bit[3:2]: sclk2x root divider 00: SCLK2x = pll_clki 01: SCLK2x = pll_clki/2 10: SCLK2x= pll_clki/4 11: SCLK2x= pll_clki/8 Bit[1:0]: SCLK root divider 00: SCLK = pll_clki 01: SCLK = pll_clki/2 10: SCLK= pll_clki/4 11: sclk= pll_clki/8

0x3103

SCCB SYSTEM CTRL1

0x00

RW

0x3104~ 0x3107

SCCB SYSTEM CTRL0



RW

0x3108

SYSTEM ROOT DIVIDER

0x16

RW

7.3 SRB control [0x3200 ~ 0x3211]
table 7-3
address
0x3200 0x3201 0x3202 0x3203 0x3204~ 0x3211

SRB control registers (sheet 1 of 2)
register name
GROUP ADDR0 GROUP ADDR1 GROUP ADDR2 GROUP ADDR3 GROUP WRITE CONTROL REGISTERS

default value
0x40 0x4A 0x54 0x5E –

R/W
RW RW RW RW RW

description
SRAM Group Address0 SRAM Group Address1 SRAM Group Address2 SRAM Group Address3 Group Write Registers Changing these values is not recommended

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-9

table 7-3
address

SRB control registers (sheet 2 of 2)
register name default value R/W description
SRM Group Access Bit[7]: Group launch enable Bit[6]: Test mode access group Bit[5]: Group launch Bit[4]: Group hold end Bit[3:0]: Group ID 00x: Group for register access 011: Group to hold register address of embedded line SOF 100: Group to hold register address of embedded line EOF 101: Test mode for store register value to memory 110: Test mode for restore register value from memory 111: Group for write mask address SRM Group Status Bit[7]: Store Bit[6]: Restore Bit[5]: Group hold Bit[4]: Group launch Bit[3]: Group write Bit[2:0]: Group select

0x3212

SRM GROUP ACCESS



W

0x3213

SRM GROUP STATUS



R

7.4 AWB gain control [0x3400 ~ 0x3406]
table 7-4
address
0x3400 0x3401 0x3402 0x3403 0x3404 0x3405

AWB gain control registers
register name
AWB R GAIN AWB R GAIN AWB G GAIN AWB G GAIN AWB B GAIN AWB B GAIN AWB MANUAL CONTROL

default value
0x04 0x00 0x04 0x00 0x04 0x00

R/W
RW RW RW RW RW RW

description
Bit[3:0]: AWB R gain[11:8] Bit[7:0]: AWB R gain[7:0] Bit[3:0]: AWB G gain[11:8] Bit[7:0]: AWB G gain[7:0] Bit[3:0]: AWB B gain[11:8] Bit[7:0]: AWB B gain[7:0] Bit[7:1]: Debug mode Bit[0]: AWB gain manual enable 0: Auto 1: Manual

0x3406

0x00

RW

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PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.5 AEC/AGC control [0x3500 ~ 0x350D]
table 7-5
address
0x3500

AEC/AGC control registers
register name
AEC PK EXPOSURE

default value
0x00

R/W
RW

description
Exposure Output Bit[7:4]: Debug mode Bit[3:0]: Exposure [19:16] Exposure Output Bit[7:0]: Exposure [15:8] Exposure Output Bit[7:0]: Exposure [7:0] Lower four bits are a fraction of a line; they should be 0 since OV5640 does not support fraction line exposure AEC Manual Mode Control Bit[7:2]: Debug mode Bit[1]: AGC manual 0: Auto enable 1: Manual enable Bit[0]: AEC manual 0: Auto enable 1: Manual enable Real Gain Bit[7:2]: Debug mode Bit[1:0]: Real gain[9:8] Real Gain Bit[7:0]: Real gain[7:0] AEC VTS Output Bit[7:0]: VTS[15:8] AEC VTS Output Bit[7:0]: VTS[7:0]

0x3501

AEC PK EXPOSURE

0x02

RW

0x3502

AEC PK EXPOSURE

0x00

RW

0x3503

AEC PK MANUAL

0x00

RW

0x350A

AEC PK REAL GAIN

0x00

RW

0x350B 0x350C 0x350D

AEC PK REAL GAIN AEC PK VTS AEC PK VTS

0x10 0x00 0x00

RW RW RW

7.6 VCM control [0x3600 ~ 0x3606]
table 7-6
address
0x3600~ 0x3601

VCM control registers (sheet 1 of 2)
register name
DEBUG MODE

default value


R/W


description
Debug Mode

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-11

table 7-6
address

VCM control registers (sheet 2 of 2)
register name default value R/W description
VCM Control Bit[7:4]: VCM target value[3:0] Bit[3]: Slew rate control s3 Bit[2:0]: Slew rate control s2,s1,s0 VCM Control Bit[7]: PWDN VCM Bit[6]: Debug mode Bit[5:0]: VCM target value[9:4] VCM Control Bit[7:0]: vcm_rdiv[7:0] VCM Control Bit[7:5]: Debug mode Bit[4]: VCM RIH Bit[3:0]: vcm_rdiv[11:8] VCM Control Bit[7:3]: Debug mode Bit[2:0]: ib_vcm

0x3602

VCM CONTROL 0

0x50

RW

0x3603

VCM CONTROL 1

0x01

RW

0x3604

VCM CONTROL 2

0x05

RW

0x3605

VCM CONTROL 3

0x46

RW

0x3606

VCM CONTROL 4

0x00

RW

7.7 timing control [0x3800 ~ 0x3821]
table 7-7
address
0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807

timing control registers (sheet 1 of 3)
register name
TIMING HS TIMING HS TIMING VS TIMING VS TIMING HW TIMING HW TIMING VH TIMING VH

default value
0x00 0x00 0x00 0x00 0x0A 0x3F 0x07 0x9F

R/W
RW RW RW RW RW RW RW RW

description
Bit[7:4]: Debug mode Bit[3:0]: X address start[11:8] Bit[7:0]: X address start[7:0] Bit[7:4]: Debug mode Bit[3:0]: Y address start[11:8] Bit[7:0]: Y address start[7:0] Bit[7:4]: Debug mode Bit[3:0]: X address end[11:8] Bit[7:0]: X address end[7:0] Bit[7:3]: Debug mode Bit[2:0]: Y address end[10:8] Bit[7:0]: Y address end[7:0]

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-7
address
0x3808 0x3809 0x380A 0x380B 0x380C 0x380D 0x380E 0x380F 0x3810 0x3811 0x3812 0x3813 0x3814 0x3815 0x3816 0x3817 0x3818 0x3819

timing control registers (sheet 2 of 3)
register name
TIMING DVPHO TIMING DVPHO TIMING DVPVO TIMING DVPVO TIMING HTS TIMING HTS TIMING VTS TIMING VTS TIMING HOFFSET TIMING_HOFFSET TIMING VOFFSET TIMING VOFFSET TIMING X INC TIMING Y INC HSYNC START HSYNC START HSYNC WIDTH HSYNC WIDTH

default value
0x0A 0x20 0x07 0x98 0x0B 0x1C 0x07 0xB0 0x00 0x10 0x00 0x04 0x11 0x11 0x00 0x00 0x00 0x00

R/W
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

description
Bit[7:4]: Debug mode Bit[3:0]: DVP output horizontal width[11:8] Bit[7:0]: DVP output horizontal width[7:0] Bit[7:3]: Debug mode Bit[2:0]: DVP output vertical height[10:8] Bit[7:0]: DVP output vertical height[7:0] Bit[7:5]: Debug mode Bit[4:0]: Total horizontal size[12:8] Bit[7:0]: Total horizontal size[7:0] Bit[7:0]: Total vertical size[15:8] Bit[7:0]: Total vertical size[7:0] Bit[7:4]: Debug mode Bit[3:0]: ISP horizontal offset[11:8] Bit[7:0]: Horizontal offset[7:0] Bit[7:3]: Debug mode Bit[2:0]: Vertical offset[10:8] Bit[7:0]: Vertical offset[7:0] Bit[7:4]: Horizontal odd subsample increment Bit[3:0]: Horizontal even subsample increment Bit[7:4]: Vertical odd subsample increment Bit[3:0]: Vertical even subsample increment Bit[7:4]: Debug mode Bit[3:0]: HSYNC start point[11:8] Bit[7:0]: HSYNC start point[7:0] Bit[7:4]: Debug mode Bit[3:0]: HSYNC width[11:8] Bit[7:4]: Debug mode Bit[3:0]: HSYNC width[7:8] Timing Control Bit[7:3]: Debug mode Bit[2]: ISP vflip Bit[1]: Sensor vflip

0x3820

TIMING TC REG20

0x40

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-13

table 7-7
address

timing control registers (sheet 3 of 3)
register name default value R/W description
Timing Control Bit[7:6]: Debug mode Bit[5]: JPEG enable Bit[4:3]: Debug mode Bit[2]: ISP mirror Bit[1]: Sensor mirror Bit[0]: Horizontal binning enable

0x3821

TIMING TC REG21

0x00

RW

7.8 AEC/AGC power down domain control [0x3A00 ~ 0x3A25]
table 7-8
address

AEC/AGC power down domain control registers (sheet 1 of 4)
register name default value R/W description
AEC System Control (0: disable; 1: enable) Bit[7]: Debug mode Bit[6]: Less one line enable Bit[5]: Band function enable Bit[4]: Less 1 band enable Bit[3]: Start selection Bit[2]: Night mode Bit[1]: New balance function Bit[0]: Freeze Minimum Exposure Output Limit Bit[7:0]: Minimum exposure 60Hz Maximum Exposure Output Limit Bit[7:0]: Maximum exposure[15:8] 60Hz Maximum Exposure Output Limit Bit[7:0]: Maximum exposure[7:0] Debug Mode

0x3A00

AEC CTRL00

0x78

RW

0x3A01 0x3A02 0x3A03 0x3A04

AEC MIN EXPOSURE AEC MAX EXPO (60HZ) AEC MAX EXPO (60HZ) DEBUG MODE

0x01 0x3D 0x80 –

RW RW RW –

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-8
address

AEC/AGC power down domain control registers (sheet 2 of 4)
register name default value R/W description
AEC System Control 2 Bit[7]: Debug mode Bit[6]: frame insert 0: In night mode, insert frame disable 1: In night mode, insert frame enable Bit[5]: Step auto enable 0: Step manual mode 1: Step auto mode Bit[4:0]: Step auto ratio In step auto mode, step ratio setting to adjust speed AEC System Control 3 Bit[7:5]: Debug mode Bit[4:0]: Step manual setting 1 Step manual Increase mode fast step AEC Manual Step Register Bit[7:4]: Step manual setting 2 Step manual, slow step Bit[3:0]: Step manual setting 3 Step manual, decrease mode fast step 50Hz Band Width Bit[7:2]: Debug mode Bit[1:0]: B50 step[9:8] 50Hz Band Width Bit[7:0]: B50 step[7:0] 60Hz Band Width Bit[7:2]: Debug mode Bit[1:0]: B60 step[13:8] 60Hz Band Width Bit[7:0]: B60 step[7:0] Bit[7:4]: E1 max Decimal line high limit zone Bit[3:0]: E1 min Decimal line low limit zone 60Hz Max Bands in One Frame Bit[7:6]: Debug mode Bit[5:0]: B60 max 50Hz Max Bands in One Frame Bit[7:6]: Debug mode Bit[5:0]: B50 max

0x3A05

AEC CTRL05

0x30

RW

0x3A06

AEC CTRL06

0x10

RW

0x3A07

AEC CTRL07

0x18

RW

0x3A08

AEC B50 STEP

0x01

RW

0x3A09

AEC B50 STEP

0x27

RW

0x3A0A

AEC B60 STEP

0x00

RW

0x3A0B

AEC B60 STEP

0xF6

RW

0x3A0C

AEC CTRL0C

0xE4

RW

0x3A0D

AEC CTRL0D

0x08

RW

0x3A0E

AEC CTRL0E

0x06

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-15

table 7-8
address
0x3A0F 0x3A10 0x3A11 0x3A12

AEC/AGC power down domain control registers (sheet 3 of 4)
register name
AEC CTRL0F AEC CTRL10 AEC CTRL11 DEBUG MODE

default value
0x78 0x68 0xD0 –

R/W
RW RW RW –

description
Stable Range High Limit (Enter) Bit[7:0]: WPT Stable Range Low Limit (Enter) Bit[7:0]: BPT Step Manual Mode, Fast Zone High Limit Bit[7:0]: VPT high Debug Mode Bit[7]: Debug mode Bit[6]: Pre-gain enable Bit[5:0]: Pre-gain value 0x40 = 1x 50Hz Maximum Exposure Output Limit Bit[7:4]: Debug mode Bit[3:0]: Max exposure[15:8] 50Hz Maximum Exposure Output Limit Bit[7:0]: Max exposure[7:0] Debug Mode Gain Base When in Night Mode Bit[7:2]: Debug mode Bit[1:0]: Gain night threshold 00: 00 01: 10 10: 30 11: 70 Gain Output Top Limit Bit[7:2]: Debug mode Bit[1:0]: AEC gain ceiling[9:8] Real gain format Gain Output Top Limit Bit[7:0]: AEC gain ceiling[7:0] Real gain format Reserved Default Value for This Register Bit[7:0]: Difference minimal Stable Range High Limit (Go Out) Bit[7:0]: WPT2 Exposure Values Added When Strobe is On Bit[7:0]: AEC LED add row[15:8] Exposure Values Added When Strobe is On Bit[7:0]: AEC LED add row[7:0]

0x3A13

AEC CTRL13

0x40

RW

0x3A14

AEC MAX EXPO (50HZ) AEC MAX EXPO (50HZ) DEBUG MODE

0x0E

RW

0x3A15 0x3A16

0x40 –

RW –

0x3A17

AEC CTRL17

0x01

RW

0x3A18

AEC GAIN CEILING

0x03

RW

0x3A19

AEC GAIN CEILING

0xE0

RW

0x3A1A 0x3A1B 0x3A1C 0x3A1D

AEC DIFF MIN AEC CTRL1B LED ADD ROW LED ADD ROW

0x04 0x78 0x06 0x18

RW RW RW RW

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PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-8
address
0x3A1E 0x3A1F

AEC/AGC power down domain control registers (sheet 4 of 4)
register name
AEC CTRL1E AEC CTRL1F

default value
0x68 0x40

R/W
RW RW

description
Stable Range Low Limit (Go Out) Bit[7:0]: BPT2 Step Manual Mode, Fast Zone Low Limit Bit[7:0]: VPT low Bit[7:3]: Debug mode Bit[2]: Strobe option Bit[1:0]: Debug mode Bit[7]: Debug mode Bit[6:4]: Insert frame number Bit[3:0]: Debug mode Debug Mode Bit[7:5]: Debug mode Bit[4:2]: Freeze counter Bit[1:0]: Debug mode

0x3A20

AEC CTRL20

0x20

RW

0x3A21 0x3A22~ 0x3A24 0x3A25

AEC CTRL21

0x78

RW

DEBUG MODE





AEC CTRL25

0x00

RW

7.9 strobe control [0x3B00 ~ 0x3B0C]
table 7-9
address

strobe registers (sheet 1 of 2)
register name default value R/W description
Bit[7]: Strobe request on/off 0: Off 1: On Bit[6]: Strobe pulse reverse Bit[3:2]: width_in_xenon Bit[1:0]: Strobe mode 00: Xenon 01: LED1 10: LED2 11: LED3 Bit[7:0]: FREX exposure time[23:16] Bit[7:6]: Debug mode Bit[5:0]: Shutter delay time[12:8] Bit[7:0]: Shutter delay time[7:0] Unit: 64x SCLK cycle Bit[7:0]: FREX exposure time[15:8] Bit[7:0]: FREX exposure time[7:0] Unit: Tline

0x3B00

STROBE CTRL

0x00

RW

0x3B01 0x3B02 0x3B03 0x3B04 0x3B05

FREX EXPOSURE 02 FREX SHUTTER DELAY 01 FREX SHUTTER DELAY 00 FREX EXPOSURE 01 FREX EXPOSURE 00

0x00 0x08 0x00 0x04 0x00

RW RW RW RW RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-17

table 7-9
address
0x3B06

strobe registers (sheet 2 of 2)
register name
FREX CTRL 07

default value
0x04

R/W
RW

description
Bit[7:4]: FREX frame delay Bit[3:0]: Strobe width[3:0] FREX Mode Selection Bit[1:0]: FREX mode 00: FREX strobe mode0 01: FREX strobe mode1 1x: Rolling strobe FREX Request FREX HREF Delay Bit[7:3]: Debug mode Bit[2:0]: FREX precharge length 000: 1/16 Tline 001: 1/8 Tline 010: 1/4 Tline 011: 1/2 Tline 100: 1 Tline 101: 2 Tline 110: 4 Tline 111: 8 Tline Bit[7:0]: Strobe width[19:12] Bit[7:0]: Strobe width[11:4]

0x3B07

FREX MODE

0x08

RW

0x3B08 0x3B09

FREX REQUEST FREX HREF DELAY

0x00 0x02

RW RW

0x3B0A

FREX RST LENGTH

0x04

RW

0x3B0B 0x3B0C

STROBE WIDTH STROBE WIDTH

0x00 0x3D

RW RW

7.10 50/60Hz detector control [0x3C00 ~ 0x3C1E]
table 7-10
address

5060Hz detector registers (sheet 1 of 3)
register name default value R/W description
Bit[7:6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1:0]: Debug mode Time counter threshold divisor enable Low limit enable Debug mode Band50 default value Time counter threshold 00: 1s 01: 2s 10: 4s 11: 8s

0x3C00

5060HZ CTRL00

0x00

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-10
address

5060Hz detector registers (sheet 2 of 3)
register name default value R/W description
Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3:0]: Band manual enable Band begin reset enable Sum auto mode enable Band counter enable Band counter Counter threshold for band change

0x3C01

5060HZ CTRL01

0x00

RW

0x3C02

5060HZ CTRL02

0x00

RW

Bit[7:6]: Debug mode Bit[5:0]: Low light threshold No detection under low light Bit[7:6]: Low light limit mode Bit[7:0]: Counter threshold for low light Bit[7:0]: Threshold for low sum Bit[7:0]: Threshold for high sum Bit[7:0]: Lightmeter1 threshold[15:8] Bit[7:0]: Lightmeter1 threshold[7:0] Bit[7:0]: Lightmeter2 threshold[15:8] Bit[7:0]: Lightmeter2 threshold[7:0] Bit[7:0]: Sample number[15:8] Bit[7:0]: Sample number[7:0] Bit[7:4]: Band counter Bit[1]: Sign bit of sum50/60 Bit[0]: Band50/60 0: 60Hz light 1: 50Hz light Bit[7:5]: Debug mode Bit[4:0]: Sum50[28:24] Bit[7:0]: Sum50[23:16] Bit[7:0]: Sum50[15:8] Bit[7:0]: Sum50[7:0] Bit[7:5]: Debug mode Bit[4:0]: Sum60[28:24] Bit[7:0]: Sum60[23:16] Bit[7:0]: Sum60[15:8]

0x3C03 0x3C04 0x3C05 0x3C06 0x3C07 0x3C08 0x3C09 0x3C0A 0x3C0B

5060HZ CTRL03 5060HZ CTRL04 5060HZ CTRL05 LIGHT METER1 THRESHOLD LIGHT METER1 THRESHOLD LIGHT METER2 THRESHOLD LIGHT METER2 THRESHOLD SAMPLE NUMBER SAMPLE NUMBER

0x00 0x20 0x70 0x00 0x00 0x01 0x2C 0x4E 0x1F

RW RW RW RW RW RW RW RW RW

0x3C0C

SIGMADELTA CTRL0C



R

0x3C0D 0x3C0E 0x3C0F 0x3C10 0x3C11 0x3C12 0x3C13

SUM 50 SUM 50 SUM 50 SUM 50 SUM 60 SUM 60 SUM 60

– – – – – – –

R R R R R R R

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-19

table 7-10
address
0x3C14 0x3C15 0x3C16 0x3C17 0x3C18 0x3C19 0x3C1A 0x3C1B 0x3C1C 0x3C1D 0x3C1E

5060Hz detector registers (sheet 3 of 3)
register name
SUM 60 SUM 50 60 SUM 50 60 BLOCK COUNTER BLOCK COUNTER B6 B6 LIGHTMETER OUTPUT LIGHTMETER OUTPUT LIGHTMETER OUTPUT SUM THRESHOLD

default value
– – – – – – – – – – –

R/W
R R R R R R R R R R R

description
Bit[7:0]: Sum60[7:0] Bit[7:0]: Sum50/60[15:8] Bit[7:0]: Sum50/60[7:0] Bit[7:0]: Block counter[15:8] Bit[7:0]: Block counter[7:0] Bit[7:0]: B6[15:8] Bit[7:0]: B6[7:0] Bit[7:4]: Debug mode Bit[3:0]: Light meter output[19:16] Bit[7:0]: Light meter output[15:8] Bit[7:0]: Light meter output[7:0] Sum Threshold

7.11 OTP control [0x3D00 ~ 0x3D21]
table 7-11
address
0x3D00 0x3D01 0x3D02 0x3D03 0x3D04 0x3D05 0x3D06 0x3D07 0x3D08 0x3D09 0x3D0A 0x3D0B

OTP control functions (sheet 1 of 2)
register name
OTP DATA00 OTP DATA01 OTP DATA02 OTP DATA03 OTP DATA04 OTP DATA05 OTP DATA06 OTP DATA07 OTP DATA08 OTP DATA09 OTP DATA0A OTP DATA0B

default value
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

R/W
RW RW RW RW RW RW RW RW RW RW RW RW

description
OTP Dump/Load Data00 OTP Dump/Load Data01 OTP Dump/Load Data02 OTP Dump/Load Data03 OTP Dump/Load Data04 OTP Dump/Load Data05 OTP Dump/Load Data06 OTP Dump/Load Data07 OTP Dump/Load Data08 OTP Dump/Load Data09 OTP Dump/Load Data0a OTP Dump/Load Data0b

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-11
address
0x3D0C 0x3D0D 0x3D0E 0x3D0F 0x3D10 0x3D11 0x3D12 0x3D13 0x3D14 0x3D15 0x3D16 0x3D17 0x3D18 0x3D19 0x3D1A 0x3D1B 0x3D1C 0x3D1D 0x3D1E 0x3D1F

OTP control functions (sheet 2 of 2)
register name
OTP DATA0C OTP DATA0D OTP DATA0E OTP DATA0F OTP DATA10 OTP DATA11 OTP DATA12 OTP DATA13 OTP DATA14 OTP DATA15 OTP DATA16 OTP DATA17 OTP DATA18 OTP DATA19 OTP DATA1A OTP DATA1B OTP DATA1C OTP DATA1D OTP DATA1E OTP DATA1F

default value
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

R/W
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

description
OTP Dump/Load Data0c OTP Dump/Load Data0d OTP Dump/Load Data0e OTP Dump/Load Data0f OTP Dump/Load Data10 OTP Dump/Load Data11 OTP Dump/Load Data12 OTP Dump/Load Data13 OTP Dump/Load Data14 OTP Dump/Load Data15 OTP Dump/Load Data16 OTP Dump/Load Data17 OTP Dump/Load Data18 OTP Dump/Load Data19 OTP Dump/Load Data1A OTP Dump/Load Data1B OTP Dump/Load Data1C OTP Dump/Load Data1D OTP Dump/Load Data1E OTP Dump/Load Data1F Bit[7]: OTP program busy Bit[6:2]: Debug mode Bit[1]: OTP program speed 0: Fast 1: Slow Bit[0]: OTP program enable Bit[7]: Bit[1]: OTP read busy OTP read speed 0: Fast 1: Slow OTP read enable

0x3D20

OTP PROGRAM CTRL

0x00

RW

0x3D21

OTP READ CTRL

0x00

RW Bit[0]:

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-21

7.12 MC control [0x3F00 ~ 0x3F0D]
table 7-12
address

MC registers (sheet 1 of 3)
register name default value R/W description
Bit[7:5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Debug mode DW8051 manual reset enable DW8051 manual reset IRAM manual reset enable IRAM manual reset Soft reset MCU 0: Debug mode 1: Reset MCU

0x3F00

MC CTRL00

0x00

RW

0x3F01

MC INTERRUPT MASK0

0x00

RW

Bit[7:0]: Mask0 for interrupt 0: Disable interrupt bit 1: Enable interrupt bit Bit[7:0]: Mask1 for interrupt 0: Disable interrupt bit 1: Enable interrupt bit Bit[7:0]: Set high byte for SCCB address that will trigger interrupt when read Bit[7:0]: Set low byte for SCCB address that will trigger interrupt when read Bit[7:0]: Set high byte for SCCB address that will trigger interrupt when written Bit[7:0]: Set low byte for SCCB address that will trigger interrupt when written Bit[7:6]: Interrupt1[7] source selection 0x: AEC done 10: Debug mode 11: DVP HREF falling edge Bit[5:4]: Interrupt1[6] source selection 00: ISP average done 01: FREX rising edge 10: Debug mode 11: DVP VSYNC falling edge Bit[3:2]: Interrupt1[5] source selection 00: AEC trigger 01: FREX falling edge 10: MIPI frame end 11: DVP VSYNC rising edge Bit[1:0]: Interrupt1[4] source selection 0x: JEPG over size 10: MIPI line end 11: DVP HREF rising edge

0x3F02

MC INTERRUPT MASK1 MC READ INTERRUPT ADDRESS MC READ INTERRUPT ADDRESS MC WRITE INTERRUPT ADDRESS MC WRITE INTERRUPT ADDRESS

0x00

RW

0x3F03 0x3F04 0x3F05 0x3F06

0x70 0x00 0x70 0x04

RW RW RW RW

0x3F08

MC INTERRUPT SOURCE SELECTION1

0x00

RW

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-12
address

MC registers (sheet 2 of 3)
register name default value R/W description
Bit[7:6]: Interrupt1[3] source selection 0x: Debug mode 11: SRM operation start Bit[5:4]: Interrupt1[2] source selection 0x: Debug mode 11: SRM operation done Bit[3:2]: Interrupt1[1] source selection 0x: Debug mode 11: DVP frame counter change Bit[1:0]: Interrupt1[0] source selection 0x: BLC SOF 11: Debug mode Bit[7:6]: Interrupt0[7] source selection 00: JFIFO over flow 01: ISP end frame 10: SFIFO end of frame 11: JFIFO end frame Bit[5:4]: Interrupt0[6] source selection 0x: JFIFO end of image 10: F1 FIFO write 11: VFIFO ready Bit[3:2]: Interrupt0[5] source selection 00: ISP end of frame 01: SFIFO end of frame 10: JFIFO end of frame 11: VFIFO end of frame Bit[1:0]: Interrupt0[4] source selection 00: ISP start of frame 01: SFIFO start of frame 10: JFIFO start of frame 11: VFIFO start of frame

0x3F09

MC INTERRUPT SOURCE SELECTION2

0x00

RW

0x3F0A

MC INTERRUPT SOURCE SELECTION3

0x00

RW

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table 7-12
address

MC registers (sheet 3 of 3)
register name default value R/W description
Bit[7:6]: Interrupt0[3] source selection 0x: AFC done 10: HREF falling edge 11: BIST done Bit[5:4]: Interrupt0[2] source selection 00: AWB done 01: ISP start of frame 10: SFIFO start of frame 11: JFIFO start of frame Bit[3:2]: Interrupt0[1] source selection 00: VFIFO full 01: ISP FC SOF 10: f2_fifo_wr 11: Write a specific address Bit[1:0]: Interrupt0[0] source selection 00: VFIFO empty 01: ISP line 10: ISP end of frame 11: Read a specific address Bit[7:0]: Interrupt0 status indication Bit[7:0]: Interrupt1 status indication

0x3F0B

MC INTERRUPT SOURCE SELECTION4

0x00

RW

0x3F0C 0x3F0D

MC INTERRUPT0 STATUS MC INTERRUPT1 STATUS

– –

R R

7.13 BLC control [0x4000 ~ 0x4033]
table 7-13
address

BLC registers (sheet 1 of 3)
register name default value R/W description
BLC Control 00 (0: disable; 1: enable) Bit[7:3]: Debug mode Bit[2]: Apply2blackline Bit[1]: Black line average frame Bit[0]: BLC enable Bit[7:6]: Debug mode Bit[5:0]: BLC start line

0x4000

BLC CTRL00

0x89

RW

0x4001

BLC CTRL01

0x00

RW

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-13
address

BLC registers (sheet 2 of 3)
register name default value R/W description
Bit[7]: Format change enable BLC update when format changes Bit[6]: BLC auto enable 0: Manual 1: Auto Bit[5:0]: Reset frame number Frame number BLC do after reset Bit[7]: BLC redo enable Write 1 to this bit will trigger a BLC redo N frames begin, where N is 0x4003[5:0] Bit[6]: BLC freeze Bit[5:0]: Manual frame number Bit[7:0]: BLC line number Specify the line number BLC process Bit[7:2]: Debug mode Bit[1]: BLC always update 0: Normal freeze 1: BLC always update Bit[0]: Debug mode Debug Mode Bit[7:5]: Debug mode Bit[4:3]: Window selection 00: Full image 01: A windows not contain the first 16 pixels and the end 16 pixels 10: A windows not contain the first 1/16 image and the end 1/16 image 11: A windows not contain the first 1/8 image and the end 1/8 image Bit[2:0]: Debug mode Debug Mode Bit[7:0]: BLC black level target at 10-bit range Debug Mode Bit[7:0]: Blacklevel00[15:8] With 3 decimal Bit[7:0]: Blacklevel00[7:0] With 3 decimal

0x4002

BLC CTRL02

0x45

RW

0x4003

BLC CTRL03

0x08

RW

0x4004

BLC CTRL04

0x08

RW

0x4005

BLC CTRL05

0x18

RW

0x4006

DEBUG MODE





0x4007

BLC CTRL07

0x00

RW

0x4008 0x4009 0x400C~ 0x402B 0x402C 0x402D

DEBUG MODE BLACK LEVEL DEBUG MODE BLACK LEVEL00 BLACK LEVEL00

– 0x10 – 0x00 0x00

– RW – RW RW

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table 7-13
address
0x402E 0x402F 0x4030 0x4031 0x4032 0x4033

BLC registers (sheet 3 of 3)
register name
BLACK LEVEL01 BLACK LEVEL01 BLACK LEVEL10 BLACK LEVEL10 BLACK LEVEL11 BLACK LEVEL11

default value
0x00 0x00 0x00 0x00 0x00 0x00

R/W
RW RW RW RW RW RW

description
Bit[7:0]: Blacklevel01[15:8] With 3 decimal Bit[7:0]: Blacklevel01[7:0] With 3 decimal Bit[7:0]: Blacklevel10[15:8] With 3 decimal Bit[7:0]: Blacklevel10[7:0] With 3 decimal Bit[7:0]: Blacklevel11[15:8] With 3 decimal Bit[7:0]: Blacklevel11[7:0] With 3 decimal

7.14 frame control [0x4201 ~ 0x4202]
table 7-14
address

frame control registers
register name default value R/W description
Control Passed Frame Number When both ON and OFF number set to 0x00, frame control is in bypass mode Bit[7:4]: Debug mode Bit[3:0]: Frame ON number Control Masked Frame Number When both ON and OFF number set to 0x00, frame control is in bypass mode Bit[7:4]: Debug mode BIT[3:0]: Frame OFF number

0x4201

FRAME CTRL01

0x00

R/W

0x4202

FRAME CTRL02

0x00

R/W

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.15 format control [0x4300 ~ 0x430D]
table 7-15
address

format control registers (sheet 1 of 5)
register name default value R/W description
Format Control 00 Bit[7:4]: Output format of formatter module 0x0: RAW Bit[3:0]: Output sequence 0x0: BGBG... / GRGR... 0x1: GBGB... / RGRG... 0x2: GRGR... / BGBG... 0x3: RGRG... / GBGB... 0x4~0xF: Not allowed 0x1: Y8 Bit[3:0]: Does not matter 0x2: YUV444/RGB888 (not available for full resolution) Bit[3:0]: Output sequence 0x0: YUVYUV..., or GBRGBR... 0x1: YVUYVU..., or GRBGRB... 0x2: UYVUYV..., or BGRBGR... 0x3: VYUVYU..., or RGBRGB... 0x4: UVYUVY..., or BRGBRG... 0x5: VUYVUY..., or RBGRBG... 0x6~0xE: Not allowed 0xF: UYVUYV..., or BGRBGR... 0x3: YUV422 Bit[3:0]: Output sequence 0x0: YUYV... 0x1: YVYU... 0x2: UYVY... 0x3: VYUY... 0x4~0xE: Not allowed 0xF: UYVY... 0x4: YUV420 Bit[3:0]: Output sequence 0x0: YYYY... / YUYV... 0x1: YYYY... / YVYU... 0x2: YYYY... / UYVY... 0x3: YYYY... / VYUY... 0x4: YUYV... / YYYY... 0x5: YVYU... / YYYY...

0x4300

FORMAT CONTROL 00

0xF8

RW

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table 7-15
address

format control registers (sheet 2 of 5)
register name default value R/W description
0x6: UYVY... / YYYY... 0x7: VYUY... / YYYY... 0x8~0xE: Not allowed 0xF: YYYY... / UYVY... YUV420 (for MIPI only) Bit[3:0]: Output sequence 0x0~0xD: Not allowed 0xE: VYYVYY... / UYYUYY... 0xF: UYYUYY... / VYYVYY... RGB565 Bit[3:0]: Output sequence 0x0: {b[4:0],g[5:3]}, {g[2:0],r[4:0]} 0x1: {r[4:0],g[5:3]}, {g[2:0],b[4:0]} 0x2: {g[4:0],r[5:3]}, {r[2:0],b[4:0]} 0x3: {b[4:0],r[5:3]}, {r[2:0],g[4:0]} 0x4: {g[4:0],b[5:3]}, {b[2:0],r[4:0]} 0x5: {r[4:0],b[5:3]}, {b[2:0],g[4:0]} 0x6~0xE: Not allowed 0xF: {g[2:0],b[4:0]}, {r[4:0],g[5:3]} RGB555 format 1 Bit[3:0]: Output sequence 0x0: {b[4:0],g[4:2]}, {g[1:0],1'b0,r[4:0]} 0x1: {r[4:0],g[4:2]}, {g[1:0],1'b0,b[4:0]} 0x2: {g[4:0],r[4:2]}, {r[1:0],1'b0,b[4:0]} 0x3: {b[4:0],r[4:2]}, {r[1:0],1'b0,g[4:0]} 0x4: {r[4:0],b[4:2]}, {b[1:0],1'b0,g[4:0]} 0x5: {g[4:0],b[4:2]}, {b[1:0],1'b0,r[4:0]} 0x6~0xE: Not allowed 0xF: {g[1:0],1'b0,b[4:0]}, {r[4:0],g[4:2]} RGB555 format 2 Bit[3:0]: Output sequence 0x0: {1'b0,b[4:0],g[4:3]}, {g[2:0],r[4:0]}

0x5:

0x6:

0x7:

0x8:

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-15
address

format control registers (sheet 3 of 5)
register name default value R/W description
0x1: {1'b0,r[4:0],g[4:2]}, {g[2:0],b[4:0]} 0x2: {1'b0,g[4:0],r[4:2]}, {r[2:0],b[4:0]} 0x3: {1'b0,b[4:0],r[4:2]}, {r[2:0],g[4:0]} 0x4: {1'b0,r[4:0],b[4:2]}, {b[2:0],g[4:0]} 0x5: {1'b0,g[4:0],b[4:2]}, {b[2:0],r[4:0]} 0x6: {b[4:0],1'b0,g[4:3]}, {g[2:0],r[4:0]} 0x7: {r[4:0],1'b0,g[4:2]}, {g[2:0],b[4:0]} 0x8: {g[4:0],1'b0,r[4:2]}, {r[2:0],b[4:0]} 0x9: {b[4:0],1'b0,r[4:2]}, {r[2:0],g[4:0]} 0xA: {r[4:0],1'b0,b[4:2]}, {b[2:0],g[4:0]} 0xB: {g[4:0],1'b0,b[4:2]}, {b[2:0],r[4:0]} 0xC~0xF: Not allowed 0x9: RGB444 format 1 Bit[3:0]: Output sequence 0x0: {1'b0,b[3:0],2'h0,g[3]}, {g[2:0],1'b0,r[3:0]} 0x1: {1'b0,r[3:0],2'h0,g[3]}, {g[2:0],1'b0,b[3:0]} 0x2: {1'b0,g[3:0],2'h0,r[3]}, {r[2:0],1'b0,b[3:0]} 0x3: {1'b0,b[3:0],2'h0,r[3]}, {r[2:0],1'b0,g[3:0]} 0x4: {1'b0,r[3:0],2'h0,b[3]}, {b[2:0],1'b0,g[3:0]} 0x5: {1'b0,g[3:0],2'h0,b[3]}, {b[2:0],1'h0,r[3:0]} 0x6: {b[3:0],1'b0,g[3:1]}, {g[0],2'h0,r[3:0],1'b0} 0x7: {r[3:0],1'b0,g[3:1]}, {g[0],2'h0,b[3:0],1'b0} 0x8: {g[3:0],1'b0,r[3:1]}, {r[0],2'h0,b[3:0],1'b0} 0x9: {b[3:0],1'b0,r[3:1]}, {r[0],2'h0,g[3:0],1'b0} 0xA: {r[3:0],1'b0,b[3:1]}, {b[0],2'h0,g[3:0],1'b0} 0xB: {g[3:0],1'b0,b[3:1]}, {b[0],2'h0,r[3:0],1'b0} 0xC~0xE: Not allowed

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table 7-15
address

format control registers (sheet 4 of 5)
register name default value R/W description
0xF: {g[0],2'h2,b[3:0],1'b1}, {r[3:0],1'b1,g[3:1]} 0xA: RGB444 format 2 Bit[3:0]: Output sequence 0x0: {4'b0,b[3:0]}, {g[3:0],r[3:0]} 0x1: {4'b0,r[3:0]}, {g[3:0],b[3:0]} 0x2: {4'b0,b[3:0]}, {r[3:0],g[3:0]} 0x3: {4'b0,r[3:0]}, {b[3:0],g[3:0]} 0x4: {4'b0,g[3:0]}, {b[3:0],r[3:0]} 0x5: {4'b0,g[3:0]}, {r[3:0],b[3:0]} 0x6: {b[3:0],g[3:0],2'h0}, {r[3:0],b[3:0],2'h0,g[3: 0],r[3:0],2'h0} 0x7: {r[3:0],g[3:0],2'h0}, {b[3:0],r[3:0],2'h0,g[3: 0],b[3:0],2'h0} 0x8: {b[3:0],r[3:0],2'h0}, {g[3:0],b[3:0],2'h0,r[3: 0],g[3:0],2'h0} 0x9: {r[3:0],b[3:0],2'h0}, {g[3:0],r[3:0],2'h0,b[3: 0],g[3:0],2'h0} 0xA: {g[3:0],b[3:0],2'h0}, {r[3:0],g[3:0],2'h0,b[3: 0],r[3:0],2'h0} 0xB: {g[3:0],r[3:0],2'h0}, {b[3:0],g[3:0],2'h0,r[3: 0],b[3:0],2'h0} 0xC~0xF: Not allowed 0xB~0xE: Not allowed 0xF: Bypass formatter module (not recommended) Bit[3:0]: Output format 0x8: Raw 0x9: YUV422 0xA: YUV444 0xE: VYYVYY.../UYYUYY 0xF: UYYUYY.../VYYVYY

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-15
address

format control registers (sheet 5 of 5)
register name default value R/W description
Format Control 01 Bit[1:0]: YUV422 UV control 00: U/V generated from average 01: U/V generated from first pixel 10: Not valid 11: U/V generated from second pixel Bit[7:2]: Debug mode Bit[1:0]: Y max clip value[9:8] Bit[7:0]: Y max clip value[7:0] Bit[7:2]: Debug mode Bit[1:0]: Y min clip value[9:8] Bit[7:0]: Y min clip value[7:0] Bit[7:2]: Debug mode Bit[1:0]: U max clip value[9:8] Bit[7:0]: U max clip value[7:0] Bit[7:2]: Debug mode Bit[1:0]: U min clip value[9:8] Bit[7:0]: U min clip value[7:0] Bit[7:2]: Debug mode Bit[1:0]: V max clip value[9:8] Bit[7:0]: V max clip value[7:0] Bit[7:2]: Debug mode Bit[1:0]: V min clip value[9:8] Bit[7:0]: V min clip value[7:0]

0x4301

FORMAT CONTROL 01

0x00

RW

0x4302 0x4303 0x4304 0x4305 0x4306 0x4307 0x4308 0x4309 0x430A 0x430B 0x430C 0x430D

YMAX VALUE YMAX VALUE YMIN VALUE YMIN VALUE UMAX VALUE UMAX VALUE UMIN VALUE UMIN VALUE VMAX VALUE VMAX VALUE VMIN VALUE VMIN VALUE

0x03 0xFF 0x00 0x00 0x03 0xFF 0x00 0x00 0x03 0xFF 0x00 0x00

RW RW RW RW RW RW RW RW RW RW RW RW

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7.16 JPEG control [0x4400 ~ 0x4431]
table 7-16
address

JPEG control registers (sheet 1 of 3)
register name default value R/W description
Bit[7]: input_format 0: YUV420 1: YUV422 Bit[6:0]: JFIFO read speed control Bit[7:4]: SFIFO output buffer speed control Bit[3]: Read SRAM enable when blanking 0: Disable 1: Enable Bit[2]: Read SRAM at first blanking 0: Disable 1: Enable Bit[1:0]: SFIFO read speed control SFIFO output control mode 0: Control by HREF and valid which before scale down 1: Control by input HREF and valid Bit[6:4]: SOF control 001: Start at the first valid HREF 010: Start at the eighth valid HREF Bit[3:0]: SFIFO output buffer speed control at last stripe Bit[7]: Memory select 0: Select ROM QT 1: Select SRAM QT MPEG enable Enable zero stuff Enable Huffman table output Rounding enable for C Rounding enable for Y Input shift 128 select for C Input shift 128 select for Y Bit[7]:

0x4400

JPEG CTRL00

0x81

RW

0x4401

JPEG CTRL01

0x01

RW

0x4402

JPEG_CTRL02

0x10

RW

0x4403

JPEG CTRL03

0x33

RW

Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Bit[7]: Bit[6]: Bit[5]: Bit[4]:

0x4404

JPEG CTRL04

0x24

RW

jfifo_pwrdn SFIFO PWRDN Header output enable Enable gated clock 0: Disable gated clock 1: Enable gated clock Bit[3]: Substitute 0xFF to 0xFE in QT Bit[2:0]: Quantization rounding bias: Set value = Bias/8 Bit[7:0]: QZ out truncate for Y

0x4405

JPEG CTRL05

0x40

RW

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table 7-16
address
0x4406 0x4407

JPEG control registers (sheet 2 of 3)
register name
JPEG CTRL06 JPEG CTRL07

default value
0x40 0x0C

R/W
RW RW

description
Bit[7:0]: QZ out truncate for C Bit[7]: Enable read QTA auto increment Bit[5:0]: QS Quantization scale Bit[7]: Scalado mode enable 0: Normal 1: Insert 0xFF after EOB Bit[6]: JPEG size manual enable Bit[5:4]: Debug mode Bit[3]: Replace 0xFF to 0xFE in comment data Bit[2]: Cut 0xD9 at the end of frame Bit[1]: EOI generation enable Bit[0]: ISI insert Bit[7:0]: D9 data Bit[7:0]: JFIFO output delay Bit[5]: Dummy read speed manual mode Bit[4:0]: SFIFO SOF delay Bit[7:0]: Dummy read speed Debug Mode Bit[7:0]: QT data Bit[7:0]: QT address Bit[7:0]: ISI data Bit[7:4]: Debug mode Bit[3]: D9 odd (read only) Bit[2]: Reset counter write 0: Debug mode 1: Reset counter Bit[1]: ISO EOF Bit[7:0]: JPEG length[23:16] Bit[7:0]: JPEG length[15:8] Bit[7:0]: JPEG length[7:0] Bit[7:1]: Debug mode Bit[0]: JFIFO overflow indicator Debug Mode

0x4408

JPEG ISI CTRL

0x00

RW

0x4409 0x440A 0x440B 0x440C 0x440D~ 0x440F 0x4410 0x4411 0x4412

JPEG CTRL09 JPEG CTRL0A JPEG CTRL0B JPEG CTRL0C DEBUG MODE JPEG QT DATA JPEG QT ADDR JPEG ISI DATA

0x00 0x4E 0x16 0x00 – 0x00 0x00 0x00

RW RW RW RW – RW RW RW

0x4413

JPEG ISI CTRL



RO

0x4414 0x4415 0x4416 0x4417 0x4418~ 0x4419

JPEG LENGTH JPEG LENGTH JPEG LENGTH JFIFO OVERFLOW DEBUG MODE

– – – – –

RO RO RO RO –

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table 7-16
address
0x4420~ 0x442F 0x4430 0x4431

JPEG control registers (sheet 3 of 3)
register name
JPEG COMMENT JPEG COMMENT JPEG COMMENT

default value
0x00 0x00 0xFE

R/W
RW RW RW

description
JPEG Comment Data Embedded in JPEG Data Comment Length Two bytes align Comment Data Marker

7.17 VFIFO control [0x4600 ~ 0x460D]
table 7-17
address

VFIFO registers (sheet 1 of 2)
register name default value R/W description
VFIFO Control 00 Bit[7:6]: Reserved Bit[5]: Compression output fixed height enable 0: In compression mode2, compression height is different in each frame 1: In compression mode2, compression height is fixed in each frame Debug Mode Compression Output Width High Byte Compression Output Width Low Byte Compression Output Height High Byte Compression Output Height Low Byte Debug Mode

0x4600

VFIFO CTRL00

0x80

RW

0x4601 0x4602 0x4603 0x4604 0x4605 0x4606~ 0x460B

DEBUG MODE VFIFO HSIZE VFIFO HSIZE VFIFO VSIZE VFIFO HSIZE DEBUG MODE

– 0x04 0x00 0x03 0x00 –

– RW RW RW RW –

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-17
address

VFIFO registers (sheet 2 of 2)
register name default value R/W description
Bit[7:4]: JPEG dummy data pad speed Bit[2]: Footer disable JPEG footer disable 0: In jpg_mode2 footer will be added in the last six bytes of each frame 1: Disable footer Bit[1]: PCLK manual enable 0: DVP PCLK divider control by auto mode 1: DVP PCLK divider control by 0x3824[4:0] Dummy Data

0x460C

VFIFO CTRL0C

0x20

RW

0x460D

VFIFO CTRL0D

0x00

RW

7.18 DVP control [0x4709 ~ 0x4745]
table 7-18
address
0x4709 0x470A 0x470B 0x470C~ 0x4710 0x4711

DVP control registers (sheet 1 of 4)
register name
DVP VYSNC WIDTH0 DVP VYSNC WIDTH1 DVP VYSNC WIDTH2 DEBUG MODE PAD LEFT CTRL

default value
0x02 0x00 0x01 – 0x00

R/W
RW RW RW – RW

description
VSYNC Width Line Unit Bit[7:0]: VSYNC width PCLK unit[15:8] Bit[7:0]: VSYNC width PCLK unit[7:0] Debug Mode HSYNC Mode Left Padding Pixel Counter Add padding data at start of a line HSYNC Mode Right Padding Pixel Counter Add padding data at end of a line

0x4712

PAD RIGHT CTRL

0x00

RW

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version 2.03

7-35

table 7-18
address

DVP control registers (sheet 2 of 4)
register name default value R/W description
Bit[7:3]: Debug mode Bit[2:0]: JPEG mode select 001: JPEG mode 1 010: JPEG mode 2 011: JPEG mode 3 100: JPEG mode 4 101: JPEG mode 5 110: JPEG mode 6 Bit[7:4]: Debug mode Bit[3:0]: CCIR656 dummy line number Control dummy line number at beginning of the frame Bit[7:2]: Debug mode Bit[1:0]: CCIR656 EAV/SAV option Bit[7:1]: Debug mode Bit[0]: HSYNC mode enable Bit[7:2]: Debug mode Bit[1:0]: vsync_mode 00: VSYNC positive edge trigger by end of field, negative edge trigger by start of frame 01: VSYNC positive edge trigger by end of frame, the width define by register 10: VSYNC positive edge trigger by start of field, the width define by register HREF Minimum Blanking in JPEG Mode23 Bit[7:4]: Debug mode Bit[3:0]: Vertical start delay between video output and video input Bit[7:4]: Debug mode Bit[3:0]: Vertical end delay between video output and video input DVP JPEG Mode456 Skip Line Number

0x4713

JPG MODE SELECT

0x02

RW

0x4715

656 DUMMY LINE

0x00

RW

0x4719 0x471B

CCIR656 CTRL HSYNC CTRL00

0x00 0x02

RW RW

0x471D

DVP VSYNC CTRL

0x01

RW

0x471F

DVP HREF CTRL VERTICAL START OFFSET

0x40

RW

0x4721

0x00

RW

0x4722 0x4723

VERTICAL END OFFSET DVP CTRL23

0x00 0x00

RW RW

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color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-18
address

DVP control registers (sheet 3 of 4)
register name default value R/W description
SYNC code selection 0: Auto generate sync code 1: Sync code from register setting 0x4732~4735 Bit[6]: f value in CCIR656 SYNC code when fixed f value Bit[5]: Fixed f value Bit[4:3]: Blank toggle data options 00: Toggle data is 1'h040/1'h200 01: Use register setting 0x4736~0x4738 10: Blanking data always keep 0 Bit[1]: Clip data disable Bit[0]: CCIR656 mode enable Bit[7:1]: Debug mode Bit[0]: Blanking toggle data order option CCIR656 SYNC Code Frame Start CCIR656 SYNC Code Frame End CCIR6656 SYNC Code Line Start CCIR656 SYNC Code Line End Bit[7:4]: Debug mode Bit[3:2]: Toggle data0[9:8] Bit[1:0]: Toggle data1[9:8] Bit[7:0]: Toggle data0[7:0] Bit[7:0]: Toggle data1[7:0] Bit[7:6]: Debug mode Bit[5]: PCLK polarity 0: Active low 1: Active high Bit[3]: Gate PCLK under VSYNC Bit[2]: Gate PCLK under HREF Bit[1]: HREF polarity 0: Active low 1: Active high Bit[0]: VSYNC polarity 0: Active low 1: Active high Bit[7]:

0x4730

CCIR656 CTRL00

0x00

RW

0x4731 0x4732 0x4733 0x4734 0x4735 0x4736 0x4737 0x4738

CCIR656 CTRL01 CCIR656 FS CCIR656 FE CCIR656 LS CCIR656 LE CCIR656 CTRL6 CCIR656 CTRL7 CCIR656 CTRL8

0x00 0x01 0x0F 0x00 0x00 0x00 0x00 0x00

RW RW RW RW RW RW RW RW

0x4740

POLARITY CTRL00

0x20

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-37

table 7-18
address

DVP control registers (sheet 4 of 4)
register name default value R/W description
Bit[7:3]: Debug mode Bit[2]: Test pattern enable Bit[1]: Test pattern select 0: Output test pattern 0 1: Output test pattern 1 Bit[0]: Test pattern 8-bit/10-bit 0: 10-bit test pattern 1: 8-bit test pattern Debug Mode Bit[7:3]: Debug mode Bit[2:1]: DVP order option for debug 00: Data[9:0] 10: {data[7:0],data[9:8]} x1: {data[1:0],data[9:2]} Bit[0]: Output data order 0: Normal output 1: Reverse output data bit order

0x4741

TEST PATTERN

0x00

RW

0x4742~ 0x4744

DEBUG MODE





0x4745

DATA ORDER

0x00

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.19 MIPI control [0x4800 ~ 0x4837]
table 7-19
address

MIPI transmitter registers (sheet 1 of 3)
register name default value R/W description
MIPI Control 00 Bit[7:6]: Debug mode Bit[5]: Clock lane gate enable 0: Clock lane is free running 1: Gate clock lane when no packet to transmit Bit[4]: Line sync enable 0: Do not send line short packet for each line 1: Send line short packet for each line Bit[3]: Lane select 0: Use lane1 as default data lane 1: Use lane2 as default data lane Bit[2]: Idle status 0: MIPI bus will be LP00 when no packet to transmit 1: MIPI bus will be LP11 when no packet to transmit Bit[1:0]: Debug mode MIPI Control 01 Bit[7:5]: Debug mode Bit[4]: PH bit order for ECC 0: {DI[7:0],WC[7:0],WC[15:8]} 1: {DI[0:7],WC[0:7],WC[8:15]} Bit[3]: PH byte order for ECC 0: {DI,WC_l,WC_h} 1: {DI,WC_h,WC_l} Bit[2]: PH byte order2 for ECC 0: {DI,WC} 1: {WC,DI} Bit[1:0]: Debug mode Debug Mode Bit[7]: MIPI lane1 disable 1: Disable MIPI data lane1 Lane1 will be LP00 Bit[6]: MIPI lane1 disable 1: Disable MIPI data lane1 Lane1 will be LP00 Bit[5]: LPX Global timing select 0: Auto calculate t_lpx_o in pclk2x domain, unit clk2x 1: Use lp_p_min[7:0] Bit[6:0]: Debug mode

0x4800

MIPI CTRL 00

0x04

RW

0x4801

MIPI CTRL 01

0x04

RW

0x4802~ 0x4804

DEBUG MODE





0x4805

MIPI CTRL 05

0x10

RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-39

table 7-19
address
0x4806~ 0x4809

MIPI transmitter registers (sheet 2 of 3)
register name
DEBUG MODE

default value


R/W


description
Debug Mode Bit[7:3]: Debug mode Bit[2]: Bit order reverse Bit[1:0]: Bit position adjust 01: {data[7:0],data[9:8]} 10: {data[1:0],data[9:2]} Debug Mode High Byte of Minimum Value of hs_zero Unit ns Low Byte of Minimum Value of hs_zero hs_zero_real = hs_zero_min_o + Tui*ui_hs_zero_min_o High Byte of Minimum Value of hs_trail Unit ns Low Byte of Minimum Value of hs_trail hs_trail_real = hs_trail_min_o + Tui*ui_hs_trail_min_o High Byte of Minimum Value of clk_zero Low Byte of Minimum Value of clk_zero clk_zero_real = clk_zero_min_o + Tui*ui_clk_zero_min_o High Byte of Minimum Value of clk_prepare Unit ns Low Byte of Minimum Value of clk_prepare clk_prepare_real = clk_prepare_min_o + Tui*ui_clk_prepare_min_o High Byte of Minimum Value of clk_post Unit ns Low Byte of Minimum Value of clk_post clk_post_real = clk_post_min_o + Tui*ui_clk_post_min_o High Byte of Minimum Value of clk_trail Unit ns Low Byte of Minimum Value of clk_trail clk_trail_real = clk_trail_min_o + Tui*ui_clk_trail_min_o High Byte of Minimum Value of lpx_p Unit ns Low Byte of Minimum Value of lpx_p lpx_p_real = lpx_p_min_o + Tui*ui_lpx_p_min_o

0x480A

MIPI DATA ORDER

0x00

RW

0x480B~ 0x4817 0x4818 0x4819 0x481A 0x481B 0x481C 0x481D 0x481E

DEBUG MODE MIN HS ZERO H MIN HS ZERO L MIN MIPI HS TRAIL H MIN MIPI HS TRAIL L MIN MIPI CLK ZERO H MIN MIPI CLK ZERO L MIN MIPI CLK PREPARE H MIN MIPI CLK PREPARE L MIN CLK POST H MIN CLK POST L MIN CLK TRAIL H MIN CLK TRAIL L MIN LPX PCLK H MIN LPX PCLK L

– 0x00 0x96 0x00 0x3C 0x01 0x86 0x00

– RW RW RW RW RW RW RW

0x481F

0x3C

RW

0x4820 0x4821 0x4822 0x4823 0x4824 0x4825

0x00 0x56 0x00 0x3C 0x00 0x32

RW RW RW RW RW RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-19
address
0x4826

MIPI transmitter registers (sheet 3 of 3)
register name
MIN HS PREPARE H MIN HS PREPARE L MIN HS EXIT H MIN HS EXIT L MIN HS ZERO/UI MIN HS TRAIL/UI MIN CLK ZERO/UI MIN CLK PREPARE/UI MIN CLK POST/UI MIN CLK TRAIL/UI MIN LPX PCLK/UI MIN HS PREPARE/UI MIN HS EXIT/UI DEBUG MODE PCLK PERIOD

default value
0x00

R/W
RW

description
High Byte of Minimum Value of hs_prepare Unit ns Low Byte of Minimum Value of hs_prepare hs_prepare_real = hs_prepare_min_o + Tui*ui_hs_prepare_min_o High Byte of Minimum Value of hs_exit Unit ns Low Byte of Minimum Value of hs_exit hs_exit_real = hs_exit_min_o + Tui*ui_hs_exit_min_o Minimum UI Value of hs_zero Unit UI Minimum UI Value of hs_trail Unit UI Minimum UI Value of clk_zero Unit UI Minimum UI Value of clk_prepare Unit UI Minimum UI Value of clk_post Unit UI Minimum UI Value of clk_trail Unit UI Minimum UI Value of lpx_p(pclk2x domain) Unit UI Minimum UI Value of hs_prepare Unit UI Minimum UI Value of hs_exit Unit UI Debug Mode Period of pixel clock, pclk_div=1, and 1-bit decimal

0x4827

0x32

RW

0x4828 0x4829 0x482A 0x482B 0x482C 0x482D 0x482E 0x482F 0x4830 0x4831 0x4832 0x4833~ 0x4836 0x4837

0x00 0x64 0x05 0x04 0x00 0x00 0x34 0x00 0x00 0x04 0x00 – 0x10

RW RW RW RW RW RW RW RW RW RW RW – RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-41

7.20 ISP frame control [0x4901 ~ 0x4902]
table 7-20
address

ISP frame control registers
register name default value R/W description
Control Passed Frame Number When both ON and OFF number set to 0x00, frame control is in bypass mode Bit[7:4]: Debug mode Bit[3:0]: Frame ON number Control Masked Frame Number When both ON and OFF number set to 0x00, frame control is in bypass mode Bit[7:4]: Debug mode Bit[3:0]: Frame OFF number

0x4901

FRAME CTRL01

0x00

RW

0x4902

FRAME CTRL02

0x00

RW

7.21 ISP top control [0x5000 ~ 0x5063]
table 7-21
address

ISP top control registers (sheet 1 of 5)
register name default value R/W description
Bit[7]: LENC correction enable 0: Disable 1: Enable Bit[6]: Debug mode Bit[5]: RAW GMA enable 0: Disable 1: Enable Bit[4:3]: Debug mode Bit[2]: Black pixel cancellation enable 0: Disable 1: Enable Bit[1]: White pixel cancellation enable 0: Disable 1: Enable Bit[0]: Color interpolation enable 0: Disable 1: Enable

0x5000

ISP CONTROL 00

0x06

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-21
address

ISP top control registers (sheet 2 of 5)
register name default value R/W description
Bit[7]: Special digital effect enable 0: Disable 1: Enable Bit[6]: Debug mode Bit[5]: Scale enable 0: Disable 1: Enable Bit[4:3]: Debug mode Bit[2]: UV average enable 0: Disable 1: Enable Bit[1]: Color matrix enable 0: Disable 1: Enable Bit[0]: Auto white balance enable 0: Disable 1: Enable Debug Mode Bit[7:3]: Debug mode Bit[2]: Bin enable 0: Disable 1: Enable Bit[1]: Draw window for AFC enable 0: Disable 1: Enable Bit[0]: Solarize enable 0: Disable 1: Enable Debug Mode

0x5001

ISP CONTROL 01

01

RW

0x5002

DEBUG MODE





0x5003

ISP CONTROL 03

08

RW

0x5004

DEBUG MODE





proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-43

table 7-21
address

ISP top control registers (sheet 3 of 5)
register name default value R/W description
Bit[7]: Bit[6]: Debug mode AWB bias manual enable 0: Disable 1: Enable AWB bias ON enable 0: Disable 1: Enable AWB bias plus enable 0: Disable 1: Enable Debug mode LENC bias ON enable 0: Disable 1: Enable GMA bias ON enable 0: Disable 1: Enable LENC bias manual enable 0: Disable 1: Enable

Bit[5]:

Bit[4]: 0x5005 ISP CONTROL 05 0x36 RW

Bit[3]: Bit[2]:

Bit[1]:

Bit[0]:

0x5006~ 0x501C

DEBUG MODE





Debug Mode Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3:0]: Debug mode SDE AVG manual enable AWB YUV2CBCR enable Average size manual enable Debug mode

0x501D

ISP MISC

0x00

RW

0x501E

ISP MISC

0x00

RW

Bit[7]: Debug mode Bit[6]: Scale ratio manual enable Bit[5:0]: Debug mode Format MUX Control Bit[7:4]: Debug mode Bit[3]: Fmt vfirst Bit[2:0]: Format select 000: ISP YUV422 001: ISP RGB 010: ISP dither 011: ISP RAW (DPC) 100: SNR RAW 101: ISP RAW (CIP) Bit[7]: Bit[6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Debug mode Dither MUX R dithering G dithering B dithering

0x501F

FORMAT MUX CONTROL

0x00

RW

0x5020

DITHER CTRL 0

0x00

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

table 7-21
address
0x5021~ 0x5026

ISP top control registers (sheet 4 of 5)
register name
DEBUG MODE

default value


R/W


description
Debug Mode Bit[7:1]: Debug mode Bit[0]: Draw window control 0: No fixed Y 1: Fixed Y Bit[7:4]: Debug mode Bit[3:0]: Draw window left[11:8]

0x5027

DRAW WINDOW CONTROL 00 DRAW WINDOW LEFT POSITION CONTROL DRAW WINDOW LEFT POSITION CONTROL DRAW WINDOW RIGHT POSITION CONTROL DRAW WINDOW RIGHT POSITION CONTROL DRAW WINDOW TOP POSITION CONTROL DRAW WINDOW TOP POSITION CONTROL DRAW WINDOW BOTTOM POSITION CONTROL DRAW WINDOW BOTTOM POSITION CONTROL DRAW WINDOW HORIZONTAL BOUNDARY WIDTH CONTROL DRAW WINDOW HORIZONTAL BOUNDARY WIDTH CONTROL DRAW WINDOW VERTICAL BOUNDARY WIDTH CONTROL

0x02

RW

0x5028

0x04

RW

0x5029

0x90

RW

Bit[7:0]: Draw window left[7:0]

0x502A

0x05

RW

Bit[7:4]: Debug mode Bit[3:0]: Draw window right[11:8]

0x502B

0x90

RW

Bit[7:0]: Draw window right[7:0]

0x502C

0x03

RW

Bit[7:3]: Debug mode Bit[2:0]: Draw window top[10:8]

0x502D

0x6C

RW

Bit[7:0]: Draw window top[7:0]

0x502E

0x04

RW

Bit[7:3]: Debug mode Bit[2:0]: Draw window bottom[10:8]

0x502F

0x2C

RW

Bit[7:0]: Draw window bottom[7:0]

0x5030

0x00

RW

Bit[7:4]: Debug mode Bit[3:0]: Draw window horizontal boundary width[11:8]

0x5031

0x14

RW

Bit[7:0]: Draw window horizontal boundary width[7:0]

0x5032

0x00

RW

Bit[7:3]: Debug mode Bit[2:0]: Draw window vertical boundary width[10:8]

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-45

table 7-21
address

ISP top control registers (sheet 5 of 5)
register name
DRAW WINDOW VERTICAL BOUNDARY WIDTH CONTROL DRAW WINDOW Y CONTROL DRAW WINDOW U CONTROL DRAW WINDOW V CONTROL DEBUG MODE

default value

R/W

description

0x5033

0x14

RW

Bit[7:0]: Draw window vertical boundary width[7:0]

0x5034 0x5035 0x5036 0x5037~ 0x503C

0x80 0x2A 0x14 –

RW RW RW –

Bit[7:0]: Fixed Y for draw window Bit[7:0]: Fixed U for draw window Bit[7:0]: Fixed V for draw window Debug Mode Bit[7]: Pre ISP test enable 0: Test disable 1: Color bar enable Bit[6]: Rolling Bit[5]: Transparent Bit[4]: Square BW Bit[3:2]: Pre ISP bar style 00: Standard 8 color bar 01: Gradual change at vertical mode 1 10: Gradual change at horizontal 11: Gradual change at vertical mode 2 Bit[1:0]: Test select 00: Color bar 01: Random data 10: Square data 11: Black image Debug Mode ISP Sensor Bias I ISP Sensor Gain I ISP Sensor Gain I

0x503D

PRE ISP TEST SETTING 1

0x00

RW

0x503E~ 0x5060 0x5061 0x5062 0x5063

DEBUG MODE ISP SENSOR BIAS I ISP SENSOR GAIN I ISP SENSOR GAIN I

– – – –

– R R R

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.22 AWB control [0x5180 ~ 0x51D0]
table 7-22
address
0x5180

AWB registers (sheet 1 of 2)
register name
AWB CONTROL 00

default value
0xFF

R/W
RW

description
Bit[7:0]: AWB B block Bit[7:6]: Bit[5:4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Step local Step fast Slop 8x Slop 4x One zone AVG all

0x5181

AWB CONTROL 01

0x58

RW

0x5182

AWB CONTROL 02

0x11

RW

Bit[7:4]: Max local counter Bit[3:0]: Max fast counter Bit[7]: AWB simple enable 0: AWB advance 1: AWB simple Bit[6]: AWB advance 0: YUV enable 1: Simple YUV enable Bit[5]: AWB preset Bit[4]: AWB SIMF Bit[3:2]: AWB win Bit[0]: Debug mode Bit[7:6]: Bit[5]: Bit[4:2]: Bit[1:0]: Count area selection G enable Count limit control Counter threshold

0x5183

AWB CONTROL 03

0x90

RW

0x5184

AWB CONTROL 04

0x25

RW

0x5185

AWB CONTROL 05

0x24

RW

Bit[7:4]: Stable range unstable Threshold for unstable to stable change Bit[3:0]: Stable range stable Threshold for stable to unstable change Advanced AWB Control Registers Bit[7:0]: AWB top limit Bit[7:0]: AWB bottom limit Bit[7:0]: Red limit Bit[7:0]: Green limit Bit[7:0]: Blue limit

0x5186~ 0x5190 0x5191 0x5192 0x5193 0x5194 0x5195

AWB CONTROL AWB CONTROL 17 AWB CONTROL 18 AWB CONTROL 19 AWB CONTROL 20 AWB CONTROL 21

– 0xFF 0x00 0xF0 0xF0 0xF0

– RW RW RW RW RW

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-47

table 7-22
address

AWB registers (sheet 2 of 2)
register name default value R/W description
Bit[7:6]: Bit[5]: Bit[4]: Bit[3:2]: Debug mode AWB freeze Debug mode AWB simple selection 00: AWB simple from after AWB gain 01: AWB simple from after RAW GMA 10: AWB simple from after RAW GMA 11: AWB simple from after AWB gain Fast enable AWB bias stat

0x5196

AWB CONTROL 22

0x03

RW

Bit[1]: Bit[0]: 0x5197 0x5198~ 0x519D AWB CONTROL 23 DEBUG MODE 0x02 – RW –

Bit[7:0]: Local limit Debug Mode Bit[7:4]: Bit[3]: Bit[2]: Bit[1:0]: Debug mode Local limit select Simple stable select Debug mode

0x519E

AWB CONTROL 30

0x00

RW

0x519F 0x51A0 0x51A1 0x51A2 0x51A3 0x51A4 0x51A5 0x51A6 0x51A7

AWB CURRENT R GAIN AWB CURRENT R GAIN AWB CURRENT G GAIN AWB CURRENT G GAIN AWB CURRENT B GAIN AWB CURRENT B GAIN AWB AVERAGE B AWB AVERAGE B AWB AVERAGE B

– – – – – – – – –

R R R R R R R R R

Bit[7:4]: Debug mode Bit[3:0]: Current R setting[11:8] Bit[7:0]: Current R setting[7:0] Bit[7:4]: Debug mode Bit[3:0]: Current G setting[11:8] Bit[7:0]: Current G setting[7:0] Bit[7:4]: Debug mode Bit[3:0]: Current B setting[11:8] Bit[7:0]: Current B setting[7:0] Bit[7:0]: Average R[9:2] Bit[7:0]: Average G[9:2] Bit[7:0]: Average B[9:2] Bit[7:6]: Bit[5]: Bit[4]: Bit[3]: Bit[2:1]: Bit[0]: Debug mode R large G large B large Current type Debug mode

0x51D0

AWB CONTROL74



R

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.23 CIP control [0x5300 ~ 0x530F]
table 7-23
address
0x5300 0x5301

CIP control registers
register name
CIP SHARPENMT THRESHOLD 1 CIP SHARPENMT THRESHOLD 2 CIP SHARPENMT OFFSET1 CIP SHARPENMT OFFSET2 CIP DNS THRESHOLD 1 CIP DNS THRESHOLD 2 CIP DNS OFFSET1 CIP DNS OFFSET2

default value
0x08 0x48

R/W
RW RW

description
Color Interpolation Sharpen MT Threshold 1 Color Interpolation Sharpen MT Threshold 2 CIP Sharpen MT Offset1 (Y edge mt manual setting when 0x5308[6]=1) CIP Sharpen MT Offset2 CIP DNS Threshold 1 CIP DNS Threshold 2 CIP DNS Offset1 (DNS threshold manual setting when 0x5308[4]=1) CIP DNS Offset2 Bit[7]: Bit[6]: Bit[4]: Bit[2:0]: Debug mode CIP edge MT manual enable CIP DNS manual enable CIP threshold for BR sharpen

0x5302 0x5303 0x5304 0x5305 0x5306 0x5307

0x18 0x0E 0x08 0x48 0x09 0x16

RW RW RW RW RW RW

0x5308

CIP CTRL

0x25

RW

0x5309 0x530A

CIP SHARPENTH THRESHOLD 1 CIP SHARPENTH THRESHOLD 2 CIP SHARPENTH OFFSET1 CIP SHARPENTH OFFSET2 CIP EDGE MT AUTO CIP DNS THRESHOLD AUTO CIP SHARPEN THRESHOLD AUTO

0x08 0x48

RW RW

CIP Sharpen TH Threshold 1 CIP Sharpen TH Threshold 2 CIP Sharpen TH Offset1 (Sharpen threshold manual setting when 0x5308[6]=1) CIP Sharpen TH Offset2 CIP Edge MT Auto Read CIP DNS Threshold Auto Read CIP Sharpen Threshold Auto Read

0x530B 0x530C 0x530D 0x530E 0x530F

0x04 0x06 – – –

RW RW R R R

proprietary to OmniVision Technologies

PRODUCT SPECIFICATION

version 2.03

7-49

7.24 CMX control [0x5380 ~ 0x538B]
table 7-24
address

CMX control registers
register name default value R/W description
Bit[7:2]: Debug mode Bit[1]: CMX precision switch 0: 1.7 mode 1: 2.6 mode Bit[0]: Debug mode Bit[7:2]: Debug mode Bit[1]: CMX1 for Y Bit[0]: Debug mode Bit[7:0]: CMX2 for Y Bit[7:0]: CMX3 for Y Bit[7:0]: CMX4 for U Bit[7:0]: CMX5 for U Bit[7:0]: CMX6 for U Bit[7:0]: CMX7 for V Bit[7:0]: CMX8 for V Bit[7:0]: CMX9 for V Cmxsign Bit[7:1]: Debug mode Bit[0]: CMX9 sign Cmxsign Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: CMX8 sign CMX7 sign CMX6 sign CMX5 sign CMX4 sign CMX3 sign CMX2 sign CMX1 sign

0x5380

CMX CTRL

0x00

RW

0x5381 0x5382 0x5383 0x5384 0x5385 0x5386 0x5387 0x5388 0x5389 0x538A

CMX1 CMX2 CMX3 CMX4 CMX5 CMX6 CMX7 CMX8 CMX9 CMXSIGN

0x20 0x64 0x08 0x30 0x90 0xC0 0xA0 0x98 0x08 0x01

RW RW RW RW RW RW RW RW RW RW

0x538B

CMXSIGN

0x98

RW

05.26.2011

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

OV5640

color CMOS QSXGA (5 megapixel) image sensor with OmniBSI? technology

7.25 gamma control [0x5480 ~ 0x5490]
table 7-25
address
0x5480 0x5481 0x5482 0x5483 0x5484 0x5485 0x5486 0x5487 0x

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5M85_MIPI_AF+OV5640 bma250 TPS61165(TI) MT29C4G96MAZAPCJA-5 E IT Auto detection(tsl2771 ) Auto detection( tsl2771 ) akmd8962c MPU_3050 max...
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