APPLICATION NOTE U161
Ron Fiorello Unitrode Corporation
POWERING A 35W DC METAL HALIDE HIGH INTENSITY DISCHARGE (HID) LAMP USING THE UCC3305 HID LAMP CONTROLLER
UNITRODE CORPORATION
APPLICATION NOTE U161
POWERING A 35W DC METAL HALIDE HIGH INTENSITY DISCHARGE (HID) LAMP USING THE UCC3305 HID LAMP CONTROLLER
by Ron Fiorello Unitrode Corporation ABSTRACT
High Intensity Discharge (HID) metal halide lamps are being used in more and more applications where lamp color, long life and efficiency are important. From automotive and industrial lighting to theatrical and stage lighting, HID promises to be the light of the future. HID lamps offer many advantages over many other types of discharge lamps because of their luminous efficiency (their ability to convert electrical power to visible light) and the color of the light output is closer to an ideal source (the sun) then other types of discharge lamps i.e.; low pressure sodium, high pressure sodium etc. The purpose of this application note is to demonstrate the use of the UCC3305 HID lamp controller IC. Information is presented on a design example to help the user better understand all of the controllers many features.
INTRODUCTION The following section specifies typical design requirements necessary of an HID ballast which would be powering a DC headlamp in an automotive application. The headlamp used in this application is a 35W DC metal halide lamp manufactured by OSRAM/SYLVANIA. Input Voltage Requirements  9 to 16VDC Startup Requirements  Must run/startup down to 6VDC Protection/Fault Monitor Protection against input overvoltage, output open circuit and output short circuit. Power Regulation  Regulate power to the lamp within +10% over a lamp voltage variation of 60 to 100VDC. Lamp Ignition Voltage  Provide an open circuit voltage of greater then 500VDC at startup in order to ignite the lamp. Efficiency  greater than 85%. Cold Start  The light output on initial startup must be within a window as specified by SAE J2009. Hot Restrike  The ballast must be able to properly light the lamp when hot without a cool down period. The load presented to the ballast by the lamp is nonlinear. Before ignition occurs, the lamp draws very little current from the ballast. The ballast sees essentially an open circuit on its output at startup. The open circuit voltage feeds an ignitor circuit (internal to the lamp) which stepsup the voltage in order to provide the approximately 20kV ignition voltage necessary for the lamp. Upon ignition, metals and gases inside the lamp are ionized causing the lamp voltage to collapse. During ionization, the lamp will require significant current from the ballast to properly establish and maintain the arc discharge. During this time, the current into the lamp must also be controlled to protect the lamp electrodes [1]. The initial startup power into the lamp is higher then its steady state value. This is necessary in order to get the light output up to 75% of its steadystate value within 2 seconds, which is a requirement for an automotive application as specified under SAE J2009. The lamp voltage right after the glow to arc transition varies from lamp to lamp but is usually between 20 and 40VDC. As the lamp warms up and the internal pressure inside the arc tube increases, the voltage begins to rise and will gradually reach a steadystate value of between 60 and 110VDC after 150 seconds. This depends on the age of the lamp. A typical steadystate voltage of this type of lamp is between 75 and 90VDC.
APPLICATION NOTE
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UDG96239
Figure 1. Power Regulation Loop
Optimal converter topology The optimal converter topology for this application would meet the following requirements; 1) Output voltage that is capable of being higher then input voltage. 2) Low input current ripple for reduced input filter requirements 3) High efficiency 4) Minimal number of magnetic components 5) Minimal number of power semiconductors There are a few candidate topologies which meet some of the above requirements. The best choice for this particular application is the SEPIC converter which meets all of the above requirements for a 35W lamp. The schematic of this circuit is shown in Figure 2 [2]. The UCC3305 HID controller The features of the UCC3305 HID controller are outlined below: ? ? ? ? ? ? ? ? ? OV input protection Output fault protection/timing Power regulation vs. lamp voltage Lamp startup/cool down simulation Currentmode control Fixed frequency operation DC or AC lamp drive capability High current drive capability On board charge pump to provide gate drive down to 6VDC ? Adjustable startup to steadystate current ratio
Below is a summation of the different functional blocks of the UCC3305 and their major electrical characteristics; VCC/OV Protection/VREF/VBOOST Block VCC Maximum Voltage  8 Volts Must bypass with 0.1?F to 1.0?F Ceramic Monolithic Capacitor as close to the IC as possible OV Threshold  Internal Comparator with reference voltage tied to internal 5V. OV threshold adjustable with external resistor divider VREF: 5.0V Trimmed Bandgap Reference Must bypass with 0.1?F Low ESR Capacitor as close to the IC as possible VBOOST Max Voltage  12 Volts Supplies drive for output drive stage Must bypass with 0.1?F to 1?F Ceramic Monolithic Capacitor as close to IC as possible Output Drive Stage: PWMOUT: 1.0A Peak current drive capability Q and Q not outputs Outputs to drive external bridge via external MOSFET drivers Output frequency is fs/512 At lamp start, outputs are disabled via RC from NOTON and DIV. PAUSE
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APPLICATION NOTE
Oscillator: OSC: Sawtooth Oscillator with Programmable Frequency DMAX from 0% to 100% possible With RSET = 150k, Fs ~ 22xe6/COSC Maximum operating frequency is 300kHz Load Power and Main Error Amplifiers: LOADSENSE, LPOWER, COMP AND FB The LOADSENSE amplifier, the main error amplifier and its external associated resistors and capacitors will determine where the peak of the power curve occurs as well as the shape of the frequency response of the ballast. Below is an analysis of this operational block based on the 35W DC lamp in an attempt to show how the power curve of the ballast is determined for this particular application. From the simplified schematic of this loop shown in Figure 2 below, the power curve equation is determined as follows; Power curve equation From the simplified schematic of the power regulation loop, shown in Figure1, the currents I1 and I2 can be found as follows; I1 = VREF ? KV ? VO R2 KV ? VO + KI ? IO R1
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I2 =
where KV and KI are the proportionality constants for voltage and current respectively; since I1 = I2 VREF ? KV ? VO = R2 KV ? VO + KI ? IO R1 R1 ? KV ? VO R2
rearranging the above equation and solving for IO, KI ? IO = (VREF ? KV ? VO) ? IO = [(VREF ? KV ? VO) ? since PO = VO ? IO substituting the expression found for IO into the power equation,
R1 1 ? KV ? Vo] ? R2 KI
UDG96240
Figure 2. 35W DC HID Ballast Schematic
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UDG96242
The expression for PO1 is valid for lamp voltages from 60 to 105V. The expression for PO2 is valid for lamp voltages above 105V (This is due to the limiter block inside the UCC3305). Above approximately 105V, the lamp will be driven in a constant current mode which results in the straight line for power vs. lamp voltage as shown. The output power can be regulated with a variation of less than ±10% from a nominal of 34.5W with a lamp voltage variation from 60 to 110V. As the lamp ages, the voltage will normally increase due to the lamp electrode material erosion over time. Therefore it is beneficial to limit the current available to the lamp above a certain voltage.
Figure 3. Calculated Power Curve vs. Lamp Voltage of UCC3305 Controlled 35W Ballast Powering DC Metal Halide Osram/Sylvania Lamp
PO = where
VO R1 R1 ? [VREF ? ? KV ? VO ? (1 + )] KI R2 R2 RA ? RB RA + RB
REQ = 5.078 ? K KV ≈ 0.0032 KI = 0.75 KI is equal to the current sense resistor value Substituting the values found for the constants KV and KI and the actual resistor values used in the circuit into the power equation, the power curve can be plotted for a range of lamp voltages as shown in the figure below. KV ≈ 0.0032 R1 = 4.7k
REQ =
from block diagram of UCC3305, where 1/120 is the voltage divider attenuation ratio. REQ is the parallel combination of the 100k and the 5.35k internal resistors. KV ≈ REQ 1 ? 120 REQ+ 7.85k
RA = 100k RB = 5.35k
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APPLICATION NOTE
KI = 0.75 R2 = 16k VO1 = 60, 65..110 VREF = 2.5 VO2 = 110, 115..120 PVo(1) = VO1 R1 ?[( ) ? VREF ? KV ? VO1 KI R2 ?( PVo(2) = R1 + 1)], R2
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By the addition of an external resistor from the ADJ. pin to ground, this ratio can be programmed. At the instant of startup, the output of the limiter is at zero volts since the WARMUPC capacitor has not charged. Because of this, the inverting input to amplifier A1 is at ground with 20?A ? RADJ volts on its noninverting input. As an example, if RADJ = 150k, then the voltage at the noninverting input is 3V. V VO(?) = ?( (?) ) ? 10k 83k V VO(?) = ?( (?) ) ? 10k + V(+) 83k where VO(+) = the contribution of the noninverting input to VO of A1 VO(?) = the contribution of the inverting input to VO of A1 V(+) = the voltage at the noninverting input of A1 VO = V(+) ? ( on startup, V(?) = 0 so; VO = 3.36 Volts 10k 10k + 1) ? V(?) ? ( ) 83k 83k
VO2 R1 ?[( KI R2
) ? VREF ? 0.322
? ( R1 + 1)] R2 Current sense comparators/amplifiers The INPUT ISENSE comparitor/amplifier inside the UCC3305 provides cycle by cycle current control as in a typical peak currentmode controller. An added feature allows the user to program the startup to steadystate current ratio of this current. This allows the ballast to provide increased power to the lamp at startup in order to get the lamp light output up to its steadystate level as quick as possible. The simplified schematic of this section is shown in Figure 4 below.
ISENSEIN
A1 ADJ

R WARMUP C
UDG96241
Figure 4. Current Sense / Limit Block
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The current sense threshold is then; VS = 3.36 10
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The current which flows thru the feedback resistor of the load sense amplifier is; ILS = 5.46 ? 0.30 12k
VS = 0.336 Volts This translates to a peak switch current at startup of; IP = 3.36 0.02
ILS = 430?Α Assuming that the current which flows thru the feedback resistor also flows thru the inverting input resistor, the voltage across the output current sense resistor is; VCS = 0.30 ? (430?A ? 5.1k) VCS = 1.89V (the negative sign of the voltage is ignored since this is defined as positive current) IL = 1.89 0.83
IP = 16.8 Amps This current threshold will gradually decrease as the WARMUPC capacitor charges up to 10V. The limiter limits the inverting input of A1 at steadystate to 5V. The current limit at this point is then; VO = 3.36 ? 0.6 VO = 2.76 Volts IP = 0.276 0.02
IL = 2.3 Amps This defines the maximum startup current which flows into the lamp at ignition. The current into the lamp will decay exponentially due to the voltage charging characteristic of the WARMUPC and SLOPEC capacitors. The current will decay to a steadystate value of approximately 450mA after a period of time given by the time constant of the internal 50 Meg resistor and the capacitor placed from the SLOPEC pin to ground. In this example, the time to steadystate is 150 seconds from: t = 50 exp(6) ? CSLOPEC The capacitors used for the SLOPEC and WARMUPC functions must have low leakage characteristics since they are charged from nanoamp current sources internal to the IC. Any significant amount of leakage current caused by these components will have an effect on the output power regulation characteristic of the ballast. Slope compensation resistor Slope compensation in the UCC3305 is provided by the addition of an external resistor in series with the INPUT ISENSE pin. This resistor adds a portion of the oscillator ramp into the current sense signal to provide the necessary slope compensation for duty cycles exceeding 50%. The amount of slope compensation that is needed is dependent on the topology used as well as the inductor values chosen. In the SEPIC converter, both input and output inductors need to be considered when determining how much slope compensation is necessary.
IP = 13.8 Amps The switch current in the SEPIC converter is a combination of the input inductor current plus the reflected load current. At steadystate, 9 VIN, the peaktopeak current thru the output rectifier is approximately 1A. This reflects back to the primary as 6A into the switch plus 3.1 Amps from the inductor. The total current thru Q1 is then 9.1 Amps. Output current limit on startup From Figure 2 the startup current limit into the lamp can be determined. On startup, the WARMUPV pin, which is a buffered version of WARMUPC, is at ground.Therefore, the two 27k resistors are in parallel resulting in an equivalent resistance of 13.5k. The current that flows from FB to ground is then; I= 2.5 13.5k
I1 = 185?Α The voltage at the output of the load sense amplifier is then; VLS = 185?Α ? 16k + 2.5V VLS = 5.46V
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APPLICATION NOTE
The current sense comparator compares the current sense signal to the output of the error amplifier to determine the duty cycle of the power switch [3]. VI, the voltage at the current sense resistor can be determined as follows N VI = RI ? ( S ) ? ( IOAV + M2 ? t) NP + RI (IIN + where; NS = number of turns of secondary winding of L2 NP = number of turns of primary windings of L2 RI = current sense resistor LOAV = secondary average output current M2 = down slope of secondary current thru L2 M1 = down slope of primary current thru L1 IIN = average input current tOFF = off time of switch The above equation can be rewritten as follows; Ns VI = RI ? ( N ) ? (LOAV + M2 ? (T ? tON))
P
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From the simplified schematic of the current sense circuit; 2 10 ? exp(?6) where S is defined as the slope of the oscillator ramp. Substituting the following values into the equation for RP will allow us to determine the value of the slope compensation resistor. S= M2 = 178571 NS = 60 M1 = 178571 NP = 10 RI = 0.01 S = 181818 M1 NS ? RI + N ? RI ? M2 2 P RP = 2 RP = 0.064 R4 = 50k R3 is the slope compensation resistor and R4 is the internal 50k? resistor; RP = R3 R3 + R4 R4 1 ? 0.064
M1 ? tOFF) 2
M1 ? (T ? tON)] 2 The first term is the contribution of the output current thru L2 (output inductor) to the current sense resistor. The second term is the contribution of the input current thru L1 (input inductor) to the current sense resistor + RI [IIN + This signal is set equal to the voltage at the output of the error amplifier. This results in the following equation after rearranging terms; N RI ( S ) ? LOAV = VEA + tON NP M N ? ( 1 ? RI + RI s ? M2 ? m) 2 NP ? IIN ? M1 ? T ? RI ? M2 ? T 2
Solving for R3; R3 = 0.064 ? R3 = 3.419k Therefore, the slope compensation resistor chosen must be greater than 3.42k in order for stable converter operation at duty cycles which exceed 50%. Frequency response of the power regulation loop The frequency response of the ballast is determined by analysis of the power regulation loop. Since it is really the output current that is being regulated and not the output voltage (any change in output voltage is attenuated by 1/120), the analysis can be simplified by modeling the power stage as a voltage controlled current source with some transconductance gain GM. This assumption is valid for a loop cross over frequency below resonance of the power stage which is approximately 10kHz.
In order to eliminate the possibility of subharmonic oscillations, the term which multiplies tON should be set equal to zero eliminating any dependency on duty cycle. M1 NS 2 ? RI + RI ? NP ? M2 = M
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APPLICATION NOTE
The transconductance gain, GM, can be found as follows; GM = ?IO ?VE
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phase margin with these component values is greater than 20dB and 60 degrees, respectively. CIRCUIT EXAMPLE: A 9 to 16VDC input SEPIC converter powering a 35W OSRAM/SYLVANIA DC lamp was built and tested. Data on efficiency, power curve and various oscillagrams of current and voltages in the power/control circuit were taken and are discussed. Magnetics Design L1 The input inductor L1, is designed based on the same criteria as a boost inductor. Energy is stored in L1 during the on time of Q1 and transferred during the off time. L1 is designed to operate in the continuous mode with low current ripple. At 9 VIN with 36W of output power and a converter efficiency of 85%, the average input current is 4.7 Amps. If a total peaktopeak ripple current of 2 Amps is assumed the inductance of L1 can be found. But before we can calculate the inductance required, the minimum and maximum duty cycle must be found so that the maximum and minimum on time of Q1 can be determined. The SEPIC converter has a DC transfer function of; D ; VO = VIN ? n 1?D The turns ratio, n can be found from the maximum acceptable voltage stress on Q1. The stress on Q1 is the sum of the capacitor voltage plus the reflected secondary voltage. The capacitor voltage is essentially equal to VIN, so; VO VDS = VIN + ; n The worst case output voltage on startup of the lamp is restricted to 500V, since this voltage will be reflected back to the drain of Q1. The turns ratio must be chosen so that the drain voltage never exceeds its maximum rating. A IRF1310 was chosen for this application in part because of its 45m? on resistance and VDS = 100V. Calculating the turns ratio at VIN = 16V; n is then found to be 5.8. A turns ratio of 6 is used. The maximum duty cycle can now be determined from the DC transfer function. To find the maximum duty cycle, the worst case steadystate lamp voltage is used of 110VDC at VIN = 9V. Lamp voltages between 60 and 110V will be within the power regulation range of the ballast. Lamp voltages outside of this range will be operated in the constant current mode. Therefore;
The output current is converted to a voltage by the output current sense resistor. The gain of the power stage is then; GP = RIs or; GP = RIs GM where; Rls = the load sense resistance (0.75?) ?IO = load current change (500mA) ?VE = error amp voltage change (5V) GP = ?22.5dB The loop response must now be tailored for good power regulation (high DC gain) and adequate phase and gain margin at the loop crossover frequency. The gain of the LOAD SENSE amplifier is restricted due to the fact that gain of this stage effects the power curve characteristic as shown in above analysis of the power curve equation. The LOADSENSE amplifier should be set up as an integrator so that it can filter out switching frequency noise from the control loop. The pole frequency was chosen to be at 1kHz to give good rejection of the switching frequency noise. This results in a capacitor value of 0.01?F. The low frequency gain of this amplifier is set to 7.5dB. The combination of this gain and the power stage gain results in ?15dB of low frequency gain with a pole at 1kHz. The response can now be tailored with the main error amplifier. A zero must be added in the amplifier response at some midband frequency so that the DC gain for the overall loop is as high as possible. The high frequency gain of this amplifier must be well below 0dB to ensure adequate gain and phase margin for the open loop gain. Since the 16k?, resistor has been determined from the power curve characteristic desired, only the feedback resistor value can be chosen. If this resistor is chosen so that the high frequency gain is to be less then ?20dB for good gain margin, or the feedback resistor value of 1k?, the capacitor value can then be determined. If a zero frequency of 3.4kHz this assumed, this will give an adequate low frequency gain boost. From this, the value of the capacitor can now be determined to be 0.047?F. The gain and ?IO ?VE
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APPLICATION NOTE
DMAX = 0.67 The minimum duty cycle is determined using the minimum steadystate lamp voltage of 60VDC and VIN = 16V. DMIN = 0.38 For a switching frequency of 100kHz, tON MAX = 6.7?S, tON MIN = 3.8?S The inductance based on tON MAX at VIN MIN can be calculated; 9 ? 6.7?S = 30?H. 2 L1 consists of 30T of 19AWG wound on a Micrometals E100 ?18 core. L1= L2 The voltage across the primary winding of L2 when Q1 is on, is for all practical purposes, equal to the input voltage (neglecting voltage ripple on the capacitor) since the series capacitor is switched across the primary. The inductance of the primary winding is chosen based on the peak current desired (it is desired that the inductor current is continuous). The peak current chosen is based on a tradeoff between the voltage stress on Q1 and minimal number of turns to minimize the leakage inductance which in turn means reducing the number of layers of windings. If the peak current thru L2 is restricted to 3.0A, the primary inductance can then calculated as; 9 ? 6.7?S = 20?H. 3 The inductance of L1 and L2 could have been set equal to each other. This would have made both inductors “easy” to integrate on the same core. This was not attempted here because of leakage inductance concerns between the primary and secondary windings of L2. L2 = The number of turns for L2 can now be determined based on the particular core geometry chosen. The area product (AP) required is found from; AP = L ? IP.? IRMS = 0.362 cm2 KF ? J ? BM L = 20?H K = 0.4 IP = 4.7A IRMS = 5.2A
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An RM10PA2503F3 core was used which has an AP of 0.379. The number of primary turns is then; L ? IP 20?H ? 3A = = 7T AE ? B 89 ? e6 ? 0.1T (10T is used since this will easily fit in one layer with the desired core and wire gauge chosen) NP = This ferrite core must be gapped since it stores energy. It is desired that the total gap be placed in the center leg. The gap is calculated from; LP = uO ? uR ? NP2 ? AE = 12.56 ? 107 L
0.89 ? 100 = 0.56mm = 0.02 in 0.020mH The secondary turns can be calculated from the turns ratio as 60T. The core used for L2 has a center leg gap of 0.022 in. Multifilar wire is used for both the primary and secondary turns to minimize the copper losses. The winding sequence used was; primarysecondaryprimarysecondaryprimary. Performance data Performance data on the ballast is presented in the following curves showing efficiency and the measured power curve. Oscillograms of Q1 voltage and current are also given as well as startup characteristics of the lamp voltage and current. The maximum efficiency achieved was 86.2% at a lamp voltage of 100V. The efficiency decrease after this point is due to an increase in output power which occurs at lamp voltages above 100 to 105V. The lamp cold start voltage and current waveforms are shown with a time base of 50mS and 1Sec. As can be seen, the ballast output voltage is 600V before lamp ignition. Once the lamp ignites, the voltage collapses and the lamp current increases to 2A. Eventually, the lamp voltage begins to increase and the current decreases. They will arrive to their steadystate values of 80 to 90VDC and 450mA respectively after approximately 150 seconds.
This is based on the following parameters; B = 0.1T J = 450A/cm
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UDG96243
UDG96244
Figure 5. Efficiency and Power Curve of 35W HID Ballast
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Figure 6. Ballast Output Voltage and Current
Figure 7. Ballast Output Voltage and Current
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Figure 8. MOSFET (Q1) Gate and Drain Voltage at Steady State
Figure 9. MOSFET (Q1) Drain Voltage and Current at Steady State
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Figure 10. Output Rectifier (D1) Current at Steady State
Figure 11. Ballast Hot Restrike Voltage and Current
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35W HID BALLAST PARTS LIST
REF DES RI R2 R3, R5 R4 R6 R7 R9 R11 R12 R13 R14 R15 R16 R17,R18 R19,R25,R32,R8 R20 R21 R22,R23 R24 R26,R27 R30 R31 C33 C1 C2,C3,C26 C4 C8,C11 C6,C7 C9 C10 C12,C13 C14 C15 C16 C17,C18,C19 C5,C24 C25 C30 C31 C32 Z1 Q2,Q3 Q1 D1 HS2,3,4,5 U1 HS1 L1 PART DESCRIPTION 4.7? 1/4 W CC 0.02? 1W 1k 1/4W CC 3.3k 1/4W CC 270k 1/4W CC 100k 1/4W CC 180? 1/2W CC 5.1k 1/4W CC 12.5k 1/4W CC 16.1k 1/4W CC 1k 1/4W CC 150k 1/4W CC 250k 1/4W CC 27k 1/4W CC 10k 1/4W CC 0.75? 3W CC 565k 1/4W CC 282k 1/4W CC 560? 1/2W CC 100k 1/4W CC 18? 3W CC 330? 3W CC 10?F/100V POLY FILM 1?F/50V METALLIZED FILM 470?F/50V ALUM ELEC 0.47?F/630V POLY FILM 0.47?F/50V CERAMIC 4.7?F/250V ALUM ELEC 470pF/25V CERAMIC 10?F/35V ALUM ELEC 1?F METALIZED FILM, NISSEI #R68105K63B 150pF/50V CERAMIC 0.056?F/25V CERAMIC 47?F/25V ALUM ELEC 0.01?F/50V CERAMIC 0.1?F/50V CERAMIC 1000pF/50V CERAMIC 100?F/25V ALUM ELEC 180pF/1kV CERAMIC DISK 1000pF/100V CERAMIC 1N5235B, 6.8V ZENER 2N3904, 40V, 0.200mA TRANISTOR IRF1310, 100V, 0.027? MUR860, 600V, 8A FST REC THERMALLOY#7128D, HS FOR Q2,Q3,Q4 UCC3305JP THERMALLOY #6398P2,HS FOR Q1 E1008 MICROMETALS CORE30T #18AWG 35?H RM10PA2503F3 PHILIPS 10T PRIMARY LITZ(2X10X,1) 60T SECONDARY LITZ(1X15X,1) WINDING SEQUENCE (PRIM10T, SEC30T, PRIM10T,SEC30T, PRIM10T) DIGIKEY NUMBER 10QBKND 1KQBKND 4KQBKND 270KQBKND 100KQBKND 220HBKND 5.1KQBKND 15KQBKND 16KQBKND 1KQBKND 150KQBKND 250KQBKND 27KQBKND 10KQBKND VC3D.75ND 562KXBKND 280KXBKND 560HBKND 100KQBKND VC3D18ND VC3D330ND EF1106ND P4675ND P1248ND EF4225ND P4671ND P6187ND P4808ND P1227ND P4804ND P1240ND P1220ND P4513ND P4525ND P4812ND P1221ND P4119ND P4036ND 1N5235BCTND NEWARK#IRF1310 NEWARK#MUR860 NEWARK#95F715 QTYPER 1 1 2 1 1 1 1 1 1 1 1 1 1 2 4 1 1 2 1 2 1 1 1 1 3 1 2 2 1 1 2 1 1 1 3 2 1 1 1 1 1 2 1 1 4 1 1 1
L2
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APPLICATION NOTE
CONCLUSION The performance data presented of a typical UCC3305 HID lamp controller application, demonstrated it to be a excellent means of controlling a 35W DC metal halide HID lamp. The power regulation and efficiency achieved using the SEPIC converter topology proved it to be a good alternative to other conventional circuit topologies for an automotive lighting application. The many protection and control features of the UCC3305 simplify the task of the ballast designer considerably, making it an economically feasable choice for AC as well as DC HID lamp applications. REFERENCES
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[1] Waymouth: ELECTRIC DISCHARGE LAMPS M.I.T. PRESS, Cambridge Mass. [2] Lloyd Dixon, “High Power Factor Preregular Using Sepic Converter”, Unitrode Power Supply Seminar SEM1100. [3] Abraham Pressman: SWITCHING POWER SUPPLY DESIGN, Mc GrawHill, Inc.
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