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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

description
The TMS320C64x? DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP ge

neration in the TMS320C6000? DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x? is a code-compatible member of the C6000? DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x? DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units〞two multipliers for a 32-bit result and six arithmetic logic units (ALUs)〞 with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI? architecture. The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000? DSP platform devices.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. All three Video Port peripherals have the capability to operate as a video-capture port, a video-display port, or a transport stream interface (TSI) capture port. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU每BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M). These three video port peripherals are configurable and can support either video capture and video display modes. Each video port consists of two channels 〞 A and B with a 5120-byte capture/display buffer that is splittable between the two channels. For capture operation, the video port can operate as two 8/10-bit channels of BT.656 or two 8/10-bit channel of raw video capture; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI. For display operation, the video port can operate as a single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the TMS320DM642 Technical Overview (literature number 每 TBD).

TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.

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PRODUCT PREVIEW

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port (GP0) with 16 GPIO pins; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

description (continued)
The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. VXCO interpolated control port (VIC) 每 TBD Ethernet MAC (EMAC) 每 TBD Management data input/output (MDIO) 每 TBD

PRODUCT PREVIEW

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger interface for visibility into source code execution.

Windows is a registered trademark of the Microsoft Corporation.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

device characteristics
Table 1 provides an overview of the DM642 DSP. The table shows significant features of the DM642 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the DM642 Processor
HARDWARE FEATURES EMIFA (64-bit bus width) (clock source = AECLKIN) EDMA (64 independent channels) McASP0 (uses AUXCLK or SYSCLK2) I2C0 (uses SYSCLK2) Peripherals Peri herals Not all peripherals pins are available at the same time (For more detail detail, see the Device Configuration section). HPI (32- or 16-bit user selectable) PCI (32-bit), 66-MHz McBSPs (internal clock source = CPU/4 clock frequency) Configurable Video Ports (VP0, VP1, VP2) 10/100 Ehternet MAC (EMAC) Management Data Input/Output (MDIO) VXCO Interpolated Control Port (VIC) 32-Bit Timers (internal clock source = CPU/8 clock frequency) General-Purpose Input/Output Port (GP0) Size (Bytes) On-Chip Memory Organization Control Status Register (CSR.[31:16]) JTAGID register (address location: 0x01B3F008) MHz ns DM642 1 1 1 1 1 (HPI16 or HPI32) 1 2 3 1 1 3 16 288K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 256KB Unified Mapped RAM/Cache (L2) 0x0C01 0x0007902F 500, 600 2 ns (DM642-500 [500 MHz CPU, 100 MHz EMIF]) 1.67 ns (DM642-600 [600 MHz CPU, 100 MHz EMIF]) 1.67 ns (DM642-603 [600 MHz CPU, 133 MHz EMIF]) 1.2 V (-500) 1.4 V (-600, -603) 3.3 V Bypass (x1), x6, x12 548-Pin BGA (GDK) 0.12 ?m PP

CPU ID + CPU Rev ID JTAG BSDL_ID Frequency Cycle Time

Voltage PLL Options BGA Package Process Technology Product Status?

Core (V) I/O (V) CLKIN frequency multiplier 23 x 23 mm ?m Product Preview (PP) Advance Information (AI) Production Data (PD) (For more details on the C6000? DSP part numbering, see Figure 4)

Device Part Numbers

TMX320DM642GDK

? On this DM64x? device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device speed portion of this data sheet. ? PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PRODUCT PREVIEW

1

TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

device compatibility
The DM642 device is a code-compatible member of the C6000? DSP platform. TBD

PRODUCT PREVIEW

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

functional block and CPU (DSP core) diagram
SDRAM SBSRAM ZBT SRAM FIFO SRAM ROM/FLASH I/O Devices Video Port 2 (VP2) Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path A A Register File A31每A16 A15每A0 Data Path B B Register File B31每B16 B15每B0
64

EMIF A Timer 2 Timer 1 Timer 0 VCXO Interpolated Control Port (VIC)

DM642
L1P Cache Direct-Mapped 16K Bytes Total

C64x DSP Core Instruction Fetch Control Registers Control Logic Test Advanced In-Circuit Emulation Interrupt Control

Video Port 0 (VP0) OR 8/10-bit VP0 AND McBSP0? OR McASP0 Control Enhanced DMA Controller (edma) L2 Cache Memory 256kBytes

.L1

.S1

.M1 .D1

.D2 .M2 .S2

.L2

Video Port 1 (VP1) OR 8/10-bit VP1 AND McBSP1? OR McASP0 Data

L1D Cache 2-Way Set-Associative 16K Bytes Total

See Note A

PLL (x1, x6, x12)

Power-Down Logic

PCI-66 OR HPI32 OR HPI16 AND EMAC MDIO Boot Configuration

16

GP0
16

I2C0

? McBSPs: Framing Chips 每 H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

CPU (DSP core) description
The CPU fetches VelociTI? advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI? VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x? VelociTI.2? extensions add enhancements to the TMS320C62x? DSP VelociTI? architecture. These enhancements include:

PRODUCT PREVIEW

D D D D D D

Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x? VelociTI? VLIW architecture, the C64x? register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a ※data cross path§〞a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x? DSP fixed-point instructions, the C64x? DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2? extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key factor for video and imaging applications. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically ※true§).
TMS320C62x is a trademark of Texas Instruments.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

CPU (DSP core) description (continued)
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 ℅ 16-bit multiplies or four 8 ℅ 8-bit multiplies per clock cycle. The .M unit can also perform 16 ℅ 32-bit multiply operations, dual 16 ℅ 16-bit multiplies with add/subtract operations, and quad 8 ℅ 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are ※linked§ together by ※1§ bits in the least significant bit (LSB) position of the instructions. The instructions that are ※chained§ together for simultaneous execution (up to eight in total) compose an execute packet. A ※0§ in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x? DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x?/TMS320C67x? DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x? DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) TMS320DM642 Technical Brief (literature number TBD)

TMS320C67x is a trademark of Texas Instruments.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

CPU (DSP core) description (continued)
src1 .L1 src2 8 8

dst long dst long src ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A src2 long dst dst .M1 src1 src2

8 8 Register File A (A0每A31)

See Note A See Note A

PRODUCT PREVIEW

LD1b (Load Data) LD1a (Load Data) DA1 (Address)

32 MSBs 32 LSBs .D1 dst src1 src2 2X 1X src2

DA2 (Address) LD2a (Load Data) LD2b (Load Data) 32 LSBs 32 MSBs

.D2

src1 dst

src2 .M2 src1 dst long dst src2 Data Path B .S2 src1 dst long dst long src See Note A See Note A Register File B (B0每 B31) 8 8

ST2a (Store Data) ST2b (Store Data)

32 MSBs 32 LSBs long src long dst dst .L2 src2 src1 Control Register File 8 8

NOTE B: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.

Figure 1. TMS320C64x? CPU (DSP Core) Data Paths

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

memory map summary
Table 2 shows the memory map address ranges of the DM642 device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the DM642 device begin at the hex address location 0x8000 0000 for EMIFA. Table 2. TMS320DM642 Memory Map Summary
MEMORY BLOCK DESCRIPTION Internal RAM (L2) Reserved Reserved External Memory Interface A (EMIFA) Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers EDMA RAM and EDMA Registers Reserved Timer 2 Registers GP0 Registers Device Configuration Registers I2C0 Data and Control Registers Reserved McASP0 Control Registers Reserved Reserved Emulation PCI Registers VP0 Control VP1 Control VP2 Control VIC Control Reserved EMAC Control EMAC Wrapper EWRAP Registers MDIO Control Registers Reserved QDMA Registers Reserved McBSP 0 Data McBSP 1 Data Reserved BLOCK SIZE (BYTES) 256K 768K 23M 256K 256K 256K 256K 256K 256K 256K 256K 256K 512K 256K 256K 每 4K 4K 16K 32K 16K 192K 256K 256K 256K 16K 16K 16K 16K 192K 4K 8K 2K 2K 3.5M 52 928M 每 52 64M 64M 64M HEX ADDRESS RANGE

0000 0004 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01AC 01B0 01B3 01B4 01B4 01B4 01B5 01B8 01BC 01C0 01C4 01C4 01C4 01C4 01C5 01C8 01C8 01C8 01C8 01C8 0200 0200 3000 3400 3800

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 F000 0000 4000 C000 0000 0000 0000 0000 0000 4000 8000 C000 0000 0000 1000 3000 3800 4000 0000 0034 0000 0000 0000

每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每

0003 000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01AB 01AF 01B3 01B3 01B4 01B4 01B4 01B7 01BB 01BF 01C3 01C4 01C4 01C4 01C4 01C7 01C8 01C8 01C8 01C8 01FF 0200 2FFF 33FF 37FF 3BFF

FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF EFFF FFFF 3FFF BFFF FFFF FFFF FFFF FFFF FFFF 3FFF 7FFF BFFF FFFF FFFF 0FFF 2FFF 37FF 3FFF FFFF 0033 FFFF FFFF FFFF FFFF

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

McASP0 Data Reserved Reserved VP0 Channel A Data VP0 Channel B Data VP1 Channel A Data VP1 Channel B Data VP2 Channel A Data VP2 Channel B Data EMIFA CE0 EMIFA CE1 EMIFA CE2 EMIFA CE3 Reserved

1M 64M 每 1M 832M 32M 32M 32M 32M 32M 32M 256M 256M 256M 256M 1G

3C00 3C10 4000 7400 7600 7800 7A00 7C00 7E00 8000 9000 A000 B000 C000

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

每 每 每 每 每 每 每 每 每 每 每 每 每 每

3C0F 3FFF 73FF 75FF 77FF 79FF 7BFF 7DFF 7FFF 8FFF 9FFF AFFF BFFF FFFF

FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF

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TMS320DM642 DIGITAL MEDIA PROCESSOR
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peripheral register descriptions
Table 3 through Table 27 identify the peripheral registers for the DM642 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 3. EMIFA Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 每 0180 0040 0180 0044 0180 0048 0180 004C 0180 0050 0180 0054 0180 0058 每 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 每 CECTL2 CECTL3 SDCTL SDTIM SDEXT 每 CESEC1 CESEC0 每 CESEC2 CESEC3 每 EMIFA global control EMIFA CE1 space control EMIFA CE0 space control Reserved EMIFA CE2 space control EMIFA CE3 space control EMIFA SDRAM control EMIFA SDRAM refresh control EMIFA SDRAM extension Reserved EMIFA CE1 space secondary control EMIFA CE0 space secondary control Reserved EMIFA CE2 space secondary control EMIFA CE3 space secondary control Reserved REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)

Table 4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE 0184 0000 0184 2000 0184 2004 0184 2008 0184 200C 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 ACRONYM CCFG 每 L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 每 L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC 每 L2FLUSH L2CLEAN 每 0184 8000 每0184 81FC 0184 8200 0184 8204 0184 8208 0184 820C 0184 8210 0184 8214 0184 8218 0184 821C 0184 8220 0184 8224 0184 8228 0184 822C 0184 8230 0184 8234 0184 8238 0184 823C 0184 8240 0184 8244 0184 8248 MAR0 to MAR127 MAR128 MAR129 MAR130 MAR131 MAR132 MAR133 MAR134 MAR135 MAR136 MAR137 MAR138 MAR139 MAR140 MAR141 MAR142 MAR143 MAR144 MAR145 MAR146 Reserved L2 allocation register 0 L2 allocation register 1 L2 allocation register 2 L2 allocation register 3 Reserved L2 flush base address register L2 flush word count register L2 clean base address register L2 clean word count register L1P flush base address register L1P flush word count register L1D flush base address register L1D flush word count register Reserved L2 flush register L2 clean register Reserved Reserved Controls EMIFA CE0 range 8000 0000 每 80FF FFFF Controls EMIFA CE0 range 8100 0000 每 81FF FFFF Controls EMIFA CE0 range 8200 0000 每 82FF FFFF Controls EMIFA CE0 range 8300 0000 每 83FF FFFF Controls EMIFA CE0 range 8400 0000 每 84FF FFFF Controls EMIFA CE0 range 8500 0000 每 85FF FFFF Controls EMIFA CE0 range 8600 0000 每 86FF FFFF Controls EMIFA CE0 range 8700 0000 每 87FF FFFF Controls EMIFA CE0 range 8800 0000 每 88FF FFFF Controls EMIFA CE0 range 8900 0000 每 89FF FFFF Controls EMIFA CE0 range 8A00 0000 每 8AFF FFFF Controls EMIFA CE0 range 8B00 0000 每 8BFF FFFF Controls EMIFA CE0 range 8C00 0000 每 8CFF FFFF Controls EMIFA CE0 range 8D00 0000 每 8DFF FFFF Controls EMIFA CE0 range 8E00 0000 每 8EFF FFFF Controls EMIFA CE0 range 8F00 0000 每 8FFF FFFF Controls EMIFA CE1 range 9000 0000 每 90FF FFFF Controls EMIFA CE1 range 9100 0000 每 91FF FFFF Controls EMIFA CE1 range 9200 0000 每 92FF FFFF REGISTER NAME Cache configuration register COMMENTS

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TMS320DM642 DIGITAL MEDIA PROCESSOR
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peripheral register descriptions (continued)
Table 4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE 0184 824C 0184 8250 0184 8254 0184 8258 0184 825C 0184 8260 0184 8264 0184 8268 0184 826C 0184 8270 0184 8274 0184 8278 0184 827C 0184 8280 0184 8284 0184 8288 0184 828C 0184 8290 0184 8294 0184 8298 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 0184 82B8 0184 82BC 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0184 82D4 0184 82D8 0184 82DC 0184 82E0 0184 82E4 0184 82E8 0184 82EC 0184 82F0 ACRONYM MAR147 MAR148 MAR149 MAR150 MAR151 MAR152 MAR153 MAR154 MAR155 MAR156 MAR157 MAR158 MAR159 MAR160 MAR161 MAR162 MAR163 MAR164 MAR165 MAR166 MAR167 MAR168 MAR169 MAR170 MAR171 MAR172 MAR173 MAR174 MAR175 MAR176 MAR177 MAR178 MAR179 MAR180 MAR181 MAR182 MAR183 MAR184 MAR185 MAR186 MAR187 MAR188 REGISTER NAME Controls EMIFA CE1 range 9300 0000 每 93FF FFFF Controls EMIFA CE1 range 9400 0000 每 94FF FFFF Controls EMIFA CE1 range 9500 0000 每 95FF FFFF Controls EMIFA CE1 range 9600 0000 每 96FF FFFF Controls EMIFA CE1 range 9700 0000 每 97FF FFFF Controls EMIFA CE1 range 9800 0000 每 98FF FFFF Controls EMIFA CE1 range 9900 0000 每 99FF FFFF Controls EMIFA CE1 range 9A00 0000 每 9AFF FFFF Controls EMIFA CE1 range 9B00 0000 每 9BFF FFFF Controls EMIFA CE1 range 9C00 0000 每 9CFF FFFF Controls EMIFA CE1 range 9D00 0000 每 9DFF FFFF Controls EMIFA CE1 range 9E00 0000 每 9EFF FFFF Controls EMIFA CE2 range A000 0000 每 A0FF FFFF Controls EMIFA CE2 range A100 0000 每 A1FF FFFF Controls EMIFA CE2 range A200 0000 每 A2FF FFFF Controls EMIFA CE2 range A300 0000 每 A3FF FFFF Controls EMIFA CE2 range A400 0000 每 A4FF FFFF Controls EMIFA CE2 range A500 0000 每 A5FF FFFF Controls EMIFA CE2 range A600 0000 每 A6FF FFFF Controls EMIFA CE2 range A700 0000 每 A7FF FFFF Controls EMIFA CE2 range A800 0000 每 A8FF FFFF Controls EMIFA CE2 range A900 0000 每 A9FF FFFF Controls EMIFA CE2 range AA00 0000 每 AAFF FFFF Controls EMIFA CE2 range AB00 0000 每 ABFF FFFF Controls EMIFA CE2 range AC00 0000 每 ACFF FFFF Controls EMIFA CE2 range AD00 0000 每 ADFF FFFF Controls EMIFA CE2 range AE00 0000 每 AEFF FFFF Controls EMIFA CE2 range AF00 0000 每 AFFF FFFF Controls EMIFA CE3 range B000 0000 每 B0FF FFFF Controls EMIFA CE3 range B100 0000 每 B1FF FFFF Controls EMIFA CE3 range B200 0000 每 B2FF FFFF Controls EMIFA CE3 range B300 0000 每 B3FF FFFF Controls EMIFA CE3 range B400 0000 每 B4FF FFFF Controls EMIFA CE3 range B500 0000 每 B5FF FFFF Controls EMIFA CE3 range B600 0000 每 B6FF FFFF Controls EMIFA CE3 range B700 0000 每 B7FF FFFF Controls EMIFA CE3 range B800 0000 每 B8FF FFFF Controls EMIFA CE3 range B900 0000 每 B9FF FFFF Controls EMIFA CE3 range BA00 0000 每 BAFF FFFF Controls EMIFA CE3 range BB00 0000 每 BBFF FFFF Controls EMIFA CE3 range BC00 0000 每 BCFF FFFF Controls EMIFA CE1 range 9F00 0000 每 9FFF FFFF COMMENTS

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE 0184 82F4 0184 82F8 0184 82FC 0184 8300 每0184 83FC 0184 8400 每0187 FFFF ACRONYM MAR189 MAR190 MAR191 MAR192 to MAR255 每 REGISTER NAME Controls EMIFA CE3 range BD00 0000 每 BDFF FFFF Controls EMIFA CE3 range BE00 0000 每 BEFF FFFF Controls EMIFA CE3 range BF00 0000 每 BFFF FFFF Reserved Reserved COMMENTS

Table 5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 每 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 QSOPT QSSRC QSCNT QSDST QSIDX ACRONYM QOPT QSRC QCNT QDST QIDX REGISTER NAME QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA psuedo source address register QDMA psuedo frame count register QDMA destination address register QDMA psuedo index register

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 6. EDMA Registers (C64x)
HEX ADDRESS RANGE 01A0 0800 每 01A0 FF98 01A0 FF9C 01A0 FFA4 01A0 FFA8 01A0 FFAC 01A0 FFB0 01A0 FFB4 01A0 FFB8 01A0 FFBC 01A0 FFC0 01A0 FFC4 01A0 FFC8 01A0 FFCC 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 每 01A3 FFFF ACRONYM 每 EPRH CIPRH CIERH CCERH ERH EERH ECRH ESRH PQAR0 PQAR1 PQAR2 PQAR3 EPRL PQSR CIPRL CIERL CCERL ERL EERL ECRL ESRL 每 Reserved Event polarity high register Channel interrupt pending high register Channel interrupt enable high register Channel chain enable high register Event high register Event enable high register Event clear high register Event set high register Priority queue allocation register 0 Priority queue allocation register 1 Priority queue allocation register 2 Event polarity low register Priority queue status register Channel interrupt pending low register Channel interrupt enable low register Channel chain enable low register Event low register Event enable low register Event clear low register Event set low register Reserved Priority queue allocation register 3 REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 7. EDMA Parameter RAM (C64x)?
HEX ADDRESS RANGE 01A0 0000 每 01A0 0017 01A0 0018 每 01A0 002F 01A0 0030 每 01A0 0047 01A0 0048 每 01A0 005F 01A0 0060 每 01A0 0077 01A0 0078 每 01A0 008F 01A0 0090 每 01A0 00A7 01A0 00A8 每 01A0 00BF 01A0 00C0 每 01A0 00D7 01A0 00D8 每 01A0 00EF 01A0 00F0 每 01A0 00107 01A0 0108 每 01A0 011F 01A0 0120 每 01A0 0137 01A0 0138 每 01A0 014F 01A0 0150 每 01A0 0167 01A0 0168 每 01A0 017F 01A0 0150 每 01A0 0167 01A0 0168 每 01A0 017F ... 01A0 05D0 每 01A0 05E7 01A0 05E8 每 01A0 05FF 01A0 0600 每 01A0 0617 01A0 0618 每 01A0 062F ... 01A0 07E0 每 01A0 07F7 01A0 07F8 每 01A0 07FF 01A0 0800 每 01A0 0817 ... 01A0 13C8 每 01A0 13DF 01A0 13E0 每 01A0 13F7 01A0 13F8 每 01A0 13FF 01A0 1400 每 01A3 FFFF 每 每 每 每 每 每 每 每 每 每 每 ACRONYM 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 REGISTER NAME Parameters for Event 0 (6 words) Parameters for Event 1 (6 words) Parameters for Event 2 (6 words) Parameters for Event 3 (6 words) Parameters for Event 4 (6 words) Parameters for Event 5 (6 words) Parameters for Event 6 (6 words) Parameters for Event 7 (6 words) Parameters for Event 8 (6 words) Parameters for Event 9 (6 words) Parameters for Event 10 (6 words) Parameters for Event 11 (6 words) Parameters for Event 12 (6 words) Parameters for Event 13 (6 words) Parameters for Event 14 (6 words) Parameters for Event 15 (6 words) Parameters for Event 16 (6 words) Parameters for Event 17 (6 words) ... Parameters for Event 62 (6 words) Parameters for Event 63 (6 words) Reload/link parameters for Event 0 (6 words) Reload/link parameters for Event 1 (6 words) ... Reload/link parameters for Event 20 (6 words) Reload/link parameters for Event 21 (6 words) Reload/link parameters for Event 22 (6 words) ... Reload/link parameters for Event 147 (6 words) Reload/link parameters for Event 148 (6 words) Scratch pad area (2 words) Reload/Link Parameters for other Event 0每15 COMMENTS Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event

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Reserved ? The DM64x device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 每 019C 01FF 019C 0200 019C 0204 每 019F FFFF ACRONYM MUXH MUXL EXTPOL 每 PDCTL 每 REGISTER NAME Interrupt multiplexer high Interrupt multiplexer low External interrupt polarity Reserved Peripheral power-down control register (see Table 9) Reserved COMMENTS Selects which interrupts drive CPU interrupts 10每15 (INT10每INT15) Selects which interrupts drive CPU interrupts 4每9 (INT04每INT09) Sets the polarity of the external interrupts (EXT_INT4每EXT_INT7)

Table 9. Peripheral Power-Down Control Register
HEX ADDRESS RANGE 019C 0200 ACRONYM PDCTL REGISTER NAME Peripheral power-down control register

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 10. Ethernet MAC (EMAC) Registers
HEX ADDRESS RANGE 01C4 C000 01C4 C004 01C4 C008 01C4 C00C 01C4 C010 01C4 C014 01C4 C018 01C4 C01C 01C4 C020 每 01C4 FFFF 01C4 C00C 每 01C4 FFFF 01C4 C00C 每 01C4 FFFF 每 每 每 Reserved Reserved RX_IdVer Rx_Control Rx_Teardown Receive (RX) identification and version register RX control register RX teardown register ACRONYM TX_IdVer Tx_Control Tx_Teardown TX control register TX teardown register REGISTER NAME Transmit (TX) identification and version register

Table 11. Device Configuration Registers

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HEX ADDRESS RANGE 01B3 F000

ACRONYM PERCFG

REGISTER NAME Peripheral Configuration Register

COMMENTS Enables or disables specific peripherals. This register is also used for power-down of disabled peripherals. Read-only. Provides status of the User*s device configuration on reset. Read-only. Provides 32-bit JTAG ID of the device.

01B3 F004 01B3 F008 01B3 F00C 01B3 F010 01B3 F014 每 01B3 FFFF

DEVSTAT JTAGID 每 每 每

Device Status Register JTAG Identification Register Reserved Reserved Reserved

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SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 12. McBSP 0 Registers
HEX ADDRESS RANGE 018C 0000 0x3000 0000 每 0x33FF FFFF 018C 0004 0x3000 0000 每 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018C 002C 018C 0030 018C 0034 018C 0038 018C 003C 018C 0040 每 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCERE00 XCERE00 PCR0 RCERE10 XCERE10 RCERE20 XCERE20 RCERE30 XCERE30 每 REGISTER NAME McBSP0 data receive register via Configuration Bus McBSP0 data receive register via Peripheral Bus McBSP0 data transmit register via Configuration Bus McBSP0 data transmit register via Peripheral Bus McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 McBSP0 enhanced transmit channel enable register 0 McBSP0 pin control register McBSP0 enhanced receive channel enable register 1 McBSP0 enhanced transmit channel enable register 1 McBSP0 enhanced receive channel enable register 2 McBSP0 enhanced transmit channel enable register 2 McBSP0 enhanced receive channel enable register 3 McBSP0 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 13. McBSP 1 Registers
HEX ADDRESS RANGE 0190 0000 0x3400 0000 每 0x37FF FFFF 0190 0004 0x3400 0000 每 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0190 002C 0190 0030 0190 0034 0190 0038 0190 003C 0190 0040 每 0193 FFFF ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCERE01 XCERE01 PCR1 RCERE11 XCERE11 RCERE21 XCERE21 RCERE31 XCERE31 每 REGISTER NAME McBSP1 data receive register via Configuration Bus McBSP1 data receive register via Peripheral Bus McBSP1 data transmit register via Configuration Bus McBSP1 data transmit register via Peripheral Bus McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 McBSP1 enhanced transmit channel enable register 0 McBSP1 pin control register McBSP1 enhanced receive channel enable register 1 McBSP1 enhanced transmit channel enable register 1 McBSP1 enhanced receive channel enable register 2 McBSP1 enhanced transmit channel enable register 2 McBSP1 enhanced receive channel enable register 3 McBSP1 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 14. Timer 0 Registers
HEX ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer 0 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.

0194 0004

PRD0

Timer 0 period register

0194 0008 0194 000C 每 0197 FFFF

CNT0 每

Timer 0 counter register Reserved

Table 15. Timer 1 Registers
HEX ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer 1 control register COMMENTS

0198 0004

PRD1

Timer 1 period register

Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.

0198 0008 0198 000C 每 019B FFFF

CNT1 每

Timer 1 counter register Reserved

Table 16. Timer 2 Registers
HEX ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME Timer 2 control register COMMENTS Determines the operating mode of the timer, monitors the timer status. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.

01AC 0004

PRD2

Timer 2 period register

01AC 0008 01AC 000C 每 01AF FFFF

CNT2 每

Timer 2 counter register Reserved

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Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.

TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 17. HPI Registers (C64x)
HEX ADDRESS RANGE 每 0188 0000 0188 0004 0188 0008 ACRONYM HPID HPIC HPIA (HPIAW)? HPIA (HPIAR)? HPI data register HPI control register HPI address register (Write) HPI address register (Read) REGISTER NAME COMMENTS Host read/write access only HPIC has both Host/CPU read/write access HPIA has both Host/CPU read/write access

0188 0001 每 018B FFFF 每 Reserved ? Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.

Table 18. GP0 Registers (C64x)
HEX ADDRESS RANGE 01B0 0000 ACRONYM GPEN GPDIR GPVAL 每 GPDH GPHM GPDL GPLM GPGC GPPOL 每 REGISTER NAME GP0 enable register GP0 direction register GP0 value register Reserved GP0 delta high register GP0 high mask register GP0 delta low register GP0 low mask register GP0 global control register GP0 interrupt polarity register Reserved

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01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 每 01B3 EFFF

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 19. PCI Peripheral Registers
HEX ADDRESS RANGE 01C0 0000 01C0 0004 01C0 0008 01C0 000C 01C0 0010 01C0 0014 01C0 0018 01C0 001C 01C0 0020 01C0 0024 01C0 0028 01C0 002C 每 01C1 FFEF 0x01C1 FFF0 0x01C1 FFF4 0x01C1 FFF8 0x01C1 FFFC 01C2 0000 01C2 0004 01C2 0008 01C2 000C 每 01C2 FFFF 01C3 0000 01C3 0004 每 01C3 FFFF TBD ACRONYM RSTSRC PMDCSR PCIIS PCIIEN DSPMA PCIMA PCIMC CDSPA CPCIA CCNT 每 每 HSR HDCR DSPP 每 EEADD EEDAT EECTL 每 PCI_TRCNTL 每 PID REGISTER NAME DSP Reset source/status register Power management DSP control/status register PCI interrupt source register PCI interrupt enable register DSP master address register PCI master address register PCI master control register Current DSP address register Current PCI address register Current byte count register Reserved Reserved Host status register Host-to-DSP control register DSP page register Reserved EEPROM address register EEPROM data register EEPROM control register Reserved PCI transfer request control register Reserved Peripheral device identification register Register value TBD

Table 20. VXCO Interpolated Control Port (VIC) Registers
HEX ADDRESS RANGE 01C8 C000 01C8 C004 01C8 C008 01C4 C00C 每 01C4 FFFF ACRONYM VIC_CTL VIC_IN VP_DIV 每 VIC control register VIC input register VIC clock divider register Reserved REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 21. MDIO Registers
HEX ADDRESS RANGE 01C8 3800 01C8 3804 01C8 3808 01C8 380C 01C8 3810 每 01C8 3FFF 每 Reserved ACRONYM REGISTER NAME

Table 22. Video Port 2 (VP2) Control Registers TBD
HEX ADDRESS RANGE 01C4 8000 01C4 8004 01C4 8008 01C4 800C 01C4 8010 01C4 8014 ACRONYM VP_CTL VP_STAT VP_IE VP_IS VP2 control register VP2 status register VP2 interrupt enable register VP2 interrupt status register REGISTER NAME

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TBD 每 01C4 BFFF



Reserved

Table 23. Video Port 1 (VP1) Control Registers TBD
HEX ADDRESS RANGE 01C4 4000 01C4 4004 01C4 4008 01C4 400C 01C4 4010 01C4 4014 TBD 每 01C4 7FFF 每 Reserved ACRONYM VP_CTL VP_STAT VP_IE VP_IS VP1 control register VP1 status register VP1 interrupt enable register VP1 interrupt status register REGISTER NAME

Table 24. Video Port 0 (VP0) Control Registers TBD
HEX ADDRESS RANGE 01C4 0000 01C4 0004 01C4 0008 01C4 000C 01C4 8010 01C4 8014 TBD 每 01C4 3FFF 每 Reserved ACRONYM VP_CTL VP_STAT VP_IE VP_IS VP0 control register VP0 status register VP0 interrupt enable register VP0 interrupt status register REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)

Table 25. McASP0 Registers 每 TBD Need to Split Control and Data
HEX ADDRESS RANGE 01B4 C000 01B4 C004 01B4 C008 01B4 C00C 01B4 C010 01B4 C014 01B4 C018 01B4 C01C 01B4 C020 01B4 C024 每 01B4 C040 01B4 C044 01B4 C048 01B4 C04C 01B4 C050 01B4 C054 每 01B4 C05C 01B4 C060 01B4 C064 01B4 C068 01B4 C06C 01B4 C070 01B4 C074 01B4 C078 01B4 C07C 01B4 C080 01B4 C084 01B4 C088 01B4 C08C 每 01B4 C09C 01B4 C0A0 01B4 C0A4 01B4 C0A8 01B4 C0AC 01B4 C0B0 01B4 C0B4 01B4 C0B8 01B4 C0BC 01B4 C0C0 01B4 C0C4 01B4 C0C8 ACRONYM PID PWRDEMU 每 每 PFUNC PDIR PDOUT PDIN/PDSET PDCLR 每 GBLCTL AMUTE DLBCTL DITCTL 每 RGBLCTL RMASK RFMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RSTAT RSLOT RCLKCHK 每 XGBLCTL XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XSTAT XSLOT XCLKCHK REGISTER NAME Peripheral Identification register [Register value: TBD] Power down and emulation management register Reserved Reserved Pin function register Pin direction register Pin data out register Pin data in / data set register Read returns: PDIN Writes affect: PDSET Pin data clear register Global control register Mute control register Digital Loop-back control register DIT mode control register Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0每31 register Receiver interrupt control register Status register 每 Receiver Current receive TDM slot register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register Transmit TDM slot 0每31 register Transmit interrupt control register Status register 每 Transmitter Current transmit TDM slot Transmit clock check control register

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Reserved

TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 25. McASP0 Registers (Continued)每 TBD Need to Split Control and Data
HEX ADDRESS RANGE 01B4 C0CC 01B4 C0D0 每 01B4 C0FC 01B4 C100 01B4 C104 01B4 C108 01B4 C10C 01B4 C110 01B4 C114 01B4 C118 01B4 C11C 01B4 C120 01B4 C124 01B4 C128 01B4 C12C 01B4 C130 01B4 C134 01B4 C138 01B4 C13C 01B4 C140 01B4 C144 01B4 C148 01B4 C14C 01B4 C150 01B4 C154 01B4 C158 01B4 C15C 01B4 C160 每 01B4 C17C 01B4 C180 01B4 C184 01B4 C188 01B4 C18C 01B4 C190 01B4 C194 01B4 C198 01B4 C19C 01B4 C1A0 每 01B4 C1FC 01B4 C200 01B4 C204 01B4 C208 01B4 C20C 01B4 C210 01B4 C214 ACRONYM XEVTCTL 每 DITCSRA0 DITCSRA1 DITCSRA2 DITCSRA3 DITCSRA4 DITCSRA5 DITCSRB0 DITCSRB1 DITCSRB2 DITCSRB3 DITCSRB4 DITCSRB5 DITUDRA0 DITUDRA1 DITUDRA2 DITUDRA3 DITUDRA4 DITUDRA5 DITUDRB0 DITUDRB1 DITUDRB2 DITUDRB3 DITUDRB4 DITUDRB5 每 SRCTL0 SRCTL1 SRCTL2 SRCTL3 SRCTL4 SRCTL5 SRCTL6 SRCTL7 每 XBUF0 XBUF1 XBUF2 XBUF3 XBUF4 XBUF5 Tranmitter DMA control register Reserved Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Reserved Serializer 0 control register Serializer 1 control register Serializer 2 control register Serializer 3 control register Serializer 4 control register Serializer 5 control register Serializer 6 control register Serializer 7 control register Reserved Transmit Buffer for Serializer 0 Transmit Buffer for Serializer 1 Transmit Buffer for Serializer 2 Transmit Buffer for Serializer 3 Transmit Buffer for Serializer 4 Transmit Buffer for Serializer 5 REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

peripheral register descriptions (continued)
Table 25. McASP0 Registers (Continued)每 TBD Need to Split Control and Data
HEX ADDRESS RANGE 01B4 C218 01B4 C21C 01B4 C220 每 01B4 C27C 01B4 C280 01B4 C284 01B4 C288 01B4 C28C 01B4 C290 01B4 C294 01B4 C298 01B4 C29C 01B4 C2A0 每 01B4 FFFF ACRONYM XBUF6 XBUF7 每 RBUF0 RBUF1 RBUF2 RBUF3 RBUF4 RBUF5 RBUF6 RBUF7 每 Transmit Buffer for Serializer 6 Transmit Buffer for Serializer 7 Reserved Receive Buffer for Serializer 0 Receive Buffer for Serializer 1 Receive Buffer for Serializer 2 Receive Buffer for Serializer 3 Receive Buffer for Serializer 4 Receive Buffer for Serializer 5 Receive Buffer for Serializer 6 Receive Buffer for Serializer 7 Reserved REGISTER NAME

Table 26. McASP0 Data Registers TBD
HEX ADDRESS RANGE 3C00 0000 3C00 0004 3C00 0008 3C00 000C 每 3C0F FFFF ACRONYM register REGISTER NAME

Table 27. I2C0 Registers
HEX ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B4 0024 01B4 0028 01B4 002C 01B4 0030 01B4 0034 01B4 0038 01B4 003C 每 01B4 3FFF ACRONYM I2COAR0 I2CIER0 I2CSTR0 I2CCLKL0 I2CCLKH0 I2CCNT0 I2CDRR0 I2CSAR0 I2CDXR0 I2CMDR0 I2CISRC0 每 I2CPSC0 I2CPID10 I2CPID20 每 I2C0 own address register I2C0 interrupt enable register I2C0 interrupt status register I2C0 clock low-time divider register I2C0 clock high-time divider register I2C0 data count register I2C0 data receive register I2C0 slave address register I2C0 data transmit register I2C0 mode register I2C0 interrupt source register Reserved I2C0 prescaler register I2C0 Peripheral Identification register 1 [DA610 value: 0x0000 0101] I2C0 Peripheral Identification register 2 [DA610 value: 0x0000 0005] Reserved REGISTER NAME

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TMS320DM642 DIGITAL MEDIA PROCESSOR
SPRS200 每 JULY 2002

EDMA channel synchronization events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 28 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the DM642 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 28. TMS320DM642 EDMA Channel Synchronization Events? 每 TBD
EDMA CHANNEL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20每23 24 25 26 27每31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

EVENT NAME
DSP_INT TINT0 TINT1 SD_INTA GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 VP0EVTYA VP0EVTUA VP0EVTVA TINT2 每 VP0EVTYB VP0EVTUB VP0EVTVB 每 AXEVTE0 AXEVTO0 AXEVT0 AREVTE0 AREVTO0 AREVT0 VP1EVTYB VP1EVTUB VP1EVTVB VP2EVTYB VP2EVTUB VP2EVTVB ICREVT0 ICXEVT0 HPI/PCI-to-DSP interrupt Timer 0 interrupt Timer 1 interrupt EMIFA SDRAM timer interrupt GP0 event 4/External interrupt pin 4 GP0 event 5/External interrupt pin 5 GP0 event 6/External interrupt pin 6 GP0 event 7/External interrupt pin 7 GP0 event 0 GP0 event 1 GP0 event 2 GP0 event 3 McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event VP0 Channel A Y event DMA request VP0 Channel A Cb event DMA request VP0 Channel A Cr event DMA request Timer 2 interrupt None VP0 Channel B Y event DMA request VP0 Channel B Cb event DMA request VP0 Channel B Cr event DMA request None McASP0 transmit event 每每TBD McASP0 tranmit event 每每TBD McASP0 tranmit event 每每TBD McASP0 receive event 每每TBD McASP0 receive event 每每TBD McASP0 receive event 每每TBD VP1 event YB 每每TBD VP1 event UB 每每TBD VP1 event VB 每每TBD VP2 event YB 每每TBD VP2 event UB 每每TBD VP2 event VB 每每TBD I2C0 receive event 每每TBD I2C0 tranmit event 每每TBD

EVENT DESCRIPTION

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SPRS200 每 JULY 2002 46每47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62每63 每 GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 VP1EVTYA VP1EVTUA VP1EVTVA VP2EVTYA VP2EVTUA VP2EVTVA 每 None GP0 event 8 GP0 event 9 GP0 event 10 GP0 event 11 GP0 event 12 GP0 event 13 GP0 event 14 GP0 event 15 VP1 event YA 每每TBD VP1 event UA 每每TBD VP1 event VA 每每TBD VP2 event YA 每每TBD VP2 event UA 每每TBD VP2 event VA 每每TBD None

? In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).

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