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RK3288 TRM

Chapter 2 System Overview 2.1 Address Mapping
RK3288 support to boot from internal bootrom, which support remap function by software programming. Remap is controlle

d by SGRF_SOC_CON0 bit[11].
Before Remap FF72_0000
Bus Int Mem (96K)

After Remap FFFF_FFFF/FF72_0000 FFFE_0000/FF70_0000 FFFE_0000
Bus Int Mem (96K)

FF70_0000 FF30_0000
Reserved (320K)

FFE0_0000 FFD0_0000
Core AXI Bus (1M) Core SLV (512K)

FFFF_FFFF
BOOTROM (20K)

BOOTROM (20K)

FF2B_0000 FF2A_0000 FF29_0000 FF28_0000 FF27_0000
PS2C (64K) TSADC (64K) Reserved (64K) PERI MMU (64K) GMAC (64K)

FFFF_0000

FFFD_0000

FFC8_0000
Core GIC (512K)

FFC0_0000 FF96_0000
VIP (64K)

FFB8_0000 FFB5_0000

A17_Debug (512K) Reserved (192K) eFuse-256bits (64K)

FF95_0000
VOP_LIT (64K)

FF70_0000
Reserved (64K)

FF94_0000
VOP_BIG (64K)

FFB4_0000
Reserved (64K)

FF26_0000
DMAC_PERI (64K)

FF6F_0000
CCS (64K)

FF93_0000
RGA (64K)

FFB3_0000
Security DMAC_BUS (64K)

FF25_0000
Reserved (448K)

FF6E_0000
Reserved (64K)

FF92_0000
ISP MINI (64K)

FFB2_0000
eFuse-1024bits (64K)

FF1E_0000 FF1D_0000 FF1C_0000
UART_GPS (64K) SCR (64K) UART_EXP (64K)

FF6D_0000 FF6C_0000 FF6B_0000 FF6A_0000 FF69_0000 FF68_0000 FF67_0000 FF66_0000 FF65_0000 FF64_0000
DDR_PCTL1 (64K) I2C_AUDIO (64K) I2C_PMU (64K) DDR_PUBL1 (64K) Reserved (64K) UART_DBG (64K) RK_PWM 0/1/2/3 (64K) DW_PWM 0/1/2/3 (64K) CCP (64K) TIMER(6ch) (64K)

FF91_0000
IEP (64K)

FFB1_0000
TZPC (64K)

FF90_0000
Reserved (256K)

FFB0_0000
Service HEVC (64K)

FF8C_0000 FF8B_0000 FF8A_0000 FF89_0000 FF88_0000 FF82_0000 FF81_0000 FF80_0000
GPIO8 (64K) SPDIF 8CH (64K) CRYPTO (64K) I2S/PCM(8ch) (64K) SPDIF(2ch) (64K) Reserved (384K)

FFAF_0000

FF1B_0000
Reserved (64K)

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FFAE_0000 FFAD_0000 FFAC_0000 FFAB_0000 FFAA_0000 FFA9_0000 FFA8_0000 FFA4_0000 FFA3_0000 FFA2_0000 FF9D_0000 FF9C_0000 FF9B_0000 FF9A_0000 FF98_0000 FF97_4000 FF97_0000 FF96_C000 FF96_8000 FF96_4000 FF96_0000

Service VPU (64K) Service VIO (64K) Service BUS (64K) Service PERI (64K) Service GPU (64K) Service DMA (64K) Service Core (64K) Reserved (256K) GPU (64K) HOST (64K) Reserved (320K) HEVC (64K) Reserved (64K) VIDEO (64K) HDMI (128K) Reserved (48K) eDP (16K) LVDS (16K) CSI HOST (16K) DSI HOST 1 (16K) DSI HOST 0 (16K)

FF1A_0000
UART_BB (64K)

FF19_0000
UART_BT (64K)

FF18_0000
I2C_HDMI (64K)

FF17_0000
I2C_TP (64K)

Timer 6~7 (64K) WDT (64K)

FF16_0000 FF15_0000 FF14_0000
SPI2 (64K) I2C_CAM (64K) I2C_SENSOR (64K)

FF63_0000
DDR_PUBL0 (64K)

FF7F_0000
GPIO7 (64K)

ip
FF7D_0000 FF7C_0000 FF7B_0000 FF7A_0000 FF79_0000 FF78_0000 FF77_0000 FF76_0000 FF75_0000 FF74_0000 FF73_0000 FF72_0000

FF13_0000 FF12_0000 FF11_0000 FF10_0000 FF0F_0000
SDIO 1 (64K) SPI1 (64K)

FF62_0000
DDR_PCTL0 (64K)

FF7E_0000

FF61_0000
SPI0 (64K) DMAC_BUS (64K)

FF60_0000
SAR-ADC (64K) HSIC (256K)

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USB OTG (256K) Reserved (832K) TSP (64K) NandC 1 (64K) NandC 0 (64K)

FF5C_0000
eMMC (64K)

FF58_0000 FF54_0000 FF52_0000

FF0E_0000
SDIO 0 (64K)

USB HOST 1 (256K)

FF0D_0000
SD/MMC (64K)

TUSB HOST 0 EHCI (128K) PERI AXI Bus (1M)

USB HOST 0 OHCI (128K)

FF0C_0000 FF08_0000 FF00_0000 FF00_0000
DDR (4G-16M) HSADC (256K) GPS (512K)

FF50_0000

FF43_0000

FF42_0000 FF41_0000 FF40_0000 FF30_0000

SECURE GRF (64K) PMU (64K) PMU Internal Mem (4K)

0000_0000

Fig. 2-1 RK3288 Address Mapping

2.2 System Boot
RK3288 provides system boot from off-chip devices such as SDMMC card, 8bits async nand flash or toggle nand flash, SPI nor or nand, and eMMC memory. When boot code is not ready
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GPIO6 (64K) GPIO5 (64K) GPIO4 (64K) GPIO3 (64K) GPIO2 (64K) GPIO1 (64K) GRF (64K) CRU (64K) GPIO0 (64K)

RK3288 TRM in these devices, also provide system code download into them by USB OTG interface. All of the boot code will be stored in internal bootrom. The following is the whole boot procedure for boot code, which will be stored in bootrom in advance. The following features are supports. ? ? Support secure boot mode and non-secure boot mode Support system boot from the following device: ? 8bits Async Nand Flash ? 8bits Toggle Nand Flash ? SPI2_CS0 interface ? eMMC interface ? SDMMC Card Support system code download by USB OTG

?

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RK3288 TRM
Cortex-A17 get first instruction from address 0xffff0000, romcode start to run

Check ID BLOCK from external Nand Flash

ID BLOCK correct? No

Yes

Check ID BLOCK from external eMMC device

ID BLOCK correct? No

Yes

Check ID BLOCK from external SPI Nor Flash

1.Read 2K SDRAM initialization image code to internal SRAM 2.Run image code to do DDR initialization 3.Transfer boot image code to DDR 4.Run boot image code

ID BLOCK correct? No

Yes

ID BLOCK correct? No Check ID BLOCK from external SDMMC card

Yes

ID BLOCK correct? No

Yes

Initialize USB port

1.Wait request for download DDR image code 2.Download DDR image code to internal SRAM 3.Run DDR image code 4.Wait request for download loader image code 5.Download loader image code to DDR 6.Run loader image

TOS, Boot or download end

Fig. 2-2 RK3288 boot procedure flow

2.3 System Interrupt connection
RK3288 provides an general interrupt controller(GIC) for Cortex-A17 MPCore processor, which
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Check ID BLOCK from external SPI Nand Flash

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RK3288 TRM has 112 SPI (shared peripheral interrupts) interrupt sources and 3 PPI(Private peripheral interrupt) interrupt source and separately generates one nIRQ and one nFIQ to CPU. The triggered type for each interrupts is high level sensitive, not programmable. The detailed interrupt sources connection is in the following table. For detailed GIC setting, please refer to Chapter 12. Table 2-1 RK3288 Interrupt connection list
IRQ Type IRQ ID 26 PPI 27 29 30 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SPI 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 FuZhou Rockchip Electronics Co.,Ltd. Source(spi) HYPERVISOR TIMER VIRTUAL TIMER SECURE PHYSICAL TIMER NON-SECURE PHY TIMER DMAC_BUS (0) DMAC_BUS (1) DMAC_PERI (0) DMAC_PERI (1) UPCTL 0 UPCTL 1 GPU_IRQJOB GPU_IRQMMU GPU_IRQGPU VIDEO ENCODER VIDEO DECODER VIDEO MMU HEVC VIP ISP VOP_BIG VOP_LIT Polarity High level High level High level High level High level High level High level High level High level High level High level High level High level

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IEP RGA DSI 0 HOST DSI 1 HOST CSI HOST 0 CSI HOST 1 USB OTG USB HOST 0 EHCI USB HOST 1 HSIC GMAC GMAC PMT GPS GPS TIMER HS-ADC/TSI SD/MMC SDIO 0 SDIO 1

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High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level 40

RK3288 TRM
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 eMMC SARADC TSADC NANDC 0 PERI MMU NANDC 1 USB HOST 0 OHCI TPS SCR SPI0 SPI1 SPI2 PS2C CRYPTO HOST PULSE 0 HOST PULSE 1 HOST 0 HOST 1 I2S/PCM (8ch) SPDIF(8ch) UART_BT UART_BB UART_DBG UART_GPS UART_EXP I2C_PMU I2C_AUDIO I2C_SENSOR High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level

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I2C_CAM I2C_TP I2C_HDMI TIMER 6CH 0 TIMER 6CH 1 TIMER 6CH 2 TIMER 6CH 3 TIMER 6CH 4 TIMER 6CH 5 TIMER 2CH 0 TIMER 2CH 1 PWM0 PWM1 PWM2 PWM3 RK_PWM WDT

ch T100 101 102 103 104 105 106 107 108 109 110 111 FuZhou Rockchip Electronics Co.,Ltd.

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High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level

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RK3288 TRM
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 186 187 188 189 PMU GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 AHB ARBITER0 (USB) AHB ARBITER1 (EMEM) AHB ARBITER2 (MMC) USBOTG_ID USBOTG_BVALID USBOTG_LINESTATE USBHOST0_LINESTATE USBHOST1_LINESTATE eDP DP SDMMC_DETECT_N SDIO0_DETECT_N SDIO1_DETECT_N HDMI WAKEUP HDMI CCP CCS High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level

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SDMMC DETECT DUAL EDGE GPIO7_B3 DUAL EDGE

ip
eDP HDMI HEVC MMU PMUIRQ[0] PMUIRQ[1] PMUIRQ[2] PMUIRQ[3]

GPIO7_C6_DUAL EDGE GPIO8_A2_DUAL EDGE

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2.4 System DMA hardware request connection
RK3288 provides 2 DMA controllers: DMAC_BUS inside bus system and DMAC_PERI inside peripheral system. As for DMAC_BUS, there are 6 hardware request ports. Another, 15 hardware request ports are used in DMAC_PERI, the trigger type for each of them is high level, not programmable. For detailed descriptions of DMAC_BUS and DMAC_PERI, please refer to Chapter 10 and Chapter 11. Table 2-2 RK3288 DMAC_BUS Hardware request connection list
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High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level High level

RK3288 TRM
Req Number
0 1 2 3 4 5

Source
I2S/PCM(8CH) TX I2S/PCM(8CH) RX SPDIF(2CH) TX SPDIF(8CH) TX UART_DBG TX UART_DBG RX

Polarity
High level High level High level High level High level High level

Table 2-3 RK3288 DMAC_PERI Hardware request connection list
Req Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Source
HS-ADC/TSI UART_BT TX UART_BT RX UART_BB TX UART_BB RX N/A N/A UART_GPS TX UART_GPS RX UART_EXP TX UART_EXP RX SPI0 TX SPI0 RX SPI1 TX SPI1 RX SPI2 TX SPI2 RX

Polarity
High level High level High level High level High level N/A N/A High level High level High level High level High level High level High level High level High level High level

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