当前位置:首页 >> 信息与通信 >>

MIPI协议介绍


MIPI Protocol Introduction
MIPI Development Team 2010-9-2

What is MIPI?
? MIPI stands for Mobile Industry Processor Interface ? MIPI Alliance is a collaboration of mobile industry leaders. ? Objective to promote open standards for interfaces to mobile
?
application processors. Intends to speed deployment of new services to mobile users by establishing Spec. Intel, Motorola, Nokia, NXP,Samsung, ST, TI

? Board Members in MIPI Alliance
?

What is MIPI?
? MIPI Alliance Specification for display
? DCS (Display Command Set)
? DCS is a standardized command set intended for command mode display modules.

? DBI, DPI (Display Bus Interface, Display Pixel Interface)
? DBI:Parallel interfaces to display modules having display controllers and frame buffers. ? DPI:Parallel interfaces to display modules without on-panel display controller or frame buffer.

? DSI, CSI (Display Serial Interface, Camera Serial Interface)
? DSI specifies a high-speed serial interface between a host processor and display module. ? CSI specifies a high-speed serial interface between a host processor and camera module.

? D-PHY
? D-PHY provides the physical layer definition for DSI and CSI.

DSI Layers
DCS spec

DSI spec

D-PHY spec

Outline ? D-PHY
? Introduction ? Lane Module, State and Line levels ? Operating Modes
? Escape Mode

? System Power States ? Electrical Characteristics ? Summary

Introduction for D-PHY
? D-PHY describes a source synchronous, high speed, low power, low cost PHY ? A PHY configuration contains
? A Clock Lane ? One or more Data Lanes

? Three main lane types
? Unidirectional Clock Lane ? Unidirectional Data Lane ? Bi-directional Data Lane

? Transmission Mode
? Low-Power signaling mode for control purpose:10MHz (max) ? High-Speed signaling mode for fast-data traffic:80Mbps ~ 1Gbps per Lane

? D-PHY low-level protocol specifies a minimum data unit of one byte
? A transmitter shall send data LSB first, MSB last.

? D-PHY suited for mobile applications
? DSI:Display Serial Interface
? A clock lane, One to four data lanes.

? CSI:Camera Serial Interface

Two Data Lane PHY Configuration

Lane Module
? PHY consists of D-PHY (Lane Module) ? D-PHY may contain
? ? ? ? ? Low-Power Transmitter (LP-TX) Low-Power Receiver (LP-RX) High-Speed Transmitter (HS-TX) High-Speed Receiver (HS-RX) Low-Power Contention Detector (LP-CD)

? Three main lane types
? Unidirectional Clock Lane
? Master:HS-TX, LP-TX ? Slave:HS-RX, LP-RX

? Unidirectional Data Lane
? Master:HS-TX, LP-TX ? Slave:HS-RX, LP-RX

? Bi-directional Data Lane ? Master, Slave:HS-TX, HS-RX,LP-TX, LP-RX, LP-CD

Universal Lane Module Architecture

Lane States and Line Levels
? The two LP-TX’s drive the two Lines of a Lane independently and single-ended.
? Four possible Low-Power Lane states (LP-00, LP-01, LP-10, LP-11)

? A HS-TX drives the Lane differentially.
? Two possible High Speed Lane states (HS-0, HS-1)

? During HS transmission the LP Receivers observe LP-00 on the Lines ? Line Levels (typical)
? LP:0~1.2V ? HS:100~300mV (Swing:200mV)

? Lane States
? LP-00, LP-01, LP-10, LP-11 ? HS-0, HS-1

Operating Modes
? There are three operating modes in Data Lane
? Escape mode, High-Speed (Burst) mode and Control mode

? Possible events starting from the Stop State of control mode
? Escape mode request (LP-11→LP-10→LP-00→LP-01→LP-00) ? High-Speed mode request (LP-11→LP-01→LP-00) ? Turnaround request (LP-11→LP-10→LP-00→LP-10→LP-00)

Escape Mode
? Escape mode is a special operation for Data Lanes using LP states.
? With this mode some additional functionality becomes available:LPDT, ULPS, Trigger ? A Data Lane shall enter Escape mode via LP-11→LP-10→LP-00→LP01→LP-00 ? Once Escape mode is entered, the transmitter shall send an 8-bit entry command to ? indicate the requested action. ? Escape mode uses Spaced-One-Hot Encoding. ? means each Mark State is interleaved with a Space State (LP-00). ? Send Mark-0/1 followed by a Space to transmit a ‘zero-bit’/ ‘one-bit’ ? A Data Lane shall exit Escape mode via LP-10→LP-11

? Ultra-Low Power State
? During this state, the Lines are in the Space state (LP-00) ? Exited by means of a Mark-1 state with a length TWAKEUP(1ms) followed by a Stop state.

Escape Mode

Clock Lane Ultra-Low Power State
?
?

A Clock Lane shall enter ULPS via
? LP-11→LP-10→LP-00

exited by means of a Mark-1 with a length TWAKEUP followed by a Stop State
? LP-10 → TWAKEUP →LP-11 ? The minimum value of TWAKEUP is 1ms

High-Speed Data Transmission
? The action of sending high-speed serial data is called HS transmission or burst. ? Start-of-Transmission
? ? ? ? ? LP-11→LP-01→LP-00→SoT(0001_1101) HS Data Transmission Burst All Lanes will start synchronously But may end at different times The clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave side

? End-of-Transmission
? H Toggles differential state immediately after last payload data bit

?

and keeps that state for a time THS-TRAIL

High-Speed Clock Transmission
? Switching the Clock Lane between Clock Transmission and LP Mode
? A Clock Lane is a unidirectional Lane from Master to Slave ? In HS mode, the clock Lane provides a low-swing, differential DDR clock signal. ? the Clock Burst always starts and ends with an HS-0 state. ? the Clock Burst always contains an even number of transitions

Summary for D-PHY
? Lane Module, Lane State and Line Levels
? ? ? ? Lane Module:LP-TX, LP-RX, HS-TX, HS-RX, LP-CD Lane States:LP-00, LP-01, LP-10, LP-11, HS-0, HS-1 Line Levels (typical):LP:0~1.2V, HS:100~300mV (Swing:200mV) Escape Mode entry procedure :LP-11→LP-10→LP-00→LP-01→LP-00→Entry Code → LPD (10MHz) Escape Mode exit procedure:LP-10→LP-11 High Speed Mode entry procedure:LP-11→LP-01→LP-00→SoT(00011101) → HSD (80Mbps ~ 1Gbps) High Speed Mode exit procedure:EoT→LP-11 Control Mode - BTA transmission procedure:LP-11→LP-10→LP-00→LP-10→LP-00 Control Mode - BTA receive procedure:LP-00→LP-10→LP-11 Low-Power mode, High-Speed mode, Ultra-Low Power mode Contention Detection (LP-CD), Watchdog Timer, Sequence Error Detection (Error Report) Clock Lane Timing, Data Lane Timing Other Timing – Initialization, BTA, Wake-Up from ULPS HS-RX, LP-RX, LP-TX, LP-CD, Pin characteristic, Clock signal, Data-Clock timing DC and AC characteristic

? Operating Modes
? ?
? ? ? ? ? ? ? ? ?

? System Power States
? Fault Detection ? Global Operation Timing Parameter ? Electrical Characteristics

Outline
? DSI
? ? ? ? ? ? ? ? ? Introduction Lane Distributor/Merger Conceptual Packet Structure Data Transmission Way Processor-Sourced Packets Peripheral-Sourced Packets Reverse-Direction LP Transmission Video Mode Summary

Introduction for DSI
? DSI is a Lane-scalable interface for increased performance.
? ? One Clock Lane / One to Four Data Lanes Command Mode (Similar to MPU IF)
? ? Data Lane 0:bidirectional
– For returning data, ACK or error report to host

? DSI-compliant peripherals support either of two basic modes of operation

Additional Data Lanes:unidirectional. Data Lane 0:bidirectional or unidirectional; Additional Data Lanes:unidirectional. Video data should only be transmitted using HS mode.

?

Video Mode (Similar to RGB IF)
? ? ?

? Transmission Mode
? ? High-Speed signaling mode Low-Power signaling mode
? ? Forward/Reverse direction LP transmissions shall use Data Lane 0 only For returning data, DSI-compliant systems shall only use Data Lane 0 in LP Mode

? Packet Types
? ? Short Packet:4 bytes (fixed length) Long Packet:6~65541 bytes (variable length)

Two Data Lanes HS Transmission Example

Data Transmission Way
? Separate Transmissions

? Separate Transmissions

?

KEY:
? LPS – Low Power State ? SoT – Start of Transmission ? EoT – End of Transmission SP – Short Packet LgP – Long Packet

Short Packet Structure
? Packet Header (4 bytes)
? Data Identifier (DI) * 1byte: Contains the Virtual Channel[7:6] and Data Type[5:0]. ? Packet Data * 2byte:Length is fixed at two bytes ? Error Correction Code (ECC) * 1byte:allows single-bit errors to be corrected and 2-bit errors to be detected.

? Packet Size
? Fixed length 4 bytes

? The first byte of any packet is the DI (Data Identifier) byte.
? DI[7:6]:These two bits identify the data as directed to one of four virtual channels. ? DI[5:0]:These six bits specify the Data Type.

Long Packet Structure
? Packet Header (4 bytes)
? ? ? ? ? ? ? Data Identifier (DI) * 1byte:Contains the Virtual Channel[7:6] and Data Type[5:0]. Word Count (WC) * 2byte:defines the number of bytes in the Data Payload. Error Correction Code (ECC) * 1byte:allows single-bit errors to be corrected and 2-bit errors to be detected. Length = WC × bytes If the payload has length 0, then the Checksum calculation results in FFFFh If the Checksum isn’t calculated, the Checksum value is 0000h 4 + (0~65535) + 2 = 6 ~ 65541 bytes

? Data Payload (0~65535 bytes)

? Packet Footer (2 bytes):Checksum
? Packet Size

Data Types for Processor-sourced Packets

Error Correction Code
? ? ? ? ? ? ? ? P7 = 0 P6 = 0 P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23 P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23 P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23 P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22 P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23 P0 = D0^D1^D2^D4^D5^D7^D10^D11^D13^D16^D20^D21^D22^D23

Checksum
? unsigned char xx[] = {0x01,0x5a,0x5a,0x03,0x08,0x2A, 0x00,0x01 ,0x00,0xF8,0x00,0xF6,0x57,0x00,0 X00,0xE5}; typedef unsigned short U16; typedef unsigned char U8; U16 CRC_test; U16 crc16_update(U16 crc, U8 a); int main() { U16 crc,i; crc = 0xFFFF; for (i=0; i<1; i++) crc = crc16_update(crc, xx[i]); CRC_test = crc; } ? ? ? ? ? ? ? ? ? ? ? U16 crc16_update(U16 crc, U8 a) { int i; crc ^=a; for (i = 0; i < 8; ++i) { if (crc & 1) crc = (crc >> 1) ^ 0x8408; else crc = (crc >> 1); } return crc; }

? ? ? ? ? ? ? ? ? ? ?

Peripheral-to-Processor LP Transmissions
? Detailed format description
? ? Packet structure for peripheral-to-processor transactions is the same as for the processor-to-peripheral direction

?
?

For a single-byte read response, valid data shall be returned in the first byte The second byte shall be sent as 00h If the peripheral does not support Checksum it shall return 0000h

Peripheral-to-Processor LP Transmissions
? Peripheral-to-processor transactions are of four basic types
? ? ? ? Tearing Effect (TE):trigger message (BAh) Acknowledge:trigger message (84h) Acknowledge and Error Report:short packet (Data Type is 02h) Response to Read Request:short packet or long packet
? Generic Read Response、DCS Read Response(1byte, 2byte, multi byte)

? Feature
? BTA shall take place after every peripheral-to-processor transaction ? Multi-Lane systems shall use Lane 0 for all peripheral-to-processor transmissions ? Reverse-direction signaling shall only use LP mode of transmission

Video Mode
? DSI supports three formats for Video Mode data transmission
? Non-Burst Mode with Sync Pulses ? Non-Burst Mode with Sync Events ? Burst Mode

Summary for DSI
? DSI is a Lane-scalable interface.
? One Clock Lane ? One to Four Data Lanes

? Transmission Mode
? High-Speed signaling mode (differential signal) (100mV~300mV) ? Low-Power signaling mode (single-ended signal) (0V~1.2V)
? For returning data, only use Data Lane 0 in LP Mode

? Packet Types
? Short Packet:4 bytes (fixed length)
? Data ID (1byte) + Data0 (1byte) + Data1 (1byte) + ECC (1byte)

? Long Packet:6~65541 bytes (variable length)
? Packet Header (4 bytes) + Data Payload (0~65535 bytes) + Packet Footer (2 bytes)

? Operation Mode
? Command Mode (Similar to MPU IF) ? Video Mode (Similar to RGB IF)
? Non-Burst Mode with Sync Pulses ? Non-Burst Mode with Sync Events ? Burst Mode

Thank you!


相关文章:
mipi介绍
特别要注意用于连接 D-PHY 和高层协议的物理层协议接口(PPI)的连接方式, 后文会介绍设计人员从不同的 IP 供应商中 选择 MIPI IP 时需要考虑的各种事项。 不...
MIPI接口
下面简单介绍 MIPI 的通道模式和线上电平。在正常的操作模式下,数据通道处于高速...MIPI 协议规定控制模式 4 个不同状态组成的不同时序代表着 将要进入或者退出...
什么是MIPI接口
手机摄像头 MIPI 技术介绍 宁波舜宇光电信息有限公司 徐永松 随着客户要求手机...MIPI 协议规定控制模式4个不同状态组成的不同时序代表着将要进入或者退 出高速...
D-PHY协议
D-PHY协议_信息与通信_工程科技_专业资料。在 M-...MIPI 的物理层有 D-PHY、M-PHY、C-PHY 共 3 ...5 结构本节介绍了 PHY 包括在行为层面的内部结构...
i.MX6核心板介绍
更小的尺寸方便用户开发与更换;拥有 20 多种接口协议使的该核心板可 便捷的...i.MX 6Solo 集成了 LVDS、MIPI 显示功能、MIPI 摄像 头端口、HDMI v1.4 、...
摄像头工作原理(驱动详细)
(2)、MIPI(移动行业处理器接口)是 MobileIndustry Processor Interface 的缩写 ...(Advanced Microcontroller BusArchitecture)3.0 协议中最重要的 部分,是一种面向...
力科发布MIPI M-PHY自动化物理层一致性测试
先进的 M-PHY 调试与分析 全新的 QPHY-MIPI-MPHY 一致性测试软件包含了功能强大的 M-PHY 物理层和协议解码调 试工具集。这一全面的协议解码,物理层测试和眼...
MIPI DSI 协议介绍
MIPI DSI 协议介绍分类: linux2013-08-29 21:52 6717 人阅读 评论(1) 收藏 举报 一、MIPI MIPI(移动行业处理器接口)是 Mobile Industry Processor Interface ...
Zynq高速串行CMOS接口的设计与实现
图(6)BitSlip 训练移位规律 在上面所介绍的资源中,IDELAYE2 是动态相位对其...2 LVDS 高速接口实现实例 因为 MIPI 接口有其完整的物理层协议, 因此不在这里...
更多相关标签: