当前位置:首页 >> 信息与通信 >>

Memory Interface Design made easy


Memory Interface Design Made Easy Name of presenter Date

Agenda
? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High P

erformance Solutions with Virtex-5 Virtex-6 and Spartan-6 Solutions

Memory Interfaces 2

Types of Memory Interfaces
? DRAM and SRAM
– Data buffering
? Interface bandwidth determines system performance ? Memory bandwidth at least 2X the data in/out rate
I/O Data In I/O I/O Data Out

Memory Data Buffer
(DDR3, DDR2, QDRII)

Data Processing

? Flash and PROM
– Configuration or microcontroller code storage
Memory Interfaces 3

FPGA Flash (PROM)

DRAM Market - DDR3 Adoption
? DDR2 (1.8V)
– Mature product – Volume leader 2008-2010
25000

Shipments by Technology Type

512M equivalent Units (Millions)

? DDR3 (1.5V)
– Next generation – 30% power reduction – Volume crossover 2010-2011 – Memory vendors expect bit parity
($/bit) end of 2009

20000

15000

DDR3 DDR2 DDR

10000

Mobile

5000

? Mobile DRAMs
– Driven by handset market – LPDDR (Mobile DDR) price
premium – LP DDR2 (1.2 V)
Memory Interfaces 4

0 2006 2007 2008 2009 2010 2011 2012

Data Source: iSuppli

Forecast Year

DRAM is the low cost memory driven by the PC industry

DRAM Data Rate Trend
? Major new architecture every ~4 years
– Max data rate and performance range double

? DDR3 adoption driven by PC market for 2009 ? Virtex-6 will support 1066+ Mbps data rates
Data Rate (Mbps)

1600 1200
Virtex-6

800
VirtexTM-5

Spartan-6
(x16)

400 0

SpartanTM-3A

Virtex-6 main market will use DDR3
Memory Interfaces 5

Memory in Networking Applications
? QDRII+ (BL=4)
– Higher data rate extension of QDRII (same latency) – Serves 40G Networking market

? RLDRAM II
– Higher density than QDR II – Lower latency than DDR3 – Suitable for larger packet buffers

Source: Samsung

Memory Interfaces 6

Agenda
? ? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High Performance Solutions with Virtex-5 Development Software Virtex-6 and Spartan-6 Solutions

Memory Interfaces 7

Memory Interface Design Challenges
? ? ?
Physical layer design
– Read data capture

Controller design, functional verification and integration
– Generating custom RTL files, simulation, integrating all the design modules and meeting timing closure

System design and verification
– Achieving bandwidth requirements – I/O placement, signal integrity, board routing – Meeting cost requirements
Design cycle can be long if FPGA vendor does not make it easy for you

Memory Interfaces 8

Shrinking Data-Valid Window
2.5 ns Data Rate 400 Mbps (DDR SDRAM)
Uncertainties

1.5 ns Data Rate 667 Mbps (DDR2 SDRAM) Uncertainties Data-valid window < 10% of bit-time

Data-valid window 28% of bit-time

Factors that reduce the data-valid window: ? Higher clock rate Shorter bit time ? Clock jitter, crosstalk, device timings do not scale well ? PCB trace mismatch across the parallel bus
Read data capture very challenging without a pre-engineered IP
Memory Interfaces 9

Xilinx Helps You Design Faster
? FPGA built-in silicon features
– – –
Adaptive calibration for clock to data centering Memory Interface Generator (MIG) EDK for Embedded applications

? Development software ? Hardware-verified reference
designs and kits
– –
Virtex-5 high-performance board (ML561) Low cost kits for Spartan 3A FPGAs

Memory Interfaces 10

Agenda
? ? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High Performance Solutions with Virtex-5 Development Software Virtex-6 and Spartan-6 Solutions

Memory Interfaces 11

Memory Interface Designs in Spartan-3A FPGAs
? Adaptive read-data calibration using LUTs ? MIG support for DDR and DDR2 up to 333 Mbps ? Spartan-3A Starter Kit
– – – –
400 Mbps DDR2 reference design Requires -5C Required voltage range of +/- 3% XAPP458

Memory Interfaces 12

Agenda
? ? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High Performance Solutions with Virtex-5 Development Software Virtex-6 and Spartan-6 Solutions

Memory Interfaces 13

Virtex-5 FPGAs: Built for Performance
18 Kbit

550 MHz Clock Management DCM (precision synthesis) + PLL (Low jitter)
DCM DCM PLL

550 MHz 36Kbit Dual-Port Block RAM / FIFO with ECC Higher On Chip RAM Bandwidth

550 MHz 25x18 DSP Slice Higher Performance & Precision
?p

ECC and Interconnect

FIFO Logic 18 Kbit

ExpressFabric?

VIRTEX-5

Real 6-input LUT with New Interconnect Architecture 30% Higher Logic Performance

ASIC ASSP

SRAM DRAM

Up to 1200 SelectIOs with ChipSync 1.25 Gbps LVDS, 800 Mbps Single-Ended Higher IO Bandwidth
Memory Interfaces 14

Second Generation Triple-oxide, Advanced 65nm Process, 1 Volt Core, Strained Silicon Higher Performance with Low Power

2nd Generation Sparse Chevron Superior Signal Integrity to ensure Higher IO Bandwidth

ChipSync- Adaptive Calibration
? Built-in features for high resolution delay ? IDELAY tap delays
– 75ps taps captures high data rates – Programmable during calibration stage
CLK
ChipSync ChipSync? ChipSync?

FPGA Fabric FPGA Fabric
IDELAY IDELAY IDELAY or or INC/DEC ODELAY ODELAY

FPGA Fabric
State Machine State Machine

DATA

ISERDES ISERDES
Calibration CLK

? ChipSync enables memory interfaces and LVDS standards

DELAY CNTLR DELAY CONTR. CNTLR

DATA DQS (Clock)
Memory Interfaces 15

Valid

Adaptive Read Data Calibration
? First stage
– Initialization of memory devices and internal FPGA logic after configuration

? Second stage (less than 10 us)
– Read data calibration - centering of DQS to DQ (using Chipsync -IDELAY) – Performed once in the reference designs

? Third stage
– Control handed over to main controller state machine for normal read/write operations
Memory Interfaces 16

1

Read Data Capture
SDR DATA

User Interface FIFOs (CLB)
Q2 Q1
Read Data Rising Read Data Falling

DQ

IDELAY
1st Stage Capture with Delayed DQS

DDR2 SDRAM
Data delay value per bit based on calibration

FPGA System Clock

DQS

Delayed DQS

2nd Stage Capture with FPGA System Clock

IDELAY
BUFIO

Memory Interfaces 17

2

Read Enable Logic and Timing

CLK0 Command READ

DQ @ Memory Device DQS @ Memory Device Delayed DQS @ IDDR CLK I/P

D0 D1 D2 D3

Number of registers determined during calibration ctrl_RdEn

Delayed DQ D0 D1 D2 D3 @ IDDR I/P ctrl_RdEn generated by controller after CAS Latency CLK0

WrEn Write Enable to Read Data FIFOs

No External Loop Back Required
Read Data Rising Read Data Falling WrEn D0 D1 D2 D3

Calibration without any external loop back circuit
Memory Interfaces 18

3

Write Data Path
D1

? Write data path easy to implement using DCM and Output DDR (ODDR) ? Write data transmitted using ODDR clocked by CLK90 ? Write strobe/clock generated using ODDR clocked by CLK180

Write Data Rise
D2

DQ

Write Data Fall

FPGA Clock (CLK90)

ODDR

DQS

DQS transmitted using CLK180

DQ

DQ transmitted using CLK90

Memory Interfaces 19

Xilinx Provides RTL Source
Write & Read Data Paths DQS/DQ & Read En Calibration State Machines Memory Initialization State Machine & Command MUX Read/ Write Data & Addr FIFOs Physical Layer Memory Interface TOP_TB Synthesizable Test Bench Design example with backend logic and memory checker/test bench

User Interface

Memory Interface Top

Main Memory Controller

Modify if needed to accommodate your requirements

Modular hierarchy helps you modify code as needed
Memory Interfaces 20

?RED –Parallel termination and Series termination Narrow Eye ?YELLOW – Parallel termination without Series termination GOOD EYE !!! ?PURPLE– Series termination without Parallel termination Overshoot/Undershoot

SSTL-1.8 Termination Case Study - Data Lines

Memory Interfaces 21

Hardware Verification
ML561 Memory Development Board

144-bit Wide

DDR2-667Mbps SDRAM DIMM
72-bit, up to 4 Deep

DDR3800Mbps (32-bit) DDR2 SDRAM (32-bit) QDRII SRAM 300 MHz (72-bit)
Contact your FAE for free schematics and Gerbers

RLDRAM II 333 MHz (36-bit)

Memory Interfaces 22

Logic Verification using ChipScope? Pro Tools
? On-Chip System Bus Analysis using the Integrated Logic Analyzer (ILA) core
– Test vectors file provided with the ML561 Development Board – Runs on your PC

? No additional I/O pins required
– Access via the JTAG Port
JTAG Interface

USB

ML 561 Demo Board
Memory Interfaces 23

ChipScope Pro Interface

PC

Memory Interface Verification
User Interface

Virtex-5
Addrs/cmd Addrs/cmd Addrs/cmd Addrs/cmd

Testbench Testbench Logic Logic FIFOs Compare Compare Logic Logic

Memory
Memory Memory Controller and Controller and Interface Interface Data Bus

FIFOs ChipScope Pro trace capture

Write Data Write Data Read Data Read Data

Error Signal

Read Data capture point

? ?

Testbench logic provides stimulus Compare logic provides read data verification
Memory Interfaces 24

DDR2 /DDR3 Detailed Features
? DDR2 full frequency controller
– – – –
Up to 4 banks open for higher page hit rate Dual rank DIMM support (frequency limitations) 72/144 bit ECC support for DIMMs ODT and 2T address/control timing

? DDR3 full frequency controller (component)
Virtex-5 DDR2
-1 / 533 Mbps

DDR3
-1 / Not supported -2 / 600 Mbps -3 / 800 Mbps*

Speed Grade Max. -2 / 600 Mbps Data Rate
-3 / 667 Mbps

Delivery
*DDR3 design pending full characterization
Memory Interfaces 25

MIG

Ref. design for component (XAPP867)

Component DDR3 Reference Design
? DDR3 Reference design and app note XAPP867 ? Fully parameterized reference design
– Change as needed at top level

? Reference design will support components
– ML561 uses 2 x16 components for 32 bit interface (pads for DDR3 components) – No write leveling required
Memory Interfaces 26

DDR3 DIMM Solution
? DDR3 DIMM interface is available from Xilinx Alliance Members ? Northwest Logic’s DDR3 DIMM IP for FPGAs
– – – – –
Real-time calibration-based 800 Mb/s support Write-leveling DIMM support Half frequency controller Hardware verification and characterization (ML562 board) www.nwlogic.com

Memory Interfaces 27

High Performance Controller
? High Performance: High Bandwidth & Low Latency ? High Bandwidth
– Bandwidth capability (IO data rate x Bus width) – Effective bandwidth -> Improved controller algorithm

? Low Latency
– Minimize pipeline stages – Minimize gaps between accesses -> Improved controller algorithm
Memory Interfaces 28

Improving Read Data Latency
? Least Recently Used (LRU) algorithm in Virtex-5 controller ? One row only opened algorithm in Virtex-4 controller ? Latency improved by the NEW LRU algorithm
FPGA Memory Controller Reads to an open row (no conflict) V5 DDR2 @ 125 MHz V4 DDR2 @ 125MHz V5 DDR2 @ 333 MHz V4 DDR2 @ 300 MHz 11 clocks 15 clocks 13 clocks 17 clocks Reads to four different banks (bank conflict) 12 clocks 30 clocks 14 clocks 32 clocks Reads to different bank and row (bank and row conflict) 20 clocks 30 clocks 22 clocks 32 clocks

Note: Latency numbers from the output of the address and command FIFO to the input of the read data FIFO.
Memory Interfaces 29

Improving Effective Bandwidth
? Access algorithms and address patterns influence the effective bandwidth. - Delays due to row conflicts or opening new rows lower the effective bandwidth
FPGA Memory Controller Reads to an open bank and row (no conflict) 14.7 Gbps 14.7 Gbps 41.0 Gbps 36.8 Gbps Reads to four different banks (bank conflict) 14.7 Gbps 1.8 Gbps 41.0 Gbps 4.2 Gbps Reads to different bank and row (bank and row conflict) 2.6 Gbps 1.8 Gbps 6.6 Gbps 4.2 Gbps

V5 DDR2 @ 125 MHz V4 DDR2 @ 125MHz V5 DDR2 @ 333 MHz V4 DDR2 @ 300 MHz

Note: Assuming burst length of 8 and interface width of 64 bits
Memory Interfaces 30

Data Bandwidth - Verification
? Virtex-5 FPGA controller implements LRU algorithm (four bank interleave) ? Almost 100% effectiveness (auto-refresh still needed)
Conflicts (gaps for pre-charge, open) No Conflicts (no gaps) – almost 100% effectiveness

Note: Trace capture using ChipScope Pro for DDR2 SDRAM 667 Mbps interface on the ML561 board
Memory Interfaces 31

High Performance Memory I/F Designs in Virtex-5
? ?


Adaptive calibration with 75 ps Chipsync for reliable data capture High Bandwidth interfaces
Data rates of 800 Mbps

?
– – – –

Hardware-verified reference designs
800 Mbps DDR3 SDRAM 667 Mbps DDR2 SDRAM 400 Mbps DDR SDRAM 1.2 Gbps (300 MHz) QDR II SRAM

?


Memory Interface Generator (MIG) software
Generates your custom memory controller and physical layer interface

Memory Interfaces 32

Agenda
? ? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High Performance Solutions with Virtex-5 Development Software Virtex-6 and Spartan-6 Solutions

Memory Interfaces 33

Memory Interface Generator (MIG)
? Customize your design for specific memory architecture, data rate, width, and other parameters (CAS latency, burst length)
– Generates RTL source and UCF from hardware-verified reference designs – Delivered as part of ISE tools (CORE Generator)

? Memory Interfaces supported: – Virtex-5 FPGA *
? DDR, DDR2, QDRII

– Virtex-4 FPGA
? DDR, DDR2,QDRII,RLDRAM II

– Spartan-3/3E/3A/3AN/3A DSP FPGA
? DDR, DDR2
* Note = DDR3 reference design for Virtex-5 FPGAs available as separate files and not included in the MIG 2.0
Memory Interfaces 34

MIG 2.3 – What’s New?
? New Features - MIG wizard
– Single-Ended vs. Differential system clock selection – FPGA floor plan changed to an architectural view from package view

? New Features – Virtex-5
– – – –
Virtex-5 TXT, DDRII SRAM, Dual Rank DDR2 SDRAM support Option for two data bytes per bank for DDR2 SDRAM PPC440 compatible pin-out support for DDR2 SDRAM Low power IDELAY mode

? Answer Record #31402 - MIG v2.3 - Release Notes
Memory Interfaces 35

Memory Interfaces Design Flow
Download CORE Generator? IP update Memory Interface Generator Run MIG, choose your memory parameters and generate rtl and ucf files Integrate MIG .ucf constraints to overall design constraints file Import RTL and build options into ISE project Synthesize design Customize MIG design Place and route design Integrate/customize MIG memory RTL testbench Timing simulation Perform functional simulation Optional RTL customization Verify in hardware

Memory Interfaces 36

MIG First Screen
Verify CORE Generator settings

Improve first time success rate
Memory Interfaces 37

Compatible FPGAs
Text to explain the items on each page

Memory Interfaces 38

Controller Options
Check marks to indicate which step you are on and what is next

Memory Interfaces 39

FPGA Options
Descriptive text for each option – less need to consult the User Guide. Trying to be succinct and clear but not too verbose.

Memory Interfaces 40

Bank Selection
Bank selection is improved with text instead of letters (“A”, “D”, “C”). Displays pins required.

Memory Interfaces 41

MIG Output Files
? UCF File Folder
– Pinout and clocking constraints – Batch file (ise_flow.bat) with recommended build options

? RTL files folder
– Functional modules (physical layer, user interface, controller, test bench)

? Simulation files folder
– HDL simulation files including memory device models

? Synthesis files folder ? Documentation Folder
– Includes Read, Write and Addr/Ctrl timing spreadsheets – Includes MIG Users Guide
Memory Interfaces 42

Agenda
? ? ? ? ? ?
Trends and Xilinx Roadmap Design Challenges Low Cost Solutions with Spartan-3 Generation High Performance Solutions with Virtex-5 Development Software Virtex-6 and Spartan-6 Solutions

Memory Interfaces 43

Virtex-6 Solutions
? Improved performance
– Higher data rates
? ? ? ?
Faster logic (40 nm) Enhanced I/O (50 ps/-3 IODELAY) Dedicated clocking paths Real time calibration with MMCM (PLL)

Memory Interface
DDR2 SDRAM DDR3 SDRAM QDR II+ RLDRAM II

Virtex-6 FPGA
800 Mbps* 1066+ Mbps* 400 MHz (2x 800 Mbps)* 500 MHz (1000 Mbps)*

– Higher effective bandwidth
? Reordering controller (DDR3/DDR2)

? Improved functionality
– DDR3 DIMM write leveling

? MIG for ISE design flow ? MPMC for EDK design flow
Memory Interfaces 44

* All frequencies quoted are pending characterization

We make it easier and faster to design with Virtex-6

Virtex-6 Controller
? Half frequency DDR2/DDR3 controller ? Higher effective bandwidth
– – – –
Reorder reads to minimize page misses Reorder R/W accesses to minimize bus turnarounds Bandwidth improvements up to 5X (application dependant) User configurable modes (normal and reordering)

Memory Interfaces 45

Spartan-6 Memory Controller
? New Hard Block Memory Controller
– Up to 4 controllers per device
Spartan-6

? Why a hard block?
– Very common design component – Benefits:
? Higher performance: 800 Mbps ? Lower cost: saves soft logic ? Lower power: dedicated logic
Interface DDR3 SDRAM DDR2 SDRAM DDR SDRAM LP DDR

DDR DDR2 DDR3 LP DDR

Spartan-6 800 Mbps* 800 Mbps* 400 Mbps* 400 Mbps*

– Easier to design with:
? Timing closure no longer an issue ? Configurable multiport user interface ? Coregen/MIG wizard & EDK support
Memory Interfaces 46

*All frequencies quoted are for all speedgrades except -1L

Memory Trends & Challenges

Spartan-6 Solutions

Competitive

Schedule

Spartan-6 Controller Features
? ?
User programmable features
– DDR, DDR2, DDR3, LP DDR

Memory Controller Block
CMD FIFO 0 CMD FIFO 1 CMD FIFO 2 CMD FIFO 3 CMD FIFO 4 CMD FIFO 5

Multiport user interface
– 4 uni- and 2 bi-directional data ports
? Direction and port width set at configuration

Arbiter Controller

Dedicated Routing

– TDMA Arbitration similar to MPMC2

?

Automatic calibration features
– DQS centering – DQ per bit deskew – Input termination tuning

32-bit
Bi-directional

32-bit
Bi-directional

PHY

32-bit
Uni-directional

Data Path

32-bit

?

Programmable controller options
– DRAM options – User interface and arbitration

Uni-directional

32-bit
Uni-directional

32-bit
Uni-directional

Memory Interfaces 47

Xilinx Helps You Design Faster
?


FPGA built-in silicon features
Adaptive calibration for unmatched reliability

?


Memory Interface Generator (MIG) software
Generates your custom memory controller and physical layer interface

?
– –

Complete Hardware Proven Solutions
Low cost solutions with Spartan Solutions High Performance Virtex Solutions

Memory Interfaces 48

How to Get Started
? Access latest Xilinx memory design solutions at
www.xilinx.com/memory
– Download Memory Interface Generator (MIG)
– Application Notes and Reference Designs

Thank You
Memory Interfaces 49


相关文章:
Web Interface Design
2311027-0941 Section 3 Web Interface Design i Section 3 Web Interface ...method with which this request was made, for example, GET, POST, or PUT...
12.Performing User Interface Design
Reduce user\'s memory load. Make the interface consistent. 25:What elements of a user interface design can be evaluated without building a working ...
OMAP_L138学习笔记之 EMIFA(External Memory Interface A)
OMAP_L138学习笔记之 EMIFA(External Memory Interface A)_信息与通信_工程科技_专业资料。OMAP_L138学习笔记之 EMIFA(External Memory Interface A)...
WLAN 802.11b中交换内存和总线接口的设计
The complexity of system-on-chip (SOC) devices makes standardizing the ...Exchange Memory & Bus Interface for WLAN 802.11 Chapter 3 Design Exchange ...
中英翻译Principles of User Interface Design
中英翻译Principles of User Interface Design_设计/艺术_人文社科_专业资料。...This makes it easier to learn, easier to use, and easier to add to or...
Hardware_Interface_Design-UART
Hardware_Interface_Design-UART_计算机硬件及网络_IT/计算机_专业资料。1 UART 1.1 Summary UART (Universal Asynchronous Receiver/Transmitter) 通用异步收发器, ...
ADIADSP-21469EZ-KIT高效评估方案
Next generation of the expansion interface design, provides access to most ...Easy probing of all port pins and most asynchronous memory interface (AMI)...
操作系统复习题
algorithm makes the most efficient use of memory?...A mouse used with a graphical user interface b.... would you design the operating system to use ...
外文翻译--可编程逻辑控制器-精品
The S7-200 has a brick design which means that...system memory and is the PLC decision-making ...This cable allows the serial interface of the ...
供应链管理 第三版 Unit1 习题与答案
: Easy The procurement cycle occurs at the retailer/distributor interface. ...chain strategy (or design), supply chain planning and supply chain operation...
更多相关标签:
interface design | memory design | made in design | easy design | we made a memory | easyhomedesign | made design | word power made easy |