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安捷伦在线测试 ------入门指导书

(一)

一、如何开关测试机器
1、开机 假设HP3070正处于关机状态,先把机器后面的红色旋扭 开关旋转到‘一’的位置,然后把绿色按钮开关打到‘ON’ 的位置,此时机器已经处于上电状态。这时候就可以打开主 机电源,此时显示屏的内容会有一定的变化,这时不要动键 盘和鼠标直到显示要你输入

用户名为止。输入用户名user1后, 再输入密码celetest8(注意保密),此时已经登入到HP-UX 系统中,打开一个BT-BASIC窗口,输入命令testhead power on,等几分钟出现下图后就表示testhead已经上电了,机器可 以测试线路板了。

2、关机(SHUTDOWN) 假设HP3070处于开机状态,松开夹具(如果测试头上 放有测试夹具),在BT-BASIC窗口输入testhead power off, 再关闭所有窗口。然后点击exit图标,在出现的输入用户名 窗口中输入shutdown,此用户无密码,可直接在输入密码 窗口中按enter键,此时也不要去碰鼠标和键盘,直到有提 示可以关闭电源后再关闭主机电源,然后是绿色按钮开关 和红色旋钮开关。机器这时已正常关机。

测试头已 上电标志

测试界面

常用的BT-BASIC命令
cat change changem copy to 列出当前目录的内容,类似于DOS的dir命令 用新的字符串代替已存在的字符,不区分大小写 同上,作用域在高亮显示区,而不是整个编辑区 拷贝文件,此文件名不存在

copy over
create dir delete

拷贝文件,文件名存在就覆盖,否则建立新的文件
建立一个新的目录 删除高亮显示区

duplicate
edit fetch find

复制高亮显示区到命令编辑区
把光标放到指定行的位置 拷贝指定编辑区的一行到命令编辑区 查找指定的字符串

unlink

删除文件

findn

常用的BT-BASIC命令(续表) 查找指定字符串,并继续查找下一个

get
list load merge move msi msi$

清除编辑区内容并打开文件显示在编辑区
把编辑区内容全部显示到输出设备上 同get 合并一个或多个文件到另一个文件中 移动高亮显示区到当前光标处 改变路径 显示当前目录

number
scratch save re-save

显示当前光标所在行列
清除编辑区 存盘为另一个文件 存盘

常用的BT-BASIC命令(续表) board graphics 打开板子的组装图

load board
debug board board consultant fixture consultant debug end compile

把一些目标文件调入内存,如board.o,wirelist.o
打开Pushbotton debug 窗口,进行程序调试 打开board cons图,进行如元件外形描述的编辑 打开fix consultant图,可以查找夹具上的测试针 结束Pushbotton debug 进程 编译文件,使之生成目标文件

board graphics end 结束board grap 进程

testhead power on
testhead is 1 testhead is *

给测试头上电(开机时用)
使测试头处于受控制使用状态 关闭测试头的使用

testhead power off 给测试头下电(关机时用)

常用的BT-BASIC命令(续表) faon/faoff fixture lock 打开/关闭真空气阀开关 吸合夹具

fixture unlock
unpowered powered execute exit clear nrun find pins

松开夹具
初始化系统,为不上电测试作准备 初始化系统,为上电测试作准备 在BT-BASIC 窗口中执行SHELL命令 退出BT-BASIC 窗口 使nrun的计数为零 激活测针查找功能,用guided probe查找测针

Pushbutton debug 窗口

fix consultant(针点图)

PCB board graphics

Board consultant

四、常用的shell命令介绍
man man 显示man命令的说明 kill ID ftp 强行终止某一进程 文件传输 改变密码 清屏 文件压缩 退出进程 查看文件内容 比较两文件的差异

cd dir
pwd ll dir/file ls dir/file rm file mkdir rmdir

改变目录路径
显示当前路径名

mv file1 file2 文件移动或重命名

显示当前路径内容的长列表 passwd 显示当前路径内容的短列表 clear tar exit more diff 删除文件,加-R删除目录 建立目录 删除目录

cp file1 file2 文件复制,加-R复制目录

du

查看磁盘容量

vi

打开vi编辑器

dir----catalog || file1----source file || file2----object file

特别注意! ! !
慎用此命令,除非你知道自己在做什么! ! !

SHELL窗口

五、testplan 的简介及测试原理
主 程 序
…… call Pre_shorts …… call Shorts ……. call Analog_tests …… call testjet …… call digital …… sub Characterize learn capacitance on learn capacitance off subend

子 程 序

sub Pre_Shorts ……… subend sub Shorts test “shorts” subend sub Analog_Tests test “analog/c4” test “analog/r56” ……… subend ……… sub Digital_Tests test “digital/u1” test “digital/u2” …… subend ………

1.短路测试原理 (Unpower)
短路定义: 短路,就是两个测试点之间的阻抗小于或等于预设的门限值. 开路定义: 开路, 就是两个测试点之间的阻抗大于预设的门限值. A Shorts Test is testing for unexpected shorts on the board; it requires the impedance between nodes to be greater than the threshold (open) to give a PASS indication. An Opens Test is testing for unexpected opens on the board; it requires impedance between nodes to be less than or equal to the threshold (short) to give a PASS indication.

Example: Shorts Test file

!!!! 9 0 1 !IPG: rev B.03.42 S threshold settling delay 50.0 short "#:N6" to "#: short "#:2V5" to "# short "#:N9" to "#: short "#:3V3" to "# !short "#:N213" to !short "#:-48V" to report phantoms threshold 10 nodes "#:-48V" nodes "#:N7" nodes "#:N213" nodes "#:N254" nodes "#:N143" !nodes "#:N146" settling delay 3.74 nodes "#:5V" settling delay 50.0 nodes "#:N10" !nodes "#:N11" nodes "#:N13"

Open test

Shorts test

Open test short “A” to “D” source A B D

S

detector

C D

Shorts test

侦测:
测试针首先选择“shorts”file里的第一个测试点(假设是A点 ),将它与信号源相连,再将列表中的其它点短接后与A测试,看 是否短路.如没有短路,则第二个测试点(假设B点),重复A的测 试过程.

隔离(排除法):
如果发现短路,依次断开那些预先短接的测试 点,重复上述“侦测”各步骤,直至发现短路点 .

图解:
如何发现B与E之间短路

Isolate a short

1.检测A与BCDE之间有无短路.

3.首先隔离C点,DE短接,仍发现短路.说明B与 DE间有短路.再隔离D点,B与E之间短路.最后隔 离E点,发现没有短路,说明BD之间没有短路.

2.在检测B与CDE是否短路时,发现 短路.

4.最终发现B与E短路.

Phantom shorts

Phantom short :detection find short but isolation can’t find

2.摸拟元件测试原理(Unpower) 典型模拟元件测试方法

三线测试 (S bus、I bus、G bus)

Resistor typical test program:

disconnect all connect s to “N1” connect i to “N2” connect g to “N100” resistor 10k, 5.5,5,re5,ar0.1

六线测试
(S bus、A bus、I bus、B bus、G bus、L bus)

1. S
2. I 3. G

bus
bus bus

4. A
5. B 6. L

bus
bus bus

Capacitor Test
Capacitor test:

Zc=1/2?fc
C=1/2 ? f !!!! 2 0 1 1002945327 0000 ! IPG: rev B.03.42 Sat Oct 13 11:55:28 2001 ! Common Lead Resistance 100m, Common Lead Inductance 1.00u ! Fixture: EXPRESS on failure ! 表示注解 report parallel devices report "r1 15.0k" end on failure disconnect all !! 断开所有继电器 connect s to “GND”; a to “GND” !! 连接 S bus 和 A bus 到 "GND" 点 connect i to "TREE__1022" !! 连接 I bus 到"TREE__1022" 点 connect g to "+5" !! 连接 G bus 到 "+5" 点 capacitor 100n, 13.4, 8.66, fr1024, re3, wb, ar100m, sa, en, nocomp

Zc

----

上限、下限、频率、反馈电阻、测试选项,具体含义见前面表格

Diode & Zener Test

!!!! 2 0 1 885232159 0000 ! IPG: rev B.02.54 Mon Jan 19 09:49:20 1998 ! Common Lead Resistance 500m, Common Lead Inductance 1.00u ! Fixture: EXPRESS disconnect all connect s to "VCC" connect i to "$34" diode 728m, 413m, idc5.0m, co3.0, ar828m

!!!! 2 0 1 924217662 0000 ! IPG: rev B.03.13 Wed Mar 31 11:25:15 1999 ! Common Lead Resistance 500m, Common Lead Inductance 1.00u ! Fixture: EXPRESS on failure report parallel devices report "q23 q23:fet 100, 20.0" end on failure disconnect all connect s to "TREE89" connect i to "B0" connect g to "VF" nfet 81.6, 10.0, re1, ar50.0m

FET Test Configuration

模拟测试选项参数介绍
am — amplitude 信号电压幅度,直流-10.00V----+10.00V,交流0.00----+7.07Vrms

ar — ASRU range ARSU增益范围,0----+10V
idc — DC current DC信号电流大小,100ua----150ma comp — capacitor compensation 需要电容补偿 nocomp — no compensation fr — frequency 不需要电容补偿 交流信号频率,128Hz、1024Hz、8192Hz

re — reference element 反馈电阻,re1----re6表示反馈电阻分别为10ohm----1Mohm wa — wait 在产生激励和获得读数之间等待,0----9.9999S sa — use the A bus to sense the S bus 利用A bus在S bus处检测信号电压 sb — use the B bus to sense the I bus sl — use the L bus to sense the G bus en — enhancement 利用B bus在I bus处检测电流计电压 利用L bus在G bus处检测隔离点

增强测试,其测试原理见下图

ed — extra digit

克服线周期求测量的积分,可以屏蔽线频率50Hz/60Hz

增强测试原理
Enhancement(en)

模拟测试选项参数介绍
co — voltage compliance of —offset 限制电源电压,0----10V

ico — current compliance 限制MOA输入电流大小,0=35ma,1=150ma 使交流信号产生一个直流偏置电压,-10V----+10VDC fi —filter 取平均值,1----9999

op —opposite 对测试结果取反
dwa —detector wait 在使用en选项时,使detector在测量之前等待指定时间,0----1s wb —wideband 选用MOA宽频特性,原理见下图 pf —pass/fail 用数字1(pass)和0(fail)取代测试值

pm —parallel mode
sm —serial mode

为电容和电感选择并联测试模式,电容测试常用pm
为电容和电感选择连续测试模式,电感测试常用sm

ad —adjust 允许在测量前调试可变元件,如可调电阻,可带参数0、1、2 pc — parallel capacitor 并联一个100pf的电容到被测元件上,仅在调试时使用

详细注解请见附页

Wideband theory

Wideband(wb) Versus Narrowband Frequency Responses

3.Testjet test(Unpower)

Devices devices with an internal lead frame (most digital and hybrid devices) devices with an internal ground plane (usually ceramic packages) most Ball Grid Arrays (BGAs) (except ceramic and stadium packages) some Ball Grid Arrays (CBGAs) (ceramic and stadium packages only) connectors and sockets devices with grounded heat sink flip chip devices or chip-on-board (COB) dip switches pushbuttons

HP TestJet X

HP Connect Check

X X X X X X X X

HP TestJet Architecture

HP TestJet is an unpowered test of the connectivity from each pin on a device to the circuit board. The system uses the HP TestJet hardware to measure the capacitance from a pin of a device to the HP TestJet probe. The measurement is repeated for each pin on the device, except power and ground pins. Pins that are tied together are tested as one pin.
Remark:The S (source) bus to the pin being tested,the I (input) bus to the HP TestJet probe,and the G(guard) bus to all other pins on the device.

The "testjet" File
The "testjet" file is the test file for all devices to be tested with HP TestJet; this one test file includes the tests for all HP TestJet devices.
default threshold low 200 high 10000 default throughput adjustment 1!throughput adjustment 0 device "u101”;threshold low100 high 10000 test pins 1 test pins 2,3 test pins 4,5,6 ! test pins 7 ! Ground pins commented by HP IPG. test pins 8 test pins 11;threshold low 20 high 10000 test pins 12 test pins 13 ! test pins 14 ! Fixed pins commented by HP IPG. inaccessible pins 9,10 end device The "default threshold" statement sets the test thresholds for all the devices in the file. The "default throughput adjustment" statement enables or disables throughput adjustment for all the devices in the file. There is a "device/end device" block for each device to be tested. The "device" statement specifies the device designator. If the device is mounted on the bottom side of the board, the "device” statement includes the "bottom" keyword. The "test pins" statement specifies the pin or pins to be tested. Pins that are tied together in the circuit are specified and are tested together. The "inaccessible pins" statement declares pins that are not tested because they are not accessible.This statement always appears at the end of the device block.

Testjet Probe Assemble

Testjet Probe Assemble

HP TestJet Probe and Mux Card Connections.

Pin Numbers for the Right-Angle Connector.

Mux Card Jumpers J4 and J5.

An Example of HP TestJet Wiring in the Top Side of the Fixture.

4.The Setup_Power_Supplies Routine
sub Setup_Power_Supplies 打印第一组电源的上电 global Pslimit 电压和允许最大电流 cps 有optimize选项 sps 1,5.00,0.50;optimize | rps 1 ,V,I | print V,I 表示两组同时上电 sps 2,-5.00,2.00;optimize Pslimit = pslimit 1,5.00,0.50 pass device if Pslimit then dps 第一组电源,上电+5V,允许最大电流0.50A fail device I=1 第二组电源,上电-5V,允许最大电流2.00A for Pscount=1 to 2 如果不能上电,则 if binand(Pslimit,I) then 执行此语句来循环 report “Power Supply Number” 2,-5.00,2.00 判断哪组电源不能 report Pscount report “In Current Limit” 上电 end if I=2*I cps----Connect Power Supply next Pscount report “------------------------------------” sps----Set Power Supply report “Check for backwards” dps----Disconnect Power Supply report “IC?s or Capacitors.” report “------------------------------------” end if rps----Report Power Supply subend

5.数字测试原理(Powered)

Timing in a vector

在向量中的时间分隔段

The parts of a Digital Test(VCL简介)
! Declaration Section ! Device Type

Vector Control Language
! Timing Section Details are covered in Advanced Digital Class

! assignment section

! Vector Definition Section Vector Initial_State set Reset to “0” set CS_bar to “0” ! Vector Execution section ………... unit “Test Reset” execute Initial_State execute Assert_reset ……….

1 2

3

Truth Table 真值表

4 5

6
Input 1 E1 0 0 1 1 Input2 0 1 0 1 Output 1 1 1 0

9

10

8
E1 E1 E1

12 13

11

NAND GATE与非门

注 解 声明 测试 类型

! ! !

7400 NAND, 2-Input, Quad revision A.01.00

combinatorial vector cycle 500n receive delay 400n assign VCC to pins 14 assign GND to pins 7 assign assign assign assign assign assign assign assign E1_Inputs E2_Inputs E3_Inputs E4_Inputs E1_Output E2_Output E3_Output E4_Output to to to to to to to to pins pins pins pins pins pins pins pins

定义每 一个向 量的持 续时间

Digital library
(Declaration Section)

定义元 件引脚 组名称

1,2 4,5 9,10 12,13 3 6 8 11

指定哪些引 脚组被连接 到电源点 指定用于信号输 入的元件引脚组

power family

VCC, GND定义逻辑电平 TTL

指定用于 信号输出 的元件引 脚组

inputs outputs

E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputs E1_Output,E2_Output,E3_Output,E4_Output

Digital library test (Vector Definition Section)
向量 单元 指定 高低 电平 向量 开始 结束 标志
vector E1_Input_00 set E1_Inputs set E1_Output end vector vector E1_Input_01 set E1_Inputs set E1_Output end vector vector E1_Input_10 set E1_Inputs set E1_Output end vector vector E1_Input_11 set E1_Inputs set E1_Output end vector to "00" to "1" vector E4_Input_00 set E4_Inputs set E4_Output end vector vector E4_Input_01 set E4_Inputs set E4_Output end vector vector E4_Input_10 set E4_Inputs set E4_Output end vector vector E4_Input_11 set E4_Inputs set E4_Output end vector

to "00" to "1"

to "01" to "1"

to "01" to "1"

to "10" to "1"

to "10" to "1"

to "11" to "0"

to "11" to "0"

………

Digital library (unit section)
unit "Element number 1" execute E1_Input_11 execute E1_Input_01 execute E1_Input_00 execute E1_Input_10 end unit unit "Element number 2" execute E2_Input_11 execute E2_Input_01 execute E2_Input_00 execute E2_Input_10 end unit unit "Element number 3" execute E3_Input_11 execute E3_Input_01 execute E3_Input_00 execute E3_Input_10 end unit unit "Element number 4" execute E4_Input_11 execute E4_Input_01 execute E4_Input_00 execute E4_Input_10 end unit

测试 单元

执行 向量

各种逻辑符号的含义 “0” set a logic low on the node. “1” set a logic high on the node.

“K” keep the previous state.
“T” toggle from the previous state.

“Z” set the device to a high impedance state.
“X” don’t care this receiver.

Overdrive and Backdrive
VCC

Vector E1_Input_11
A C B

set A to “1” set B to “1” set C to “0”

end vector

VCC

Back drive current

standard_cmos safeguard file
PATH:/hp3070/standard/safeguard/standard_cmos !!!! 8 0 1 591688800 0000 parameters "standard_cmos" ! ! subfamily : standard CMOS ! ! characteristics : low level output current <= 3 mA ! Vcc = 5 V ! backdrive current of 0.005 for "0" , 0.050 for "1" overdrive power 0.02 , 0.02 dissipated by heat source heat source 100 by 10 , 1 per output operating temperature 40 thermal resistance 60 package ceramic end parameters

Library level Safeguard File
! Standard Safeguard Template include "standard_cmos" use use use use use use use use use use use use use parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" for for for for for for for for for for for for for "TL7702AH_1" "28SCID0490CH_1" "74ABT244H_3" "74F08H_1" "S02F" "358H_2" "74F112H_2" "74F175H_1" "74F74H_2" "74F163H_1" "74F32H_1" "10H125P_3" "74F38H_1"

Board level Safeguard File
parameters "standard_cmos" backdrive current of 5m for "0", 50m for "1" bond wire 2540 by 25.4 heat source 100 by 10, 1 per output operating temperature 40 overdrive power 20m, 20m dissipated by heat source package ceramic thermal resistance 60 end parameters use use use use use use use use use use use parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters parameters "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" "standard_cmos" for for for for for for for for for for for "u1" "u2" "u3" "u4" "u5" "u6" "u8" "u9" "u10" "u11" "u12"

Digital compiler safeguard check
Digital/u15 ----------------------------------------------C O M P I L A T I O N S U M M A R Y ------------------------------------31 vectors executed 19 vector Ram slots used ,0% full 32 sequence ram slots used,0% full 13 directory ram slots used, 0% full S A F E G U A R D S U M M A R Y -------------------------------safeguard status :Not Inhibited Estimated test time:3.60e-05 Safe Test time(device):5.99e-01(u16) 201 lines,0 errers,0 warnings,object produced

Disable issue
cs
Upsteam device U21
UUT1 U1

Input
UUT2 U2

output

Disable description in library
! ! ! QMV288 U21 Library setup only revision A.01.00

vector cycle 500n receive delay 400n assign assign assign assign assign VCC GND to pins 1,2,3,4,5 to pins 25,26,27,29,30

IO to pins 5,6,7,8,9,10,11,12,13,14,15,16 IO to pins 17,18,19,20,21,22,23,24 CS to pins 28

family TTL power VCC,GND inputs CS bidirectional IO

disable IO with CS to "0"

Disable in execute test
!U2 executable test assign Disablegroup to nodes "TREE__1343” default "0" inputs Disablegroup

assign DisableFamilyTTL to nodes "TREE__1343"
family TTL on DisableFamilyTTL inputs DisableFamilyTTL

!IPG: Safeguard will ignore disabled outputs disabled device "u21" pins 5,6,7,8,9,10,11,12 disabled device "u21" pins 13,14,15,16,17,18,19 disabled device "u21" pins 20,21,22,23,24 !IPG: with pin 28 on node "TREE__1343"

The node TREE__1343(U21 Pin CS) keep at low level during U2 Test

6.Analog Functional test (Powered) ARSU Resource

s :Source

a:auxiliary source

i: detector high
l: detector low

rcva,rcvb,rcvc:frequency detector

Resource specification
Source range unit

-----------------------------------------------------------DCV -10 - +10 Vdc

SINE
SQUARE TRIANGLE

0 0 0 -

7.0
10 10

Vrms
Vpk Vpk Vdc MHz

Auxiliary source : -10 - +10 Frequency detector: 1 - 60

Analog Function Test File
!IPG: rev B.03.42 Sat Oct 13 11:56:05 2001 ! Quad TTL-ECL Translator test powered analog power pins "8", "9","16" nonanalog pins 6 connect l to ground Pins 5 connect to Source test "TRANSLATOR1_4" test "TRANSLATOR1_2" end test !----------------------------------------------subtest "TRANSLATOR1_4" Pins 4 connect to Detector connect s to pins 5 connect i to pins 4 source dcv, amplitude 2.5, icompliance 1, on detector dcv, expect -2 定义 measure -1.6,-2 检测器 wait 50m source dcv, amplitude 0.3,icompliance 1, on detector dcv, expect -1 measure -0.7,-1 end subtest subtest "TRANSLATOR1_2" ...... end subtest

Analog function 测试标志

定义 信号源

开始测量, 上限为-1.6V、 下限为-2V

Frequency Test
test powered analog power pins 7,14 nonanalog pins 1 test "OUTPUT"

end test

subtest"OUTPUT" connect rcvc to pins 8 detector frequency, expect 49.152M measure 49.152M * 1.0005,49.152M * 0.9995 end subtest

六、PushButton简介
输入以下命令可以激活PushButton窗口:
msi<board dir> | load board | debug board

PushButton窗口在board level中各菜单内容

PushButton 窗口在 device level 中各菜单 内容

testplan macros----

File menu options

Analog, Digital, Serial mode

Edit menu options

Analog, Digital, Serial mode
Debug menu options

Analog, Digital, Serial mode
Macros menu options

Mode menu options

Digital mode
Execute menu options

Display menu options

Digital mode

Set menu options

Digital mode
Util menu options

Testplan Macros Menu commands(all debug modes) Pins
执行CHEK-POINT测试并列出失败的测试点,注意 CHEK-POINT可以在子程序 Set_Custom_Options 中关闭 Preshorts 执行所有预短路测试并列出失败的测试名称 Shorts 执行短路测试并列出失败的测试名称 AutoAnalog Debug 执行并自动调试电阻电容电感和场效应管,除了可 调元件外,优化程序精确度 Calculate Test Limits… 计算并改变电阻电容电感和场效应管测试的极限 Analog Incircuit 执行在线模拟元件测试并列出失败的测试名称 TestJet 执行Agilent TestJet测试并列出失败的测试名称 Power Supplies 打开 DeviceUnderTest电源 Digital Incircuit 执行在线数字元件测试并列出失败的测试名称 Analog Functional 执行模拟元件功能测试并列出失败的测试名称 Digital Functional 执行数字元件功能测试并列出失败的测试名称

由于花 费时间 太长经 常不用

Display MOA - DC.

(二)

Agilent ICT Tester(Outline)

测试头规划图
Bank 2
1 Rows 11 13 Rows 23 78 Columns 1 78

Bank 1
Columns 1 1 Rows 11 13

Module 2

Module 0

Module 3

Module 1

Rows 23

Front View of Testhead - User’s Point of View (BRC)

Bank 2
78 1 Slots 11 1 Slots 11 Pins 1 1

Bank 1
Pins 78 11

Module 2 Module 3

Module 0 Module 1

Slots 1 11 Slots 1

双密度卡第二排

双密度卡第一排 或单密度卡

Front View of Testhead - Service Point of View (Hardware)

BRC:Bank,Row,Column :20378,203178

每个Module有1张Control card、1张ARSU card 和9张PIN cards。其中 Control card 和ARSU card 分别固定在第六槽和第一槽。其余九个槽 全部插PIN cards。

Module 1

Agilent 3X7Y硬件基础知识简介: 下图所示:我们现有的测试仪器为HP3073和HP3173
If ?x? is... 0 The testhead is... Testhead with 1 to 4 modules (4 max), with Support Bay. Board Handler optional. Testhead with 1 to 2 modules (2 max), no Support Bay. Board Handler optional. Testhead with 1 module (1 max), no Support Bay. Board Handler not allowed. If ?y? is... 0 The test capability is... Pay-Per-Use 分期付款使用

1

2

Process Testing In-circuit Testing Low-cost Combinational? Testing Functional Testing High-performance Combinational? Testing CT - Telecom Testing

2

3

4,5 9

HP3073指的是具有最多四个Module空间容量的,最多可以 有5184个测试点的在线测试系统。(78-6)*9*2*4=5184 那HP3173最多有几个测试点?想一想,很简单。

子系统(Subsystem)
? ? ? ? ? ? 电源子系统(Power Subsystem) 控制子系统(Control Subsystem) 模拟子系统(Analog Subsystem) 数字子系统(Digital Subsystem) 真空子系统(Vacuum Subsystem) 夹具子吸合系统(Fixture Pull-down Subsystem)

Power Subsystem
+5 / +24 V Power Supplies STC +5V Supply AC (3X79 only) DUT Power Supply PDU Contactors AC "Mains" Optional Test Equipment ASRU Card Other Daughter Cards STC Card DC To System Card

DC Enable DC

Control
MPU (1 of 4) EMO

DC

Branch Control

DC Power Distribution... Enable Module Mother Card (1 of 4)

Control XT Subsystem
Controller Graphics PS/2 RS-232 SCSI I/O Parallel LAN To Monitor To Keyboard, Mouse, Bar Code Scanner

To Modem, Strip Printer E3788A SCSI to RS-232
To Line Printer To Site LAN To DUT Power Supplies, Optional Test Equipment, VXI Testhead Modules Control Card 0 out
in

RS-232

PPU Button Adapter EFS Board Handler EFS Bar Code Reader Repair Terminals

HP-IB

Black Box

System Card

Control Card 1 Control Card 3 Control Card 2

Disk DDS Tape

Testhead LAN

High-Speed Link

To Footswitch

Analog Subsystem
DUT Control Card

Pin Card Driver
MOA

ASRU Card

CPU

Seq

Receive r

S

MUX

Det

Formatte r

Contro l

Contro l
MUX

Analog Bus Control Bus

Mother Card

Digital Subsystem
DUT Control Card Pin Card Driver ASRU Card
MOA

CPU

Seq

Receiver

S

MUX

Det

Formatter

Control

MUX

Control

Digital Bus Control Bus Mother Card

Merged Analog/Digital Subsystem
DUT Control Card Pin Card
MOA

ASRU Card

Driver

CPU

Seq

Receiver

S

MUX

Det

Formatter

Contro l

Separate Channels for D-A

MUX

Formatte r

Contro l

Digital Bus

Analog Bus Control Bus

Mother Card

Vacuum Subsystem
J60b +24V Power Supply + 15

Auxiliary Relays 1 2 3 4 5

System Card

16

J3

Auxiliary Ports

1 2 + AUX1
Relay 1

3 4 + AUX2
Relay 2

5 6 + AUX3
Relay 3

7 8 + AUX4
Relay 4

9 10 + AUX5
Relay 5

11

12
Remote Emergency Shutdown Jumper

Twisted Pair Wires To Auxiliary Ports * * Vacuum Source

Vacuum Ports on Testhead for Modules 0,1,2,3 2 0 3 1

*
* Air-piloted solenoids also need a source of compressed air * Vacuum Solenoids

Flexible Vacuum Hoses

Fixture Pull-down Subsystem
Fixture Pull-down Towers
To Solenoid Regulator (Top View) To Handler Input

Air Output (for Board Handler)

Air Lines Air Input Test Button Control Wires

Pull-down Line Release Line Solenoid Valve

Air Regulator

Drain Valve Fixture Pull-down Relay J60b 15 + 16 System Card

Fan Power J560a J561
1 2

+24V Power Supply

Bracket in rear of testhead below the modules


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