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MT41K256M16HA-125E


4Gb: x4, x8, x16 DDR3L SDRAM Description

1.35V DDR3L SDRAM
MT41K1G4 – 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description

r />DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 SDRAM (1.5V). ? TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C ? Self refresh temperature (SRT) ? Automatic self refresh (ASR) ? Write leveling ? Multipurpose register ? Output driver calibration

Features
? VDD = V DDQ = 1.35V (1.283–1.45V) ? Backward compatible to V DD = V DDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications ? Differential bidirectional data strobe ? 8n-bit prefetch architecture ? Differential clock inputs (CK, CK#) ? 8 internal banks ? Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals ? Programmable CAS (READ) latency (CL) ? Programmable posted CAS additive latency (AL) ? Programmable CAS (WRITE) latency (CWL) ? Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) ? Selectable BC4 or BL8 on-the-fly (OTF) ? Self refresh mode

Options
? Configuration – 1 Gig x 4 – 512 Meg x 8 – 256 Meg x 16 ? FBGA package (Pb-free) – x4, x8 – 78-ball (10.5mm x 12mm) Rev. D – 78-ball (9mm x 10.5mm) Rev. E, J ? FBGA package (Pb-free) – x16 – 96-ball (10mm x 14mm) Rev. D – 96-ball (9mm x 14mm) Rev. E ? Timing – cycle time – 1.071ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) ? Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) – Industrial (–40°C ≤ T C ≤ +95°C) ? Revision

Marking
1G4 512M8 256M16 RA RH RE HA -107 -125 -15E -187E None IT :D/:E/:J

Table 1: Key Timing Parameters
Speed Grade -1071, 2, 3 -1251, 2 -15E1 -187E Notes: Data Rate (MT/s) 1866 1600 1333 1066 Target tRCD-tRP-CL 13-13-13 11-11-11 9-9-9 7-7-7
tRCD

(ns)

tRP

(ns)

CL (ns) 13.91 13.75 13.5 13.1

13.91 13.75 13.5 13.1

13.91 13.75 13.5 13.1

1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-107).

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Description
Table 2: Addressing
Parameter Configuration Refresh count Row address Bank address Column address Page size 1 Gig x 4 128 Meg x 4 x 8 banks 8K 64K (A[15:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1KB 512 Meg x 8 64 Meg x 8 x 8 banks 8K 64K (A[15:0]) 8 (BA[2:0]) 1K (A[9:0]) 1KB 256 Meg x 16 32 Meg x 16 x 8 banks 8K 32K (A[14:0]) 8 (BA[2:0]) 1K (A[9:0]) 2KB

Figure 1: DDR3L Part Numbers
Example Part Number: MT41K512M8RH-125:E MT41K Configuration Package Speed : Revision

{
:D/:E/:J Revision Configuration 1 Gig x 4 512 Meg x 8 256 Meg x 16 1G4 512M8 256M16 Speed Grade Package 78-ball 10.5mm x 12mm FBGA 78-ball 9mm x 10.5mm FBGA 96-ball 10.0mm x 14mm FBGA 96-ball 9mm x 14mm FBGA Rev. D E, J D E Mark RA RH RE HA -107 -125 -15E -187E
tCK tCK tCK tCK

Temperatu re Commercial Industrial temperature None IT

= 1.071ns, CL = 13 = 1.25ns, CL = 11 = 1.5ns, CL = 9 = 1.87ns, CL = E

Note:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings.

FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions

Ball Assignments and Descriptions
Figure 2: 78-Ball FBGA – x4, x8 (Top View)

1 A
VSS

2
VDD VSSQ DQ2

3
NC

4

5

6

7

8
VSS VSSQ DQ3

9
VDD VDDQ VSSQ VSSQ VDDQ NC

NF, NF/TDQS#

B
VSS DQ0
DM, DM/TDQS

C
VDDQ DQS DQ1

D
VSSQ NF, DQ6 DQS# VDD VSS

E
VREFDQ VDDQ NF, DQ4 VSS VDD CS# RAS# NF, DQ7 NF, DQ5

F
NC CK VSS VDD ZQ

G
ODT CAS# CK# CKE

H
NC WE# A10/AP NC

J
VSS BA0 BA2 A15 VREFCA BA1 VSS VDD VSS VDD VSS

K
VDD A3 A0 A12/BC#

L
VSS A5 A2 A1 A4

M
VDD A7 A9 A11 A6

N
VSS RESET# A13 A14 A8

Notes:

1. Ball descriptions listed in Table 3 (page 5) are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions
Figure 3: 96-Ball FBGA – x16 (Top View)

1

2

3

4

5

6

7

8

9

A B C

VDDQ VSSQ VDDQ

DQ13 VDD DQ11

DQ15 VSS DQ9

DQ12

VDDQ DQ14

VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC

UDQS#

UDQS

DQ10

D
VSSQ VDDQ VSSQ DQ2 UDM DQ8 VSSQ VSSQ DQ3

E
VSS DQ0 LDM

F
VDDQ LDQS DQ1

G
VSSQ DQ6 LDQS# VDD DQ7 VSS DQ5

H
VREFDQ VDDQ VSS VDD CS# DQ4

J
NC RAS# CK VSS VDD ZQ

K
ODT CAS# CK# CKE

L
NC WE# A10/AP NC

M
VSS BA0 BA2 NC VREFCA BA1 VSS VDD VSS VDD VSS

N
VDD A3 A0 A12/BC#

P
VSS A5 A2 A1 A4

R
VDD A7 A9 A11 A6

T
VSS RESET# A13 A14 A8

Note:

1. A slash defines a selectable function.

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol [15:13], A12/BC#, A11, A10/AP, A[9:0] Type Input Description Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in the DDR3 SDRAM data sheet. Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to REFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.

BA[2:0]

Input

CK, CK#

Input

CKE

Input

CS#

Input

DM

Input

ODT

Input

RAS#, CAS#, WE# RESET#

Input Input

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol DQ[3:0] DQ[7:0] DQS, DQS# TDQS, TDQS# Type I/O I/O I/O Output Description Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to REFDQ. Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Reference voltage for data:REFDQ must be maintained at all times (excluding self refresh) for proper device operation. Ground. DQ ground: Isolated on the device for improved noise immunity. External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4].

VDD VDDQ VREFCA VREFDQ VSS VSSQ ZQ NC NF

Supply Supply Supply Supply Supply Supply Reference – –

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol [14:13], A12/BC#, A11, A10/AP, A[9:0] Type Input Description Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in the DDR3 SDRAM data sheet. Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.

BA[2:0]

Input

CK, CK#

Input

CKE

Input

CS#

Input

LDM

Input

ODT

Input

RAS#, CAS#, WE#

Input

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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4Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol RESET# Type Input Description Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Ground. DQ ground: Isolated on the device for improved noise immunity. External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls).

UDM

Input

DQ[7:0] DQ[15:8] LDQS, LDQS# UDQS, UDQS# VDD VDDQ VREFCA VREFDQ VSS VSSQ ZQ NC

I/O I/O I/O I/O Supply Supply Supply Supply Supply Supply Reference –

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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4Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions

Package Dimensions
Figure 4: 78-Ball FBGA – x4, x8 (RA)
0.155 Seating plane

A 1.8 CTR Nonconductive overmold 78X ?0.45 Dimensions apply to solder balls postreflow on ?0.35 SMD ball pads.

0.12 A

Ball A1 ID
9 8 7 3 2 1 A B C D E F G H J K L M N

Ball A1 ID

12 ±0.1 9.6 CTR

0.8 TYP

0.8 TYP 6.4 CTR 10.5 ±0.1

1.1 ±0.1 0.25 MIN

Notes:

1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions
Figure 5: 78-Ball FBGA – x4, x8 (RH)
0.155 Seating plane

A 1.8 CTR Nonconductive overmold

0.12 A

78X ?0.45 Dimensions apply to solder balls postreflow on ?0.35 SMD ball pads.

Ball A1 ID (covered by SR)
9 8 7 3 2 1 A B C D E F

Ball A1 ID

10.5 ±0.1 9.6 CTR

G H J K L M N

0.8 TYP 0.8 TYP 6.4 CTR 9 ±0.1 1.1 ±0.1 0.25 MIN

Notes:

1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions
Figure 6: 96-Ball FBGA – x16 (RE)
0.155 Seating plane

A 1.8 CTR Nonconductive overmold 96X ?0.45 Dimensions apply to solder balls post-reflow on ?0.35 SMD ball pads

0.12 A

Ball A1 ID
9 8 7 3 2 1 A B C D E F G H J K L M N P R T

Ball A1 ID

14 ±0.1 12 CTR

0.8 TYP

0.8 TYP 6.4 CTR 10 ±0.1

1.1 ±0.1 0.25 MIN

Notes:

1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions
Figure 7: 96-Ball FBGA – x16 (HA)
0.155 Seating plane 1.8 CTR Nonconductive overmold

A

0.12

A

96X ?0.45 Dimensions apply to solder balls post-reflow on ?0.35 SMD ball pads.

9

8

7

3

2

1 A B C D E F G H J K L M N P R T

Ball A1 Index (covered by SR)

Ball A1 Index

12 CTR

14 ±0.1

0.8 TYP

0.8 TYP 6.4 CTR 9 ±0.1

1.1 ±0.1 0.25 MIN

Notes:

1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics – 1.35V operating IDD Specifications

Electrical Characteristics – 1.35V operating IDD Specifications
Table 5: IDD Maximum Limits - Die Rev. D
Speed Bin Parameter Operating current 0: One bank ACTIVATE-to-PRECHARGE Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE Precharge power-down current: Slow exit Precharge power-down current: Fast exit Precharge quiet standby current Precharge standby current Precharge standby ODT current Active power-down current Active standby current Burst read operating current Symbol IDD0 IDD1 Width x4, x8 x16 x4 x8 x16 IDD2P0 IDD2P1 IDD2Q IDD2N IDD2NT IDD3P IDD3N IDD4R All All All All x4, x8 x16 All x4, x8 x16 x4 x8 x16 Burst write operating current IDD4W x4 x8 x16 Burst refresh current Room temperature self refresh Extended temperature self refresh All banks interleaved read current Reset current IDD5B IDD6 IDD6ET IDD7 IDD8 All All All x4, x8 x16 All DDR3L-1066 60 75 70 77 105 20 30 39 42 40 45 53 52 68 135 147 220 115 125 180 205 22 28 210 260 IDD2P + 2mA DDR3L-1333 65 80 75 82 110 20 32 44 45 45 50 58 57 73 155 164 240 135 145 200 210 22 28 250 285 IDD2P + 2mA DDR3L-1600 75 90 80 87 115 20 37 47 50 50 55 63 62 77 175 187 280 155 165 225 220 22 28 290 320 IDD2P + 2mA Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics – 1.35V operating IDD Specifications
Table 6: IDD Maximum Limits Die Rev. E, J
Speed Bin Parameter Operating current 0: One bank ACTIVATE-to-PRECHARGE Operating current 1: One bank ACTIVATE-to-READ-toPRECHARGE Precharge power-down current: Slow exit Precharge power-down current: Fast exit Precharge quiet standby current Precharge standby current Precharge standby ODT current Active power-down current Active standby current Burst read operating current Symbol IDD0 Width x4, x8 x16 IDD1 x4 x8 x16 IDD2P0 IDD2P1 IDD2Q IDD2N IDD2NT IDD3P IDD3N IDD4R All All All All x4, x8 x16 All x4, x8 x16 x4 x8 x16 Burst write operating current IDD4W x4 x8 x16 Burst refresh current Room temperature self refresh Extended temperature self refresh All banks interleaved read current Reset current IDD5B IDD6 IDD6ET IDD7 IDD8 All All All x4, x8 x16 All DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 44 55 53 59 80 18 26 27 28 32 35 32 32 41 113 123 185 87 95 137 224 20 25 160 198 IDD2P + 2mA 47 58 57 62 84 18 28 28 29 35 39 35 35 45 130 140 202 103 110 152 228 20 25 190 217 IDD2P + 2mA 55 66 61 66 87 18 32 32 32 39 42 38 38 47 147 157 235 118 125 171 235 20 25 220 243 IDD2P + 2mA 62 73 65 70 91 18 37 35 35 42 45 41 41 49 164 174 252 133 141 190 242 20 25 251 274 IDD2P + 2mA Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications

Electrical Specifications
Table 7: Input/Output Capacitance
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet DDR3L-800 DDR3L-1066 DDR3L-1333 Capacitance Parameters Single-end I/O: DQ, DM Differential I/O: DQS, DQS#, TDQS, TDQS# Inputs (CTRL, CMD,ADDR) Symbol CIO CIO CI Min 1.5 1.5 0.75 Max 2.5 2.5 1.3 Min 1.5 1.5 0.75 Max 2.5 2.5 1.3 Min 1.5 1.5 0.75 Max 2.3 2.3 1.3 DDR3L-1600 Min 1.5 1.5 0.75 Max 2.2 2.2 1.2 DDR3L-1866 Min 1.5 1.5 0.75 Max 2.1 2.1 1.2 Units pF pF pF

Table 8: DC Electrical Characteristics and Operating Conditions – 1.35V Operation
All voltages are referenced to VSS Parameter/Condition Symbol Supply voltage I/O supply voltage Notes: VDD VDDQ Min 1.283 1.283 Nom 1.35 1.35 Max 1.45 1.45 Units V V Notes 1, 2, 3, 4 1, 2, 3, 4

1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (for example, 1 sec). 2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 8 (page 27)).

Table 9: DC Electrical Characteristics and Operating Conditions – 1.5V Operation
All voltages are referenced to VSS Parameter/Condition Symbol Supply voltage I/O supply voltage Notes: VDD VDDQ Min 1.425 1.425 Nom 1.5 1.5 Max 1.575 1.575 Units V V Notes 1, 2, 3 1, 2, 3

1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 8 (page 27)).

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 10: Input Switching Conditions – Command and Address
Parameter/Condition Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 Note: Symbol VIH(AC160)min
1 1

DDR3L-800/1066 160 135 – 90 –90 – –135 –160

DDR3L-1333/1600 160 135 – 90 –90 – –135 –160

DDR3L-1866 – 135 125 90 –90 –125 –135 –

Units mV mV mV mV mV mV mV mV

VIH(AC135)min

VIH(AC125)min1 VIH(DC90)min VIL(DC90)min VIL(AC125)min
1

VIL(AC135)min1 VIL(AC160)min
1

1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135) of 365ps; independently, the data inputs may use either VIH(AC160),min or VIH(AC135),min.

Table 11: Input Switching Conditions – DQ and DM
Parameter/Condition Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 Note: Symbol VIH(AC160)min
1 1 1

DDR3L-800/1066 160 135 – 90 –90 – –135 –160

DDR3L-1333/1600 160 135 – 90 –90 – –135 –160

DDR3L-1866 – 135 130 90 –90 –130 –135 –

Units mV mV mV mV mV mV mV mV

VIH(AC135)min

VIH(AC130)min VIL(DC90)min VIL(AC130)min

VIH(DC90)min
1 1

VIL(AC135)min

VIL(AC160)min1

1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the data inputs must use either VIH(AC160),min with tIS(AC160) of 90ps or VIH(AC135),min with tIS(AC135) of 140ps; independently, the address/command inputs may use either VIH(AC160),min or VIH(AC135),min.

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 12: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition Differential input logic high – slew Differential input logic low – slew Differential input logic high Differential input logic low Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes Single-ended low level for CK, CK# VSEL Symbol VIH,diff(AC)slew VIL,diff(AC)slew VIH,diff(AC) VIL,diff(AC) VSEH Min 180 N/A 2 × (VIH(AC) - VREF) VSS/VSSQ VDDQ/2 + 160 VDD/2 + 160 VSSQ VSS Max N/A –180 VDD/VDDQ 2 × (VIL(AC) - VREF) VDDQ VDD VDDQ/2 - 160 VDD/2 - 160 Units mV mV mV mV mV mV mV mV

Table 13: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
DDR3L-800/1066/1333/1600 Slew Rate (V/ns) >4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 <1.0 Note: at 320mV (ps) 189 189 162 109 91 69 40 Note1 Note1 Note1
tDVAC

DDR3L-1866 at 270mV (ps) 163 163 140 95 80 62 37 5 Note1 Note1
tDVAC

at 270mV (ps) 201 201 179 134 119 100 76 44 Note1 Note1

tDVAC

at 250mV (ps) 168 168 147 105 91 74 52 22 Note1 Note1

tDVAC

at 260mV (ps) 176 176 154 111 97 78 55 24 Note1 Note1

tDVAC

1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 14: RTT Effective Impedance
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [9, 6, 2] RTT Resistor VOUT Min 0, 1, 0 120Ω RTT,120PD240 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RTT,120PU240 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ 120Ω 0, 0, 1 60Ω RTT,60PD120 VIL(AC) to VIH(AC) 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RTT,60PU120 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ 60Ω 0, 1, 1 40Ω RTT,40PD80 VIL(AC) to VIH(AC) 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RTT,40PU80 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ 40Ω 1, 0, 1 30Ω RTT,30PD60 VIL(AC) to VIH(AC) 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RTT,30PU60 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ 30Ω 1, 0, 0 20Ω RTT,20PD40 VIL(AC) to VIH(AC) 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RTT,20PU40 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ 20Ω VIL(AC) to VIH(AC) 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.15 1.15 1.45 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.45 1.15 1.15 1.65

Units RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 15: Reference Settings for ODT Timing Measurements
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Measured Parameter RTT,nom Setting RTT(WR) Setting
tAON

VSW1 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV

VSW2 100mv 200mV 100mv 200mV 100mv 200mV 100mv 200mV 250mV

RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/12 (20Ω)

N/A N/A N/A N/A N/A N/A N/A N/A RZQ/2 (20Ω)

tAOF

tAONPD

tAOFPD

tADC

Table 16: 34Ω Driver Impedance Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [5, 1] RON Resistor VOUT Min 0, 1 34.3Ω RON,34PD 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RON,34PU 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ Pull-up/pull-down mismatch (MMPUPD) Note: VIL(AC) to VIH(AC) 0.6 0.9 0.9 0.9 0.9 0.6 –10

Nom 1.0 1.0 1.0 1.0 1.0 1.0 N/A

Max1 1.15 1.15 1.45 1.45 1.15 1.15 10

Units RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 %

1. A larger maximum limit will result in slightly lower minimum currents.

Table 17: 40Ω Driver Impedance Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [5, 1] RON Resistor VOUT Min 0, 0 40Ω RON,40PD 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ RON,40PU 0.2 × VDDQ 0.5 × VDDQ 0.8 × VDDQ Pull-up/pull-down mismatch (MMPUPD) Note: VIL(AC) to VIH(AC) 0.6 0.9 0.9 0.9 0.9 0.6 –10

Nom 1.0 1.0 1.0 1.0 1.0 1.0 N/A

Max1 1.15 1.15 1.45 1.45 1.15 1.15 10

Units RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 %

1. A larger maximum limit will result in slightly lower minimum currents.

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 18: Single-Ended Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Parameter/Condition Symbol Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.09 × VDDQ and VOH(AC) = VREF + 0.09 × VDDQ SRQse Min 1.75 Max 6 Units V/ns

Table 19: Differential Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Parameter/Condition Symbol Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = –0.18 × VDDQ and VOH,diff(AC) = 0.18 × VDDQ Output differential crosspoint voltage SRQdiff Min 3.5 Max 12 Units V/ns

VOX(AC)

VREF - 135

VREF + 135

mV

Table 20: Electrical Characteristics and AC Operating Conditions
Note 1 applies to base timing specifications DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Parameter Data setup time to DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# CTRL, CMD, ADDR setup to CK, CK# CTRL, CMD, ADDR setup to CK, CK# Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 2 V/ns Base (specification) VREF @ 2 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns
tIS tIS tDH tDS tDH tDS

Symbol
tDS

Min 90 250 140 275 160 250 N/A N/A N/A N/A 215 375 365 500

Max – – – – – – – – – – – – – –

Min 40 200 90 225 110 200 N/A N/A N/A N/A 140 300 290 425

Max – – – – – – – – – – – – – –

Min N/A N/A 45 180 75 165 N/A N/A N/A N/A 80 240 205 340

Max – – – – – – – – – – – – – –

Min N/A N/A 25 160 55 145 N/A N/A N/A N/A 60 220 185 320

Max – – – – – – – – – – – – – –

Min N/A N/A N/A N/A N/A N/A 70 135 75 110 N/A N/A 65 200

Max Units – – – – – – – – – – – – – – ps ps ps ps ps ps ps ps ps ps ps ps ps ps

DQ Input Timing (AC160)

(AC135)

(DC90)

(AC130)

(DC90) Command and Address Timing (AC160)

(AC135)

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 20: Electrical Characteristics and AC Operating Conditions (Continued)
Note 1 applies to base timing specifications DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Parameter CTRL, CMD, ADDR setup to CK, CK# Base (specification) VREF @ 1 V/ns
tIH

Symbol
tIS

Min N/A N/A 285 375

Max – – – –

Min N/A N/A 210 300

Max – – – –

Min N/A N/A 150 240

Max – – – –

Min N/A N/A 130 220

Max – – – –

Min 150 275 110 200

Max Units – – – – ps ps ps ps

(AC125)

CTRL, CMD, Base ADDR hold (specification) from CK, CK# V REF @ 1 V/ns Notes:

(DC90)

1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min with tDS(AC160) of 90ps or VIH(AC135),min with tDS(AC135) of 140ps. 2. When DQ single-ended slew rate is 1V/ns, the DQS differential slew rate is 2V/ns; when DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns;

Table 21: Derating Values for tIS/tIH – AC160/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns ΔtIS ΔtIH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 80 53 0 –1 –3 –5 –8 –20 –40 45 30 0 –3 –8 –13 –20 –30 –45 CK, CK# Differential Slew Rate 3.0 V/ns ΔtIS 80 53 0 –1 –3 –5 –8 –20 –40 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 2.0 V/ns ΔtIS 80 53 0 –1 –3 –5 –8 –20 –40 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 1.8 V/ns ΔtIS 88 61 8 7 5 3 0 –12 –32 ΔtIH 53 38 8 5 1 –5 –12 –22 –37 1.6 V/ns ΔtIS 96 69 16 15 13 11 8 –4 –24 ΔtIH 61 46 16 13 9 3 –4 –14 –29 1.4 V/ns ΔtIS 104 77 24 23 21 19 16 4 –16 ΔtIH 69 54 24 21 17 11 4 –6 –21 1.2 V/ns ΔtIS 112 85 32 31 29 27 24 12 –8 ΔtIH 79 64 34 31 27 21 14 4 –11 1.0 V/ns ΔtIS 120 93 40 39 37 35 32 20 0 ΔtIH 95 80 50 47 43 37 30 20 5

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 22: Derating Values for tIS/tIH – AC135/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns ΔtIS ΔtIH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 68 45 0 2 3 6 9 5 –3 45 30 0 –3 –8 –13 –20 –30 –45 CK, CK# Differential Slew Rate 3.0 V/ns ΔtIS 68 45 0 2 3 6 9 5 –3 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 2.0 V/ns ΔtIS 68 45 0 2 3 6 9 5 –3 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 1.8 V/ns ΔtIS 76 53 8 10 11 14 17 13 6 ΔtIH 53 38 8 5 1 –5 –12 –22 –37 1.6 V/ns ΔtIS 84 61 16 18 19 22 25 21 14 ΔtIH 61 46 16 13 9 3 –4 –14 –29 1.4 V/ns ΔtIS 92 69 24 26 27 30 33 29 22 ΔtIH 69 54 24 21 17 11 4 –6 –21 1.2 V/ns ΔtIS 100 77 32 34 35 38 41 37 30 ΔtIH 79 64 34 31 27 21 14 4 –11 1.0 V/ns ΔtIS 108 85 40 42 43 46 49 45 38 ΔtIH 95 80 50 47 43 37 30 20 5

Table 23: Derating Values for tIS/tIH – AC125/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns ΔtIS ΔtIH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 63 42 0 3 6 10 16 15 13 45 30 0 –3 –8 –13 –20 –30 –45 CK, CK# Differential Slew Rate 3.0 V/ns ΔtIS 63 42 0 3 6 10 16 15 13 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 2.0 V/ns ΔtIS 63 42 0 3 6 10 16 15 13 ΔtIH 45 30 0 –3 –8 –13 –20 –30 –45 1.8 V/ns ΔtIS 71 50 8 11 14 18 24 23 21 ΔtIH 53 38 8 5 1 –5 –12 –22 –37 1.6 V/ns ΔtIS 79 58 16 19 22 26 32 31 29 ΔtIH 61 46 16 13 9 3 –4 –14 –29 1.4 V/ns ΔtIS 87 66 24 27 30 34 40 39 37 ΔtIH 69 54 24 21 17 11 4 –6 –21 1.2 V/ns ΔtIS 95 74 32 35 38 42 48 47 45 ΔtIH 79 64 34 31 27 21 14 4 –11 1.0 V/ns ΔtIS 103 82 40 43 46 50 56 55 53 ΔtIH 95 80 50 47 43 37 30 20 5

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 24: Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition
DDR3L-800/1066/1333/1600 Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 Note:
tVAC

DDR3L-1866
tVAC

at 160mV (ps) 70 53 47 35 31 26 20 12 Note 1 Note 1

tVAC

at 135mV (ps) 209 198 194 186 184 181 177 171 164 164

at 135mV (ps) tVAC at 125mV (ps) 200 200 178 133 118 99 75 43 Note 1 Note 1 205 205 184 143 129 111 89 59 18 18

1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than VIL(AC) level.

Table 25: Derating Values for tDS/tDH – AC160/DC90-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns 80 53 0 45 30 0 3.0 V/ns 80 53 0 –1 45 30 0 –3 2.0 V/ns 80 53 0 –1 –3 45 30 0 –3 –8 61 8 7 5 –3 38 8 5 1 –5 16 15 13 11 8 16 13 9 3 –4 23 21 19 16 4 21 17 11 4 6 29 27 24 12 –8 27 21 14 4 –11 35 32 20 0 37 30 20 5 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

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4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications
Table 26: Derating Values for tDS/tDH – AC135/DC90-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns 68 45 0 45 30 0 3.0 V/ns 68 45 0 2 45 30 0 –3 2.0 V/ns 68 45 0 2 3 45 30 0 –3 –8 53 8 10 11 14 38 8 5 1 –5 16 18 19 22 25 16 13 9 3 –4 26 27 30 33 39 21 17 11 4 –6 35 38 41 37 30 27 21 14 4 –11 46 49 45 38 37 30 20 5 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

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DQ Slew Rate V/ns

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Table 27: Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns
Shaded cells indicate slew rate combinations not supported ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQS, DQS# Differential Slew Rate 8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

Δ
tDS

Δ
tDH

4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

33 28 22

23 19 15

33 28 22 13

23 19 15 9

33 28 22 13 0

23 19 15 9 0 28 22 13 0 –22 19 15 9 0 –15 22 13 0 –22 –65 15 9 0 –15 –45 13 0 –22 –65 –62 9 0 –15 –45 –48 0 –22 –65 –62 –61 0 –15 –45 –48 –53 –14 –57 –54 –53 –49 –7 –37 –40 –45 –50 –49 –46 –45 –41 –37 –29 –32 –37 -42 -49 –38 –37 –33 –29 –31 –24 –29 –34 –41 –51 –29 –25 –21 –23 –28 –19 –24 –31 –41 –56 –17 –13 –15 –20 –8 –15 –25 –40

25

4Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications

4Gb: x4, x8, x16 DDR3L SDRAM Voltage Initialization / Change
Table 28: Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition
Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 Note:
tVAC

at 160mV (ps) 165 165 138 85 67 45 16 Note1 Note1 Note1

tVAC

at 135mV (ps) 113 113 90 45 30 11 Note1 Note1 Note1 Note1

tVAC

at 130mV (ps) 95 95 73 30 16 Note1 – – – –

1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than VIL(AC) level.

Voltage Initialization / Change
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, voltage can be increased to the 1.5V operating range provided that: ? Just prior to increasing the 1.35V operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. ? The 1.5V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. ? The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to any READ command. ? The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating voltages are stable and prior to any READ command. If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage can be reduced to the 1.35V operation range provided that: ? Just prior to reducing the 1.5V operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. ? The 1.35V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. ? The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to any READ command. ? The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating voltages are stable and prior to any READ command.

PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

26

Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3L SDRAM Voltage Initialization / Change VDD Voltage Switching
After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 8 is maintained. Figure 8: VDD Voltage Switching
Ta Tb
(( )) (( )) (( )) (( ))

Tc
(( )) (( ))
tCKSRX

Td
(( )) (( ))

Te
(( )) (( ))

Tf
(( )) (( ))

Tg
(( )) (( ))

Th
(( )) (( ))

Ti
(( )) (( ))

Tj
(( )) (( ))

Tk

CK, CK#

VDD, VDDQ (DDR3) VDD, VDDQ (DDR3L)

TMIN = 10ns
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))

TMIN = 10ns TMIN = 200?s

T = 500?s

RESET#

(( )) (( )) (( )) (( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

tIS
TMIN = 10ns
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
tDLLK

CKE

(( )) (( ))

(( )) (( ))

Valid

tXPR tIS

tMRD

tMRD

tMRD

tMOD

tZQinit

Command

(( )) (( ))

(( )) (( ))

Note 1

(( )) (( ))
(( )) (( ))

MRS

(( )) (( )) (( )) (( ))

MRS

(( )) (( ))

MRS

(( )) (( ))

MRS

(( )) (( ))

ZQCL

(( )) (( ))

Note 1

(( )) (( ))

Valid

BA

(( )) (( ))

(( )) (( ))

MR2

MR3

(( )) (( ))

MR1

(( )) (( ))

MR0

(( )) (( ))

(( )) (( ))

(( )) (( ))

Valid
tIS

tIS

ODT

(( )) (( ))

(( )) (( ))

(( )) (( ))

(( (( (( (( )) )) )) )) Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW (( (( (( (( )) )) )) ))

(( )) (( ))

(( )) (( ))

Valid

RTT

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( ))

(( )) Time break (( ))

Don’t Care

Note:

1. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84780270 4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN

27

Micron Technology, Inc. reserves the right to change products or specifications without notice. ? 2011 Micron Technology, Inc. All rights reserved.


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