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各类IC芯片可靠性分析与测试


The fifth chapter: 5﹑All kinds of IC Reliability Test and analysis

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Kinds of IC Reliability Test item

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MSL or Pre-condition Test T/C Test (Temperature Cycling Test) T/S Test (Thermal Shock Test) HTST (High Temperature Storage Test) T&H Test (Temperature & Humidity Test) THB Test (Temperature, Humidity & Bias Test) PCT (Pressure Cooker Test) Un-Bias HAST (Highly Accelerated Stress Test) HAST (Highly Accelerated Stress Test) HTOL (High Temperature Operation Life Test / Burn-in) Data Retention Teat(數據保持測試) Joint Defect Test(連接點缺陷測試) Migration Defect Test(移植缺陷測試) Other Test

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Packing Level Reliability Test
PRECON TEST

T/C

T/S
(option)

HTS

T&H

PCT
(option)

Un-bias HAST

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MSL and Pre-condition
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The purpose of MSL (moisture sensitive level) test is:
(1) To specify packing method, dry pack or normal pack. (2) To specify the level of pre-condition test.

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The purpose of pre-condition test is:
(1) To simulate(模擬) the procedure (程序)of shipping, storage and SMD board mount.

Reference: JESD22-A113, J-STD-020
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IC Transportation Environment

T/C

Reflow for Soldering
220/240/260

T&H
PCB

y Dr

k ac P

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MSL Test Flow & Simulate Item
EXT. Visual INSP & O/S Test SAM Inspection
Electrical Test
NDT(Non-Destructive Test 非破壞性試驗)using SAM

Temperature Cycle Test(-55oC/125oC, 5X) Dry Bake(125oC, 24HRS)

Simulate Temp. Changes during Transportation to customer Simulate Drying Process of silica gel(硅膠凝體) by dry pack in Production line

Temp & Humidity Test(Level 1,2,2a,3,4,5,6) Simulate Moisture Absorption Reflow(220/235/260oC, 3X) EXT. Visual INSP & O/S Test SAM Inspection
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Simulate Soldering Process Electrical Test

Decision
NDT using SAM

Moisture Sensitive Level
(滲透必要條件)

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Moisture Distribution(濕度分配)
Critical Point for Interfacial Moisture (界面濕度臨界點)is Pad Top Corner
Min =0.875mg/cm3 Max =2.216 0.875 1.024 1.173 1.322 1.471 1.620 1.769 1.918 2.067 2.216

Level 3, 30C/60%, 192hr, 20x20x1.4 QFP

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Moisture Absorption & De-sorption
0.40 0.35

MOISTURE ABSORPTION 潮濕吸收

0.40 0.35

MOISTURE DESORPTION 潮氣吸附作用

Moisture(wt %)

Moisture(wt%)

0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 24 48 72 96 120 144 168 192 216 240

0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 6 12 18 24 30 36 42 48

Time(hrs)
L3 L2 L1 L3

Time(hrs)
L2 L1

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Defect after MSL/Pre-con. Test
1. Package Crack 2. Delamination 3. Electrical Open/Short
PKG CRACK DELAMINATION

CHIP CRACK

PKG CRACK

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Defect after MSL/Pre-con. Test

Die Top Delamination

Die Crack

Package Crack

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Factors cause MSL failure
1. Moisture Exist Inside Package Liquid Gas : Volume Expansion 1900X
240deg.C

1900X
Gas

Liquid

2. CTE Difference in Semiconductor Materials 3. Low Adhesive (低粘接性)btw Semiconductor Materials 4. Low Strength (低應力)of Semiconductor Materials

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MSD control process
Process Material Receive 1. 2. 3. 1. 2. 1. Warehouse storage 2. 3. Control Item Do not open vacuum packing. Check is there any damage of vacuum packing. If vacuum pack damage, ask buyer inform supplier to rework, or change vacuum bag internally by receiving warehouse ,or base on indicator color to decide baking or not when take off vacuum packing.. Finish incoming inspection within 30 minutes after open vacuum packing, then re-packing again. Stick (粘貼)a control label on the bag, to record open/re-packing time for floor life evaluation. Check vacuum packing before issue material, no damage, no improper sealing. For reel package, one reel as one unit when issue material. For tray package, base on MO Q’ty, issue material within 30 minutes. If open the vacuum packing, it’s necessary to stick a control label on the bag to record open/repacking time for floor life evaluation. Check the indicator immediately when take off vacuum bag. If there is no indicator, check is there any control label from IQC or warehouse. Take off vacuum packing on line, and control by component’s moisture sensitive level. Store the MSD component in the moisture-proof cabinet(防潮柜) when line down or SMT machine down time. Record open time & entrance cabinet time on the control label, to evaluate floor life. Programming MSD IC within 1 hour. Use tray & vacuum packing after IC programming. Stick a control label on it for floor life evaluation. Follow component MSL to bake PCBA before repairing. Take of NG IC from PCBA by heat up under the PCBA to avoid IC delamination.

Incoming inspection

SMT

1. 2. 3.

4. Repaired 1. 2.

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Process contents
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Base on indicator color to decide baking or not when take off vacuum packing.

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Baking condition: (1) Tray: use 125°C, follow MSL criteria to define baking time. (2) Reel: use 40°C, <5%RH, follow MSL criteria to define baking time. There will be baking condition outside the vacuum bag normally. If there is no definition, follow the table(4-1) next page to do baking. Control item of moisture-proof cabinet: (1)Moisture controller should be “ON”. (2)Carton & paper can not put into cabinet. (3)The data of electronic moisture monitor should within specific value. (4)Keep cabinet temperature on 25±5°C, moisture <5%~10%RH.

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Reference baking condition

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Reliability: Bath Curve
? Design issue ? Test SPEC ? Process Deviation ? Component / Material wear

? Component / Material Application issue ? Design Margin

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Difference between Reliability & Screen
Reliability Purpose Sample Size Test Remark Check the Quality performance Sampling, LTPD is typical used Long term reliability with or without Pre-conditioning Destructive(破壞性) Screen
Eliminate Early Failure (排除早期失效)

100% Burn-in Temp. Cycling Nondestructive

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Stress affect Reliability
l Thermal

Stress(熱應力) l Humidity Stress(濕度應力) l Bias Stress l Pressure Stress(壓應力) l Mechanical Stress(機械應力) l Vibration Stress(振動應力) l Others Stress

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Reflow Profile Setting

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Typical Reflow Profile

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Purpose of T/C & T/S
To know the durability of Semiconductor package resisting expansion and shrinkage by high and low Temperature.

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Temperature Cycle Test
Test Conditions:

150 C Air

1) Temp : C, +150 / -65 oC B, +125/ -55oC 2) Time : 15 min/ zone 3) Read-out Point : 500,1000 cycles 4) Reference: Mil-Std-883, 1010 JESD22-A104 Measurement: - Open/Short Test

-65 C Air

T/C Chamber

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Effect of T/C Test
EMC

150 C Air

WIRE Cu L/F

Expansion
Cu L/F

SILICON CHIP

-65 C Air

EMC

WIRE Cu L/F

Shrinkage
Cu L/F

SILICON CHIP

T/C Chamber

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Thermal Shock (熱沖擊)Test
Test Conditions: 1) Temp : +150 / -65 deg.C 2) Time : 5 min/ zone 3) Read-out Point : 1000 cycle 4) Reference: JESD22-A106 Measurement: - Open/Short Test 150 C Liquid -65 C Liquid

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Failure Mode after T/C & T/S
1) Open or Intermittent(間斷性) Open due to Bond Lift or Ball Neck Broken by the Chip Surface Delamination 2) Short due to Die Crack & Passivation(鈍化) Crack. 3) Parameter Drift due to Resistance of PN Junction increase
DELAMINATION

CHIP CRACK

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OPEN after T/C & T/S
Delamination Broken Neck(斷頸)

Delamination

Die Top Delamination & Ball Neck Broken

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OPEN Failure Improvement
1. Reduce the CTE difference Between EMC & Si Chip. (CTE of EMC : CTE of Si = 3 : 1 2 or 1 : 1)

2. Coating(覆蓋) Si Chip Surface with Gel. Gel(凝膠體) EMC Die

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HTST, HTOL & Data Retention
Purpose of HTST
To know the durability of Semiconductor package when exposed under the high Temperature for long time.

Purpose of HTOL & Data Retention
To know the durability of Semiconductor Device when exposed under the high Temperature and

Power/Signal for long time.
Reliability.
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– Device Level

High Temperature Storage Test

Test Conditions: 1) Temp : 150 deg.C

150 C N2 gas

2) Read-out Point : 500, 1000 Hrs 3) Reference: JESD22-A103 Measurement: - Open/Short Test

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High Temperature Operation Life

Test Conditions:

150 C N2 gas

1) Temp : 150 deg.C 2) Read-out Point : 500, 1000 Hrs 3) Reference: JESD22-A108 Measurement: - DC and AC parameter

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Data Retention
Only for E2PROM

150 C N2 gas

Test Conditions: 1) Temp : 150 deg.C 2) Read-out Point : 10000, 20000 cycles Measurement: - No Need, The measurement was done during test, it’s a dynamic test.

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Failure after HTST & HTOL
1) Open or Intermittent Open due to Intermetallic material. 2) Short due to Die Crack & Metal Migration. 3) Parameter Drift due to Resistance of PN Junction increase

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OPEN after HTST (metal migration)
Kirkendall void EMC Au

Au
Al Si die

EMC
Kirkendall Voids Diffusion speed

Au
Au4 Al(Diffusion speed : Slow) Au5 Al2 (Diffusion speed : Fast) Au2 Al (White Plague)
AuAl

Al : Fast Au : Slow

AuAl2(Purple Plaque)

Al-Metalization
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Improvement for HTST Failure
1. Change to anti-diffusion materials in high temp. ex) Bonding Wire: Au(commercial) Al(military) 2. Add impurities to control diffusion 3. Avoid expose under high temp for long time

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T&H Test and THB Test
Purpose of T&H Test To know the durability of Semiconductor PKG under the high Temperature and Humidity condition Purpose of THB Test To know the durability of Semiconductor device under the high Temperature and Humidity condition with Power. – Device Level Reliability.
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T&H Test
T&H Chamber
Test Conditions: 1) Temp : 85 oC 2) Humidity : 85 RH% 3) Read-out Point : 500, 1000 Hrs 4) Reference: JESD22-A101 Measurement: - Open/Short Test

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THB Test
Test Conditions:

T&H Chamber

1) Temp : 85 oC 2) Humidity : 85 RH% 3) Power: DC connect to VCC and In-put pin, etc.. GND connect to GND and Out-put pin. 4) Read-out Point : 500, 1000 Hrs 5) Reference: JESD22-A101 Measurement: - Open/Short Test

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Effect of T&H Test and THB Test
1) Al bonding pad corrosion due to moisture which was absorbed through EMC than makes Open failure 2) Short or Leakage due to ion which moves through moisture inside package
Moisture

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Failure after T&H / THB Test
1) Open failure due to bonding pad corrosion. 2) Short or Leakage due to moisture in package and ion migration. 3) Parameter Drift due to Resistance of PN Junction increase

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Failure after T&H Test
L/F L/F EMC EMC L/F EMC EMC L/F

L/F

Tape

L/F

Leakage by the Dendrite

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Ion Migration

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Improvement of T&H Test Failure
1) Packaging with wetproof materials: EMC (commercial) Ceramic(military) 2) Increase wetproof of EMC Improve chemicals of EMC

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Purpose of PCT & Un-Bias Test
To know the existence of gap between EMC & substrate by high Temperature (Over 100oC) and high Humidity. (Pressure will be generated in this Condition.)

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Pressure Cook Test
Test Conditions:

PCT CHAMBER

1) Temp : 121 oC 2) Humidity : 100 RH% 3) Pressure : 15 Psig 4) Read-out Point : 168, 336, 504Hrs 5) reference: JESD22A-102 Measurement: - Open/Short Test

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Un-Bias HAST
Test Conditions:

HAST CHAMBER

1) Temp : 130 oC 2) Humidity : 85 RH% 3) Pressure : 27 Psig* 4) Read-out Point : 48, 168Hrs 5) reference: JESD22A-118 Measurement: - Open/Short Test

* Psig: pound per sqare inch gauge 磅/平方英寸(表壓)
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Effect of PCT & Un-Bias Test
Aluminum bonding pad corrosion (侵蝕)failure can be occur by the moisture which was penetrated(滲透) through a gap between EMC and Lead Frame. This corrosion can makes open failure.
Moisture
2 ATM
Lead Frame

EMC

Au Wire Die

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Failure Mode after PCT & UnBias Test
1) Open failure due to bonding pad corrosion. 2) Short or Leakage due to package gap, moisture in package. 3) Parameter Drift due to Resistance of PN Junction increase

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Pad Corrosion(Pad腐蝕)

NO CORROSION

CORROSION

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Improvement of PCT Failure
1. Increase the adhesive strength(粘合強度) between EMC and L/F by the improvement of chemicals in EMC. 2. Increase the adhesive strength between EMC and L/F by the improvement of Surface

Condition of L/F.

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Improvement of PCT Failure
Scratch Scratch

Die

Lead Frame

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Wire Bond OPEN
1st Bond OPEN cause parameter drift (freq. drift) Au ball bonding was open. Pin 25, ball lift, due to improper bonding condition

Fig. 2: After IC U401was decapped, it was found that a Au wire ball bonding connecting Pin 25 to IC bond pad was open.
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Wire Bond SHORT
Smear ball bond, cause pin SHORT !!

Use a FA sample to explain smear ball bond.

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Molding Cause Wire OPEN
The removed gold wire

2nd bond OPEN cause signal abnormal.
Mold Flow direction

Improper molding condition cause wire sweep too large, 2nd bond OPEN !!

Gold wire missing

Fig. 3: After IC U5 was decapped, it is confirmed that the gold wire was broken and shorted other wires.
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Die Crack
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Failed Pins 94, 95, 97 Shaded areas indicate lifted surface caused by die cracking and chipping. Side view of die edge reveals separation of metal/ insulator layers from die. All units evaluated showed this type of damage. Cracking results in open connections in metal interconnect.

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Die Crack – cont’
Photos show die edge metal delamination and micro-crack as seen in RMA FA

Micro Delamination

Micro crack

Crack

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Die Crack – cont’
Cross-section unit under SEM inspection (FLOW A unit #3):
Cross-section line

Metal Crack shows lifted die edge showing same failure mode as RMA units

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Die Crack caused by SAW
Single saw equipment – Second cut comes in contact with upper die edge

- Two cuts are made with same saw. - First cut made to this depth.

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Die Crack Improvement
Dual Saw reduces upper die edge chipping

Z2

Z1

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