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基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK


Jian 程序
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- a

ny Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lcd is port( clk, reset : in bit; SF_D : out bit_vector(3 downto 0); LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit; LED : out bit_vector(7 downto 0) ); end lcd; architecture behavior of lcd is type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done); signal tx_state : tx_sequence := done; signal tx_byte : bit_vector(7 downto 0); signal tx_init : bit := '0'; type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done); signal init_state : init_sequence := idle; signal init_init, init_done : bit := '0'; signal i : integer range 0 to 750000 := 0; signal i2 : integer range 0 to 2000 := 0; signal i3 : integer range 0 to 82000 := 0; signal SF_D0, SF_D1 : bit_vector(3 downto 0); signal LCD_E0, LCD_E1 : bit; signal mux : bit; type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g, char_a, done); signal cur_state : display_state := init; begin LED <= tx_byte; --for diagnostic purposes SF_CE0 <= '1'; --disable intel strataflash LCD_RW <= '0'; --write only --The following "with" statements simplify the process of adding and removing states. --when to transmit a command/data and when not to with cur_state select tx_init <= '0' when init | pause | done, '1' when others;

--control the bus with cur_state select mux <= '1' when init, '0' when others; --control the initialization sequence with cur_state select init_init <= '1' when init, '0' when others;--register select with cur_state select LCD_RS <= '0' when function_set|entry_set|set_display|clr_display|set_addr, '1' when others; --what byte to transmit to lcd --refer to datasheet for an explanation of these values with cur_state select tx_byte <= "00101000" when function_set, "00000110" when entry_set, "00001100" when set_display, "00000001" when clr_display, "10000000" when set_addr, "01001010" when char_J, "01001001" when char_I, "01000001" when char_A, "01001110" when char_N, "00000000" when others; --main state machine display: process(clk, reset) begin if(reset='1') then cur_state <= function_set; elsif(clk='1' and clk'event) then case cur_state is --refer to intialize state machine below when init => if(init_done = '1') then cur_state <= function_set; else cur_state <= init; end if; --every other state but pause uses the transmit state machine when function_set => if(i2 = 2000) then cur_state <= entry_set; else cur_state <= function_set;

end if; when entry_set => if(i2 = 2000) then cur_state <= set_display; else cur_state <= entry_set; end if; when set_display => if(i2 = 2000) then cur_state <= clr_display; else cur_state <= set_display; end if; when clr_display => i3 <= 0; if(i2 = 2000) then cur_state <= pause; else cur_state <= clr_display; end if; when pause => if(i3 = 82000) then cur_state <= set_addr; i3 <= 0;else cur_state <= pause; i3 <= i3 + 1; end if; when set_addr => if(i2 = 2000) then cur_state <= char_J; else cur_state <= set_addr; end if; when char_J => if(i2 = 2000) then cur_state <= char_I; else cur_state <= char_J; end if; when char_I => if(i2 = 2000) then cur_state <= char_A; else cur_state <= char_I;

end if; when char_A=> if(i2 = 2000) then cur_state <= char_N; else cur_state <= char_A; end if; when char_N => if(i2 = 2000) then cur_state <= done; else cur_state <= char_N; end if; when done => cur_state <= done; end case; end if; end process display; with mux select SF_D <= SF_D0 when '0', --transmit SF_D1 when others; --initialize with mux select LCD_E <= LCD_E0 when '0', --transmit LCD_E1 when others; --initialize --specified by datasheet transmit : process(clk, reset, tx_init) begin if(reset='1') then tx_state <= done; elsif(clk='1' and clk'event) then case tx_state is when high_setup => --40ns LCD_E0 <= '0'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 2) then tx_state <= high_hold; i2 <= 0; else tx_state <= high_setup;i2 <= i2 + 1; end if; when high_hold => --230ns LCD_E0 <= '1'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 12) then

tx_state <= oneus; i2 <= 0; else tx_state <= high_hold; i2 <= i2 + 1; end if; when oneus => LCD_E0 <= '0'; if(i2 = 50) then tx_state <= low_setup; i2 <= 0; else tx_state <= oneus; i2 <= i2 + 1; end if; when low_setup => LCD_E0 <= '0'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 2) then tx_state <= low_hold; i2 <= 0; else tx_state <= low_setup; i2 <= i2 + 1; end if; when low_hold => LCD_E0 <= '1'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 12) then tx_state <= fortyus; i2 <= 0; else tx_state <= low_hold; i2 <= i2 + 1; end if; when fortyus => LCD_E0 <= '0'; if(i2 = 2000) then tx_state <= done; i2 <= 0; else tx_state <= fortyus; i2 <= i2 + 1; end if;

when done => LCD_E0 <= '0'; if(tx_init = '1') then tx_state <= high_setup; i2 <= 0; else tx_state <= done; i2 <= 0; end if; end case; end if; end process transmit;--specified by datasheet power_on_initialize: process(clk, reset, init_init) --power on initialization sequence begin if(reset='1') then init_state <= idle; init_done <= '0'; elsif(clk='1' and clk'event) then case init_state is when idle => init_done <= '0'; if(init_init = '1') then init_state <= fifteenms; i <= 0; else init_state <= idle; i <= i + 1; end if; when fifteenms => init_done <= '0'; if(i = 750000) then init_state <= one; i <= 0; else init_state <= fifteenms; i <= i + 1; end if; when one => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=two; i <= 0;

else init_state<=one; i <= i + 1; end if; when two => LCD_E1 <= '0'; init_done <= '0'; if(i = 205000) then init_state<=three; i <= 0; else init_state<=two; i <= i + 1; end if; when three => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=four; i <= 0; else init_state<=three; i <= i + 1; end if; when four => LCD_E1 <= '0'; init_done <= '0'; if(i = 5000) then init_state<=five;i <= 0; else init_state<=four; i <= i + 1; end if; when five => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=six; i <= 0; else init_state<=five; i <= i + 1;

end if; when six => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=seven; i <= 0; else init_state<=six; i <= i + 1; end if; when seven => SF_D1 <= "0010"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=eight; i <= 0; else init_state<=seven; i <= i + 1; end if; when eight => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=done; i <= 0; else init_state<=eight; i <= i + 1; end if; when done => init_state <= done; init_done <= '1'; end case; end if; end process power_on_initialize; end behavior;

源程序
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lcd is port( clk, reset : in bit; SF_D : out bit_vector(3 downto 0); LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit; LED : out bit_vector(7 downto 0) ); end lcd; architecture behavior of lcd is type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done); signal tx_state : tx_sequence := done; signal tx_byte : bit_vector(7 downto 0); signal tx_init : bit := '0'; type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done); signal init_state : init_sequence := idle; signal init_init, init_done : bit := '0'; signal i : integer range 0 to 750000 := 0; signal i2 : integer range 0 to 2000 := 0; signal i3 : integer range 0 to 82000 := 0; signal SF_D0, SF_D1 : bit_vector(3 downto 0); signal LCD_E0, LCD_E1 : bit; signal mux : bit; type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g, char_a, done); signal cur_state : display_state := init; begin LED <= tx_byte; --for diagnostic purposes SF_CE0 <= '1'; --disable intel strataflash LCD_RW <= '0'; --write only --The following "with" statements simplify the process of adding and removing states. --when to transmit a command/data and when not to

with cur_state select tx_init <= '0' when init | pause | done, '1' when others; --control the bus with cur_state select mux <= '1' when init, '0' when others; --control the initialization sequence with cur_state select init_init <= '1' when init, '0' when others;--register select with cur_state select LCD_RS <= '0' when function_set|entry_set|set_display|clr_display|set_addr, '1' when others; --what byte to transmit to lcd --refer to datasheet for an explanation of these values with cur_state select tx_byte <= "00101000" when function_set, "00000110" when entry_set, "00001100" when set_display, "00000001" when clr_display, "10000000" when set_addr, "01000110" when char_f, "01010000" when char_p, "01000111" when char_g, "01000001" when char_a, "00000000" when others; --main state machine display: process(clk, reset) begin if(reset='1') then cur_state <= function_set; elsif(clk='1' and clk'event) then case cur_state is --refer to intialize state machine below when init => if(init_done = '1') then cur_state <= function_set; else cur_state <= init; end if; --every other state but pause uses the transmit state machine when function_set => if(i2 = 2000) then

cur_state <= entry_set; else cur_state <= function_set; end if; when entry_set => if(i2 = 2000) then cur_state <= set_display; else cur_state <= entry_set; end if; when set_display => if(i2 = 2000) then cur_state <= clr_display; else cur_state <= set_display; end if; when clr_display => i3 <= 0; if(i2 = 2000) then cur_state <= pause; else cur_state <= clr_display; end if; when pause => if(i3 = 82000) then cur_state <= set_addr; i3 <= 0;else cur_state <= pause; i3 <= i3 + 1; end if; when set_addr => if(i2 = 2000) then cur_state <= char_f; else cur_state <= set_addr; end if; when char_f => if(i2 = 2000) then cur_state <= char_p; else cur_state <= char_f; end if; when char_p => if(i2 = 2000) then

cur_state <= char_g; else cur_state <= char_p; end if; when char_g => if(i2 = 2000) then cur_state <= char_a; else cur_state <= char_g; end if; when char_a => if(i2 = 2000) then cur_state <= done; else cur_state <= char_a; end if; when done => cur_state <= done; end case; end if; end process display; with mux select SF_D <= SF_D0 when '0', --transmit SF_D1 when others; --initialize with mux select LCD_E <= LCD_E0 when '0', --transmit LCD_E1 when others; --initialize --specified by datasheet transmit : process(clk, reset, tx_init) begin if(reset='1') then tx_state <= done; elsif(clk='1' and clk'event) then case tx_state is when high_setup => --40ns LCD_E0 <= '0'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 2) then tx_state <= high_hold; i2 <= 0; else tx_state <= high_setup;i2 <= i2 + 1; end if; when high_hold => --230ns

LCD_E0 <= '1'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 12) then tx_state <= oneus; i2 <= 0; else tx_state <= high_hold; i2 <= i2 + 1; end if; when oneus => LCD_E0 <= '0'; if(i2 = 50) then tx_state <= low_setup; i2 <= 0; else tx_state <= oneus; i2 <= i2 + 1; end if; when low_setup => LCD_E0 <= '0'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 2) then tx_state <= low_hold; i2 <= 0; else tx_state <= low_setup; i2 <= i2 + 1; end if; when low_hold => LCD_E0 <= '1'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 12) then tx_state <= fortyus; i2 <= 0; else tx_state <= low_hold; i2 <= i2 + 1; end if; when fortyus => LCD_E0 <= '0'; if(i2 = 2000) then tx_state <= done; i2 <= 0; else

tx_state <= fortyus; i2 <= i2 + 1; end if; when done => LCD_E0 <= '0'; if(tx_init = '1') then tx_state <= high_setup; i2 <= 0; else tx_state <= done; i2 <= 0; end if; end case; end if; end process transmit;--specified by datasheet power_on_initialize: process(clk, reset, init_init) --power on initialization sequence begin if(reset='1') then init_state <= idle; init_done <= '0'; elsif(clk='1' and clk'event) then case init_state is when idle => init_done <= '0'; if(init_init = '1') then init_state <= fifteenms; i <= 0; else init_state <= idle; i <= i + 1; end if; when fifteenms => init_done <= '0'; if(i = 750000) then init_state <= one; i <= 0; else init_state <= fifteenms; i <= i + 1; end if; when one => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0';

if(i = 11) then init_state<=two; i <= 0; else init_state<=one; i <= i + 1; end if; when two => LCD_E1 <= '0'; init_done <= '0'; if(i = 205000) then init_state<=three; i <= 0; else init_state<=two; i <= i + 1; end if; when three => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=four; i <= 0; else init_state<=three; i <= i + 1; end if; when four => LCD_E1 <= '0'; init_done <= '0'; if(i = 5000) then init_state<=five;i <= 0; else init_state<=four; i <= i + 1; end if; when five => SF_D1 <= "0011"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=six; i <= 0;

else init_state<=five; i <= i + 1; end if; when six => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=seven; i <= 0; else init_state<=six; i <= i + 1; end if; when seven => SF_D1 <= "0010"; LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=eight; i <= 0; else init_state<=seven; i <= i + 1; end if; when eight => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=done; i <= 0; else init_state<=eight; i <= i + 1; end if; when done => init_state <= done; init_done <= '1'; end case; end if; end process power_on_initialize; end behavior;

第三种 verilog
该程序实现对 SPARTAN3E 上 2x16 LCD 的初始化及各种初始设置,最后输出“OK”字 样 `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:43:15 10/03/2009 // Design Name: // Module Name: lcd_disp_ok // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module lcd_disp_ok(clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce); input clk; input reset; output lcd_rs; output lcd_rw; output lcd_e; output [3:0] lcd_d; output flash_ce; reg lcd_rs,lcd_e; reg [3:0] lcd_d;

assign flash_ce = 1; assign lcd_rw = 0; reg [19:0] delay_count; reg [19:0] num_count; parameter state1 = 6'b000001; parameter state2 = 6'b000010; parameter state3 = 6'b000011; parameter state4 = 6'b000100; parameter state5 = 6'b000101; parameter state6 = 6'b000110; parameter state7 = 6'b000111; parameter state8 = 6'b001000; parameter state9 = 6'b001001; parameter state10 = 6'b001010; parameter state11 = 6'b001011; parameter state12 = 6'b001100; parameter state13 = 6'b001101; parameter state14 = 6'b001110; parameter state15 = 6'b001111; parameter state16 = 6'b010000; parameter state17 = 6'b010001; parameter state18 = 6'b010010; parameter state19 = 6'b010011; parameter state20 = 6'b010100; parameter state21 = 6'b010101; parameter state22 = 6'b010110; parameter state23 = 6'b010111; parameter state24 = 6'b011000; parameter state25 = 6'b011001; parameter state26 = 6'b011010; parameter state27 = 6'b011011; parameter state28 = 6'b011100; parameter state29 = 6'b011101; parameter state30 = 6'b011110; parameter state31 = 6'b011111; parameter state32 = 6'b100000; parameter state33 = 6'b100001; parameter state34 = 6'b100010; parameter state35 = 6'b100011; parameter state36 = 6'b100100; parameter state37 = 6'b100101; parameter state38 = 6'b100110;

parameter state39 = 6'b100111; parameter state40 = 6'b101000; parameter state41 = 6'b101001; parameter state42 = 6'b101010; parameter state43 = 6'b101011; parameter state44 = 6'b101100; parameter state45 = 6'b101101; parameter state46 = 6'b101110; parameter state47 = 6'b101111; parameter state48 = 6'b110000; parameter state49 = 6'b110001; parameter state50 = 6'b110010; parameter state51 = 6'b110011; parameter state52 = 6'b110100; parameter state53 = 6'b110101; parameter state54 = 6'b110110; parameter state55 = 6'b110111; parameter state56 = 6'b111000; parameter state57 = 6'b111001; parameter state58 = 6'b111010; parameter state59 = 6'b111011;

reg [5:0] state; reg state_change; always @(posedge clk or posedge reset) if(reset) begin state_change <= 1'b0; delay_count <= 1'b1; end else if(delay_count == num_count - 1) begin state_change <= 1'b1; delay_count <= 1'b1; end else begin state_change <= 1'b0; delay_count <= delay_count + 1'b1;

end always @(posedge state_change or posedge reset) if(reset) begin state <= state1; num_count <= 20'd750000; end else case(state) state1:begin state <= state2; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h3; end state2:begin state <= state3; num_count <= 20'd12; lcd_e <= 1'b1; end state3:begin state <= state4; num_count <= 20'd205000; lcd_e <= 1'b0; end state4:begin state <= state5; num_count <= 20'd4; lcd_d <= 4'h3; end state5:begin state <= state6; num_count <= 20'd12; lcd_e <= 1'b1; end

state6:begin state <= state7; num_count <= 20'd5000; lcd_e <= 1'b0; end state7:begin state <= state8; num_count <= 20'd4; lcd_d <= 4'h2; end state8:begin state <= state9; num_count <= 20'd12; lcd_e <= 1'b1; end state9:begin state <= state10; num_count <= 20'd4000; lcd_e <= 1'b0; end //set funtion mode state10:begin state <= state11; num_count <= 20'd4; lcd_rs <= 0; lcd_d <= 4'h2; end state11:begin state <= state12; num_count <= 20'd12; lcd_e <= 1'b1; end state12:begin state <= state13; num_count <= 20'd80; lcd_e <= 1'b0; end state13:begin

state <= state14; num_count <= 20'd4; lcd_d <= 4'h8; end state14:begin state <= state15; num_count <= 20'd12; lcd_e <= 1'b1; end state15:begin state <= state16; num_count <= 20'd4000; lcd_e <= 1'b0; end //set entry mode state16:begin state <= state17; num_count <= 20'd4; lcd_d <= 4'h0; end state17:begin state <= state18; num_count <= 20'd12; lcd_e <= 1'b1; end state18:begin state <= state19; num_count <= 20'd80; lcd_e <= 1'b0; end state19:begin state <= state20; num_count <= 20'd4; lcd_d <= 4'h6; end state20:begin state <= state21; num_count <= 20'd12; lcd_e <= 1'b1;

end state21:begin state <= state22; num_count <= 20'd4000; lcd_e <= 1'b0; end //set display on/off state22:begin state <= state23; num_count <= 20'd4; lcd_d <= 4'h0; end state23:begin state <= state24; num_count <= 20'd12; lcd_e <= 1'b1; end state24:begin state <= state25; num_count <= 20'd80; lcd_e <= 1'b0; end state25:begin state <= state26; num_count <= 20'd4; lcd_d <= 4'hc; end state26:begin state <= state27; num_count <= 20'd12; lcd_e <= 1'b1; end state27:begin state <= state28; num_count <= 20'd4000; lcd_e <= 1'b0; end //clear display state28:begin state <= state29; num_count <= 20'd4; lcd_d <= 4'h0; end state29:begin

state <= state30; num_count <= 20'd12; lcd_e <= 1'b1; end state30:begin state <= state31; num_count <= 20'd80; lcd_e <= 1'b0; end state31:begin state <= state32; num_count <= 20'd4; lcd_d <= 4'h1; end state32:begin state <= state33; num_count <= 20'd12; lcd_e <= 1'b1; end state33:begin state <= state34; num_count <= 20'd2000; lcd_e <= 1'b0; end state34:begin state <= state35; num_count <= 20'd82000; end //set DD RAM address state35:begin state <= state36; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h8; end state36:begin state <= state37; num_count <= 20'd12; lcd_e <= 1'b1; end state37:begin

state <= state38; num_count <= 20'd80; lcd_e <= 1'b0; end state38:begin state <= state39; num_count <= 20'd4; lcd_d <= 4'h0; end state39:begin state <= state40; num_count <= 20'd12; lcd_e <= 1'b1; end state40:begin state <= state41; num_count <= 20'd4000; lcd_e <= 1'b0; end // now starts writing data to DD RAM state41:begin state <= state42; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end state42:begin state <= state43; num_count <= 20'd12; lcd_e <= 1'b1; end state43:begin state <= state44; num_count <= 20'd80; lcd_e <= 1'b0; end state44:begin state <= state45;

num_count <= 20'd4; lcd_d <= 4'hf; end state45:begin state <= state46; num_count <= 20'd12; lcd_e <= 1'b1; end state46:begin state <= state47; num_count <= 20'd2000; lcd_e <= 1'b0; end state47:begin state <= state48; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end state48:begin state <= state49; num_count <= 20'd12; lcd_e <= 1'b1; end state49:begin state <= state50; num_count <= 20'd80; lcd_e <= 1'b0; end state50:begin state <= state51; num_count <= 20'd4; lcd_d <= 4'hb; end state51:begin state <= state52; num_count <= 20'd12; lcd_e <= 1'b1; end

state52:begin state <= state53; num_count <= 20'd2000; lcd_e <= 1'b0; end state53:begin state <= state54; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h2; end state54:begin state <= state55; num_count <= 20'd12; lcd_e <= 1'b1; end state55:begin state <= state56; num_count <= 20'd80; lcd_e <= 1'b0; end state56:begin state <= state57; num_count <= 20'd4; lcd_d <= 4'h1; end state57:begin state <= state58; num_count <= 20'd12; lcd_e <= 1'b1; end state58:begin state <= state59; num_count <= 20'd4000; lcd_e <= 1'b0; end state59:begin state <= state35; num_count <= 20'd800; end

default:begin state <= state1; num_count <= 20'd800; end endcase

endmodule

4、编译成功的程序
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:48:30 04/21/2015 // Design Name: // Module Name: lcd // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module lcd(clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce); input clk; input reset; output lcd_rs; output lcd_rw; output lcd_e; output [3:0] lcd_d; output flash_ce; reg lcd_rs,lcd_e; reg[3:0] lcd_d; assign flash_ce = 1; assign lcd_rw = 0; reg [19:0] delay_count; reg [19:0] num_count; parameter state1 = 6'b000001; parameter state2 = 6'b000010; parameter state3 = 6'b000011; parameter state4 = 6'b000100; parameter state5 = 6'b000101;

parameter state6 = 6'b000110; parameter state7 = 6'b000111; parameter state8 = 6'b001000; parameter state9 = 6'b001001; parameter state10 = 6'b001010; parameter state11 = 6'b001011; parameter state12 = 6'b001100; parameter state13 = 6'b001101; parameter state14 = 6'b001110; parameter state15 = 6'b001111; parameter state16 = 6'b010000; parameter state17 = 6'b010001; parameter state18 = 6'b010010; parameter state19 = 6'b010011; parameter state20 = 6'b010100; parameter state21 = 6'b010101; parameter state22 = 6'b010110; parameter state23 = 6'b010111; parameter state24 = 6'b011000; parameter state25 = 6'b011001; parameter state26 = 6'b011010; parameter state27 = 6'b011011; parameter state28 = 6'b011100; parameter state29 = 6'b011101; parameter state30 = 6'b011110; parameter state31 = 6'b011111; parameter state32 = 6'b100000; parameter state33 = 6'b100001; parameter state34 = 6'b100010; parameter state35 = 6'b100011; parameter state36 = 6'b100100; parameter state37 = 6'b100101; parameter state38 = 6'b100110; parameter state39 = 6'b100111; parameter state40 = 6'b101000; parameter state41 = 6'b101001; parameter state42 = 6'b101010; parameter state43 = 6'b101011; parameter state44 = 6'b101100; parameter state45 = 6'b101101; parameter state46 = 6'b101110; parameter state47 = 6'b101111; parameter state48 = 6'b110000; parameter state49 = 6'b110001;

parameter state50 = 6'b110010; parameter state51 = 6'b110011; parameter state52 = 6'b110100; parameter state53 = 6'b110101; parameter state54 = 6'b110110; parameter state55 = 6'b110111; parameter state56 = 6'b111000; parameter state57 = 6'b111001; parameter state58 = 6'b111010; parameter state59 = 6'b111011;

reg [5:0] state; reg state_change; always @(posedge clk or posedge reset) if(reset) begin state_change <= 1'b0; delay_count <= 1'b1; end else if(delay_count == num_count - 1) begin state_change <= 1'b1; delay_count <= 1'b1; end else begin state_change <= 1'b0; delay_count <= delay_count + 1'b1; end always @(posedge state_change or posedge reset) if(reset) begin state <= state1; num_count <= 20'd750000; end else case(state)

state1:begin state <= state2; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h3; end state2:begin state <= state3; num_count <= 20'd12; lcd_e <= 1'b1; end state3:begin state <= state4; num_count <= 20'd205000; lcd_e <= 1'b0; end state4:begin state <= state5; num_count <= 20'd4; lcd_d <= 4'h3; end state5:begin state <= state6; num_count <= 20'd12; lcd_e <= 1'b1; end state6:begin state <= state7; num_count <= 20'd5000; lcd_e <= 1'b0; end state7:begin state <= state8; num_count <= 20'd4; lcd_d <= 4'h2; end

state8:begin state <= state9; num_count <= 20'd12; lcd_e <= 1'b1; end state9:begin state <= state10; num_count <= 20'd4000; lcd_e <= 1'b0; end //set funtion mode state10:begin state <= state11; num_count <= 20'd4; lcd_rs <= 0; lcd_d <= 4'h2; end state11:begin state <= state12; num_count <= 20'd12; lcd_e <= 1'b1; end state12:begin state <= state13; num_count <= 20'd80; lcd_e <= 1'b0; end state13:begin state <= state14; num_count <= 20'd4; lcd_d <= 4'h8; end state14:begin state <= state15; num_count <= 20'd12; lcd_e <= 1'b1; end

state15:begin state <= state16; num_count <= 20'd4000; lcd_e <= 1'b0; end //set entry mode state16:begin state <= state17; num_count <= 20'd4; lcd_d <= 4'h0; end state17:begin state <= state18; num_count <= 20'd12; lcd_e <= 1'b1; end state18:begin state <= state19; num_count <= 20'd80; lcd_e <= 1'b0; end state19:begin state <= state20; num_count <= 20'd4; lcd_d <= 4'h6; end state20:begin state <= state21; num_count <= 20'd12; lcd_e <= 1'b1; end state21:begin state <= state22; num_count <= 20'd4000; lcd_e <= 1'b0; end //set display on/off state22:begin state <= state23; num_count <= 20'd4; lcd_d <= 4'h0;

end state23:begin state <= state24; num_count <= 20'd12; lcd_e <= 1'b1; end state24:begin state <= state25; num_count <= 20'd80; lcd_e <= 1'b0; end state25:begin state <= state26; num_count <= 20'd4; lcd_d <= 4'hc; end state26:begin state <= state27; num_count <= 20'd12; lcd_e <= 1'b1; end state27:begin state <= state28; num_count <= 20'd4000; lcd_e <= 1'b0; end //clear display state28:begin state <= state29; num_count <= 20'd4; lcd_d <= 4'h0; end state29:begin state <= state30; num_count <= 20'd12; lcd_e <= 1'b1; end state30:begin state <= state31; num_count <= 20'd80; lcd_e <= 1'b0; end state31:begin state <= state32;

num_count <= 20'd4; lcd_d <= 4'h1; end state32:begin state <= state33; num_count <= 20'd12; lcd_e <= 1'b1; end state33:begin state <= state34; num_count <= 20'd2000; lcd_e <= 1'b0; end state34:begin state <= state35; num_count <= 20'd82000; end //set DD RAM address state35:begin state <= state36; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h8; end state36:begin state <= state37; num_count <= 20'd12; lcd_e <= 1'b1; end state37:begin state <= state38; num_count <= 20'd80; lcd_e <= 1'b0; end state38:begin state <= state39; num_count <= 20'd4; lcd_d <= 4'h0; end

state39:begin state <= state40; num_count <= 20'd12; lcd_e <= 1'b1; end state40:begin state <= state41; num_count <= 20'd4000; lcd_e <= 1'b0; end // now starts writing data to DD RAM state41:begin state <= state42; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end state42:begin state <= state43; num_count <= 20'd12; lcd_e <= 1'b1; end state43:begin state <= state44; num_count <= 20'd80; lcd_e <= 1'b0; end state44:begin state <= state45; num_count <= 20'd4; lcd_d <= 4'hf; end state45:begin state <= state46; num_count <= 20'd12; lcd_e <= 1'b1; end state46:begin state <= state47; num_count <= 20'd2000;

lcd_e <= 1'b0; end state47:begin state <= state48; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end state48:begin state <= state49; num_count <= 20'd12; lcd_e <= 1'b1; end state49:begin state <= state50; num_count <= 20'd80; lcd_e <= 1'b0; end state50:begin state <= state51; num_count <= 20'd4; lcd_d <= 4'hb; end state51:begin state <= state52; num_count <= 20'd12; lcd_e <= 1'b1; end state52:begin state <= state53; num_count <= 20'd2000; lcd_e <= 1'b0; end state53:begin state <= state54; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h2;

end state54:begin state <= state55; num_count <= 20'd12; lcd_e <= 1'b1; end state55:begin state <= state56; num_count <= 20'd80; lcd_e <= 1'b0; end state56:begin state <= state57; num_count <= 20'd4; lcd_d <= 4'h1; end state57:begin state <= state58; num_count <= 20'd12; lcd_e <= 1'b1; end state58:begin state <= state59; num_count <= 20'd4000; lcd_e <= 1'b0; end state59:begin state <= state35; num_count <= 20'd800; end default:begin state <= state1; num_count <= 20'd800; end endcase endmodule


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