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ADV7393


Data Sheet
FEATURES

Low Power, Chip Scale, 10-Bit SD/HD Video Encoder ADV7390/ADV7391/ADV7392/ADV7393
Fully programmable YCrCb to RGB matrix Gamma correction Programmable

adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Dual data rate (DDR) input support Enhanced definition (ED) programmable features (525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator Color and black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support Standard definition (SD) programmable features 16× oversampling (216 MHz) Internal test pattern generator Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF filter with programmable gain/attenuation PrPb SSAF Separate pedestal control on component and composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only) Copy generation management system (CGMS) Wide screen signaling (WSS) Closed captioning Serial MPU interface with I2C compatibility 2.7 V or 3.3 V analog operation 1.8 V digital operation 1.8 V or 3.3 V I/O operation Temperature range: ?40°C to +85°C Qualification for automotive applications is in progress

3 high quality, 10-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 RGB (SD) Multiformat video output support Composite (CVBS) and S-Video (Y-C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Lead frame chip scale package (LFCSP) options 32-lead, 5 mm × 5 mm LFCSP 40-lead, 6 mm × 6 mm LFCSP Wafer level chip scale package (WLCSP) option 30-ball, 5 × 6 WLCSP Advanced power management Patented content-dependent low power DAC operation Automatic cable detection and DAC power-down Individual DAC on/off control Sleep mode with minimal power consumption 74.25 MHz 8-/10-/16-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) EIA/CEA-861B compliance support NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (fSC) and phase Luma delay High definition (HD) programmable features (720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator Color and black bar, hatch, flat field/frame

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ?2006-2011 Analog Devices, Inc. All rights reserved.

ADV7390/ADV7391/ADV7392/ADV7393 TABLE OF CONTENTS
Features .............................................................................................. 1? Revision History ............................................................................... 3? Applications....................................................................................... 5? General Description ......................................................................... 5? Functional Block Diagrams............................................................. 6? Specifications..................................................................................... 7? Power Supply Specifications........................................................ 7? Input Clock Specifications .......................................................... 7? Analog Output Specifications..................................................... 7? Digital Input/Output Specifications—3.3 V ............................. 8? Digital Input/Output Specifications—1.8 V ............................. 8? MPU Port Timing Specifications ............................................... 8? Digital Timing Specifications—3.3 V ........................................ 9? Digital Timing Specifications—1.8 V ...................................... 10? Video Performance Specifications ........................................... 11? Power Specifications .................................................................. 11? Timing Diagrams........................................................................ 12? Absolute Maximum Ratings.......................................................... 18? Thermal Resistance .................................................................... 18? ESD Caution................................................................................ 18? Pin Configurations and Function Descriptions ......................... 19? Typical Performance Characteristics ........................................... 21? MPU Port Description................................................................... 26? I2C Operation.............................................................................. 26? Register Map Access....................................................................... 28? Register Programming............................................................... 28? Subaddress Register (SR7 to SR0) ............................................ 28? ADV7390/ADV7391 Input Configuration ................................. 45? Standard Definition.................................................................... 45? Enhanced Definition/High Definition .................................... 45? Enhanced Definition (at 54 MHz) ........................................... 45? ADV7392/ADV7393 Input Configuration ................................. 46? Standard Definition.................................................................... 46? Enhanced Definition/High Definition .................................... 47? Enhanced Definition (at 54 MHz) ........................................... 47? Output Configuration .................................................................... 48? Design Features............................................................................... 49? Output Oversampling ................................................................ 49? ED/HD Nonstandard Timing Mode........................................ 49?

Data Sheet
HD Interlace External HSYNC and VSYNC Considerations ....................................................................................................... 50? ED/HD Timing Reset ................................................................ 50? SD Subcarrier Frequency Lock, Subcarrier Reset, and Timing Reset ............................................................................................. 50? SD VCR FF/RW Sync ................................................................ 51? Vertical Blanking Interval ......................................................... 51? SD Subcarrier Frequency Control............................................ 52? SD Noninterlaced Mode............................................................ 52? SD Square Pixel Mode ............................................................... 52? Filters............................................................................................ 54? ED/HD Test Pattern Color Controls ....................................... 55? Color Space Conversion Matrix ............................................... 55? SD Luma and Color Scale Control........................................... 57? SD Hue Adjust Control.............................................................. 57? SD Brightness Detect ................................................................. 57? SD Brightness Control............................................................... 57? SD Input Standard Autodetection............................................ 58? Double Buffering ........................................................................ 58? Programmable DAC Gain Control .......................................... 58? Gamma Correction .................................................................... 59? ED/HD Sharpness Filter and Adaptive Filter Controls......... 60? ED/HD Sharpness Filter and Adaptive Filter Application Examples...................................................................................... 61? SD Digital Noise Reduction...................................................... 62? SD Active Video Edge Control ................................................. 64? External Horizontal and Vertical Synchronization Control. 65? Low Power Mode........................................................................ 66? Cable Detection .......................................................................... 66? DAC Autopower-Down............................................................. 66? Sleep Mode .................................................................................. 66? Pixel and Control Port Readback............................................. 67? Reset Mechanisms ...................................................................... 67? SD Teletext Insertion ................................................................. 67? Printed Circuit Board Layout and Design .................................. 69? Unused Pins ................................................................................ 69? DAC Configurations.................................................................. 69? Video Output Buffer and Optional Output Filter.................. 69? Printed Circuit Board (PCB) Layout ....................................... 70? Additional Layout Considerations for the WLCSP Package 71? Typical Applications Circuits.................................................... 72?

Rev. C | Page 2 of 108

Data Sheet
Copy Generation Management System........................................74? SD CGMS .....................................................................................74? ED CGMS.....................................................................................74? HD CGMS....................................................................................74? CGMS CRC Functionality .........................................................74? SD Wide Screen Signaling..............................................................77? SD Closed Captioning ....................................................................78? Internal Test Pattern Generation...................................................79? SD Test Patterns...........................................................................79? ED/HD Test Patterns ..................................................................79? SD Timing ........................................................................................80? HD Timing.......................................................................................85? Video Output Levels .......................................................................86?

ADV7390/ADV7391/ADV7392/ADV7393
SD YPrPb Output Levels—SMPTE/EBU N10........................86? ED/HD YPrPb Output Levels ...................................................87? SD/ED/HD RGB Output Levels................................................88? SD Output Plots ..........................................................................89? Video Standards ..............................................................................90? Configuration Scripts .....................................................................92? Standard Definition ....................................................................92? Enhanced Definition ..................................................................99? High Definition .........................................................................101? ADV739x Evaluation Board ........................................................104? Outline Dimensions......................................................................105? Ordering Guide .........................................................................106? Automotive Products................................................................106?

REVISION HISTORY
9/11—Rev. B to Rev. C Changes to MPU Port Description Section.................................26 Updated Outline Dimensions......................................................106 7/10—Rev. A to Rev. B Changes to Features Section ............................................................1 Change to Applications Section ......................................................5 Changes to General Description .....................................................5 Added Table 2, Renumbered Subsequent Tables ..........................5 Added Figure 2, Renumbered Subsequent Figures.......................6 Changes to Full-Drive Output Current Parameter, Table 5.........7 Changes to Table 14 ........................................................................18 Added Figure 20 ..............................................................................19 Changes to Table 15 ........................................................................19 Changes to ADV7390/ADV7391 Input Configuration Section ..............................................................................................45 Added Additional Layout Considerations for the WLCSP Package Section ...............................................................................71 Added Figure 97 ..............................................................................73 Changes to Configuration Scripts Section...................................92 Changes to Subaddress 0x00, Table 66 .........................................93 Changes to Subaddress 0x00, Table 80 .........................................95 Changes to Subaddress 0x00, Table 83 .........................................95 Changes to Subaddress 0x00, Table 97 .........................................98 Updated Outline Dimensions, Added Figure 150 ....................106 Changes to Ordering Guide.........................................................106 3/09—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Deleted Detailed Features Section, Changes to Table 1 ...............4 Changes to Figure 1, Added Figure 2 .............................................5 Changes to Table 2, Input Clock Specifications Section, and Analog Output Specifications Section............................................6 Changes to Digital Input/Output Specifications—3.3 V Section and Table 5 .........................................................................................7 Added Digital Input/Output Specifications—1.8 V Section and Table 6.................................................................................................7 Changes to MPU Port Timing Specifications Section, Default Conditions............................................................................7 Changes to Digital Timing Specifications—3.3 V Section and Table 8.................................................................................................8 Added Digital Timing Specifications—1.8 V Section and Table 9.................................................................................................9 Added Video Performance Specifications Section, Default Conditions........................................................................................10 Added Power Specifications Section, Default Conditions.........10 Changes to Table 11 ........................................................................10 Changes to Figure 16 ......................................................................16 Changes to Table 12 ........................................................................17 Changes to Table 14, Pin 19 and Pin 1 Descriptions..................18 Changes to MPU Port Description Section.................................25 Changes to I2C Operation Section................................................25 Added Table 15 ................................................................................25 Changes to Table 17 ........................................................................28 Changes to Table 19, 0x30 Bit Description..................................30 Changes to Table 27 ........................................................................37 Changes to Table 29, 0x8B Bit Description .................................39 Changes to Table 30 ........................................................................40 Changes to Table 31 ........................................................................41 Added Table 32 ................................................................................42 Renamed Features Section to Design Features Section .............48 Changes to ED/HD Nonstandard Timing Mode Section..........48 Added the HD Interlace External HSYNC and VSYNC Considerations Section...................................................................49 Changes to SD Subcarrier Frequency Lock, Subcarrier Reset, and Timing Reset Section ..............................................................49 Changes to Subaddress 0x8C to Subaddress 0x8F Section........51 Changes to Programming the FSC Section ...................................51 Changes to Subaddress 0x82, Bit 4 Section .................................51 Added SD Manual CSC Matrix Adjust Feature Section ............54

Rev. C | Page 3 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Added Table 47 ............................................................................... 55 Changes to Subaddress 0xBA Section.......................................... 56 Added Sleep Mode Section............................................................ 65 Changes to Pixel and Control Port Readback Section............... 66 Changes to Reset Mechanisms Section........................................ 66 Added SD Teletext Insertion Section........................................... 66 Added Figure 87.............................................................................. 67 Added Figure 88.............................................................................. 68 Changes to DAC Configuration Section ..................................... 68

Data Sheet
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 56 Added Unused Pins Section.......................................................... 68 Changes to Power Supply Sequencing Section........................... 70 Changes to Internal Test Pattern Generation Section ............... 77 Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = XXXXX000) Section.................................. 78 10/06—Revision 0: Initial Version

Rev. C | Page 4 of 108

Data Sheet
APPLICATIONS
Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7392 and ADV7393 only)

ADV7390/ADV7391/ADV7392/ADV7393
Table 1. Standards Directly Supported by the LFCSP Packages1
Active Resolution 720 × 240 720 × 288 720 × 480 720 × 576 640 × 480 768 × 576 720 × 483 720 × 483 720 × 483 720 × 576 720 × 483 720 × 576 1920 × 1035 1920 × 1035 1280 × 720 1280 × 720 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080
1 2

I/P2 P P I I I I P P P P P P I I P P I I P P P

Frame Rate (Hz) 59.94 50 29.97 25 29.97 25 59.94 59.94 59.94 50 59.94 50 30 29.97 60, 50, 30, 25, 24 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97 24

Clock Input (MHz) 27 27 27 27 24.54 29.5 27 27 27 27 27 27 74.25 74.1758 74.25 74.1758 74.25 74.1758 74.25 74.1758 74.25

Standard

GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for the WLCSP package) provide support for composite (CVBS), S-Video (Y-C), or component (YPrPb/RGB) analog outputs in either standard definition (SD) or high definition (HD) video formats. The single DAC WLCSP package supports CVBS (NTSC and PAL) output only in SD resolution (see Table 2). Optimized for low power operation, occupying a minimal footprint, and requiring few external components, these encoders are ideally suited to portable and power-sensitive applications requiring TV-out functionality. Cable detection and DAC autopower-down features ensure that power consumption is kept to a minimum. The ADV7390/ADV7391 have an 8-bit video input port that supports SD video formats over an SDR interface and HD video formats over a DDR interface. The ADV7392/ADV7393 have a 16-bit video input port that can be configured in a variety of ways. SD RGB input is supported. All members of the family support embedded EAV/SAV timing codes, external video synchronization signals, and the I2C? and communication protocol. Table 1 and Table 2 list the video standards directly supported by the ADV739x family.

ITU-R BT.601/656 ITU-R BT.601/656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 240M SMPTE 296M SMPTE 296M SMPTE 274M SMPTE 274M SMPTE 274M SMPTE 274M ITU-R BT.709-5

Other standards are supported in the ED/HD nonstandard timing mode. I = interlaced, P = progressive.

Table 2. Standards Directly Supported by the WLCSP Package
Active Resolution 720 × 480 720 × 576 640 × 480 768 × 576
1

I/P 1 I I I I

Frame Rate (Hz) 29.97 25 29.97 25

Clock Input (MHz) 27 27 24.54 29.5

Standard ITU-R BT.601/656 ITU-R BT.601/656 NTSC Square Pixel PAL Square Pixel

I = interlaced, P = progressive.

Rev. C | Page 5 of 108

ADV7390/ADV7391/ADV7392/ADV7393
FUNCTIONAL BLOCK DIAGRAMS
DGND (2) VDD (2) SCL SDA ALSB SFL AGND VAA GND_IO VDD_IO ADD SYNC VBI DATA SERVICE INSERTION

Data Sheet

MPU PORT

ADV7390/ADV7391
SUBCARRIER FREQUENCY LOCK (SFL) YCrCb TO RGB 16× FILTER 11-BIT DAC 1 11-BIT DAC 2 DAC 1

MULTIPLEXER

8-BIT SD OR 8-BIT ED/HD

SDR/DDR SD/ED/HD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE

PROGRAMMABLE LUMINANCE FILTER

DAC 2

ADD BURST ASYNC BYPASS YCrCb HDTV TEST PATTERN GENERATOR

PROGRAMMABLE CHROMINANCE FILTER

SIN/COS DDS BLOCK

16× FILTER

11-BIT DAC 3

DAC 3

PROGRAMMABLE ED/HD FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL

YCbCr TO RGB MATRIX

4× FILTER

POWER MANAGEMENT CONTROL

VIDEO TIMING GENERATOR

16×/4× OVERSAMPLING PLL

REFERENCE AND CABLE DETECT

RSET
06234-001

RESET

HSYNC

VSYNC

CLKIN

PVDD

PGND EXT_LF

COMP

Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)

DGND (2)

VDD (2)

SCL

SDA

ALSB

SFL

AGND

VAA

GND_IO VDD_IO

VBI DATA SERVICE INSERTION

MPU PORT

ADV7390BCBZ
SUBCARRIER FREQUENCY LOCK (SFL)

8-BIT SD

SDR/DDR SD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE

ADD SYNC

MULTIPLEXER

PROGRAMMABLE LUMINANCE FILTER

16× FILTER

11-BIT DAC 1

DAC 1

ADD BURST

PROGRAMMABLE CHROMINANCE FILTER

SIN/COS DDS BLOCK

16× FILTER

POWER MANAGEMENT CONTROL

VIDEO TIMING GENERATOR

16× OVERSAMPLING PLL

REFERENCE AND CABLE DETECT

RSET
06234-146

RESET

HSYNC

VSYNC

CLKIN

PVDD

PGND EXT_LF

COMP

Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)

DGND (2)

VDD (2)

SCL

SDA

ALSB

SFL

AGND

VAA

GND_IO VDD_IO

VBI DATA SERVICE INSERTION

MPU PORT

ADV7392/ADV7393
SUBCARRIER FREQUENCY LOCK (SFL) YCrCb TO RGB 16× FILTER 12-BIT DAC 1 12-BIT DAC 2 DAC 1

MULTIPLEXER

8-/10-/16-BIT SD OR 8-/10-/16-BIT ED/HD

SDR/DDR SD/ED/HD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE

RGB TO YCrCb MATRIX

ADD SYNC

PROGRAMMABLE LUMINANCE FILTER

DAC 2

ADD BURST ASYNC BYPASS YCrCb HDTV TEST PATTERN GENERATOR

PROGRAMMABLE CHROMINANCE FILTER

SIN/COS DDS BLOCK

16× FILTER

12-BIT DAC 3

DAC 3

PROGRAMMABLE ED/HD FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL

YCbCr TO RGB MATRIX

4× FILTER

POWER MANAGEMENT CONTROL

VIDEO TIMING GENERATOR

16x/4x OVERSAMPLING PLL

REFERENCE AND CABLE DETECT

RSET
06234-145

RESET

HSYNC

VSYNC

CLKIN

PVDD

PGND EXT_LF

COMP

Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
Rev. C | Page 6 of 108

Data Sheet SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 3.
Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO

ADV7390/ADV7391/ADV7392/ADV7393

Min 1.71 1.71 1.71 2.6

Typ 1.8 3.3 1.8 3.3 0.002

Max 1.89 3.63 1.89 3.465

Unit V V V V %/%

INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 4.
Parameter fCLKIN Conditions 1 SD/ED ED (at 54 MHz) HD Min Typ 27 54 74.25 Max Unit MHz MHz MHz % of one clock cycle % of one clock cycle ±ns

CLKIN High Time, t9 CLKIN Low Time, t10 CLKIN Peak-to-Peak Jitter Tolerance
1

40 40 2

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 5.
Parameter Full-Drive Output Current Conditions RSET = 510 Ω, RL = 37.5 Ω All DACs enabled RSET = 510 Ω, RL = 37.5 Ω DAC 1 enabled only 1 RSET = 4.12 kΩ, RL = 300 Ω DAC 1, DAC 2, DAC 3 Min 33 31.5 Typ 34.6 33.5 4.3 2.0 0 10 6 1 1.4 Max 37 37 Unit mA mA mA % V pF ns ns

Low-Drive Output Current DAC-to-DAC Matching Output Compliance, VOC Output Capacitance, COUT Analog Output Delay 2 DAC Analog Output Skew
1 2

DAC 1, DAC 2, DAC 3

The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12. Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.

Rev. C | Page 7 of 108

ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 6.
Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance Conditions Min 2.0 Typ Max 0.8 ±10 4 ISOURCE = 400 μA ISINK = 3.2 mA VIN = 0.4 V, 2.4 V 2.4 0.4 ±1 4 Unit V V μA pF V V μA pF

Data Sheet

VIN = VDD_IO

DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 7.
Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Output Capacitance Conditions Min 0.7 VDD_IO Typ Max 0.3 VDD_IO 4 ISOURCE = 400 μA ISINK = 3.2 mA VDD_IO – 0.4 0.4 4 Unit V V pF V V pF

MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 8.
Parameter MPU PORT, I2C MODE 1 SCL Frequency SCL High Pulse Width, t1 SCL Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDA, SCL Rise Time, t6 SDA, SCL Fall Time, t7 Setup Time (Stop Condition), t8
1

Conditions See Figure 17

Min 0 0.6 1.3 0.6 0.6 100

Typ

Max 400

Unit kHz μs μs μs μs ns ns ns μs

300 300 0.6

Guaranteed by characterization.

Rev. C | Page 8 of 108

Data Sheet
DIGITAL TIMING SPECIFICATIONS—3.3 V

ADV7390/ADV7391/ADV7392/ADV7393

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 9.
Parameter VIDEO DATA AND VIDEO CONTROL PORT 2, 3 Data Input Setup Time, t11 4 Conditions 1 SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) Min 2.1 2.3 2.3 1.7 1.0 1.1 1.1 1.0 2.1 2.3 1.7 1.0 1.1 1.0 12 10 4.0 3.5 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Data Input Hold Time, t124

Control Input Setup Time, t114

Control Input Hold Time, t124

Control Output Access Time, t134 Control Output Hold Time, t144 PIPELINE DELAY 5 SD1 CVBS/Y-C Outputs (2×) CVBS/Y-C Outputs (8×) CVBS/Y-C Outputs (16×) Component Outputs (2×) Component Outputs (8×) Component Outputs (16×) ED1 Component Outputs (1×) Component Outputs (4×) Component Outputs (8×) HD1 Component Outputs (1×) Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time
1 2

SD oversampling disabled SD oversampling enabled SD oversampling enabled SD oversampling disabled SD oversampling enabled SD oversampling enabled ED oversampling disabled ED oversampling enabled ED oversampling enabled HD oversampling disabled HD oversampling enabled HD oversampling enabled 100

68 79 67 78 69 84 41 49 46 40 42 44

Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles ns

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video control: HSYNC and VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design.

Rev. C | Page 9 of 108

ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (?40°C to +85°C), unless otherwise noted. Table 10.
Parameter VIDEO DATA AND VIDEO CONTROL PORT 2, 3 Data Input Setup Time, t11 4 Conditions 1 SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) Min 1.4 1.9 1.9 1.6 1.4 1.5 1.5 1.3 1.4 1.2 1.0 1.4 1.0 1.0 13 12 4.0 5.0 Typ Max

Data Sheet

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Data Input Hold Time, t124

Control Input Setup Time, t114

Control Input Hold Time, t124

Control Output Access Time, t134 Control Output Hold Time, t144 PIPELINE DELAY 5 SD1 CVBS/Y-C Outputs (2×) CVBS/Y-C Outputs (8×) CVBS/Y-C Outputs (16×) Component Outputs (2×) Component Outputs (8×) Component Outputs (16×) ED1 Component Outputs (1×) Component Outputs (4×) Component Outputs (8×) HD1 Component Outputs (1×) Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time
1 2

SD oversampling disabled SD oversampling enabled SD oversampling enabled SD oversampling disabled SD oversampling enabled SD oversampling enabled ED oversampling disabled ED oversampling enabled ED oversampling enabled HD oversampling disabled HD oversampling enabled HD oversampling enabled 100

68 79 67 78 69 84 41 49 46 40 42 44

Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles ns

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video control: HSYNC and VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design.

Rev. C | Page 10 of 108

Data Sheet
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C. Table 11.
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1, 2 STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) 3 ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma Bandwidth HIGH DEFINITION (HD) MODE Luma Bandwidth Chroma Bandwidth
1 2

ADV7390/ADV7391/ADV7392/ADV7393

Conditions

Min

Typ 10 0.5 0.5 0.5 0.5 0.6 58 75 12.5 5.8 30.0 13.75

Max

Unit Bits LSBs LSBs ±% % Degrees dB dB MHz MHz MHz MHz

RSET = 510 Ω, RL = 37.5 Ω RSET = 510 Ω, RL = 37.5 Ω

NTSC NTSC Luma ramp Flat field full bandwidth

Measured on DAC 1, DAC 2, and DAC 3. Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value. For ?ve DNL, the actual step value lies below the ideal step value. 3 Measured on the ADV7392/ADV7393 operating in 10-bit input mode.

POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C. Table 12.
Parameter NORMAL POWER MODE 1, 2 IDD 3 Conditions SD (16× oversampling enabled), CVBS (only one DAC turned on) SD (16× oversampling enabled), YPrPb (three DACs turned on) ED (8× oversampling enabled) 4 HD (4× oversampling enabled)4 One DAC enabled All DACs enabled Min Typ 33 68 59 81 1 50 122 4 5 0.3 0.2 0.1 Max Unit mA mA mA mA mA mA mA mA μA μA μA μA

IDD_IO IAA 5 IPLL SLEEP MODE IDD IAA IDD_IO IPLL
1 2 3

101 10 151 10

RSET = 510 Ω (all DACs operating in full-drive mode). 75% color bar test pattern applied to pixel data pins. IDD is the continuous current required to drive the digital core. 4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes. 5 IAA is the total current required to supply all DACs.

Rev. C | Page 11 of 108

ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11: ? ? ? ? t9 = clock high time t10 = clock low time t11 = data setup time t12 = data hold time
CLKIN

Data Sheet
? t13 = control output access time ? t14 = control output hold time In addition, see Table 35 for the ADV7390/ADV7391 pixel port input configuration and Table 36 for the ADV7392/ADV7393 pixel port input configuration.

t9
CONTROL INPUTS HSYNC VSYNC

t10

t12
IN SLAVE MODE

PIXEL PORT

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

t11
CONTROL OUTPUTS

t13
IN MASTER/SLAVE MODE

t14

Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000

CLKIN

t9
CONTROL INPUTS HSYNC VSYNC

t10

t12
IN SLAVE MODE

PIXEL PORT

Y0

Y1

Y2

Y3

PIXEL PORT

Cb0

Cr0

Cb2

Cr2

t11
CONTROL OUTPUTS

t13
IN MASTER/SLAVE MODE

06234-002

t14

Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000

Rev. C | Page 12 of 108

06234-003

Data Sheet
CLKIN

ADV7390/ADV7391/ADV7392/ADV7393

t9
CONTROL INPUTS HSYNC VSYNC

t10

t12

PIXEL PORT

G0

G1

G2

PIXEL PORT

B0

B1

B2

t11
PIXEL PORT R0 R1 R2

CONTROL OUTPUTS
06234-004

t14 t13

Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000

CLKIN

t9
CONTROL INPUTS HSYNC VSYNC

t10

t12

PIXEL PORT

Y0

Y1

Y2

Y3

Y4

Y5

PIXEL PORT

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

t11
CONTROL OUTPUTS

t13

t14

Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001

CLKIN*

t9
CONTROL INPUTS HSYNC VSYNC

t10

PIXEL PORT

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

t11

t12 t11

t12 t13

CONTROL OUTPUTS

t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 010

Rev. C | Page 13 of 108

06234-006

06234-005

ADV7390/ADV7391/ADV7392/ADV7393
CLKIN*

Data Sheet

t9

t10

PIXEL PORT

3FF

00

00

XY

Cb0

Y0

Cr0

Y1

t11

t12 t11

t12 t13

CONTROL OUTPUTS

t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010

CLKIN

t9
CONTROL INPUTS HSYNC VSYNC Cb0

t10

PIXEL PORT

Y0

Cr0

Y1

Cb2

Y2

Cr2

t11
CONTROL OUTPUTS

t12

t13 t14
06234-008

Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111

CLKIN

t9

t10

PIXEL PORT

3FF

00

00

XY

Cb0

Y0

Cr0

Y1

t11
CONTROL OUTPUTS

t12

t13 t14
06234-009

Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111

Rev. C | Page 14 of 108

06234-007

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Y0

Y1

Y2

Y3

PIXEL PORT*

Cb0

Cr0

Cb2

Cr2

a a = AS PER RELEVANT STANDARD.
06234-010

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Cb0

Y0

Cr0

Y1

a

a(MIN) = 244 CLOCK CYCLES FOR 525p. a(MIN) = 264 CLOCK CYCLES FOR 625p.
06234-011

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram

Rev. C | Page 15 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Y0

Y1

Y2

Y3

PIXEL PORT

Cb0

Cr0

Cb2

Cr2

a

a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Cb0

Y0

Cr0

Y1

a a = AS PER RELEVANT STANDARD.
06234-013

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram

Rev. C | Page 16 of 108

06234-012

Data Sheet
HSYNC

ADV7390/ADV7391/ADV7392/ADV7393

VSYNC

PIXEL PORT

Cb

Y

Cr

Y

PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES

Figure 16. SD Input Timing Diagram (Timing Mode 1)

t3
SDA

t5

t3

t6
SCL

t1 t2 t7 t4
2

t8

Figure 17. MPU Port Timing Diagram (I C Mode)

Rev. C | Page 17 of 108

06234-015

06234-014

ADV7390/ADV7391/ADV7392/ADV7393 ABSOLUTE MAXIMUM RATINGS
Table 13.
Parameter VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Max CLKIN Input Frequency Storage Temperature Range (tS) Junction Temperature (tJ) Lead Temperature (Soldering, 10 sec)
1

Data Sheet
THERMAL RESISTANCE

1

Rating ?0.3 V to +3.9 V ?0.3 V to +2.3 V ?0.3 V to +2.3 V ?0.3 V to +3.9 V ?0.3 V to +0.3 V ?0.3 V to +0.3 V ?0.3 V to +0.3 V ?0.3 V to +0.3 V ?0.3 V to +0.3 V ?0.3 V to +0.3 V ?0.3 V to VDD_IO + 0.3 V ?0.3 V to VAA 80 MHz ?60°C to +100°C 150°C 260°C

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 14. Thermal Resistance1
Package Type 30-Ball WLCSP 32-Lead LFCSP 40-Lead LFCSP
1 2

θJA2 35 27 26

θJC 1 32 32

Unit °C/W °C/W °C/W

Values are based on a JEDEC 4-layer test board. With the exposed metal paddle on the underside of the LFCSP soldered to the PCB ground.

The ADV739x is an RoHS-compliant, Pb-free product. The lead finish is 100% pure Sn electroplate. The device is suitable for Pbfree applications up to 255°C (±5°C) IR reflow (JEDEC STD-20). The ADV739x is backward compatible with conventional SnPb soldering processes. The electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220°C to 235°C.

Analog output short circuit to any power supply or common can be of an indefinite duration.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 18 of 108

Data Sheet
GND_IO P1 P0 DGND VDD HSYNC VSYNC SFL

ADV7390/ADV7391/ADV7392/ADV7393
BALL A1 CORNER 1 A
24 23 22 21 20 19 18 17 RSET COMP DAC 1 DAC 2 DAC 3 VAA AGND PVDD

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
HSYNC

3 VDD

4 P0

5
VDD_IO

32 31 30 29 28 27 26 25

RSET

VDD_IO P2 P3 P4 VDD DGND P5 P6

1 2 3 4 5 6 7 8

PIN 1 INDICATOR

B

DAC1

VSYNC

SFL

P1

P2

ADV7390/ ADV7391
TOP VIEW (Not to Scale)
9 10 11 12 13 14 15 16

C

VAA

COMP

DGND

P3

P4

D

AGND

GND_IO

RESET

VDD

DGND

P7 ALSB SDA SCL CLKIN RESET PGND EXT_LF

E

PVDD

EXT_LF

ALSB

P5

P6

06234-017

NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND (AGND).

F

PGND

SDA

SCL

CLKIN

P7
06234-147

Figure 18. ADV7390/ADV7391 Pin Configuration
GND_IO P3 P2 P1 DGND VDD P0 HSYNC VSYNC SFL

TOP VIEW (BALL SIDE DOWN) Not to Scale

Figure 20. ADV7390BCBZ-A Pin Configuration

VDD_IO 1 P4 2 P5 3 P6 4 P7 5 VDD 6 DGND 7 P8 8 P9 9 P10 10

40 39 38 37 36 35 34 33 32 31

PIN 1 INDICATOR

ADV7392/ ADV7393
TOP VIEW (Not to Scale)

30 29 28 27 26 25 24 23 22 21

RSET COMP DAC 1 DAC 2 DAC 3 VAA AGND PVDD EXT_LF PGND

Figure 19. ADV7392/ADV7393 Pin Configuration

Table 15. Pin Function Descriptions
ADV7390/ ADV7391 9 to 7, 4 to 2, 31, 30 Pin No. ADV7392/ ADV7393 ADV7390 WLCSP F5, E5, E4, C5, C4, B5, B4, A4 Input/ Output I I

Mnemonic P7 to P0 P15 to P0

06234-018

NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND (AGND).

P11 ALSB SDA SCL P12 P13 P14 P15 CLKIN RESET

11 12 13 14 15 16 17 18 19 20

13 27

18 to 15, 11 to 8, 5 to 2, 39 to 37, 34 19 33

Description 8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for input modes (ADV7390/ADV7391). 16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for input modes (ADV7392/ADV7393). Pixel Clock Input for HD (74.25 MHz), ED 1 (27 MHz or 54 MHz), or SD (27 MHz). Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section. Subcarrier Frequency Lock (SFL) Input. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.

F4 A2

CLKIN HSYNC

I I/O

26

32

B2

VSYNC

I/O

25

31

B3

SFL

I/O

Rev. C | Page 19 of 108

ADV7390/ADV7391/ADV7392/ADV7393
ADV7390/ ADV7391 24 Pin No. ADV7392/ ADV7393 30 ADV7390 WLCSP A1 Input/ Output I

Data Sheet

Mnemonic RSET

23

29

C2 B1

COMP DAC 1 DAC 1, DAC 2, DAC 3 SCL SDA ALSB RESET VAA VDD

O O O I I/O I I P P

22, 21, 20 12 11 10 14 19 5, 28

28, 27, 26 14 13 12 20 25 6, 35 F3 F2 E3 D3 C1 A3, D4

Description Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET to AGND. For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be connected from RSET to AGND. Compensation Pin. Connect a 2.2 nF capacitor from COMP to VAA. DAC Output. Full-drive and low-drive capable DAC DAC Outputs. Full-drive and low-drive capable DACs. I2C Clock Input. I2C Data Input/Output. ALSB sets up the LSB 2 of the MPU I2C address. Resets the on-chip timing generator and sets the ADV739x into its default mode. Analog Power Supply (2.7 V or 3.3 V). Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. Input/Output Digital Power Supply (1.8 V or 3.3 V). PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. External Loop Filter for the Internal PLL. PLL Ground Pin. Analog Ground Pin. Digital Ground Pin. Input/Output Supply Ground Pin. Connect to analog ground (AGND).

1 17

1 23

A5 E1

VDD_IO PVDD

P P

16 15 18 6, 29 32 External Pad
1 2

22 21 24 7, 36 40 External Pad

E2 F1 D1 C3, D5 D2

EXT_LF PGND AGND DGND GND_IO EPAD

I G G G G G

ED = enhanced definition = 525p and 625p. LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the ADV7391/ADV7393, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.

Rev. C | Page 20 of 108

Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0

ADV7390/ADV7391/ADV7392/ADV7393
Y RESPONSE IN ED 8× OVERSAMPLING MODE

1.0 0.5

–10 –20 GAIN (dB)
GAIN (dB)
06234-019

0 –0.5 –1.0 –1.5 –2.0 –2.5
06234-022

–30 –40 –50 –60 –70 –80

0

20

40

60

80 100 120 140 FREQUENCY (MHz)

160

180

200

–3.0

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response
ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20
GAIN (dB)

Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
10 0 –10 –20 –30 HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

GAIN (dB)
06234-020

–30 –40 –50 –60 –70 –80

–40 –50 –60 –70 –80 –90

0

20

40

60

80 100 120 140 FREQUENCY (MHz)

160

180

200

0

18.5

37.0

55.5 74.0 92.5 FREQUENCY (MHz)

111.0

129.5

148.0

Figure 22. ED 8× Oversampling, PrPb Filter (SSAF?) Response
Y RESPONSE IN ED 8× OVERSAMPLING MODE 0 –10 –20

Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE 0 –10 –20 –30

GAIN (dB)

GAIN (dB)

–30 –40 –50 –60 –70
06234-021

–40 –50 –60 –70 –80 –90

10 20 30 40 50 60 70 80 90 100 110 120 130 140 FREQUENCY (MHz)

Figure 23. ED 8× Oversampling, Y Filter Response

Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)

Rev. C | Page 21 of 108

06234-024

–80

0

20

40

60

80 100 120 140 FREQUENCY (MHz)

160

180

200

–100

06234-023

–100

ADV7390/ADV7391/ADV7392/ADV7393
10 0 –10 –20 –30
GAIN (dB) MAGNITUDE (dB)

Data Sheet
0 –10 –20 –30 –40 –50 –60 –70

Y RESPONSE IN HD 4× OVERSAMPLING MODE

–40 –50 –60 –70 –80 –90
06234-025

0

18.5

37.0

55.5 74.0 92.5 FREQUENCY (MHz)

111.0

129.5

148.0

0

2

4 6 8 FREQUENCY (MHz)

10

12

Figure 27. HD 4× Oversampling, Y Filter Response
3.0 1.5 0 –1.5
MAGNITUDE (dB)

Figure 30. SD PAL, Luma Low-Pass Filter Response

Y PASS BAND IN HD 4x OVERSAMPLING MODE
0 –10 –20 –30 –40 –50 –60

GAIN (dB)

–3.0 –4.5 –6.0 –7.5 –9.0

–10.5
06234-026

0

2

FREQUENCY (MHz)

4 6 8 FREQUENCY (MHz)

10

12

Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)

Figure 31. SD NTSC, Luma Notch Filter Response

0 –10 –20 –30 –40 –50 –60 –70

0 –10 –20 –30 –40 –50 –60 –70

MAGNITUDE (dB)

MAGNITUDE (dB)

06234-027

0

2

4 6 8 FREQUENCY (MHz)

10

12

0

2

4 6 8 FREQUENCY (MHz)

10

12

Figure 29. SD NTSC, Luma Low-Pass Filter Response

Figure 32. SD PAL, Luma Notch Filter Response

Rev. C | Page 22 of 108

06234-030

06234-029

–12.0 27.750 30.063 32.375 34.688 37.000 39.312 41.625 43.937 46.250

–70

06234-028

–100

Data Sheet
Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20

ADV7390/ADV7391/ADV7392/ADV7393
5

4

GAIN (dB)

–30 –40 –50 –60

MAGNITUDE (dB)

3

2

1

0 –70
06234-031

0

20

40

60

80 100 120 140 FREQUENCY (MHz)

160

180

200

0

1

2

3 4 FREQUENCY (MHz)

5

6

7

Figure 33. SD 16× Oversampling, Y Filter Response
1 0 –10 –20 –30 –40 –50 –60 –70 –4 0

Figure 36. SD Luma SSAF Filter, Programmable Gain

MAGNITUDE (dB)

MAGNITUDE (dB)

–1

–2

–3

06234-032

0

2

4 6 8 FREQUENCY (MHz)

10

12

0

1

2

3 4 FREQUENCY (MHz)

5

6

7

Figure 34. SD Luma SSAF Filter Response up to 12 MHz

Figure 37. SD Luma SSAF Filter, Programmable Attenuation

4 2 0

0 –10 –20 –30 –40 –50 –60 –70

MAGNITUDE (dB)

–2 –4 –6 –8 –10
06234-033

0

1

2

3 4 FREQUENCY (MHz)

5

6

7

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 35. SD Luma SSAF Filter, Programmable Responses

Figure 38. SD Luma CIF Low-Pass Filter Response

Rev. C | Page 23 of 108

06234-036

–12

MAGNITUDE (dB)

06234-035

–5

06234-034

–80

–1

ADV7390/ADV7391/ADV7392/ADV7393
0 –10 –20 –30 –40 –50 –60 –70 0 –10 –20 –30 –40 –50 –60 –70

Data Sheet

MAGNITUDE (dB)

MAGNITUDE (dB)

0

2

4

06234-037

6 8 FREQUENCY (MHz)

10

12

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 39. SD Luma QCIF Low-Pass Filter Response

Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response

0 –10 –20 –30 –40 –50 –60 –70

0 –10 –20 –30 –40 –50 –60 –70

MAGNITUDE (dB)

MAGNITUDE (dB)

0

2

4

6 8 FREQUENCY (MHz)

10

12

06234-038

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response

Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response

0 –10 –20 –30 –40 –50 –60 –70

0 –10 –20 –30 –40 –50 –60
06234-039

MAGNITUDE (dB)

MAGNITUDE (dB)

0

2

4

6 8 FREQUENCY (MHz)

10

12

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response

Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response

Rev. C | Page 24 of 108

06234-042

–70

06234-041

06234-040

Data Sheet
0 –10 –20 –30 –40 –50 –60
06234-043

ADV7390/ADV7391/ADV7392/ADV7393
0 –10 –20 –30 –40 –50 –60 –70

MAGNITUDE (dB)

0

2

4

6 8 FREQUENCY (MHz)

10

12

0

2

4

6 8 FREQUENCY (MHz)

10

12

Figure 45. SD Chroma CIF Low-Pass Filter Response

Figure 46. SD Chroma QCIF Low-Pass Filter Response

Rev. C | Page 25 of 108

06234-044

–70

MAGNITUDE (dB)

ADV7390/ADV7391/ADV7392/ADV7393 MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the ADV739x through a 2-wire serial (I2C-compatible) bus. After power-up or reset, the MPU port is configured for I2C operation.

Data Sheet
defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (7-bit address plus the R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition occurs when the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV739x acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should issue only a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV739x does not issue an acknowledge but returns to the idle condition. If the user uses the auto-increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: ? In read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition occurs when the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV739x, and the part returns to the idle condition.

I2C OPERATION
The ADV739x supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two wires, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV739x. The slave address depends on the device (ADV7390, ADV7391, ADV7392, or ADV7393), the operation (read or write), and the state of the ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The LSB sets either a read or a write operation. Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation. A1 is controlled by setting the ALSB pin of the ADV739x to Logic 0 or Logic 1. Table 16. ADV739x I2C Slave Addresses
Device ADV7390 and ADV7392 ADV7391 and ADV7393 ALSB 0 0 1 1 0 0 1 1 Operation Write Read Write Read Write Read Write Read Slave Address 0xD4 0xD5 0xD6 0xD7 0x54 0x55 0x56 0x57

1

1

0

1

0

1

A1

X

ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ
06234-045

Figure 47. ADV7390/ADV7392 I2C Slave Address

0

1

0

1

0

1

A1

X

ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ
06234-046

?

Figure 48. ADV7391/ADV7393 I2C Slave Address

Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read sequences.

The various devices on the bus use the following protocol. The master initiates a data transfer by establishing a start condition,

Rev. C | Page 26 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SDA

S 9 1–7 8 START ADDR R/W ACK

9 1–7 8 SUBADDRESS ACK

1–7 DATA

8

9 ACK

P STOP

Figure 49. I2C Data Transfer

WRITE SEQUENCE

S

SLAVE ADDR

A(S) LSB = 0

SUBADDR

A(S)

DATA

A(S) LSB = 1

DATA

A(S) P

READ SEQUENCE

S

SLAVE ADDR

A(S)

SUBADDR

A(S) S SLAVE ADDR

A(S)

DATA

A(M)

06234-047

SCL

DATA

A(M) P
06234-048

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 50. I2C Read and Write Sequence

Rev. C | Page 27 of 108

ADV7390/ADV7391/ADV7392/ADV7393 REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the ADV739x via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines the register accessed by the next read or write operation. All communication through the MPU port starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, incrementing to the next address until the transaction is complete. Table 17. Register 0x00
SR7 to SR0 0x00 Register Power mode Bit Description Sleep mode. With this control enabled, the current consumption is reduced to μA level. All DACs and the internal PLL circuit are disabled. Registers can be read from and written to in sleep mode. PLL and oversampling control. This control allows the internal PLL circuit to be powered down and the oversampling to be switched off. DAC 3: power on/off. DAC 2: power on/off. DAC 1: power on/off. Reserved. 0 0 0 0 1 0 1 0 1 7 6 Bit Number 5 4 3 2 1 0 0 1 0 1

Data Sheet
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the MPU port is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines which register performs the next operation.

Register Setting Sleep mode off Sleep mode on PLL on PLL off DAC 3 off DAC 3 on DAC 2 off DAC 2 on DAC 1 off DAC 1 on

Reset Value 0x12

Table 18. Register 0x01 to Register 0x09
SR7 to SR0 0x01 Register Mode select Bit Description Reserved. DDR clock edge alignment (used only for ED 2 and HD DDR modes) 7 6 Bit Number 1 5 4 3 2 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SD input. ED/HD-SDR input 3 . ED/HD-DDR input. Reserved. Reserved. Reserved. Reserved. ED (at 54 MHz) input. 1 0 1 0 1 0 0 Register Setting Chroma clocked in on rising clock edge and luma clocked in on falling clock edge. Reserved. Reserved. Luma clocked in on rising clock edge and chroma clocked in on falling clock edge. Reset Value 0x00

Reserved Input mode (see Subaddress 0x30, Bits[7:3] for ED/HD standard selection)

Reserved

Rev. C | Page 28 of 108

Data Sheet
SR7 to SR0 0x02 Register Mode Register 0 Bit Description Reserved HD interlace external VSYNC and HSYNC 7 6 Bit Number 1 5 4 3 2

ADV7390/ADV7391/ADV7392/ADV7393
1 0 1 0 0 Register Setting Zero must be written to this bit. Default. If using HD HSYNC/VSYNCinterlace mode, setting this bit to 1 is recommended (see the HD Interlace External HSYNC and VSYNC Considerations section for more information). Disabled. Enabled. Disable manual CSC matrix adjust. Enable manual CSC matrix adjust. No sync. Sync on all RGB outputs. RGB component outputs. YPrPb component outputs. No sync output. Output SD syncs on HSYNC and VSYNC pins. No sync output. Output ED/HD syncs on HSYNC and VSYNC pins. x x LSBs for GY. 0x03 Reset Value 0x20

Test pattern black bar 4 Manual CSC matrix adjust Sync on RGB RGB/YPrPb output select SD sync output enable ED/HD sync output enable 0 1 0 1 0 1 0 1 0 1

0 1

0x03

0x04

ED/HD CSC Matrix 0 ED/HD CSC Matrix 1 ED/HD CSC Matrix 2 ED/HD CSC Matrix 3 ED/HD CSC Matrix 4 ED/HD CSC Matrix 5 ED/HD CSC Matrix 6 x x x x

x x x x x x x x x x

x

0x05

x

LSBs for RV. LSBs for BU. LSBs for GV. LSBs for GU. Bits[9:2] for GY.

0xF0

0x4E

0x06

x

x

x

x

x

x

x

x

Bits[9:2] for GU.

0x0E

0x07

x

x

x

x

x

x

x

x

Bits[9:2] for GV.

0x24

0x08

x

x

x

x

x

x

x

x

Bits[9:2] for BU.

0x92

0x09

x

x

x

x

x

x

x

x

Bits[9:2] for RV.

0x7C

1 2

x = Logic 0 or Logic 1. ED = enhanced definition = 525p and 625p. 3 Available on the ADV7392/ADV7393 (40-pin devices) only. 4 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).

Rev. C | Page 29 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 19. Register 0x0B to Register 0x17
SR7 to SR0 0x0B Register DAC 1, DAC 2, DAC 3 output levels Bit Description Positive gain to DAC output voltage 7 0 0 0 … 0 0 1 1 1 … 1 6 0 0 0 … 0 1 1 1 0 … 1 Bit Number 1 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 … … … … 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 … … … … 1 1 1 1 1 0 0 1 … 1 0 0 0 1 … 1 0 0 1 0 … 1 0 0 1 0 … 1 0 1 DAC 2 low power mode 0 1 DAC 3 low power mode 0 1 SD/ED oversample rate select Reserved DAC 1 cable detect Read only DAC 2 cable detect Read only Reserved Unconnected DAC autopower-down 0 0 0 0 0 1 0 1 0 0 1 Reserved P[7:0] readback (ADV7390/ADV7391) P[15:8] readback (ADV7392/ADV7393) P[7:0] readback (ADV7392/ADV7393) Reserved VSYNC readback HSYNC readback SFL readback Reserved Reserved Software reset x x x 0 0 1 0 0 0 0 0 0 x x x x x x x x x x x x x Read only. Read only. 0 x 0 x 0 x 0 0 1

Data Sheet
Reset Value 0x00

Negative gain to DAC output voltage

0x0D

DAC power mode

DAC 1 low power mode

Register Setting 0%. +0.018%. +0.036%. … +7.382%. +7.5%. ?7.5%. ?7.382%. ?7.364%. … ?0.018%. DAC 1 low power disabled. DAC 1 low power enabled. DAC 2 low power disabled. DAC 2 low power enabled. DAC 3 low power disabled. DAC 3 low power enabled. SD = 16×, ED = 8×. SD = 8×, ED = 4×. Cable detected on DAC 1. DAC 1 unconnected. Cable detected on DAC 2. DAC 2 unconnected. DAC autopower-down disable. DAC autopower-down enable.

0x00

0x10

Cable detection

0x00

0x13

Pixel Port Readback A 2 Pixel Port Readback B2 Control port readback2

x

x

x

x

x

Read only.

0xXX

0x14 0x16

0xXX 0xXX

0x17

Software reset

0x00 Writing a 1 resets the device; this is a selfclearing bit.

Reserved.
1 2

x = Logic 0 or Logic 1. For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.

Rev. C | Page 30 of 108

Data Sheet
Table 20. Register 0x30
SR7 to SR0 0x30 Register ED/HD Mode Register 1 Bit Description ED/HD output standard 7 6 Bit Number 5 4 3 2

ADV7390/ADV7391/ADV7392/ADV7393
Reset Value 0x00

1 0 0 1 1

0 0 1 0 1

ED/HD input synchronization format

0 1

ED/HD standard 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Register Setting EIA-770.2 output EIA-770.3 output EIA-770.1 output Output levels for full input range Reserved External HSYNC, VSYNC and field inputs 1 Embedded EAV/SAV codes SMPTE 293M, ITU-BT.1358 Nonstandard timing mode BTA-1004, ITU-BT.1362 ITU-BT.1358 ITU-BT.1362 SMPTE 296M-1, SMPTE 274M-2 SMPTE 296M-3 SMPTE 296M-4, SMPTE 274M-5 SMPTE 296M-6 SMPTE 296M-7, SMPTE 296M-8 SMPTE 240M Reserved Reserved SMPTE 274M-4, SMPTE 274M-5 SMPTE 274M-6 SMPTE 274M-7, SMPTE 274M-8 SMPTE 274M-9 SMPTE 274M-10, SMPTE 274M-11 ITU-R BT.709-5 Reserved

Note ED HD

525p at 59.94 Hz 525p at 59.94 Hz 625p at 50 Hz 625p at 50 Hz 720p at 60 Hz/59.94 Hz 720p at 50 Hz 720p at 30 Hz/29.97 Hz 720p at 25 Hz 720p at 24 Hz/23.98 Hz 1035i at 60 Hz/59.94 Hz

0 0 1 0 10011 to 11111

1080i at 30 Hz/29.97 Hz 1080i at 25 Hz 1080p at 30 Hz/29.97 Hz 1080p at 25 Hz 1080p at 24 Hz/23.98 Hz 1080Psf at 24 Hz

1 2

Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6. See the HD Interlace External HSYNC and VSYNC Considerations section for more information.

Rev. C | Page 31 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 21. Register 0x31 to Register 0x33
SR7 to SR0 0x31 Register ED/HD Mode Register 2 Bit Description ED/HD pixel data valid HD oversample rate select ED/HD test pattern enable ED/HD test pattern hatch/field ED/HD vertical blanking interval (VBI) open ED/HD undershoot limiter 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 7 6 Bit Number 5 4 3 2 1 0 0 1

Data Sheet
Reset Value 0x00

0 1

ED/HD sharpness filter 0x32 ED/HD Mode Register 3 ED/HD Y delay with respect to the falling edge of HSYNC

ED/HD color delay with respect to the falling edge of HSYNC

ED/HD CGMS enable ED/HD CGMS CRC enable 0x33 ED/HD Mode Register 4 ED/HD Cr/Cb sequence Reserved ED/HD input format Sinc compensation filter on DAC 1, DAC 2, DAC 3 Reserved ED/HD chroma SSAF filter Reserved ED/HD double buffering

Register Setting Pixel data valid off. Pixel data valid on. 4×. 2×. HD test pattern off. HD test pattern on. Hatch. Field/frame. Disabled. Enabled. Disabled. ?11 IRE. ?6 IRE. ?1.5 IRE. Disabled. Enabled. 0 clock cycles. One clock cycle. Two clock cycles. Three clock cycles. Four clock cycles. 0 clock cycles. One clock cycle. Two clock cycles. Three clock cycles. Four clock cycles. Disabled. Enabled. Disabled. Enabled. Cb after falling edge of HSYNC. Cr after falling edge of HSYNC. 0 must be written to this bit. 8-bit input. 10-bit input 1 . Disabled. Enabled. 0 must be written to this bit. Disabled. Enabled. 1 must be written to this bit. Disabled. Enabled.

0x00

0x68

1

Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. C | Page 32 of 108

Data Sheet
Table 22. Register 0x34 to Register 0x38
SR7 to SR0 0x34 Register ED/HD Mode Register 5 Bit Description ED/HD timing reset ED/HD HSYNC control 2 ED/HD VSYNC control2 Reserved ED Macrovision? enable 3 Reserved ED/HD VSYNC input/field input ED/HD horizontal/vertical counter mode 4 0x35 ED/HD Mode Register 6 Reserved Reserved ED/HD sync on PrPb ED/HD color DAC swap ED/HD gamma correction curve select ED/HD gamma correction enable ED/HD adaptive filter mode ED/HD adaptive filter enable 0x36 0x37 0x38
1 2

ADV7390/ADV7391/ADV7392/ADV7393
Bit Number 1 5 4 3 2 Reset Value 0x48

7

6

1

0 0 1

Register Setting Internal ED/HD timing counters enabled. Resets the internal ED/HD timing counters.
HSYNC output control (see Table 56). VSYNC output control (see Table 57).

0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 x x x

ED Macrovision disabled. ED Macrovision enabled. 0 must be written to this bit. 0 = Field input. 1 = VSYNC input. Update field/line counter. Field/line counter free running. 0x00 Disabled. Enabled. DAC 2 = Pb, DAC 3 = Pr DAC 2 = Pr, DAC 3 = Pb. Gamma Correction Curve A. Gamma Correction Curve B. Disabled. Enabled. Mode A. Mode B. Disabled. Enabled. Y level value. Cr level value. Cb level value.

ED/HD Y level 5 ED/HD Cr level5 ED/HD Cb level5

ED/HD Test Pattern Y level ED/HD Test Pattern Cr level ED/HD Test Pattern Cb level

x x x

x x x

x x x

x x x

x x x

x x x

x x x

0xA0 0x80 0x80

x = Logic 0 or Logic 1. Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1. 3 Applies to the ADV7390 and ADV7392 only. 4 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 5 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).

Rev. C | Page 33 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 23. Register 0x39 to Register 0x43
SR7 to SR0 0x39 Register ED/HD Mode Register 7 Bit Description Reserved ED/HD EIA/CEA-861B synchronization compliance Reserved ED/HD sharpness filter gain Value A 7 6 5 0 1 0 0 0 0 … 0 1 … 1 0 0 … 0 1 … 1 0 C15 C7 0 0 … 1 0 … 1 0 C14 C6 0 0 … 1 0 … 1 0 C13 C5 0 1 … 1 0 … 1 0 C12 C4 0 0 … 1 0 … 1 0 0 … 1 0 … 0 1 … 1 0 … 1 Bit Number 4 3 2 0 0 0 1 0 0 0

Data Sheet
Reset Value 0x00

Register Setting Disabled Enabled Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = ?8 … Gain A = ?1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = ?8 … Gain B = ?1 CGMS C19 to C16 CGMS C15 to C8 CGMS C7 to C0

0x40

ED/HD sharpness filter gain

0x00

ED/HD sharpness filter gain Value B

0x41 0x42 0x43

ED/HD CGMS Data 0 ED/HD CGMS Data 1 ED/HD CGMS Data 2

ED/HD CGMS data bits ED/HD CGMS data bits ED/HD CGMS data bits

C19 C11 C3

C18 C10 C2

C17 C9 C1

C16 C8 C0

0x00 0x00 0x00

Table 24. Register 0x44 to Register 0x57
SR7 to SR0 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57
1

Register ED/HD Gamma A0 ED/HD Gamma A1 ED/HD Gamma A2 ED/HD Gamma A3 ED/HD Gamma A4 ED/HD Gamma A5 ED/HD Gamma A6 ED/HD Gamma A7 ED/HD Gamma A8 ED/HD Gamma A9 ED/HD Gamma B0 ED/HD Gamma B1 ED/HD Gamma B2 ED/HD Gamma B3 ED/HD Gamma B4 ED/HD Gamma B5 ED/HD Gamma B6 ED/HD Gamma B7 ED/HD Gamma B8 ED/HD Gamma B9

Bit Description ED/HD Gamma Curve A (Point 24) ED/HD Gamma Curve A (Point 32) ED/HD Gamma Curve A (Point 48) ED/HD Gamma Curve A (Point 64) ED/HD Gamma Curve A (Point 80) ED/HD Gamma Curve A (Point 96) ED/HD Gamma Curve A (Point 128). ED/HD Gamma Curve A (Point 160) ED/HD Gamma Curve A (Point 192) ED/HD Gamma Curve A (Point 224) ED/HD Gamma Curve B (Point 24) ED/HD Gamma Curve B (Point 32) ED/HD Gamma Curve B (Point 48) ED/HD Gamma Curve B (Point 64) ED/HD Gamma Curve B (Point 80) ED/HD Gamma Curve B (Point 96) ED/HD Gamma Curve B (Point 128) ED/HD Gamma Curve B (Point 160) ED/HD Gamma Curve B (Point 192) ED/HD Gamma Curve B (Point 224)

7 x x x x x x x x x x x x x x x x x x x x

6 x x x x x x x x x x x x x x x x x x x x

5 x x x x x x x x x x x x x x x x x x x x

Bit Number 1 4 3 2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

1 x x x x x x x x x x x x x x x x x x x x

0 x x x x x x x x x x x x x x x x x x x x

Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9

Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

x = Logic 0 or Logic 1.

Rev. C | Page 34 of 108

Data Sheet
Table 25. Register 0x58 to Register 0x5D
SR7 to SR0 0x58 Register ED/HD Adaptive Filter Gain 1 Bit Description ED/HD Adaptive Filter Gain 1, Value A

ADV7390/ADV7391/ADV7392/ADV7393
Bit Number 1 5 4 3 2 0 0 0 0 … … 0 1 1 0 … … 1 1 0 0 0 1 … … 1 1 0 0 … … 1 1 0 0 0 0 … … 0 1 1 0 … … 1 1 0 0 0 1 … … 1 1 0 0 … … 1 1 0 0 0 0 … … 0 1 1 0 … … 1 1 0 0 0 1 … … 1 1 0 0 … … 1 1 x x x x x x x x x x x x Register Setting Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = ?8 … Gain A = ?1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = ?8 … Gain B = ?1 Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = ?8 … Gain A = ?1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = ?8 … Gain B = ?1 Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = ?8 … Gain A = ?1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = ?8 … Gain B = ?1 Threshold A Threshold B Threshold C Reset Value 0x00

7

6

1 0 0 … 1 0 … 1

0 0 1 … 1 0 … 1

ED/HD Adaptive Filter Gain 1, Value B

0 0 … 0 1 … 1

0 0 … 1 0 … 1

0x59

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 2, Value A

0 0 … 1 0 … 1

0 1 … 1 0 … 1

0x00

ED/HD Adaptive Filter Gain 2, Value B

0 0 … 0 1 … 1

0 0 … 1 0 … 1

0x5A

ED/HD Adaptive Filter Gain 3

ED/HD Adaptive Filter Gain 3, Value A

0 0 … 1 0 … 1

0 1 … 1 0 … 1

0x00

ED/HD Adaptive Filter Gain 3, Value B

0x5B 0x5C 0x5D
1

ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C

ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C

0 0 … 0 1 … 1 x x x

0 0 … 1 0 … 1 x x x

x x x

x x x

0x00 0x00 0x00

x = Logic 0 or Logic 1.

Rev. C | Page 35 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x5E to Register 0x6E
SR7 to SR0 0x5E Register ED/HD CGMS Type B Register 0 Bit Description ED/HD CGMS Type B enable ED/HD CGMS Type B CRC enable ED/HD CGMS Type B header bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data dits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits ED/HD CGMS Type B data bits H5 P7 P15 P23 P31 P39 P47 P55 P63 P71 P79 P87 P95 P103 P111 P119 P127 H4 P6 P14 P22 P30 P38 P46 P54 P62 P70 P78 P86 P94 P102 P110 P118 P126 H3 P5 P13 P21 P29 P37 P45 P53 P61 P69 P77 P85 P93 P101 P109 P117 P125 H2 P4 P12 P20 P28 P36 P44 P52 P60 P68 P76 P84 P92 P100 P108 P116 P124 H1 P3 P11 P19 P27 P35 P43 P51 P59 P67 P75 P83 P91 P99 P107 P115 P123 H0 P2 P10 P18 P26 P34 P42 P50 P58 P66 P74 P82 P90 P98 P106 P114 P122 P1 P9 P17 P25 P33 P41 P49 P57 P65 P73 P81 P89 P97 P105 P113 P121 P0 P8 P16 P24 P32 P40 P48 P56 P64 P72 P80 P88 P96 P104 P112 P120 7 6 5 Bit Number 4 3 2 1 0 0 1

Data Sheet
Register Setting Disabled Enabled Disabled Enabled H5 to H0 P7 to P0 P15 to P8 P23 to P16 P31 to P24 P39 to P32 P47 to P40 P55 to P48 P63 to P56 P71 to P64 P79 to P72 P87 to P80 P95 to P88 P103 to P96 P111 to P104 P119 to P112 P127 to P120 Reset Value 0x00

0 1

0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E

ED/HD CGMS Type B Register 1 ED/HD CGMS Type B Register 2 ED/HD CGMS Type B Register 3 ED/HD CGMS Type B Register 4 ED/HD CGMS Type B Register 5 ED/HD CGMS Type B Register 6 ED/HD CGMS Type B Register 7 ED/HD CGMS Type B Register 8 ED/HD CGMS Type B Register 9 ED/HD CGMS Type B Register 10 ED/HD CGMS Type B Register 11 ED/HD CGMS Type B Register 12 ED/HD CGMS Type B Register 13 ED/HD CGMS Type B Register 14 ED/HD CGMS Type B Register 15 ED/HD CGMS Type B Register 16

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

Rev. C | Page 36 of 108

Data Sheet
Table 27. Register 0x80 to Register 0x83
SR7 to SR0 0x80 Register SD Mode Register 1 Bit Description SD standard 7 6 Bit Number 5 4 3 2

ADV7390/ADV7391/ADV7392/ADV7393
Reset Value 0x10

1 0 0 1 1

0 0 1 0 1

SD luma filter

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

SD chroma filter

0x82

SD Mode Register 2

SD PrPb SSAF filter SD DAC Output 1 Reserved SD pedestal SD square pixel mode SD VCR FF/RW sync SD pixel data valid SD active video edge control 0 1 0 1 0 1 0 1 0 0 1 0 1

0 1

Register Setting NTSC PAL B, PAL D, PAL G, PAL H, PAL I PAL M PAL N LPF NTSC LPF PAL Notch NTSC Notch PAL Luma SSAF Luma CIF Luma QCIF Reserved 1.3 MHz 0.65 MHz 1.0 MHz 2.0 MHz Reserved Chroma CIF Chroma QCIF 3.0 MHz Disabled Enabled See Table 37

0x0B

0x83

SD Mode Register 3

SD pedestal YPrPb output SD Output Levels Y SD Output Levels PrPb 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1

0 1

SD vertical blanking interval (VBI) open SD closed captioning field control

Reserved

Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled No pedestal on YPrPb 7.5 IRE pedestal on YPrPb Y = 700 mV/300 mV Y = 714 mV/286 mV 700 mV p-p (PAL), 1000 mV p-p (NTSC) 700 mV p-p 1000 mV p-p 648 mV p-p Disabled Enabled Closed captioning disabled Closed captioning on odd field only Closed captioning on even field only Closed captioning on both fields Reserved

0x04

Rev. C | Page 37 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 28. Register 0x84 to Register 0x87
SR7 to SR0 0x84 Register SD Mode Register 4 Bit Description Reserved SD SFL/SCR/TR mode select 7 6 Bit Number 5 4 3 2 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 Reserved SD EIA/CEA-861B synchronization compliance Reserved SD horizontal/vertical counter mode 1 SD RGB color swap 2 0x87 SD Mode Register 6 SD luma and color scale control SD luma scale saturation SD hue adjust SD brightness SD luma SSAF gain SD input standard autodetection Reserved SD RGB input enable2 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 1 Disabled. Enabled. 0 1 0 1 1 0 1 0 1 0 0 Register Setting

Data Sheet
Reset Value 0x00

SD active video length SD chroma SD burst SD color bars SD luma/chroma swap 0x86 SD Mode Register 5 NTSC color subcarrier adjust (delay from the falling edge of output HSYNC pulse to the start of color burst)

Disabled. Subcarrier reset mode enabled. Timing reset mode enabled. SFL mode enabled. 720 pixels. 710 (NTSC), 702 (PAL). Chroma enabled. Chroma disabled. Enabled. Disabled. Disabled. Enabled. DAC 2 = luma, DAC 3 = chroma. DAC 2 = chroma, DAC 3 = luma. 5.17 μs. 5.31 μs. 5.59 μs (must be set for Macrovision compliance). Reserved.

0x02

Update field/line counter. Field/line counter free running. Normal. Color reversal enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. 0 must be written to this bit. SD YCrCb input. SD RGB input.

0x00

1

When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 2 Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. C | Page 38 of 108

Data Sheet
Table 29. Register 0x88 to Register 0x89
SR7 to SR0 0x88 Register SD Mode Register 7 Bit Description Reserved SD noninterlaced mode SD double buffering SD input format 7 6

ADV7390/ADV7391/ADV7392/ADV7393
Bit Number 5 4 3 2 Reset Value 0x00

1 0 1

0 0

Register Setting Disabled. Enabled. Disabled. Enabled. 8-bit YCbCr input. 16-bit YCbCr input. 1 10-bit YCbCr/16-bit SD RGB input.1 Reserved. Disabled. Enabled. Disabled. Enabled. Gamma Correction Curve A. Gamma Correction Curve B. Disabled. ?11 IRE. ?6 IRE. ?1.5 IRE. 0 must be written to this bit. Reserved. Disabled. 4 clock cycles. 8 clock cycles. Reserved. 0 must be written to these bits.

0 1 0 0 1 1 0 1 0 1

SD digital noise reduction SD gamma correction enable SD gamma correction curve select 0x89 SD Mode Register 8 SD undershoot limiter 0 1 0 1

0 1

0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1

0 1 0 1

0x00

Reserved Reserved SD chroma delay

Reserved
1

Available on the ADV7392/ADV7393 (40-pin devices) only.

Table 30. Register 0x8A to Register 0x98
SR7 to SR0 0x8A Register SD Timing Register 0 Bit Description SD slave/master mode SD timing mode 7 6 Bit Number 1 5 4 3 2 1 0 0 1 Register Setting Slave mode. Master mode. Mode 0. Mode 1. Mode 2. Mode 3. No delay. Two clock cycles. Four clock cycles. Six clock cycles. ?40 IRE. ?7.5 IRE. A low-high-low transition resets the internal SD timing counters. Reset Value 0x08

0 0 1 1 1 0 0 1 1 0 1 0 1 0 1

0 1 0 1

Reserved SD luma delay

SD minimum luma value SD timing reset

x

Rev. C | Page 39 of 108

ADV7390/ADV7391/ADV7392/ADV7393
SR7 to SR0 0x8B Register SD Timing Register 1 Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1. Bit Description SD HSYNC width 7 6 Bit Number 1 5 4 3 2 1 0 0 1 1 0 0 1 0 1

Data Sheet
Register Setting ta = one clock cycle. ta = four clock cycles. ta = 16 clock cycles. ta = 128 clock cycles. tb = 0 clock cycles. tb = four clock cycles. tb = eight clock cycles. tb = 18 clock cycles. tc = tb. tc = tb + 32 μs. One clock cycle. Four clock cycles. 16 clock cycles. 128 clock cycles. 0 clock cycles. One clock cycle. Two clock cycles. Three clock cycles. Subcarrier Frequency Bits[7:0]. Subcarrier Frequency Bits[15:8]. Subcarrier Frequency Bits[23:16]. Subcarrier Frequency Bits[31:24]. Subcarrier Phase Bits[9:2]. Extended Data Bits[7:0]. Extended Data Bits[15:8]. Data Bits[7:0]. Data Bits[15:8]. Setting any of these bits to 1 disables the pedestal on the line number indicated by the bit settings. Reset Value 0x00

SD HSYNC to VSYNC delay

0 0 1 1

0 1 0 1

SD HSYNC to VSYNC rising edge delay (Mode 1 only) SD VSYNC width (Mode 2 only)

X2 X2
0 0 1 1 0 0 1 1 x x x x x x x x x 17 25 17 25 0 1 0 1 x x x x x x x x x 16 24 16 24

0 1 0 1 0 1

SD HSYNC to pixel data adjust

0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98
1 2

SD FSC Register 0 3 SD FSC Register 13 SD FSC Register 23 SD FSC Register 33 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3

Subcarrier Frequency Bits[7:0] Subcarrier Frequency Bits[15:8] Subcarrier Frequency Bits[23:16] Subcarrier Frequency Bits[31:24] Subcarrier Phase Bits[9:2] Extended data on even fields Extended data on even fields Data on odd fields Data on odd fields Pedestal on odd fields Pedestal on odd fields Pedestal on even fields Pedestal on even fields

x x x x x x x x x 15 23 15 23

x x x x x x x x x 14 22 14 22

x x x x x x x x x 13 21 13 21

x x x x x x x x x 12 20 12 20

x x x x x x x x x 11 19 11 19

x x x x x x x x x 10 18 10 18

0x1F 0x7C 0xF0 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

x = Logic 0 or Logic 1. X = don’t care. 3 SD subcarrier frequency registers default to NTSC subcarrier frequency values.

Rev. C | Page 40 of 108

Data Sheet
Table 31. Register 0x99 to Register 0xA5
SR7 to SR0 0x99 Register SD CGMS/WSS 0 Bit Description SD CGMS data SD CGMS CRC SD CGMS on odd fields SD CGMS on even fields SD WSS 0x9A SD CGMS/WSS 1 SD CGMS/WSS data SD CGMS data SD CGMS/WSS data LSBs for SD Y scale value LSBs for SD Cb scale value LSBs for SD Cr scale value LSBs for SD FSC phase SD Y scale value SD Cb scale value SD Cr scale value SD hue adjust value SD brightness value SD blank WSS data SD luma SSAF gain/attenuation (only applicable if Subaddress 0x87, Bit 4 = 1) x x x x 0 1 x 0 1 7 6

ADV7390/ADV7391/ADV7392/ADV7393
Bit Number 1 5 4 3 2 x x 0 1 0 1 Reset Value 0x00

1 x

0 x

x

x

x

x

x

Register Setting CGMS Data Bits[C19:C16] Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bits[C13:C8] or WSS Data Bits[W13:W8] CGMS Data Bits[C15:C14] CGMS Data Bits[C7:C0] or WSS Data Bits[W7:W0] SD Y Scale Bits[1:0] SD Cb Scale Bits[1:0] SD Cr Scale Bits[1:0] Subcarrier Phase Bits[1:0] SD Y Scale Bits[9:2] SD Cb Scale Bits[9:2] SD Cr Scale Bits[9:2] SD Hue Adjust Bits[7:0] SD Brightness Bits[6:0] Disabled Enabled ?4 dB … 0 dB … +4 dB No gain +1/16 [?1/8] +2/16 [?2/8] +3/16 [?3/8] +4/16 [?4/8] +5/16 [?5/8] +6/16 [?6/8] +7/16 [?7/8] +8/16 [?1] No gain +1/16 [?1/8] +2/16 [?2/8] +3/16 [?3/8] +4/16 [?4/8] +5/16 [?5/8] +6/16 [?6/8] +7/16 [?7/8] +8/16 [?1]

0x00

0x9B 0x9C

SD CGMS/WSS 2 SD scale LSB

x

x

x

x

x x

x x

0x00 0x00

x x x x x x x 0 1 0 … 0 … 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x

x

0x9D 0x9E 0x9F 0xA0 0xA1

SD Y scale SD Cb scale SD Cr scale SD hue adjust SD brightness/WSS

x x x x x

x x x x x

x x x x x

0x00 0x00 0x00 0x00 0x00

0xA2

SD luma SSAF

0 … 1 … 1 0 0 0 0 1 1 1 1 0

0 … 1 … 0 0 0 1 1 0 0 1 1 0

0 … 0 … 0 0 1 0 1 0 1 0 1 0

0x00

0xA3

SD DNR 0

Reserved Coring gain border (in DNR mode, the values in brackets apply)

0x00

Coring gain data (in DNR mode, the values in brackets apply)

Rev. C | Page 41 of 108

ADV7390/ADV7391/ADV7392/ADV7393
SR7 to SR0 0xA4 Register SD DNR 1 Bit Description DNR threshold 7 6 Bit Number 1 5 4 3 2 0 0 0 0 0 0 0 0 … … … … 1 1 1 1 1 1 1 1 1 0 0 … 1 1 0 0 1 … 0 1

Data Sheet
Register Setting 0 1 … 62 63 Two pixels Four pixels Eight pixels 16 pixels Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset One pixel offset … 14 pixel offset 15 pixel offset Reset Value 0x00

Border area Block size 0xA5 SD DNR 2 DNR input select 0 1

0 1

0 0 0 1 0 1 0 0 … 1 1 0 0 … 1 1 0 0 … 1 1 0 1 … 0 1

0 1 1 0

1 0 1 0

0x00

DNR mode DNR block offset

1

x = Logic 0 or Logic 1.

Table 32. Register 0xA6 to Register 0xBB
SR7 to SR0 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA Register SD Gamma A0 SD Gamma A1 SD Gamma A2 SD Gamma A3 SD Gamma A4 SD Gamma A5 SD Gamma A6 SD Gamma A7 SD Gamma A8 SD Gamma A9 SD Gamma B0 SD Gamma B1 SD Gamma B2 SD Gamma B3 SD Gamma B4 SD Gamma B5 SD Gamma B6 SD Gamma B7 SD Gamma B8 SD Gamma B9 SD brightness detect Bit Description SD Gamma Curve A (Point 24) SD Gamma Curve A (Point 32) SD Gamma Curve A (Point 48) SD Gamma Curve A (Point 64) SD Gamma Curve A (Point 80) SD Gamma Curve A (Point 96) SD Gamma Curve A (Point 128) SD Gamma Curve A (Point 160) SD Gamma Curve A (Point 192) SD Gamma Curve A (Point 224) SD Gamma Curve B (Point 24) SD Gamma Curve B (Point 32) SD Gamma Curve B (Point 48) SD Gamma Curve B (Point 64) SD Gamma Curve B (Point 80) SD Gamma Curve B (Point 96) SD Gamma Curve B (Point 128) SD Gamma Curve B (Point 160) SD Gamma Curve B (Point 192) SD Gamma Curve B (Point 224) SD brightness value 7 x x x x x x x x x x x x x x x x x x x x x 6 x x x x x x x x x x x x x x x x x x x x x Bit Number 1 5 4 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 2 x x x x x x x x x x x x x x x x x x x x x 1 x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x x Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xXX

Rev. C | Page 42 of 108

Data Sheet
SR7 to SR0 0xBB Register Field count Bit Description Field count Reserved Encoder version code 7 6

ADV7390/ADV7391/ADV7392/ADV7393
Bit Number 1 5 4 3 2 x 0 0 0 1 x 0 x Register Setting Read only Reserved Read only; first encoder version 2 Read only; second encoder version Reset Value 0x0X

0 0

0 1

1 2

x = Logic 0 or Logic 1. See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version.

Table 33. Register 0xC9 to Register 0xCE
SR7 to SR0 0xC9 Register Teletext control Bit Description Teletext enable Teletext request mode Teletext input pin select 1 0xCA Teletext request control Reserved Teletext request falling edge position control 0 0 0 0 0 0 0 … 1 1 0 1 0 0 … 1 1 0 0 … 1 1 0 1 … 0 1 7 6 5 Bit Number 4 3 2 1 0 0 1 Register Setting Disabled. Enabled. Line request signal. Bit request signal. VSYNC. P0. Reserved. 0 clock cycles. One clock cycle. … 14 clock cycles. 15 clock cycles. 0 clock cycles. One clock cycle. … 14 clock cycles. 15 clock cycles. Setting any of these bits to 1 enables teletext on the line number indicated by the bit settings. Reset Value 0x00

0 1

0x00

Teletext request rising edge position control

0xCB 0xCC 0xCD 0xCE
1

TTX Line Enable 0 TTX Line Enable 1 TTX Line Enable 2 TTX Line Enable 3

Teletext on odd fields Teletext on odd fields Teletext on even fields Teletext on even fields

0 0 … 1 1 22 14 22 14

0 0 … 1 1 21 13 21 13

0 0 … 1 1 20 12 20 12

0 1 … 0 1 19 11 19 11

18 10 18 10

17 9 17 9

16 8 16 8

15 7 15 7

0x00 0x00 0x00 0x00

The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. C | Page 43 of 108

ADV7390/ADV7391/ADV7392/ADV7393
Table 34. Register 0xE0 to Register 0xF1
SR7 to SR0 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1
1 2

Data Sheet
Bit Number 1 4 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

Register Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision

2

Bit Description MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits MV control bits

7 x x x x x x x x x x x x x x x x x 0

6 x x x x x x x x x x x x x x x x x 0

5 x x x x x x x x x x x x x x x x x 0

2 x x x x x x x x x x x x x x x x x 0

1 x x x x x x x x x x x x x x x x x 0

0 x x x x x x x x x x x x x x x x x x

Register Setting

Bits[7:1] must be 0.

x = Logic 0 or Logic 1. Macrovision registers are available on the ADV7390 and the ADV7392 only.

Rev. C | Page 44 of 108

Data Sheet ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 default to standard definition (SD) mode on power-up. Table 35 provides an overview of all possible input configurations. Each input mode is described in detail in this section. Note that the WLCSP option is only configured to support SD as shown in Figure 51. Table 35. ADV7390/ADV7391 Input Configuration
Input Mode 000 SD 010 ED/HD-DDR 111 ED (at 54 MHz) P7 P6 P5 P4 P3 YCrCb YCrCb YCrCb P2 P1 P0

ADV7390/ADV7391/ADV7392/ADV7393
The CrCb pixel data is also input on Pin P7 to Pin P0 on the opposite edge of CLKIN. Pin P0 is the LSB. Whether the Y data is clocked in on the rising or falling edge of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52 and Figure 53).
CLKIN

P[7:0]

3FF

00

00

XY

Cb0

Y0

Cr0

Y1
06234-050

NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
CLKIN

STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported. The ITU-R BT.601/656 input standard is supported. The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
ADV7390/ ADV7391
2 MPEG2 DECODER 27MHz VSYNC, HSYNC CLKIN

P[7:0]

3FF

00

00

XY

Y0

Cb0

Y1

Cr0
06234-051

NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
MPEG2 DECODER YCrCb

ADV7390/ ADV7391
CLKIN

YCrCb INTERLACED TO PROGRESSIVE 2

8

P[7:0]

YCrCb

8

06234-049

P[7:0]

Figure 54. ED/HD-DDR Example Application

Figure 51. SD Example Application

ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit bus rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes are supported. External synchronization signals are not supported in this mode. The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
CLKIN
06234-053

ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
Enhanced definition (ED) or high definition (HD) YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit DDR bus. The clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported.

8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN. Pin P0 is the LSB.

P[7:0]

3FF

00

00

XY

Cb0

Y0

Cr0

06234-052

VSYNC, HSYNC

Y1

Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)

Rev. C | Page 45 of 108

ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 default to standard definition (SD) mode on power-up. Table 36 provides an overview of all possible input configurations. Each input mode is described in detail in this section.

Data Sheet
16-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8, with Pin P8 being the LSB. The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB. The pixel data is updated at half the rate of the clock, that is, at a rate of 13.5 MHz (see Figure 5).

STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
Standard definition YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus. A 27 MHz clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported in 8-bit and 10-bit modes.

16-Bit 4:4:4 RGB Mode Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on Pin P4 to Pin P0, the green pixel data is input on Pin P10 to Pin P5, and the blue pixel data is input on Pin P15 to Pin P11. The P0, P5, and P11 pins are the respective bus LSBs. The pixel data is updated at half the rate of the clock, that is, at a rate of 13.5 MHz (see Figure 6).
ADV7392/ ADV7393
2 MPEG2 DECODER 27MHz VSYNC, HSYNC CLKIN

8-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is input on Pin P15 to Pin P8, with Pin P8 being the LSB. The ITU-R BT.601/656 input standard is supported.

YCrCb

8/10

P[15:8]/P[15:6]

In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITUR BT.601/656 input standard is supported. Table 36. ADV7392/ADV7393 Input Configuration
Input Mode 1 000 SD 2 8-bit 10-bit 16-bit 3 16-bit3 ED/HD-SDR (16-bit) ED/HD-DDR 4 8-bit 10-bit ED (at 54 MHz) 8-bit 10-bit
1 2

Figure 56. SD Example Application

P15

P14

P13

P12

P11

P10 P9 P8 P7 P6 P5 SD RGB input enable (0x87[7]) = 0

P4

P3

P2

06234-054

10-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bits[4:3] = 10

P1

P0

YCrCb YCrCb Y B Y ED/HD input format (0x33[2]) = 0 YCrCb ED/HD input format (0x33[2]) = 1 YCrCb ED/HD input format (0x33[2]) = 0 YCrCb ED/HD input format (0x33[2]) = 1 YCrCb SD RGB input enable (0x87[7]) = 1 G CrCb CrCb R

001 010

111

The input mode is determined by Subaddress 0x01, Bits[6:4]. In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3]. 3 External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported. 4 ED = enhanced definition = 525p and 625p. Rev. C | Page 46 of 108

Data Sheet
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an 8-/10-bit DDR bus or a 16-bit SDR bus. The clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported.

ADV7390/ADV7391/ADV7392/ADV7393
MPEG2 DECODER
YCrCb

ADV7392/ ADV7393
CLKIN

CrCb 8 INTERLACED TO PROGRESSIVE Y 8 2

P[7:0] P[15:8]
06234-057

VSYNC HSYNC

16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8, with P8 being the LSB. The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.

Figure 59. ED/HD-SDR Example Application

MPEG2 DECODER YCrCb

ADV7392/ ADV7393
CLKIN

8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8/P6 on either the rising or falling edge of CLKIN. Pin P8/P6 is the LSB. The CrCb pixel data is also input on Pin P15 to Pin P8/P6 on the opposite edge of CLKIN. P8/P6 is the LSB. The 10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether the Y data is clocked in on the rising or falling edge of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57 and Figure 58).

YCrCb 8/10 INTERLACED TO PROGRESSIVE 2

P[15:8]/P[15:6]

Figure 60. ED/HD-DDR Example Application

ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes are supported. External synchronization signals are not supported in this mode.

CLKIN P[15:8]/ P]15:6]

3FF

00

00

XY

Cb0

Y0

Cr0

Y1

06234-055

NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE. 2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

The interleaved pixel data is input on Pin P15 to Pin P8/P6, with Pin P8/P6 being the LSB. The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
CLKIN

Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

CLKIN P[15:8]/ P[15:P6]

P[15:8]/P[15:6]

3FF

00

00

XY

Cb0

Y0

Cr0

06234-058

VSYNC HSYNC

Y1
06234-059

3FF

00

00

XY

Y0

Cb0

Y1

Cr0

NOTES 1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-056

NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE. 2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2 DECODER YCrCb 54MHz

Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

ADV7392/ ADV7393
CLKIN

YCrCb 8/10 INTERLACED TO PROGRESSIVE

P[15:8]/P[15:6]
06234-060

2

VSYNC, HSYNC

Figure 62. ED (at 54 MHz) Example Application

Rev. C | Page 47 of 108

ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION

Data Sheet

The ADV739x supports a number of different output configurations. Table 37 to Table 39 list all possible output configurations. Table 37. SD Output Configurations
RGB/YPrPb Output Select 1 (Subaddress 0x02, Bit 5) 0 1 1 1
1

SD DAC Output 1 (Subaddress 0x82, Bit 1) 0 0 1 1

SD Luma/Chroma Swap (Subaddress 0x84, Bit 7) 0 0 0 1

DAC 1 G Y CVBS CVBS

DAC 2 B Pb Luma Chroma

DAC 3 R Pr Chroma Luma

If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.

Table 38. ED/HD Output Configurations
RGB/YPrPb Output Select (Subaddress 0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (Subaddress 0x35, Bit 3) 0 1 0 1 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb

Table 39. ED (at 54 MHz) Output Configurations
RGB/YPrPb Output Select (Subaddress 0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (Subaddress 0x35, Bit 3) 0 1 0 1 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb

Rev. C | Page 48 of 108

Data Sheet DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV739x includes an on-chip phase-locked loop (PLL) that allows for oversampling of SD, ED, and HD video data. By default, the PLL is disabled. The PLL can be enabled using Subaddress 0x00, Bit 1 = 0. Table 40 shows the various oversampling rates supported in the ADV739x.

ADV7390/ADV7391/ADV7392/ADV7393
various output levels that can be generated. Table 41 lists the transitions required to generate the various output levels. Embedded EAV/SAV timing codes are not supported in ED/HD nonstandard timing mode. The user must ensure that appropriate pixel data is applied to the encoder where the blanking level is expected at the output. Macrovision (ADV7390/ADV7392 only) and output oversampling are not available in ED/HD nonstandard timing mode. The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in ED/HD nonstandard timing mode.
ANALOG OUTPUT a b c
06234-061

ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the standards listed in the ED/HD standard table (Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode can be used to interface to the ADV739x. ED/HD nonstandard timing mode can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001. A clock signal must be provided on the CLKIN pin. HSYNC and VSYNC must be toggled by the user to generate the appropriate horizontal and vertical synchronization pulses on the analog output from the encoder. Figure 63 illustrates the

b ACTIVE VIDEO

b BLANKING LEVEL

a = TRILEVEL SYNCHRONIZATION PULSE LEVEL. b = BLANKING LEVEL/ACTIVE VIDEO LEVEL. c = SYNCHRONIZATION PULSE LEVEL.

Figure 63. ED/HD Nonstandard Timing Mode Output Levels

Table 40. Output Oversampling Modes and Rates
Input Mode (0x01, Bits[6:4]) 000 SD 000 SD 000 SD 001/010 ED 001/010 ED 001/010 ED 001/010 HD 001/010 HD 001/010 HD 111 ED (at 54 MHz) 111 ED (at 54 MHz) 111 ED (at 54 MHz)
1

PLL and Oversampling Control (0x00, Bit 1) 1 0 0 1 0 0 1 0 0 1 0 0

SD/ED Oversample Rate Select (0x0D, Bit 3)1 X 1 0 X 1 0 X X X X 1 0

HD Oversample Rate Select (0x31, Bit 1)1 X X X X X X X 1 0 X X X

Oversampling Mode and Rate SD (2×) SD (8×) SD (16×) ED (1×) ED (4×) ED (8×) HD (1×) HD (2×) HD (4×) ED (at 54 MHz) (1×) ED (at 54 MHz) (4×) ED (at 54 MHz) (8×)

X = don’t care

Table 41. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition 1 b to c c to a a to b c to b
1 2

HSYNC 1 to 0 0 0 to 1 0 to 1

VSYNC 1 to 0 or 0 2 0 to 1 1 0

a = trilevel synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 63. If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If trilevel synchronization pulse generation is not required, VSYNC should always be 0.

Rev. C | Page 49 of 108

ADV7390/ADV7391/ADV7392/ADV7393
HD INTERLACE EXTERNAL HSYNC AND VSYNC CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01 or higher, the user should set Subaddress 0x02, Bit 1 to high. To ensure exactly correct timing in HD interlace modes when using HSYNC and VSYNC synchronization signals. If this bit is set to low, the first active pixel on each line is masked in HD interlace modes and the Pr and Pb outputs are swapped when using the YCrCb 4:2:2 input format. Setting Subaddress 0x02, Bit 1 to low causes the encoder to behave in the same way as the first version of silicon (that is, this setting is backward compatible). If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00, the setting of Subaddress 0x02, Bit 1 has no effect. In this version of the encoder, the first active pixel is masked and the Pr and Pb outputs are swapped when using YCrCb 4:2:2 input format. To avoid these limitations, use the newer revision of silicon or use a different type of synchronization. These considerations apply only to the HD interlace modes with external HSYNC and VSYNC synchronization (EAV/SAV mode is not affected and always has exactly correct timing). There is no negative effect in setting Subaddress 0x02, Bit 0 to high, and this bit can remain high for all the other video standards.

Data Sheet
Timing Reset (TR) Mode
In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is achieved in a low-to-high transition on the SFL pin. In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal may not be recognized. This timing reset applies to the SD timing counters only.

Subcarrier Phase Reset (SCR) Mode
In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high transition on the SFL pin resets the subcarrier phase to 0 on the field following the subcarrier phase reset. This reset signal must be held high for a minimum of one clock cycle. Because the field counter is not reset, it is recommended to apply the reset signal in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase then occurs on the next field, that is, Field 1, which is lined up correctly with the internal counters. The field count register at Subaddress 0xBB can be used to identify the number of the active field.

Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84, Bits[2:1] = 11), the ADV739x can be used to lock to an external video source. The SFL mode allows the ADV739x to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device such as an ADV7403 video decoder that outputs a digital data stream in the SFL format, the part automatically changes to the compensated subcarrier frequency on a line-by-line basis (see Figure 66). This digital data stream is 67 bits wide, and the subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long.

ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. This timing reset applies to the ED/HD timing counters only.

SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Together with the SFL pin and SD mode Register 4 (Subaddress 0x84, Bits[2:1]), the ADV739x can be used in timing reset mode, subcarrier phase reset mode, or SFL mode.
DISPLAY

START OF FIELD 4 OR 8

FSC PHASE = FIELD 4 OR 8

307

310

313

320

NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 FSC PHASE = FIELD 1

307

1

2

3

4

5

6

7

21

TIMING RESET PULSE TIMING RESET APPLIED

Figure 64. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 10)
Rev. C | Page 50 of 108

06234-062

Data Sheet
DISPLAY START OF FIELD 4 OR 8

ADV7390/ADV7391/ADV7392/ADV7393
FSC PHASE = FIELD 4 OR 8

307 NO FSC RESET APPLIED

310

313

320

DISPLAY

START OF FIELD 4 OR 8

FSC PHASE = FIELD 1

307

310

313

320

FSC RESET APPLIED

Figure 65. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)

ADV739x
CLKIN DAC 1

LLC1 COMPOSITE VIDEO1

SFL
P10

SFL

DAC 2 DAC 3

ADV7403 P19 TO
VIDEO DECODER PIXEL PORT5 4 BITS RESERVED

H/L TRANSITION COUNT START 128 RTC

14 BITS SUBCARRIER LOW PHASE 13 0

SEQUENCE BIT3

RESET BIT4 RESERVED

21

FSC PLL INCREMENT2

0

TIME SLOT 01

14

19 VALID SAMPLE INVALID SAMPLE 8/LINE LOCKED CLOCK

6768 5 BITS RESERVED

1FOR EXAMPLE, VCR OR CABLE. 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx FSC DDS REGISTER IS FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS. 3SEQUENCE BIT

4RESET ADV739x DDS. 5REFER TO THE ADV7390/ADV7391

AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS.

Figure 66. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)

SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached. In rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. Conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field. When the VCR FF/RW sync control is enabled (Subaddress 0x82, Bit 5), the line/field counters are updated according to the incoming VSYNC signal and when the analog output matches

the incoming VSYNC signal. This control is available in all slave-timing modes except Slave Mode 0.

VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical blanking interval (VBI) data (such as CGMS, WSS, VITS) in SD, ED, and HD modes. If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress 0x83, Bit 4 for SD), VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave timing modes. For the SMPTE 293M (525p) standard, VBI data can be inserted on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for the ITU-R BT.1358 (625p) standard. VBI data can be present on Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.

Rev. C | Page 51 of 108

06234-064

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE

06234-063

FSC RESET PULSE

ADV7390/ADV7391/ADV7392/ADV7393
In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is disabled, the CGMS data is, nevertheless, available at the output. Table 42. Typical FSC Values
Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 NTSC 0x1F 0x7C 0xF0 0x21

Data Sheet
PAL B/D/G/H/I 0xCB 0x8A 0x09 0x2A

SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
The ADV739x is able to generate the color subcarrier used in CVBS and S-Video (Y-C) outputs from the input pixel clock. Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the following equation:

SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV739x supports an SD noninterlaced mode. Using this mode, progressive inputs at twice the frame rate of NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input into the ADV739x. The SD noninterlaced mode can be enabled using Subaddress 0x88, Bit 1. A 27 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes or external horizontal and vertical synchronization signals provided on the HSYNC and VSYNC pins can be used to synchronize the input pixel data. All input configurations, output configurations, and features available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV739x should be configured for NTSC operation and Subaddress 0x88, Bit 1 should be set to 1. For 288p/50 Hz input, the ADV739x should be configured for PAL operation and Subaddress 0x88, Bit 1 should be set to 1.

Subcarrier Frequency Register = Number of subcarrier periods in one video line Number of 27 MHz clock cycles in one video line where the sum is rounded to the nearest integer. For example, in NTSC mode: 227.5 ? 32 Subcarrier Register Value = ? ? ? × 2 = 569408543 ? 1716 ? where: Subcarrier Register Value = 569408543d = 0×21F07C1F SD FSC Register 0: 0x1F SD FSC Register 1: 0x7C SD FSC Register 2: 0xF0 SD FSC Register 3: 0x21 × 2 32

SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV739x supports an SD square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. The active resolution is 640 × 480. For PAL operation, an input clock of 29.5 MHz is required. The active resolution is 768 × 576. For CVBS and S-Video (Y-C) outputs, the SD subcarrier frequency registers must be updated to reflect the input clock frequency used in SD square pixel mode. The SD input standard autodetection feature must be disabled in SD square pixel mode. In square pixel mode, the timing diagrams shown in Figure 67 and Figure 68 apply.

Programming the FSC
The subcarrier frequency register value is divided into four FSC registers as shown in the previous example. The four subcarrier frequency registers must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency updates only after the last subcarrier frequency register byte is received by the ADV739x. The SD input standard autodetection feature must be disabled.

Typical FSC Values
Table 42 outlines the values that should be written to the subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

Rev. C | Page 52 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ANALOG VIDEO

EAV CODE INPUT PIXELS C F 0 0 X 8 1 8 1 Y Y r F 0 0 Y 0 0 0 0 4 CLOCK 4 CLOCK END OF ACTIVE VIDEO LINE 0 F F A A A 0 F F B B B ANCILLARY DATA (HANC) 272 CLOCK 344 CLOCK

SAV CODE 8 1 8 1 F 0 0 X C Y C Y C Y C Y C b r b 0 0 0 0 F 0 0 Y b r 4 CLOCK 4 CLOCK START OF ACTIVE VIDEO LINE
06234-065

NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz)

1280 CLOCK 1536 CLOCK

Figure 67. Square Pixel Mode EAV/SAV Embedded Timing

HSYNC

FIELD

PIXEL DATA

Cb

Y

Cr

Y

PAL = 308 CLOCK CYCLES NTSC = 236 CLOCK CYCLES

Figure 68. Square Pixel Mode Active Pixel Timing

Rev. C | Page 53 of 108

06234-066

ADV7390/ADV7391/ADV7392/ADV7393
FILTERS
Table 43 shows an overview of the programmable filters available on the ADV739x.
Table 43. Selectable Filters
Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD PrPb SSAF ED/HD Sinc Compensation Filter ED/HD Chroma SSAF Subaddress 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x82 0x33 0x33
GAIN (dB)

Data Sheet
EXTENDED (SSAF) PrPb FILTER MODE 0

–10

–20

–30

–40

–50

0

1

2

3 4 FREQUENCY (MHz)

5

6

Figure 69. PrPb SSAF Filter

If this filter is disabled, one of the chroma filters shown in Table 44 can be selected and used for the CVBS or luma/ chroma signal.
Table 44. Internal Filter Specifications
Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF
1

SD Internal Filter Response Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The PrPb filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 38 and Figure 39. If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13 response options in the range ?4 dB to +4 dB. The desired response can be programmed using Subaddress 0xA2. Variation in frequency responses is shown in Figure 35 to Figure 37. In addition to the chroma filters listed in Table 43, the ADV739x contains an SSAF filter that is specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see Figure 69). This filter can be controlled with Bit 0 of Subaddress 0x82, Bit 0.

Pass-Band Ripple (dB)1 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic

3 dB Bandwidth (MHz)2 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5

Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in decibels. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the ?3 dB points. 2 3 dB bandwidth refers to the ?3 dB cutoff frequency.

Rev. C | Page 54 of 108

06234-067

–60

Data Sheet
ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3
The ADV739x includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 70 and Figure 71.
0.5 0.4 0.3 0.2

ADV7390/ADV7391/ADV7392/ADV7393
Table 45 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).
Table 45. Sample Color Values for EIA770.2/EIA770.3 ED/HD Output Standard Selection
Sample Color White Black Red Green Blue Yellow Cyan Magenta Y Value 235 (0xEB) 16 (0x10) 81 (0x51) 145 (0x91) 41 (0x29) 210 (0xD2) 170 (0xAA) 106 (0x6A) Cr Value 128 (0x80) 128 (0x80) 240 (0xF0) 34 (0x22) 110 (0x6E) 146 (0x92) 16 (0x10) 222 (0xDE) Cb Value 128 (0x80) 128 (0x80) 90 (0x5A) 54 (0x36) 240 (0xF0) 16 (0x10) 166 (0xA6) 202 (0xCA)

GAIN (dB)

0.1 0 –0.1 –0.2 –0.3 –0.4 0 5 10 15 20 FREQUENCY (MHz) 25 30
06234-068

COLOR SPACE CONVERSION MATRIX
Subaddress 0x03 to Subaddress 0x09
The internal color space conversion (CSC) matrix automatically performs all color space conversions based on the input mode programmed in the mode select register (Subaddress 0x01, Bits[6:4]). Table 46 and Table 47 show the options available in this matrix. An SD color space conversion from RGB-in to YPrPb-out is possible on the ADV7392/ADV7393. An ED/HD color space conversion from RGB-in to YPrPb-out is not possible.
Table 46. SD Color Space Conversion Options
YPrPb/RGB Out (Subaddress 0x02, Bit 5) 1 0 1 0 RGB In/YCrCb In (Subaddress 0x87, Bit 7) 0 0 1 1

–0.5

Figure 70. ED/HD Sinc Compensation Filter Enabled
0.5 0.4 0.3 0.2

GAIN (dB)

0.1 0 –0.1 –0.2 –0.3 –0.4
06234-069

Input YCrCb YCrCb RGB2 RGB2
0 5 10 15 20 FREQUENCY (MHz) 25 30
1 2

Output1 YPrPb RGB YPrPb RGB

–0.5

CVBS/Y-C outputs are available for all CSC combinations. Available on the ADV7392/ADV7393 (40-pin devices) only.

Figure 71. ED/HD Sinc Compensation Filter Disabled

Table 47. ED/HD Color Space Conversion Options
Input YCrCb YCrCb Output YPrPb RGB YPrPb/RGB Out (Subaddress 0x02, Bit 5) 1 0

ED/HD TEST PATTERN COLOR CONTROLS
Subaddress 0x36 to Subaddress 0x38
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38 are used to program the output color of the internal ED/HD test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it be the lines of the crosshatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. The values for the luma (Y) and color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard.

SD Manual CSC Matrix Adjust Feature
The SD manual CSC matrix adjust feature (available for the ADV7392 and ADV7393 only) provides custom coefficient manipulation for RGB to YPbPr conversion (for YPbPr to RGB conversion, this matrix adjustment is not available). Normally, there is no need to modify the SD matrix coefficients because the CSC matrix automatically performs the color space conversion based on the output color space selected (see Table 47). Note that Bit 7 in subaddress 0x87 must be set to enable RGB input and, therefore, use the CSC manual adjustment.

Rev. C | Page 55 of 108

ADV7390/ADV7391/ADV7392/ADV7393
The SD CSC matrix scalar uses the following equations:
Y = (a1 × R) + (a2 × G) + (a3 × B) + a4 Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4 Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4

Data Sheet
On power-up, the CSC matrix is programmed with the default values shown in Table 49.
Table 49. ED/HD Manual CSC Matrix Default Values
Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Default 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C

The coefficients and their default values are located in the registers shown in Table 48.
Table 48. SD Manual CSC Matrix Default Values
Coefficient a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 Subaddress 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 Default 0x42 0x81 0x19 0x10 0x70 0x5E 0x12 0x80 0x26 0x4A 0x70 0x80

When the ED/HD manual CSC matrix adjust feature is enabled, the default coefficient values in Subaddress 0x03 to Subaddress 0x09 are correct for the HD color space only. The color components are converted according to the following 1080i and 720p standards (SMPTE 274M, SMPTE 296M):
R = Y + 1.575Pr G = Y ? 0.468Pr ? 0.187Pb B = Y + 1.855Pb

ED/HD Manual CSC Matrix Adjust Feature
The ED/HD manual CSC matrix adjust feature provides custom coefficient manipulation for color space conversions and is used in ED and HD modes only. The ED/HD manual CSC matrix adjust feature can be enabled using Subaddress 0x02, Bit 3. Normally, there is no need to enable this feature because the CSC matrix automatically performs the color space conversion based on the input mode chosen (ED or HD) and the output color space selected (see Table 47). For this reason, the ED/HD manual CSC matrix adjust feature is disabled by default. If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations:
R = GY × Y + RV × Pr G = GY × Y ? (GU × Pb) ? (GV × Pr) B = GY × Y + BU × Pb

The conversion coefficients should be multiplied by 315 before being written to the ED/HD CSC matrix registers. This is reflected in the default values for GY = 0x13B, GU = 0x03B, GV = 0x093, BU = 0x248, and RV = 0x1F0. If the ED/HD manual CSC matrix adjust feature is enabled and another input standard (such as ED) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion may use different scale values. For example, SMPTE 293M uses the following conversion:
R = Y + 1.402Pr G = Y ? 0.714Pr ? 0.344Pb B = Y + 1.773Pb

The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled.

Note that subtractions are implemented in the hardware. If YPrPb output is selected, the following equations are used:
Y = GY × Y Pr = RV × Pr Pb = BU × Pb

Programming the CSC Matrix
If custom manipulation of the ED/HD CSC matrix coefficients is required for a YCrCb-to-RGB color space conversion, use the following procedure: 1. 2. 3. 4. Enable the ED/HD manual CSC matrix adjust feature (Subaddress 0x02, Bit 3). Set the output to RGB (Subaddress 0x02, Bit 5). Disable sync on PrPb (Subaddress 0x35, Bit 2). Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).

where: GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0]. GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6]. GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4]. BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2]. RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].

The GY value controls the green signal output level, the BU value controls the blue signal output level, and the RV value controls the red signal output level.

Rev. C | Page 56 of 108

Data Sheet
SD LUMA AND COLOR SCALE CONTROL
Subaddress 0x9C to Subaddress 0x9F
When enabled, the SD luma and color scale control feature can be used to scale the SD Y, Cb, and Cr output levels. This feature can be enabled using Subaddress 0x87, Bit 0. This feature affects all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB. When enabled, three 10-bit registers (SD Y scale, SD Cb scale, and SD Cr scale) control the scaling of the SD Y, Cb, and Cr output levels. The SD Y scale register contains the scaling factor used to scale the Y level from 0.0 to 1.5 times its initial level. The SD Cb scale and SD Cr scale registers contain the scaling factors to scale the Cb and Cr levels from 0.0 to 2.0 times their initial levels, respectively. The values to be written to these 10-bit registers are calculated using the following equation:
Y, Cb, or Cr Scale Value = Scale Factor × 512

ADV7390/ADV7391/ADV7392/ADV7393
For example, to adjust the hue by +4°, write 0x97 to the hue adjust control register.
4 ? ? ? 0.17578125 ? + 128 ≈ 151d = 0 x 97 ? ?

where the sum is rounded to the nearest integer. To adjust the hue by ?4°, write 0x69 to the hue adjust control register.
?4 ? ? + 128 ≈ 105d = 0 x 69 ? ? ? 0.17578125 ?

where the sum is rounded to the nearest integer.

SD BRIGHTNESS DETECT
Subaddress 0xBA
The ADV739x allows monitoring of the brightness level of the incoming video data. This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis. The information is read from the I2C and, based on this information, the color saturation, contrast, and brightness controls can be adjusted (for example, to compensate for very dark pictures). The luma data is monitored in the active video area only. The average brightness I2C register is updated on the falling edge of every VSYNC signal. The SD brightness detect register (Subaddress 0xBA) is a read-only register.

For example, if Scale Factor = 1.3
Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6 Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010011010b

Subaddress 0x9C, SD scale LSB = 0x2A Subaddress 0x9D, SD Y scale register = 0xA6 Subaddress 0x9E, SD Cb scale register = 0xA6 Subaddress 0x9F, SD Cr scale register = 0xA6 It is recommended that the SD luma scale saturation feature (Subaddress 0x87, Bit 1) be enabled when scaling the Y output level to avoid excessive Y output levels.

SD BRIGHTNESS CONTROL
Subaddress 0xA1, Bits[6:0]
When this feature is enabled, the SD brightness/WSS control register (Subaddress 0xA1) is used to control brightness by adding a programmable setup level onto the scaled Y data. This feature can be enabled using Subaddress 0x87, Bit 3. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal (see Figure 72) and for PAL, the setup can vary from ?7.5 IRE to +15 IRE.
NTSC WITHOUT PEDESTAL 100 IRE +7.5 IRE

SD HUE ADJUST CONTROL
Subaddress 0xA0
When enabled, the SD hue adjust control register (Subaddress 0xA0) is used to adjust the hue on the SD composite and chroma outputs. This feature can be enabled using Subaddress 0x87, Bit 2. Subaddress 0xA0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV739x provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Value 0xFF and Value 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode. Value 0xFF and Value 0x01 represent the upper and lower limits, respectively, of the attainable adjustment in PAL mode. The hue adjust value is calculated using the following equation:
Hue Adjust (°) = 0.17578125° (HCRd ? 128)

0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED

–7.5 IRE
06234-070

Figure 72. Examples of Brightness Control Values

The SD brightness control register is an 8-bit register. The seven LSBs of this 8-bit register are used to control the brightness level, which can be a positive or negative value. For example, to add a +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Subaddress 0xA1. 0 × (SD Brightness Value) = 0 × (IRE Value × 2.015631) = 0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28

Where HCRd = the hue adjust control register (decimal).

Rev. C | Page 57 of 108

ADV7390/ADV7391/ADV7392/ADV7393
To add a –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × (SD Brightness Value) = 0 × (IRE Value × 2.075631) = 0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b 0001110b into twos complement = 1110010b = 0x72
Table 50. Sample Brightness Control Values1
Setup Level (NTSC) with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE
1

Data Sheet
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 73. DAC 1 to DAC 3 are controlled by Register 0x0B. In Case A of Figure 73, the video output signal is gained. The absolute level of the sync tip and the blanking level increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal. In Case B of Figure 73, the video output signal is reduced. The absolute level of the sync tip and the blanking level decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal.
CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0B 700mV

Setup Level (NTSC) Without Pedestal 15 IRE 7.5 IRE 0 IRE ?7.5 IRE

Setup Level (PAL) 15 IRE 7.5 IRE 0 IRE ?7.5 IRE

Brightness Control Value 0x1E 0x0F 0x00 0x71

Values in the range of 0x3F to 0x44 may result in an invalid output signal.

SD INPUT STANDARD AUTODETECTION
Subaddress 0x87, Bit 5
The ADV739x includes an SD input standard autodetect feature that can be enabled by setting Subaddress 0x87, Bits[5:1]. When enabled, the ADV739x can automatically identify an NTSC or a PAL B/D/G/H/I input stream. The ADV739x automatically updates the subcarrier frequency registers with the appropriate value for the identified standard. The ADV739x is also configured to correctly encode the identified standard. The SD standard bits (Subaddress 0x80, Bits[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard. All registers retain their default or userdefined values.

300mV

CASE B 700mV

NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0B

DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD; Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not be made during active video but take effect prior to the start of the active video on the next field. Using Subaddress 0x33, Bit 7, double buffering can be activated on the following ED/HD registers: the ED/HD Gamma A and Gamma B curves and ED/HD CGMS registers. Using Subaddress 0x88, Bit 2, double buffering can be activated on the following SD registers: the SD Gamma A and Gamma B curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed captioning, and SD Macrovision Bits[5:0] (Subaddress 0xE0, Bits[5:0]).
300mV
06234-071

Figure 73. Programmable DAC Gain—Positive and Negative Gain

The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC gain control feature can change this output current from 4.008 mA (?7.5%) to 4.658 mA (+7.5%).

Rev. C | Page 58 of 108

Data Sheet
The reset value of the control registers is 0x00; that is, nominal DAC current is output. Table 51 is an example of how the output current of the DACs varies for a nominal 4.33 mA output current.
Table 51. DAC Gain Control
Subaddress 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 4.25 4.23 ... ... 4.018 4.013 4.008 % Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% ?0.0180% ?0.0360% ... ... ?7.3640% ?7.3820% ?7.5000% Note

ADV7390/ADV7391/ADV7392/ADV7393
Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time. For ED/HD gamma correction, curve selection is controlled using Subaddress 0x35, Bit 4. For SD gamma correction, curve selection is controlled using Subaddress 0x88, Bit 7. The shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. By altering the response at these locations, the shape of the gamma correction curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 programmable locations are at the following points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The following locations are fixed and cannot be changed: 0, 16, 240, and 255. From the curve locations, 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve, should be calculated to produce the following result:
xDESIRED = (xINPUT)γ

Reset value, nominal

GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD; Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and output brightness level (as perceived on a CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function
SignalOUT = (SignalIN)
γ

where: xDESIRED is the desired gamma corrected output. xINPUT is the linear input signal. γ is the gamma correction factor. To program the gamma correction registers, calculate the 10 programmable curve values using the following formula:
? n ? 16 ? γ ? ? γn = ?? ? ? 240 ? 16 ? × (240 ? 16) ? + 16 ? ?? ?

where γ is the gamma correction factor. Gamma correction is available for SD and ED/HD video. For both variations, there are twenty 8-bit registers. They are used to program Gamma Correction Curve A and Gamma Correction Curve B. ED/HD gamma correction is enabled using Subaddress 0x35, Bit 5. ED/HD Gamma Correction Curve A is programmed at Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma Correction Curve B is programmed at Subaddress 0x4E to Subaddress 0x57. SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9.

where: γn is the value to be written into the gamma correction register for point n on the gamma correction curve. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. γ is the gamma correction factor. For example, setting γ = 0.5 for all programmable curve data points results in the following yn values:
y24 = [(8/224)0.5 × 224] + 16 = 58 y32 = [(16/224)0.5 × 224] + 16 = 76 y48 = [(32/224)0.5 × 224] + 16 = 101 y64 = [(48/224)0.5 × 224] + 16 = 120 y80 = [(64/224)0.5 × 224] + 16 = 136 y96 = [(80/224)0.5 × 224] + 16 = 150 y128 = [(112/224)0.5 × 224] + 16 = 174 y160 = [(144/224)0.5 × 224] + 16 = 195 y192 = [(176/224)0.5 × 224] + 16 = 214 y224 = [(208/224)0.5 × 224] + 16 = 232

where the sum of each equation is rounded to the nearest integer.
Rev. C | Page 59 of 108

ADV7390/ADV7391/ADV7392/ADV7393
The gamma curves in Figure 74 and Figure 75 are examples only; any user-defined curve in the range from 16 to 240 is acceptable.
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

Data Sheet
To select one of the 256 individual responses, the corresponding gain values, ranging from ?8 to +7 for each filter, must be programmed into the ED/HD sharpness filter gain register at Subaddress 0x40.

GAMMA CORRECTED AMPLITUDE

250 SIGNAL OUTPUT 200

ED/HD Adaptive Filter Mode
In ED/HD adaptive filter mode, the following registers are used: ? ? ? ? ? ? ?
06234-072

0.5

150

100 SIGNAL INPUT

50

ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C ED/HD Adaptive Filter Gain 1 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 3 ED/HD sharpness filter gain

0

0

50

100

150 LOCATION

200

250

Figure 74. Signal Input (Ramp) and Signal Output for Gamma 0.5

To activate the adaptive filter control, the ED/HD sharpness filter and the ED/HD adaptive filter must be enabled (Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1, respectively). The derivative of the incoming signal is compared to the three programmable threshold values: ED/HD adaptive filter (Threshold A, Threshold B, and Threshold C ) registers (Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D). The recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. The edges can then be attenuated with the settings in the ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers (Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and the ED/HD sharpness filter gain register (Subaddress 0x40). There are two adaptive filter modes available. The mode is selected using the ED/HD adaptive filter mode control (Subaddress 0x35, Bit 6) as follows: ? Mode A is used when the ED/HD adaptive filter mode control is set to 0. In this case, Filter B (LPF) is used in the adaptive filter block. In addition, only the programmed values for Gain B in the ED/HD sharpness filter gain register and ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers are applied when needed. The Gain A values are fixed and cannot be changed. Mode B is used when ED/HD adaptive filter mode control is set to 1. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the ED/HD sharpness filter gain register and ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers become active when needed.

300

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

GAMMA CORRECTED AMPLITUDE

250 0.3 0.5 150
AL GN T PU IN

200

1.5

100

SI

1.8

50

0

50

100

150 LOCATION

200

250

Figure 75. Signal Input (Ramp) and Selectable Output Curves

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS
Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D
There are three filter modes available on the ADV739x: sharpness filter mode and two adaptive filter modes. ?

ED/HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges shown in Figure 76, the ED/HD sharpness filter must be enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7 = 0).

06234-073

0

Rev. C | Page 60 of 108

Data Sheet
1.5 1.4 1.3 1.2 SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5 1.4 1.3 1.2

ADV7390/ADV7391/ADV7392/ADV7393
MAGNITUDE RESPONSE (Linear Scale)
1.6 1.5 1.4 1.3 1.2 1.1 1.0

MAGNITUDE

INPUT SIGNAL STEP

1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka)

MAGNITUDE

1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb)

0

2

FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7

Figure 76. ED/HD Sharpness and Adaptive Filter Control

a
R2 1

d

b
R4 R1

e

c
1 R2

f

Block

CH1 500mV REF A

500mV 4.00?s

M 4.00?s 9.99978ms 1

CH1 ALL FIELDS

CH1 500mV REF A

500mV 4.00?s

1

M 4.00?s 9.99978ms

CH1 ALL FIELDS

Figure 77. ED/HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES
Sharpness Filter Application
The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Table 52 are used to achieve the results shown in Figure 77. Input data is generated by an external signal source.
Table 52. ED/HD Sharpness Control Settings for Figure 77
Subaddress 0x00 0x01 0x02 0x30 0x31 0x40 0x40 0x40 0x40 0x40 0x40
1

Adaptive Filter Control Application
The register settings in Table 53 are used to obtain the results shown in Figure 79, that is, to remove the ringing on the input Y signal, as shown in Figure 78. Input data is generated by an external signal source.
Table 53. Register Settings for Figure 79
Subaddress 0x00 0x01 0x02 0x30 0x31 0x35 0x40 0x58 0x59 0x5A 0x5B 0x5C 0x5D Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64

Register Setting 0xFC 0x10 0x20 0x00 0x81 0x00 0x08 0x04 0x40 0x80 0x22

Reference1

a b c d e f

See Figure 77. Rev. C | Page 61 of 108

06234-075

06234-074

6 8 4 10 FREQUENCY (MHz)

12

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet
In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise as before. However, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image.

06234-076

Figure 78. Input Signal to ED/HD Adaptive Filter

In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.
DNR MODE

06234-077

DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN

Figure 79. Output Signal from ED/HD Adaptive Filter (Mode A)

When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 80 can be obtained.
Y DATA INPUT

NOISE SIGNAL PATH

CORING GAIN DATA CORING GAIN BORDER

INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? FILTER OUTPUT > THRESHOLD MAIN SIGNAL PATH – + SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT

DNR SHARPNESS MODE

DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN

06234-078

Figure 80. Output Signal from ED/HD Adaptive Filter (Mode B)

NOISE SIGNAL PATH

CORING GAIN DATA CORING GAIN BORDER

INPUT FILTER BLOCK

SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode.
Rev. C | Page 62 of 108
Y DATA INPUT

FILTER OUTPUT > THRESHOLD? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH +

ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT
06234-079

+

Figure 81. SD DNR Block Diagram

Data Sheet
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.

ADV7390/ADV7391/ADV7392/ADV7393
Block Size—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel × 16 pixel data block, and Logic 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.

DNR Input Select—Subaddress 0xA5, Bits[2:0]
These three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal processed by DNR. Figure 84 shows the filter responses selectable with this control.
1.0 FILTER D 0.8
MAGNITUDE

Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.
APPLY DATA CORING GAIN APPLY BORDER CORING GAIN

FILTER C 0.6

0.4

FILTER B

0.2 FILTER A
06234-082

OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING
06234-080

0

0

1

2

3 4 FREQUENCY (MHz)

5

6

OXXXXXXOOXXXXXXO

Figure 84. SD DNR Input Select

DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O

DNR Mode—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal because this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using the extended SSAF filter).

Figure 82. SD DNR Offset Control

DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.

Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.
720 × 485 PIXELS (NTSC) TWO-PIXEL BORDER DATA

Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control, which allows a shift in the data block of 15 pixels maximum. The coring gain positions are fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.

8 × 8 PIXEL BLOCK

8 × 8 PIXEL BLOCK

Figure 83. SD DNR Border Area

Rev. C | Page 63 of 108

06234-081

ADV7390/ADV7391/ADV7392/ADV7393
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
The ADV739x is able to control fast rising and falling signals at the start and end of active video to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible.
LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 12.5 IRE 0 IRE LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED

Data Sheet
At the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. Approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. All other active video pixels pass through unprocessed.

Figure 85. Example of Active Video Edge Functionality

VOLTS

IRE:FLT 100

0.5 50

0

0

–50 0 2 4 6

8

10

12

Figure 86. Example of Video Output with Subaddress 0x82, Bit 7 = 0

VOLTS

IRE:FLT 100

0.5 50

0

0

–50 –2 0 2 4

6

8

10

12

Figure 87. Example of Video Output with Subaddress 0x82, Bit 7 = 1

Rev. C | Page 64 of 108

06234-085

F2 L135

06234-084

F2 L135

06234-083

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see Table 54). It is also possible to output synchronization signals on the HSYNC and VSYNC pins (see Table 55 to Table 57).
Table 54. Timing Synchronization Signal Input Options
Signal SD HSYNC In SD VSYNC/FIELD In ED/HD HSYNC In ED/HD VSYNC/FIELD In
1

Pin HSYNC VSYNC HSYNC VSYNC

Condition SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])1 SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])1 ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0) ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)

SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 55. Timing Synchronization Signal Output Options
Signal SD HSYNC Out SD VSYNC/FIELD Out ED/HD HSYNC Out ED/HD VSYNC/FIELD Out
1 2

Pin HSYNC VSYNC HSYNC VSYNC

Condition SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1 SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1 ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)2 ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)2

ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0). ED/HD timing synchronization inputs must also be disabled; that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).

Table 56. HSYNC Output Control1, 2
ED/HD Input Sync Format (Subaddress 0x30, Bit 2) ED/HD HSYNC Control (Subaddress 0x34, Bit 1) ED/HD Sync Output Enable (Subaddress 0x02, Bit 7) 0 0 1 1 1 SD Sync Output Enable (Subaddress 0x02, Bit 6) 0 1

Signal on HSYNC Pin Tristate Pipelined SD HSYNC Pipelined ED/HD HSYNC Pipelined ED/HD HSYNC based on AV Code H bit Pipelined ED/HD HSYNC based on horizontal counter

X X
0 1

X X
0 0 1

X X X

X

Duration N/A See the SD Timing section. As per HSYNC timing. Same as line blanking interval. Same as embedded HSYNC.

1 2

In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video. X = don’t care.

Table 57. VSYNC Output Control 1 , 2
ED/HD Input Sync Format (Subaddress 0x30, Bit 2) x x 0 1 1 ED/HD VSYNC Control (Subaddress 0x34, Bit 2) x x 0 0 0 ED/HD Sync Output Enable (Subaddress 0x02, Bit 7) 0 0 1 1 1 SD Sync Output Enable (Subaddress 0x02, Bit 6) 0 1 x x x

Video Standard x Interlaced x All HD interlaced standards All ED/HD progressive standards

Signal on VSYNC Pin Tristate Pipelined SD VSYNC/field Pipelined ED/HD VSYNC or field signal Pipelined field signal based on AV Code F bit Pipelined VSYNC based on AV Code V bit

Duration N/A See the SD Timing section. As per VSYNC or field signal timing. Field. Vertical blanking interval.

Rev. C | Page 65 of 108

ADV7390/ADV7391/ADV7392/ADV7393
ED/HD Input Sync Format (Subaddress 0x30, Bit 2) ED/HD VSYNC Control (Subaddress 0x34, Bit 2) 1 ED/HD Sync Output Enable (Subaddress 0x02, Bit 7) 1 SD Sync Output Enable (Subaddress 0x02, Bit 6)

Data Sheet

X

X

Video Standard All ED/HD standards except 525p 525p

Signal on VSYNC Pin Pipelined ED/HD VSYNC based on the vertical counter Pipelined ED/HD VSYNC based on the vertical counter

Duration Aligned with serration lines. Vertical blanking interval.

X

1

1

X

1 2

In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video. X = don’t care.

LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV739x supports an Analog Devices, Inc., proprietary low power mode of operation. To use this low power mode, the DACs must be operating in full-drive mode (RSET = 510 Ω, RL = 37.5 Ω). Low power mode is not available in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can be independently enabled or disabled on each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode is disabled by default on all DACs. In low-power mode, DAC current consumption is content dependent and, on a typical video stream, it can be reduced by as much as 40%. For applications requiring the highest possible video performance, low power mode should be disabled.

DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down feature can be enabled using Subaddress 0x10, Bit 4. This feature is available only when the cable detection feature is enabled. With this feature enabled, the cable detection circuitry monitors DAC 1 and/or DAC 2 once per frame and, if they are unconnected, automatically powers down some or all of the DACs. Which DAC or DACs are powered down depends on the selected output configuration. For CVBS/Y-C output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and DAC 3 power down. For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs are powered down. DAC 2 is not monitored for YPrPb and RGB output configurations. Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is detected, the appropriate DAC or DACs remain powered up for the duration of the frame. If no cable is detected, the appropriate DAC or DACs power down until the next frame, when the process is repeated.

CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV739x includes an Analog Devices proprietary cable detection feature. The cable detection feature is available on DAC 1 and DAC 2 when operating in full-drive mode (RSET = 510 Ω, RL = 37.5 Ω, assuming a connected cable). The feature is not available in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω). For a DAC to be monitored, the DAC must be powered up in Subaddress 0x00. The cable detection feature can be used with all SD, ED, and HD video standards. It is available for all output configurations, that is, CVBS, Y-C, YPrPb, and RGB output configurations. For CVBS/Y-C output configurations, both DAC 1 and DAC 2 are monitored; that is, the CVBS and Y-C luma outputs are monitored. For YPrPb and RGB output configurations, only DAC 1 is monitored; that is, the luma or green output is monitored. Once per frame, the ADV739x monitors DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a cable is detected on one of the DACs, the relevant bit is set to 0. If not, the bit is set to 1.

SLEEP MODE
Subaddress 0x00, Bit 0
In sleep mode, most of the digital I/O pins of the ADV739x are disabled. For inputs, this means that the external data is ignored, and internally the logic normally driven by a given input is just tied low or high. This includes CLKIN. For digital output pins, this means that the pin goes into tristate (high impedance) mode. There are some exceptions to allow the user to continue to communicate with the part via I2C: the RESET, ALSB, SDA and SCL pins are kept alive. Most of the analogue circuitry is powered down when in sleep mode. In addition, the cable detect feature no longer works as the DACs are powered down. Sleep mode is enabled using Subaddress 0x00, Bit 0.

Rev. C | Page 66 of 108

Data Sheet
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
The ADV739x supports the readback of most digital inputs via the I2C MPU port. This feature is useful for board-level connectivity testing with upstream devices. The pixel port (P[15:0] or P[7:0]), HSYNC, VSYNC, and SFL are available for readback via the MPU port. The readback registers are located at Subaddress 0x13, Subaddress 0x14, and Subaddress 0x16. When using this feature, apply a clock signal to the CLKIN pin to register the levels applied to the input pins. The SD input mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when using this feature.

ADV7390/ADV7391/ADV7392/ADV7393
RESET pin low long enough to cause a reset to take place. All subsequent resets can be done via software.

SD TELETEXT INSERTION
Subaddress 0xC9 to Subaddress 0xCE
The ADV739x supports the insertion of teletext data, using a two pin interface, when operating in PAL mode. Teletext insertion is enabled using Subaddress 0xC9, Bit 0. In accordance with the PAL WST teletext standard, teletext data should be inserted into the ADV739x at a rate of 6.9375 Mbps. On the ADV7390/ADV7391, the teletext data is inserted on the VSYNC pin. On the ADV7392/ADV7393, the teletext data can be inserted on the VSYNC or P0 pin (selectable through Subaddress 0xC9, Bit 2). When teletext insertion is enabled, a teletext request signal is output from the ADV739x to indicate when teletext data should be inserted. The teletext request signal is output on the SFL pin. The position (relative to the teletext data) and width of the request signal are configurable using Subaddress 0xCA. The request signal can operate in either a line or bit mode. The request signal mode is controlled using Subaddress 0xC9, Bit 1. To account for the noninteger relationship between the teletext insertion rate (6.9375 Mbps) and the pixel clock (27 MHz), a teletext insertion protocol is implemented in the ADV739x. At a rate of 6.9375 Mbps, the time taken for the insertion of 37 teletext bits equates to 144 pixel clock cycles (at 27 MHz). For every 37 teletext bits inserted into the ADV739x, the 10th, 19th, 28th, and 37th bits are carried for three pixel clock cycles, and the remainder are carried for four pixel clock cycles (totaling 144 pixel clock cycles). The teletext insertion protocol repeats every 37 teletext bits or 144 pixel clock cycles until all 360 teletext bits are inserted.
45 BYTES (360 BITS) – PAL

RESET MECHANISMS
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on the RESET pin in accordance with the timing specifications. This resets all registers to their default values. After a hardware reset, the MPU port is configured for I2C operation. For correct device operation, a hardware reset is necessary after power-up. The ADV739x also has a software reset accessible via the I2C MPU port. A software reset is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets all registers to their default values. This bit is self-clearing; that is, after a 1 has been written to the bit, the bit automatically returns to 0. A hardware reset is necessary after power-up for correct device operation. If no hardware reset functionality is required by the application, the RESET pin can be connected to an RC network to provide the hardware reset necessary after power-up. After power-up, the time constant of the RC network holds the

TELETEXT VBI LINE

ADDRESS AND DATA

Figure 88. Teletext VBI Line

Rev. C | Page 67 of 108

06234-143

RUN-IN CLOCK

ADV7390/ADV7391/ADV7392/ADV7393
tSYNTTXOUT
CVBS/Y

Data Sheet

tPD
HSYNC 10.2?s TTXDATA TTXDEL

tPD

TTXREQ PROGRAMMABLE PULSE EDGES TTXST
06234-144

TTXDEL = TTXREQ TO TTXDATA (PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]).

tSYNTTXOUT = 10.2?s. tPD = PIPELINE DELAY THROUGH ADV739x.

Figure 89. Teletext Functionality Diagram

Rev. C | Page 68 of 108

Data Sheet PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
UNUSED PINS
If the HSYNC and VSYNC pins are not used, they should be tied to VDD_IO through a pull-up resistor (10 kΩ or 4.7 kΩ). Any other unused digital inputs should be tied to ground. Unused digital output pins should be left floating. DAC outputs can either be left floating or connected to GND. Disabling these outputs is recommended.

ADV7390/ADV7391/ADV7392/ADV7393

Table 58. ADV739x Output Rates
Input Mode (Subaddress 0x01, Bits[6:4]) SD

DAC CONFIGURATIONS
The ADV739x contains three DACs. All three DACs can be configured to operate in full-drive mode. Full-drive mode is defined as 34.7 mA full-scale current into a 37.5 Ω load, RL. Full drive is the recommended mode of operation for the DACs. Alternatively, all three DACs can be configured to operate in lowdrive mode. Low-drive mode is defined as 4.33 mA full-scale current into a 300 Ω load, RL. The ADV739x contains an RSET pin. A resistor connected between the RSET pin and AGND is used to control the full-scale output current and, therefore, the output voltage levels of DAC 1, DAC 2, and DAC 3. For full-drive operation, RSET must have a value of 510 Ω and RL must have a value of 37.5 Ω. For low-drive operation, RSET must have a value of 4.12 kΩ, and RL must have a value of 300 Ω. The resistor connected to the RSET pin should have a 1% tolerance. The ADV739x contains a compensation pin, COMP. A 2.2 nF compensation capacitor should be connected from the COMP pin to VAA.

ED

HD

Oversampling Off On On Off On On Off On On

Output Rate (MHz) 27 (2×) (8×) 108 216 (16×) 27 (1×) 108 (4×) 216 (8×) 74.25 (1×) 148.5 (2×) 297 (4×)

Table 59. Output Filter Requirements
Cutoff Frequency (MHz) > 6.5 > 6.5 > 6.5 > 12.5 > 12.5 > 12.5 > 30 > 30 > 30
3

Application SD

ED

HD

Oversampling 2× 8× 16× 1× 4× 8× 1× 2× 4×
10?H

Attenuation –50 dB at (MHz) 20.5 101.5 209.5 14.5 95.5 203.5 44.25 118.5 267

VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER
An output buffer is necessary on any DAC that operates in lowdrive mode (RSET = 4.12 kΩ, RL = 300 Ω). Analog Devices produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, see the relevant op amp data sheet. An optional reconstruction (anti-imaging) low-pass filter (LPF) may be required on the ADV739x DAC outputs. The filter specifications vary with the application. The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can remove the requirement for a reconstruction filter altogether. For applications requiring an output buffer and reconstruction filter, the ADA4430-1 and ADA4411-3 integrated video filter buffers should be considered.

DAC OUTPUT 600? 22pF 600?

1 4

75?

BNC OUTPUT

560?

Figure 90. Example of Output Filter for SD, 16× Oversampling
4.7?H DAC OUTPUT 6.8pF 600? 6.8pF 600?
4 3

75?
1

BNC OUTPUT

560?

Figure 91. Example of Output Filter for ED, 8× Oversampling
DAC OUTPUT
3

300?
4

1

75?

390nH
3

BNC OUTPUT
1

33pF

33pF

75?
4

500?

500?

Figure 92. Example of Output Filter for HD, 4× Oversampling
Rev. C | Page 69 of 108

06234-088

06234-087

560?

06234-086

560?

ADV7390/ADV7391/ADV7392/ADV7393
0 –10 MAGNITUDE (dB) –20 –30 CIRCUIT FREQUENCY RESPONSE 0 24n –30 21n –60 18n –90 PHASE (Degrees) 15n –120 12n –150 GROUP DELAY (Seconds) –60 –70 –80 1M 9n –180 6n –210 3n –240 0 1G

Data Sheet
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADV739x is a highly integrated circuit containing both precision analog and high speed digital circuitry. It is designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved. The layout should be optimized for lowest noise on the ADV739x power and ground planes by shielding the digital inputs and providing good power supply decoupling.
06234-089

GAIN (dB)

–40 –50

10M 100M FREQUENCY (Hz)

It is recommended to use a 4-layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer.

Figure 93. Output Filter Plot for SD, 16× Oversampling

Component Placement
Component placement should be carefully considered to separate noisy circuits, such as clock signals and high speed digital circuitry, from analog circuitry. The external loop filter components and components connected to the COMP and RSET pins should be placed as close as possible to, and on the same side of the PCB as, the ADV739x. Adding vias to the PCB to get the components closer to the ADV739x is not recommended. It is recommended that the ADV739x be placed as close as possible to the output connector, with the DAC output traces as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV739x. The termination resistors should overlay the PCB ground plane. External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV739x to minimize the possibility of noise pickup from neighboring circuitry and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
PHASE (Degrees)

0 –10

CIRCUIT FREQUENCY RESPONSE

480 18n 400

MAGNITUDE (dB) –20 –30
GAIN (dB)

16n 320 14n 240 160 80 8n 0 6n –80 4n –160 2n –240 0 1G 12n 10n

–40 –50 –60 –70 –80

GROUP DELAY (Seconds)

PHASE (Degrees)

10M

100M

FREQUENCY (Hz)

Figure 94. Output Filter Plot for ED, 8× Oversampling

0

CIRCUIT FREQUENCY RESPONSE PHASE (Degrees) MAGNITUDE (dB)

200

–10 GROUP DELAY (Seconds)
GAIN (dB)

120

06234-090

–90 1M

–20

40

Power Supplies
It is recommended that a separate regulated supply be provided for each power domain (VAA, VDD, VDD_IO, and PVDD). For optimal performance, linear regulators rather than switch mode regulators should be used. If switch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. This is particularly true for the VAA and PVDD power domains. Each power supply should be individually connected to the system power supply at a single point through a suitable filtering device, such as a ferrite bead.

–30

–40

–40

–120

1

10 FREQUENCY (MHz)

100

Figure 95. Output Filter Plot for HD, 4× Oversampling

Rev. C | Page 70 of 108

06234-091

–50

–200

Data Sheet
Power Supply Decoupling
It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD, VDD_IO, and both VDD pins should be individually decoupled to ground. The decoupling capacitors should be placed as close as possible to the ADV739x with the capacitor leads kept as short as possible to minimize lead inductance. A 1 μF tantalum capacitor is recommended across the VAA supply in addition to the 10 nF and 0.1 μF ceramic capacitors.

ADV7390/ADV7391/ADV7392/ADV7393
ADDITIONAL LAYOUT CONSIDERATIONS FOR THE WLCSP PACKAGE
Due to the high pad density and 0.5 mm pitch of the WLCSP, it is not recommended that connections to inner bumps be routed on the top PCB layer only. The traces (track and space) must fit within the limits of the solder mask openings. Routing all traces on the top surface layer of the board, while possible, is usually not a feasible solution due to the limitations of the geometries imposed by the board fabrication technology. Given a pitch of 0.5 mm with a typical solder mask opening diameter of 0.35 mm, there is only a 0.15 mm distance between the solder mask openings. An alternative to routing on the top surface is to route out on buried layers. To achieve this, the pads are connected to the lower layers using microvias. See the AN-617 Application Note, MicroCSP Wafer Level Chip Scale Package for additional details about the board layout for the WLCSP package.

Power Supply Sequencing
The ADV739x is robust to all power supply sequencing combinations. Any sequence can be used. However, all power supplies should settle to their nominal voltages within one second.

Digital Signal Interconnect
The digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal traces should not overlay the VAA or PVDD power plane. Due to the high clock rates used, avoid long clock traces to the ADV739x to minimize noise pickup. Any pull-up termination resistors for the digital inputs should be connected to the VDD_IO power supply.

Analog Signal Interconnect
DAC output traces should be treated as transmission lines with appropriate measures taken to ensure optimal performance (for example, impedance matched traces). The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to, and on the same side of the PCB as, the ADV739x. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the traces connected to the DAC output pins. Adding ground traces between the DAC output traces is also recommended.

Rev. C | Page 71 of 108

ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL APPLICATIONS CIRCUITS
FERRITE BEAD VDD_IO 33?F 10?F 0.1?F GND_IO 0.1?F PGND 0.1?F AGND 0.1?F DGND 0.01?F GND_IO 0.01?F PGND 0.01?F AGND 0.01?F DGND 1?F VDD_IO POWER SUPPLY DECOUPLING PVDD POWER SUPPLY DECOUPLING VAA POWER SUPPLY AGND DECOUPLING

Data Sheet
NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV739x. 2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN: ALSB = 0, I2C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR 0x54 (ADV7391/ADV7393) ALSB = 1, I2C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR 0x56 (ADV7391/ADV7393) 3. THE RESISTOR CONNECTED TO THE RSET PIN SHOULD HAVE A 1% TOLERANCE. 4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULLDRIVE (RSET = 510?, RL = 37.5?).

GND_IO GND_IO FERRITE BEAD PVDD 33?F 10?F

PGND PGND FERRITE BEAD VAA 33?F 10?F

AGND AGND FERRITE BEAD VDD 33?F DGND 10?F DGND

VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN

VAA
VDD_IO PVDD
VDD VDD

VAA

2.2nF COMP RSET

P0 P1 P2 P3 P4 P5 P6 P7

ADV739x

510? AGND DAC1 TO DAC3 FULL DRIVE OPTION (RECOMMENDED) DAC 1
OPTIONAL LPF

PIXEL PORT INPUTS
P8 P9 P10 P11 P12 P13 P14 P15

DAC1 TO DAC3 LOW DRIVE OPTION DAC 1 DAC 2 DAC 3 RSET 4.12k? AGND ADA4411-3 DAC 1 LPF 300? 75? DAC 1

ADV7392/ ADV7393 ONLY

DAC 2 DAC 3 75? AGND 75?

OPTIONAL LPF

75?

OPTIONAL LPF

AGND

AGND

CONTROL INPUTS/OUTPUTS

HSYNC VSYNC

CLOCK INPUT

CLKIN AGND SDA SCL DAC 2 LPF ALSB RESET TIE EITHER LOW OR HIGH 300? AGND ADA4411-3 EXT_LF DAC 3 LPF 300? AGND
06234-092

I2C PORT

ADA4411-3 75? DAC 2

EXTERNAL LOOP FILTER PVDD 12nF 170?

75?

DAC 3

150nF

LOOP FILTER COMPONENTS SHOULD BE LOCATED AGND PGND DGND DGND GND_IO CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. AGND PGND DGND DGND GND_IO

Figure 96. ADV739x (LFCSP) Typical Applications Circuit

Rev. C | Page 72 of 108

Data Sheet
FERRITE BEAD VDD_IO 33?F 10?F 0.1?F GND_IO 0.1?F PGND 0.1?F AGND 0.1?F DGND 0.01?F GND_IO 0.01?F PGND 0.01?F AGND 0.01?F DGND 1?F VDD_IO POWER SUPPLY DECOUPLING PVDD POWER SUPPLY DECOUPLING VAA POWER SUPPLY DECOUPLING AGND

ADV7390/ADV7391/ADV7392/ADV7393
NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7390. 2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN: ALSB = 0, I2C DEVICE ADDRESS = 0xD4 ALSB = 1, I2C DEVICE ADDRESS = 0xD6 3. THE RESISTOR CONNECTED TO THE RSET PIN SHOULD HAVE A 1% TOLERANCE. 4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULLDRIVE (RSET = 510?, RL = 37.5?).

GND_IO GND_IO FERRITE BEAD PVDD 33?F 10?F

PGND PGND FERRITE BEAD VAA 33?F 10?F

AGND AGND FERRITE BEAD VDD 33?F DGND 10?F DGND

VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN

VAA
VDD_IO PVDD VDD VDD VAA

2.2nF COMP RSET 510?

PIXEL PORT INPUTS

P0 P1 P2 P3 P4 P5 P6 P7

ADV7390BCBZ

AGND

CONTROL INPUTS/OUTPUTS

HSYNC VSYNC

ALSB

TIE EITHER LOW OR HIGH DAC FULL DRIVE OPTION (RECOMMENDED)

CLOCK INPUT

CLKIN DAC 1

OPTIONAL LPF 75? VIDEO

I2C PORT

SDA SCL

DAC LOW DRIVE OPTION RESET EXTERNAL LOOP FILTER PVDD 12nF EXT_LF 150nF 170? DAC LPF 300? AGND
06234-148

RSET 4.12k? AGND ADA4411-3 75? VIDEO

LOOP FILTER COMPONENTS AGND PGND DGND DGND GND_IO SHOULD BE LOCATED CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV7390. AGND PGND DGND DGND GND_IO

Figure 97. ADV7390BCBZ-A (WLCSP) Typical Applications Circuit

Rev. C | Page 73 of 108

ADV7390/ADV7391/ADV7392/ADV7393 COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV739x supports a copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can be transmitted only when the ADV739x is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 98).

Data Sheet
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval. The HD CGMS data registers are at Subaddress 0x41, Subadress 0x42, and Subaddress 0x43. The ADV739x also supports CGMS Type B packets in HD mode (720p and 1080i) in accordance with CEA-805-A. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 720p CGMS data is applied to Line 23 of the luminance vertical blanking interval. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 1080i CGMS data is applied to Line 18 and Line 581 of the luminance vertical blanking interval. The HD CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.

ED CGMS
Subaddress 0x41 to Subaddress 0x43; Subaddress 0x5E to Subaddress 0x6E 525p Mode
The ADV739x supports a copy generation management system (CGMS) in 525p mode in accordance with EIAJ CPR-1204-1. When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p CGMS data is inserted on Line 41. The 525p CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV739x also supports CGMS Type B packets in 525p mode in accordance with CEA-805-A. When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 525p CGMS Type B data is inserted on Line 40. The 525p CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.

CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS data bits (C19 to C14) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV739x. This calculation is based on the lower 14 bits (C13 to C0) of the data in the CGMS data registers, and the result is output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits (C19 to C0) are output directly from the CGMS registers (CRC must be calculated by the user manually). If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is enabled, the upper six CGMS Type B data bits (P122 to P127) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV739x. This calculation is based on the lower 128 bits (H0 to H5 and P0 to P121) of the data in the CGMS Type B data registers. The result is output with the remaining 128 bits to form the complete 134 bits of the CGMS Type B data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5 and P0 to P127) are output directly from the CGMS Type B registers (CRC must be calculated by the user manually).

625p Mode
The ADV739x supports a copy generation management system (CGMS) in 625p mode in accordance with IEC 62375 (2004). When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. The 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43.

HD CGMS
Subaddress 0x41 to Subaddress 0x43; Subaddress 0x5E to Subaddress 0x6E
The ADV739x supports a copy generation management system (CGMS) in HD mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p CGMS data is applied to Line 24 of the luminance vertical blanking interval.

Rev. C | Page 74 of 108

Data Sheet
+100 IRE REF +70 IRE

ADV7390/ADV7391/ADV7392/ADV7393
CRC SEQUENCE

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE –40 IRE 11.2?s

2.235?s ± 20ns

Figure 98. Standard Definition CGMS Waveform

CRC SEQUENCE +700mV REF 70% ± 10% BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV –300mV 5.8?s ± 0.15?s 6T 21.2?s ± 0.22?s 22T
06234-094

T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns

Figure 99. Enhanced Definition (525p) CGMS Waveform

PEAK WHITE

R = RUN-IN S = START CODE

500mV ± 25mV

R

S

C0 C1 LSB

C2

C3

C4

C5

C6

C7

C8

C9 C10 C11 C12 C13 MSB

SYNC LEVEL

13.7?s
06234-095

5.5?s ± 0.125?s

Figure 100. Enhanced Definition (625p) CGMS Waveform

+700mV REF 70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8

CRC SEQUENCE BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV –300mV 4T 3.128?s ± 90ns

T ± 30ns 17.2?s ± 160ns 22T T = 1/(fH × 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H

06234-093

49.1?s ± 0.5?s

Figure 101. High Definition (720p) CGMS Waveform

Rev. C | Page 75 of 108

06234-096

ADV7390/ADV7391/ADV7392/ADV7393
+700mV REF 70% ± 10% CRC SEQUENCE BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

Data Sheet

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV –300mV 4T 4.15?s ± 60ns

T ± 30ns 22.84?s ± 210ns 22T T = 1/(fH × 2200/77) = 1.038?s fH = HORIZONTAL SCAN FREQUENCY 1H

Figure 102. High Definition (1080i) CGMS Waveform

+700mV START 70% ± 10% BIT 1 BIT 2

CRC SEQUENCE BIT 134

P122

P123

P124

H0

H1

H2

H3

H4

H5

P2

P3

P0

0mV
06234-098

–300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 103. Enhanced Definition (525p) CGMS Type B Waveform

P1

P4

.

.

.

+700mV 70% ±10% START BIT 1 BIT 2

CRC SEQUENCE BIT 134

P122

P123

P124

P125

P126

H0

H1

H2

H3

H4

H5

P0

P1

P2

P3

0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
06234-099

Figure 104. High Definition (720p and 1080i) CGMS Type B Waveform

Rev. C | Page 76 of 108

P4

.

.

.

P127

P127

P125

P126

06234-097

Data Sheet SD WIDE SCREEN SIGNALING
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV739x supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long. The function of each of these bits is shown in Table 60. The WSS data is preceded by a run-in sequence and a start code (see
Table 60. Function of WSS Bits
Bit Description Aspect Ratio, Format, Position 13 12 11 10 9 Bit Number 8 7 6 5

ADV7390/ADV7391/ADV7392/ADV7393
Figure 105). The latter portion of Line 23 (after 42.5 μs from the falling edge of HSYNC) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit 7. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7.

4

3 1 0 0 1 0 1 1 0

2 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1

0 0 1 0 1 0 1 0 1

Mode Color Encoding Helper Signals Reserved Teletext Subtitles Open Subtitles 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1

0 1

Surround Sound Copyright Copy Protection

Setting 4:3, full format, N/A 14:9, letterbox, center 14:9, letterbox, top 16:9, letterbox, center 16:9, letterbox, top >16:9, letterbox, center 14:9, full format, center 16:0, N/A, N/A Camera mode Film mode Normal PAL Motion Adaptive ColorPlus Not present Present N/A No Yes No Subtitles in active image area Subtitles out of active image area Reserved No Yes No copyright asserted or unknown Copyright asserted Copying not restricted Copying restricted

500mV RUN-IN SEQUENCE START CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO

11.0?s 42.5?s
06234-100

38.4?s

Figure 105. WSS Waveform Diagram

Rev. C | Page 77 of 108

ADV7390/ADV7391/ADV7392/ADV7393 SD CLOSED CAPTIONING
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color transmission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning can be enabled using Subaddress 0x83, Bits[6:5]. Closed captioning consists of a seven-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic 1 start bit. Sixteen bits of data follow the start bit. The data consists of two 8-bit bytes (seven data bits and one odd parity bit per byte). The data for these bytes is stored in SD closed captioning registers (Subaddress 0x93 to Subaddress 0x94). The ADV739x also supports the extended closed captioning operation, which is active during even fields and encoded on Line 284. The data for this operation is stored in SD closed captioning registers (Subaddress 0x91 to Subaddress 0x92). The ADV739x automatically generates all clock run-in signals and timing that support closed captioning on Line 21 and Line 284.

Data Sheet
All pixels inputs are ignored on Line 21 and Line 284 if closed captioning is enabled. The FCC Code of Federal Regulations (CFR) Title 47 Section 15.119 and EIA-608 describe the closed captioning information for Line 21 and Line 284. The ADV739x uses a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn loads the new data (two bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21. Otherwise, a TV does not recognize them. If there is a message such as “Hello World” that has an odd number of characters, it is important to add a blank character at the end to make sure that the end-of-caption, 2-byte control code lands in the same field.

10.5 ± 0.25?s

12.91?s 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A D0 TO D6 R T BYTE 0 P A R I T Y P A R I T Y

50 IRE

D0 TO D6

40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003?s 27.382?s

BYTE 1

33.764?s

Figure 106. SD Closed Captioning Waveform, NTSC

Rev. C | Page 78 of 108

06234-101

Data Sheet INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV739x is able to internally generate SD color bar and black bar test patterns. For this function, a 27 MHz clock signal must be applied to the CLKIN pin. The register settings in Table 61 are used to generate an SD NTSC 75% color bar test pattern. All other registers are set as normal/ default. Component YPrPb output is available on DAC 1 to DAC 3. On power-up, the subcarrier frequency registers default to the appropriate values for NTSC.
Table 61. SD NTSC Color Bar Test Pattern Register Writes
Subaddress 0x00 0x82 0x84 Setting 0x1C 0xC9 0x40

ADV7390/ADV7391/ADV7392/ADV7393
ED/HD TEST PATTERNS
The ADV739x is able to internally generate ED/HD color bar, black bar, and hatch test patterns. For ED test patterns, a 27 MHz clock signal must be applied to the CLKIN pin. For HD test patterns, a 74.25 MHz clock signal must be applied to the CLKIN pin. The register settings in Table 63 are used to generate an ED 525p hatch test pattern. All other registers are set as normal/ default. Component YPrPb output is available on DAC 1 to DAC 3. For component RGB output rather than YPrPb output, 0 should be written to Subaddress 0x02, Bit 5.
Table 63. ED 525p Hatch Test Pattern Register Writes
Subaddress 0x00 0x01 0x31 Setting 0x1C 0x10 0x05

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Subaddress 0x82. For component RGB output rather than YPrPb output, 0 should be written to Subaddress 0x02, Bit 5. To generate an SD NTSC black bar test pattern, the settings shown in Table 61 should be used with an additional write of 0x24 to Subaddress 0x02. For PAL output of either test pattern, the same settings are used except that Subaddress 0x80 is programmed to 0x11, and the subcarrier frequency (FSC) registers are programmed as shown in Table 62.
Table 62. PAL FSC Register Writes
Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 Setting 0xCB 0x8A 0x09 0x2A

To generate an ED 525p black bar test pattern, the settings shown in Table 63 should be used with an additional write of 0x24 to Subaddress 0x02. To generate an ED 525p flat field test pattern, the settings shown in Table 63 should be used, except that 0x0D should be written to Subaddress 0x31. The Y, Cr, and Cb levels for the hatch and flat field test patterns can be controlled using Subaddress 0x36, Subaddress 0x37, and Subaddress 0x38, respectively. For ED/HD standards other than 525p, the settings shown in Table 63 (and subsequent comments) are used, except that Subaddress 0x30, Bits[7:3] are updated as appropriate.

Note that, when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value to be written is only accepted after the FSC3 write is complete.

Rev. C | Page 79 of 108

ADV7390/ADV7391/ADV7392/ADV7393 SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)

Data Sheet

The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If the VSYNC and HSYNC pins are not used, they should be tied to VDD_IO when using this mode.

ANALOG VIDEO

EAV CODE INPUT PIXELS C F 0 0 X 8 1 8 1 Y Y r F 0 0 Y 0 0 0 0 4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK END OF ACTIVE VIDEO LINE 0 F F A A A 0 F F B B B ANCILLARY DATA (HANC) 268 CLOCK 280 CLOCK

SAV CODE 8 1 8 1 F 0 0 X C Y C Y C Y C Y C b r b 0 0 0 0 F 0 0 Y b r 4 CLOCK 4 CLOCK

1440 CLOCK 1440 CLOCK
06234-102

START OF ACTIVE VIDEO LINE

Figure 107. SD Timing Mode 0, Slave Option

Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on HSYNC and the F bit is output on VSYNC.
DISPLAY VERTICAL BLANK DISPLAY

522 H F

523

524

525

1

2

3

4

5

6

7

8

9

10

11

20

21

22

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

DISPLAY

260 H F

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

Figure 108. SD Timing Mode 0, Master Option, NTSC

Rev. C | Page 80 of 108

06234-103

Data Sheet
DISPLAY VERTICAL BLANK

ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY

622 H

623

624

625

1

2

3

4

5

6

7

21

22

23

F

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

DISPLAY

309 H

310

311

312

313

314

315

316

317

318

319

320

334

335

336

F

ODD FIELD

EVEN FIELD

Figure 109. SD Timing Mode 0, Master Option, PAL

ANALOG VIDEO

H

F

Figure 110. SD Timing Mode 0, Master Option, Data Transitions

Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively.
DISPLAY VERTICAL BLANK DISPLAY

522 HSYNC FIELD

523

524

525

1

2

3

4

5

6

7

8

9

10

11

20

06234-105

21

22

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

DISPLAY

260 HSYNC FIELD

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

06234-104

ODD FIELD

EVEN FIELD

Figure 111. SD Timing Mode 1, Slave Option, NTSC

Rev. C | Page 81 of 108

06234-106

ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY VERTICAL BLANK

Data Sheet
DISPLAY

622 HSYNC FIELD

623

624

625

1

2

3

4

5

6

7

21

22

23

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

DISPLAY

309 HSYNC FIELD

310

311

312

313

314

315

316

317

318

319

320

334

335

336

ODD FIELD

EVEN FIELD

Figure 112. SD Timing Mode 1, Slave Option, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the HSYNC and VSYNC pins, respectively.
HSYNC

FIELD

PIXEL DATA

Cb

Y

Cr

Y
06234-108

PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2

Figure 113. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input on the HSYNC and VSYNC pins, respectively.

Rev. C | Page 82 of 108

06234-107

Data Sheet
DISPLAY

ADV7390/ADV7391/ADV7392/ADV7393
VERTICAL BLANK DISPLAY

522 HSYNC VSYNC

523

524

525

1

2

3

4

5

6

7

8

9

10

11

20

21

22

EVEN FIELD DISPLAY

ODD FIELD DISPLAY

VERTICAL BLANK

260 HSYNC VSYNC

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

Figure 114. SD Timing Mode 2, Slave Option, NTSC

DISPLAY

VERTICAL BLANK

DISPLAY

622 HSYNC VSYNC

623

624

625

1

2

3

4

5

6

7

21

22

23

EVEN FIELD DISPLAY

ODD FIELD DISPLAY

VERTICAL BLANK

309 HSYNC VSYNC

310

311

312

313

314

315

316

317

318

319

320

334

335

336

ODD FIELD

EVEN FIELD

Figure 115. SD Timing Mode 2, Slave Option, PAL

Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output on the HSYNC and VSYNC pins, respectively.

HSYNC

VSYNC

PIXEL DATA PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2

Cb

Y

Cr

Y
06234-111

Figure 116. S

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